Test Structure and Method for Monitoring the Influence of Epitaxial Process on Transistor Performance

Abstract

The present application provides a test structure and method for monitoring the influence of an epitaxial process on transistor performance. The test structure includes a transistor test area and a density control area. The density control area is provided with a plurality of basic units having the same active area density, and the density of the target epitaxial layer in the test structure can be controlled by setting different quantity ratios of P-type units and N-type units. The transistor test area is provided with a plurality of target basic units, and one transistor in each target basic unit is connected in parallel through a test circuit for measuring and evaluating the performance of the transistor. Wherein, the basic unit includes at least one transistor, the target basic unit refers to one of the P-type units and the N-type units, and the transistor of the target basic unit adopts a molecular epitaxial process. The active area density refers to the area ratio of the active area in the basic unit, and the density of the target epitaxial layer refers to the area ratio of the epitaxial layer of the target basic unit in the circuit layout.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and manufacturing technologies, and particularly relates to a test structure and method for monitoring the impact of an epitaxial process on transistor performance. Background Art

[0002] As the size of semiconductor devices decreases day by day, molecular epitaxy technology has become one of the most critical processes in semiconductor manufacturing at the 28nm and below nodes, such as the SiGe molecular epitaxy technology for P-MOS. The molecular epitaxy process generates the required stress type for the channel by embedding a silicon epitaxial layer at the source and drain ends, thereby significantly improving the performance of the transistor. Since silicon epitaxy technology is of extremely high importance in advanced processes, it is an essential part for a mature semiconductor manufacturing factory to monitor the impact of the silicon epitaxy process on transistor performance from an electrical perspective.

[0003] The area ratio of the silicon epitaxial layer in the circuit layout is a very important factor affecting the growth quality of the epitaxial layer (the thickness, doping concentration, lattice defects, etc. of each layer in the epitaxial process), that is, the density of the epitaxial layer is a key factor affecting transistor performance; however, there is currently no relevant test structure. Summary of the Invention

[0004] To solve the above technical problems, a first aspect of the present application discloses a test structure for monitoring the impact of an epitaxial process on transistor performance. The test structure includes a transistor test area and a density control area;

[0005] The density control area is provided with a plurality of basic units having the same active area density, and can control the density of the target epitaxial layer in the test structure by setting different quantity ratios of P-type units and N-type units;

[0006] The transistor test area is provided with several target basic units, and one transistor in each target basic unit is connected in parallel through a test circuit for measuring and evaluating the performance of the transistor;

[0007] Wherein, each basic unit includes at least one transistor. The P-type unit is a basic unit in which the transistor is a P-channel MOS transistor, and the N-type unit is a basic unit in which the transistor is an N-channel MOS transistor; the target basic unit refers to one of the P-type unit and the N-type unit, and the transistor of the target basic unit adopts the molecular epitaxy process; the active area density is the area ratio of the active area in the basic unit; the density of the target epitaxial layer is the area ratio of the epitaxial layer of the target basic unit in the circuit layout.

[0008] Furthermore, the active area densities of all basic units in the test structure are the same.

[0009] Further, the size of the test structure is 30um×30um to 200um×200um.

[0010] Further, the number of target basic units in the transistor test area is 2 - 36.

[0011] Further, the test circuit includes a source - end measurement signal line, a drain - end measurement signal line, and a gate - end measurement signal line;

[0012] In the transistor test area, one transistor is taken from each target basic unit and connected in parallel: the source end of each transistor for parallel connection is connected to the source - end measurement signal line, the drain end of each transistor for parallel connection is connected to the drain - end measurement signal line, and the gate end of each transistor for parallel connection is connected to the gate - end measurement signal line.

[0013] The second aspect of the present application provides a method for monitoring the influence of the epitaxial process on the performance of transistors, which is realized by using the above - mentioned test structure, and includes the following steps:

[0014] According to the density range of the target epitaxial layer to be monitored, multiple target epitaxial layer density values are taken, and a test structure group is set for each target epitaxial layer density value, so that the target epitaxial layer density of the test structures in the test structure group is the corresponding target epitaxial layer density value; wherein, each test structure group includes at least one test structure;

[0015] Use the test structures in each test structure group to measure the electrical parameters of the transistors, and obtain a set of transistor electrical parameter values corresponding to the test structure group;

[0016] Evaluate the influence of the epitaxial process on the performance of the transistors according to the set of transistor electrical parameter values corresponding to the test structure group and the density range of the target epitaxial layer to be monitored.

[0017] Further, in the density control areas of all test structures, the active - area density of the basic units is the same.

[0018] Further, the target epitaxial layer density value of the test structure is controlled by setting the number ratio of P - type units and N - type units in the density control area of the test structure.

[0019] Further, evaluating the influence of the epitaxial process on the performance of the transistors according to the set of transistor electrical parameter values corresponding to the test structure group and the density range of the target epitaxial layer to be monitored includes:

[0020] Perform data processing on the set of transistor electrical parameter values of each test structure group to obtain the processed transistor electrical parameter values;

[0021] Using multiple set target epitaxial layer density values and the processed transistor electrical parameter values obtained through corresponding test structure groups, a relationship curve between the target epitaxial layer density and the transistor electrical parameters is plotted to evaluate the window size of the epitaxial process.

[0022] Further, the density range of the target epitaxial layer to be monitored is 5% - 85%.

[0023] Further, the electrical parameters of the transistor are the saturation current, the saturation threshold voltage, or the off - current.

[0024] Adopting the above - mentioned technical solution, the present application has the following beneficial effects:

[0025] The test structure for monitoring the influence of the epitaxial process on the transistor performance disclosed in the present application can, on the premise of ensuring that the area ratio of the active region in the density control region remains unchanged, obtain different target epitaxial layer densities by adjusting the ratio of N - type units and P - type units, and use the electrical parameters characterizing the transistor performance measured in the transistor test region, thereby effectively obtaining the influence of the epitaxial process on the transistor performance and realizing the monitoring of the epitaxial process. Moreover, multiple transistors are connected in parallel for testing in the transistor test region to evaluate the transistor performance, which can effectively eliminate the influence of process fluctuations on the transistor performance and avoid the influence of process instability on the monitoring data.

[0026] The method for monitoring the influence of the epitaxial process on the transistor performance disclosed in the present application, using the test structure disclosed in the present application, can set several test structure groups with different target epitaxial layer densities, respectively measure the transistor electrical parameters at different target epitaxial layer densities, obtain the relationship curve between the transistor electrical parameters and the target epitaxial layer density within the monitoring range of the target epitaxial layer density, realize the monitoring of the epitaxial process, and obtain the stable window size of the epitaxial process for semiconductor device manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 It is a schematic diagram of a test structure for monitoring the influence of the epitaxial process on the transistor performance according to an embodiment of the present application.

[0029] Figure 2 It is a schematic diagram of the structure of the basic unit of the test structure according to an embodiment of the present application.

[0030] Figure 3Schematic diagram of a test structure for monitoring the impact of epitaxial process on transistor performance in an embodiment of the present application.

[0031] Figure 4 Schematic diagram of a silicon epitaxial layer structure.

[0032] Figure 5 Schematic diagram of the transistor test area in the test structure of an embodiment of the present application.

[0033] Figure 6 Relationship curve graph of the saturation current of the transistor and the target epitaxial layer density in an embodiment of the present application.

[0034] The following is a supplementary description of the drawings:

[0035] 1 - Density control area; 11 - N-type unit; 12 - P-type unit; 2 - Transistor test area; 21 - First metal layer; 22 - Second metal layer; 23 - Channel; 24 - Contact hole; 3 - Active area; 4 - Polysilicon; 5 - Cap layer; 6 - Body layer; 7 - Seed layer. Specific implementation manners

[0036] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application.

[0037] As used herein, "one embodiment" or "embodiment" refers to a specific feature, structure, or characteristic that may be included in at least one implementation manner of the present application. In the description of the embodiments of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0038] Please refer to Figure 1 ,Figure 1 This is a schematic diagram of a test structure for monitoring the impact of an epitaxial process on transistor performance according to an embodiment of the present application. The test structure includes multiple basic units, and the test structure is divided into a density control region 1 and a transistor test region 2; Figure 2 This is a schematic diagram of an embodiment structure of a basic unit. Each basic unit includes several transistors.

[0039] As Figure 3 shown, the density control region 1 is provided with multiple basic units having the same active region density. By setting different quantity ratios of P-type units 12 and N-type units 11, the density of the target epitaxial layer in the test structure can be controlled; that is, different target epitaxial layer densities can be obtained by adjusting the quantity ratio of P-type units 12 and N-type units 11.

[0040] Among them, the P-type unit 12 refers to a basic unit in which the transistor is a P-channel MOS transistor, and the N-type unit 11 refers to a basic unit in which the transistor is an N-channel MOS transistor; the target basic unit refers to one of the P-type unit 12 and the N-type unit 11, and the transistor of the target basic unit adopts a molecular epitaxial process.

[0041] The active region density refers to the area ratio of the active region 3 in the basic unit. In the embodiment of the present application, the active region densities of all basic units in the test structure are the same;

[0042] The density of the target epitaxial layer refers to the area ratio of the epitaxial layer of the target basic unit in the circuit layout. The epitaxial layer can be a silicon epitaxial layer, and its structure is as Figure 4 shown, including a cap layer 5, a body layer 6, and a seed layer 7.

[0043] In the embodiment of the present application, the calculation method of the target epitaxial layer density can be as follows. Combining Figure 3 , for example, the target epitaxial layer is in the active region 3 of the P-type unit 12. The specific steps are as follows:

[0044] a) The active region density of the P-type unit 12: α = (X2 × Y2) / (X1 × Y1);

[0045] b) The area ratio of the P-type unit 12 in the density control region 1: β = the number of P-type units 12 / (the number of N-type units 11 + the number of P-type units 12);

[0046] c) The target epitaxial layer density γ = α × β.

[0047] Assume α = 0.6. Then, in this embodiment, the target epitaxial layer density γ = 0.6 × 0.5 = 0.3. It should be noted that since the proportion of the transistor test region 2 in the test structure is very small and can be ignored, the target epitaxial layer density of the density control region 1 can be used as the target epitaxial layer density of the test structure.

[0048] The transistor test area 2 is provided with a plurality of target basic units, and one transistor in each target basic unit is connected in parallel through a test circuit: the source end of each transistor for parallel connection is connected to the source end measurement signal line, the drain end of each transistor for parallel connection is connected to the drain end measurement signal line, and the gate end of each transistor for parallel connection is connected to the gate end measurement signal line, which is used to measure and evaluate the performance of the transistor. Considering the possible instability of the process, the transistor test area 2 generally includes 2 to 36 target basic units, that is, 2 to 36 transistors are connected in parallel for testing to evaluate the transistor performance, which can largely eliminate the influence of process fluctuations on the transistor performance. For an example of the connection method of the parallel test, reference can be made to Figure 5 , Figure 5 In the transistor test area 2 in [reference], 9 target basic units are provided. One transistor is taken from each unit, and the source ends S of these 9 transistors are all connected to the source end measurement signal line, the drain ends D are all connected to the drain end measurement signal line, and the gate ends G are all connected to the gate end measurement signal line.

[0049] The test structure disclosed in the embodiment of the present application for monitoring the influence of the epitaxial process on the transistor performance can, on the premise of ensuring that the area ratio of the active region 3 in the density control area 1 remains unchanged, obtain the densities of different target epitaxial layers by adjusting the ratio of the N-type active region 3 and the P-type active region 3, and use the transistor test area 2 to measure the electrical parameters characterizing the transistor performance, so as to effectively obtain the influence of the epitaxial process on the transistor performance and realize the monitoring of the epitaxial process. Moreover, in the transistor test area 2, multiple transistors are connected in parallel for testing to evaluate the transistor performance, which can effectively eliminate the influence of process fluctuations on the transistor performance and avoid the influence of process instability on the monitoring data. In a specific application, an epitaxial process local monitoring window with a size of 30um×30um to 200um×200um is generally selected as the test structure.

[0050] The second aspect of the embodiment of the present application discloses a method for monitoring the influence of the epitaxial process on the transistor performance

[0051] implemented by using the above test structure, which is characterized by including the following steps:

[0052] S1: According to the density range of the target epitaxial layer to be monitored, obtain multiple target epitaxial layer density values, and set a test structure group for each target epitaxial layer density value, so that the target epitaxial layer density of the test structure in the test structure group is the target epitaxial layer density value; wherein, at least one test structure is included in each test structure group;

[0053] In the embodiment of the present application, in the density control area 1 of all test structures, the density of the active region 3 of the basic unit is the same.

[0054] In the embodiments of the present application, the target epitaxial layer density value of the test structure is controlled by setting the quantity ratio of P-type units 12 and N-type units 11 in the density control region 1 of the test structure.

[0055] S2: Measure the electrical parameters of the transistor using the test structures in each test structure group, and obtain the set of transistor electrical parameter values corresponding to the test structure group;

[0056] Specifically, one electrical parameter is obtained for each test structure. Since there are multiple test structures in one test structure group, multiple electrical parameters can be obtained, that is, the set of transistor electrical parameter values corresponding to the test structure group.

[0057] S3: Evaluate the influence of the epitaxial process on the transistor performance according to the set of transistor electrical parameter values corresponding to the test structure group and the target epitaxial layer density range to be monitored.

[0058] Specifically, data processing is performed on the set of transistor electrical parameter values of each test structure group to obtain the processed transistor electrical parameter values; among them, data processing can refer to processing such as taking the average value. The average value of the multiple electrical parameters in the above-mentioned one test structure group is taken as the transistor electrical parameter value of the test structure group.

[0059] Using the set of multiple target epitaxial layer density values and the transistor electrical parameter values obtained through the corresponding test structure groups, a relationship curve between the target epitaxial layer density and the transistor electrical parameters is drawn to evaluate the window size of the epitaxial process.

[0060] In the embodiments of the present application, the density range of the target epitaxial layer to be monitored can be 5% - 85%, and

[0061] the electrical parameters of the transistor can be the saturation current Idsat, the saturation threshold voltage Vtsat, or the off-current Ioff.

[0062] Figure 6 This is an example graph of the relationship curve between the saturation current Idsat of the transistor and the target epitaxial layer density in the 28HKMG technology node in the embodiments of the present application. As Figure 6 shown, the monitored density range of the target epitaxial layer is 5% - 85%, and the electrical parameter for evaluating the transistor performance is the saturation current Idsat; transistor parameters: L = 0.03um, W = 0.1um, PMOS; in this relationship curve graph, when the target epitaxial layer density is in the range of 15% - 65%, the saturation current Idsat of the transistor fluctuates within the normal range (target value 80uA ± 5%), and this range can be determined as the window of the epitaxial process.

[0063] The method for monitoring the influence of the epitaxial process on the transistor performance disclosed in the embodiments of the present application, by using the test structure disclosed in the embodiments of the present application, can set several groups of test structures with different target epitaxial layer densities, and respectively measure the electrical parameters of the transistors at different target epitaxial layer densities, obtain the relationship curve between the electrical parameters of the transistors within the monitoring range of the target epitaxial layer density and the target epitaxial layer density, realize the monitoring of the epitaxial process, and obtain the window size of the stable epitaxial process for semiconductor device manufacturing.

[0064] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A test structure for monitoring the influence of an epitaxial process on transistor performance, characterized in that, The test structure includes a transistor test area and a density control area; The density control area is provided with a plurality of basic units having the same active region density, and can control the density of the target epitaxial layer in the test structure by setting different quantity ratios of P-type units and N-type units; The transistor test area is provided with a plurality of target basic units, and one transistor in each target basic unit is connected in parallel through a test circuit for measuring and evaluating the performance of the transistor; Wherein, each of the basic units includes at least one transistor, the P-type unit is a basic unit in which the transistor is a P-channel MOS transistor, and the N-type unit is a basic unit in which the transistor is an N-channel MOS transistor; the target basic unit refers to one of the P-type unit and the N-type unit, and the transistor of the target basic unit adopts a molecular epitaxy process; the active region density is the area ratio of the active region in the basic unit; the density of the target epitaxial layer is the area ratio of the epitaxial layer of the target basic unit in the circuit layout; A plurality of test structures with different target epitaxial layer densities are set, the electrical parameters of the transistors are measured at different target epitaxial layer densities, and the relationship between the electrical parameters of the transistors and the target epitaxial layer density within the monitoring range of the target epitaxial layer density is obtained.

2. The test structure for monitoring the influence of an epitaxial process on transistor performance according to claim 1, wherein The active region densities of all the basic units in the test structure are the same.

3. The test structure for monitoring the influence of an epitaxial process on transistor performance according to claim 1, wherein The number of target basic units in the transistor test area is 2 - 36.

4. The test structure for monitoring the influence of an epitaxial process on transistor performance according to claim 1, characterized in that, The test circuit includes a source terminal measurement signal line, a drain terminal measurement signal line, and a gate terminal measurement signal line; In the transistor test area, one transistor is taken from each target basic unit and connected in parallel: the source terminal of each transistor for parallel connection is connected to the source terminal measurement signal line, the drain terminal of each transistor for parallel connection is connected to the drain terminal measurement signal line, and the gate terminal of each transistor for parallel connection is connected to the gate terminal measurement signal line.

5. A method for monitoring the influence of an epitaxial process on the performance of a transistor, implemented by using the test structure according to any one of claims 1-4, characterized in that, Including the following steps: According to the density range of the target epitaxial layer to be monitored, a plurality of target epitaxial layer density values are taken, and a test structure group is set for each target epitaxial layer density value, so that the target epitaxial layer density of the test structures in the test structure group is the corresponding target epitaxial layer density value; wherein, each test structure group includes at least one test structure; The electrical parameters of the transistors are measured by using the test structures in each test structure group to obtain a set of transistor electrical parameter values corresponding to the test structure group; According to the set of transistor electrical parameter values corresponding to the test structure group and the density range of the target epitaxial layer to be monitored, the influence of the epitaxial process on the performance of the transistors is evaluated.

6. The method for monitoring the influence of an epitaxial process on transistor performance according to claim 5, characterized in that, In the density control areas of all the test structures, the active region densities of the basic units are the same.

7. The method for monitoring the influence of an epitaxial process on transistor performance according to claim 6, wherein The target epitaxial layer density value of the test structure is controlled by setting the quantity ratio of the P-type units and the N-type units in the density control area of the test structure.

8. The method for monitoring the influence of an epitaxial process on transistor performance according to claim 5, wherein The evaluating the influence of the epitaxial process on the performance of the transistors according to the set of transistor electrical parameter values corresponding to the test structure group and the density range of the target epitaxial layer to be monitored includes: Data processing is performed on the set of transistor electrical parameter values for each test structure group to obtain the processed transistor electrical parameter values; using multiple set target epitaxial layer density values and the processed transistor electrical parameter values obtained through the corresponding test structure groups, a relationship curve between the target epitaxial layer density and the transistor electrical parameters is plotted to evaluate the window size of the epitaxial process.

9. The method for monitoring the influence of an epitaxial process on transistor performance according to claim 5, wherein, The density range of the target epitaxial layer to be monitored is 5% - 85%.

10. The method for monitoring the influence of an epitaxial process on transistor performance according to claim 5, wherein The electrical parameters of the transistor are the saturation current, the saturation threshold voltage, or the off-current.

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