Batch density increase for improved progressive mesh compression

Abstract

The encoder includes a processor and a memory. The encoder may perform a method of progressive compression. In an example implementation, the method may include: determining a priority value associated with collapsing each of a plurality of edges. The method may further include: selecting a first edge from the plurality of edges; determining an adjusted priority value for edges near the selected first edge; after selecting the first edge, selecting a second edge from the remaining edges of the plurality of edges; and collapsing the selected edge such that vertex splitting information is generated based on the collapsing of the selected edge. In some implementations, the method may further include entropy encoding of the vertex splitting information.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a non-provisional application of U.S. Patent Application No. 15 / 951,963, filed on April 12, 2018, entitled “INCREASED DENSITY OF BATCHES FOR IMPROVED PROGRESSIVE MESH COMPRESSION”, a non-provisional application of U.S. Patent Application No. 15 / 951,944, filed on April 12, 2018, entitled “ENCODING COSTAWARE EDGE SELECTION FOR IMPROVED PROGRESSIVE MESH COMPRESSION”, and a non-provisional application of U.S. Patent Application No. 15 / 951,944, filed on April 12, 2018, entitled “VERTEX SPLIT CONNECTIVITY PREDICTION FOR IMPROVED PROGRESSIVE MESH COMPRESSION”.

[0013] This application is a continuation of and claims priority to U.S. non-provisional patent application No. 15 / 951,969, entitled "VERTEX SEPARATE CONNECTIVITY PREDICTION FOR IMPROVED PROGRESSIVE MESH COMPRESSION," the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present application relates generally to mesh compression, and more particularly to progressive mesh compression. Background Art

[0004] Progressive mesh compression (or progressive compression) is a hierarchical encoding of mesh geometry, where each level generates information about mesh connectivity, position, and other properties. Each subsequent level results in a coarser level of detail (LOD) of the model, and the encoding of the next LOD utilizes information already contained in the previous LOD. This is relevant for transmitting high-resolution models over the Internet, because the user on the receiving end (e.g., client, client device, or application) does not have to wait until the entire model is received from the server. The client can quickly display a lower resolution LOD of the model before receiving information associated with a higher resolution LOD at the client device. Summary of the invention

[0005] In one aspect, a method includes a computer-implemented method of progressive mesh compression. In an example implementation, the method may include: determining a priority value associated with a collapse of each of a plurality of edges, determining the priority value of the edge based on an associated error metric value of the edge, and selecting a first edge from the plurality of edges, selecting the first edge from the plurality of edges based on the first edge having a highest priority value among the plurality of edges. The method may further include: determining an adjusted priority value for edges adjacent to the selected first edge; after selecting the first edge, selecting a second edge from the remaining edges of the plurality of edges, selecting the second edge based on the second edge having a highest adjusted priority value, and collapsing the selected edge, such that vertex splitting information based on the collapse of the selected edge is generated. In some implementations, the method may further include entropy encoding of the vertex splitting information. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Example embodiments will become more fully understood from the detailed description given below and the accompanying drawings, wherein like elements are designated by like reference numerals, which are given by way of illustration only and thus do not limit example embodiments, and wherein:

[0007] Figure 1A Illustrate a portion of a geometric model (or an image of a geometric model) compressed using an edge collapse operation according to at least one example embodiment.

[0008] Figure 1B Illustrated is a portion of a geometric model (or an image of a geometric model) compressed using another edge collapse operation according to at least one example embodiment.

[0009] Figure 2A A full edge collapse operation is illustrated according to at least one example embodiment.

[0010] Figure 2B A half-edge collapse operation is illustrated according to at least one example embodiment.

[0011] Figure 3 An edge selection mechanism according to at least one example embodiment is illustrated.

[0012] Figure 4A A decimation mechanism for progressive compression is illustrated according to at least one example embodiment.

[0013] Figure 4B A denser decimation mechanism for improved progressive compression is illustrated according to at least one example embodiment.

[0014] Figure 5AA flow chart illustrating a method of improving batch density for improved progressive mesh compression according to at least one example embodiment.

[0015] Figure 5B Another flow chart illustrating a method of improving batch density for improved progressive mesh compression according to at least one example embodiment.

[0016] Figure 6 Examples of a computer device and a mobile computer device are illustrated according to at least one example embodiment.

[0017] It should be noted that these drawings are intended to illustrate the general characteristics of methods, structures, and / or materials utilized in certain example embodiments, and are intended to supplement the written description provided below. However, these drawings are not to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values ​​or properties encompassed by the example embodiments. The use of similar or identical reference numerals in the various drawings is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0018] For example, in one embodiment, the encoder may determine a priority value associated with the collapse of each of the plurality of edges. The encoder may determine the priority value of the edge based on the error metric value associated with the edge. The decoder selects the edge with the highest priority value (e.g., the first edge) and determines the adjusted priority values ​​of the remaining edges based on the adjustment of the priority value. The adjustment of the priority values ​​of the remaining edges may provide an opportunity to select an edge, which may increase the number of edges collapsed in one round (e.g., LOD). The encoder selects another edge with the highest adjusted priority value (e.g., the second edge). In some embodiments, the encoder may repeat the process until there are no more edges available for selection (or collapse). The selected edges are referred to as independent edge sets and are used for collapse. Collapse the selected edges so that vertex splitting information is generated. In some embodiments, the generated vertex splitting information is entropy encoded to achieve a better compression rate.

[0019] Figure 1A 1 illustrates a portion of a geometric model 100 that is compressed using an edge collapse operation according to at least one example embodiment. Figure 1A In the example, region 102 of geometric model 100 represents an area that can be compressed using improved progressive mesh compression. Figure 2AThe region 102 is compressed using a full edge collapse operation (or using a full edge collapse operator) as described in detail. During progressive mesh compression, the encoder may generate multiple LODs and associated vertex split records. The LODs and associated vertex split records may be generated by collapsing the input mesh with successive batches (e.g., one or more batches) of edge collapse operators until a very coarse mesh is generated or there are no more edges to collapse (e.g., the error metric may be too high for the LOD used for edge collapse).

[0020] Figure 1B 1 illustrates a portion of a geometric model 150 compressed using another edge collapse operation according to at least one example embodiment. Figure 1B In the example, region 152 of geometric model 150 represents an area that can be compressed using improved progressive mesh compression. Figure 2B The region 152 is compressed using a half-edge collapse operation (or using a half-edge collapse operator) as described in detail.

[0021] Figure 2A A full edge collapse operation 200 is illustrated according to at least one example embodiment.

[0022] exist Figure 2A , the edge 206 connecting the vertices 202, 210 can be collapsed via a full edge collapse operation (e.g., using a full edge collapse operator). In such a full edge collapse operation, the two vertices 202, 210 are merged into one vertex (e.g., a merged vertex, a split vertex, etc.), and a new vertex 218 is generated. The position of the new vertex 218 can be determined based on, for example, minimizing an error associated with the collapse of the edge 206 (e.g., minimizing an associated local error).

[0023] Full edge collapse operation requires a higher number of bits (e.g., when compared with Figure 2B2 (when compared to the half-edge collapse operation described above) to encode two residuals between the merged vertex 218 and its two ancestors 202, 210 so that the decoder can appropriately reverse the full edge collapse operation during decoding. During the full edge collapse operation, as edge 206 is collapsed, edges 204 and 208 collapse into a new edge (e.g., edge 216), and edges 222 and 224 collapse into another new edge (e.g., edge 226). Vertices 212 and 214 illustrate the merging of vertices 202 and 204 during the transition of the full edge operation. The collapsing of edges (e.g., using a full edge collapse operation) and the merging of vertices as described above can generate an LOD (e.g., a lower LOD) and an associated vertex split record. The decoder uses the vertex split record to decode (e.g., reconstruct) vertices and / or edges that were encoded (e.g., collapsed, merged, etc.) during the full edge collapse operation.

[0024] Figure 2B A half-edge collapse operation 250 is illustrated according to at least one example embodiment.

[0025] exist Figure 2B , the edge 206 connecting the vertices 202, 210 can be collapsed via a half-edge collapse operation (e.g., using a half-edge collapse operator). In such a half-edge collapse operation, one of the two vertices (e.g., vertex 210) can be merged into the other vertex (e.g., vertex 202), and data is generated so that the decoder can regenerate the vertex or edge during decoding.

[0026] The half-edge collapse operation requires a smaller number of bits (e.g., when compared to the above reference Figure 2A 202) because only one residual associated with the vertex being merged (e.g., vertex 210) must be encoded to reverse the half-edge collapse operation during decoding. During the half-edge collapse operation, as vertex 210 is merged into vertex 202, edge 208 is collapsed into edge 204, and edge 224 is collapsed into edge 222. Vertex 234 illustrates the merge of vertex 210 into vertex 202 during the transition of the half-edge collapse operation. As described above, collapsing or merging edges and / or merging vertices using a half-edge collapse operation can generate an LOD (e.g., a lower LOD) and associated vertex split records. The decoder uses the vertex split records to decode (e.g., reconstruct) the vertices and / or edges that were encoded (e.g., collapsed, merged, etc.) during the half-edge collapse operation. Although a half-edge collapse operation may require fewer bits (eg, when compared to a full-edge collapse operation) to represent the information needed for decoding, the distortion rate may be higher (eg, more low-distortion LCD).

[0027] Figure 3An edge selection mechanism 300 is illustrated according to at least one example embodiment.

[0028] A series of levels of detail (LODs) may be created (or generated) during progressive compression by decimating the input mesh with successive batches of edges collapsed (e.g., using an edge collapse operator) until a very coarse mesh is generated (or no more edges are available for collapse because the edge collapse error metric value may be too high for the LOD). A batch of edge collapse may include collapsing a subset of the edges of the current mesh.

[0029] During progressive mesh compression, each edge collapse can be associated with an error (e.g., an error metric value) when the edge is collapsed. The error / error metric value reflects (e.g., represents) the impact of the edge collapse on the quality of the mesh. In other words, the error metric value associated with the edge collapse indicates how the quality of the mesh may be affected (e.g., negatively affected) by the edge collapse. Therefore, in order to avoid collapsing edges that are too expensive (e.g., a major impact on the quality of the mesh, etc.), the edges can be sorted (e.g., prioritized) based on the associated error metric values ​​of the edges before being selected for collapse (or before being added to the independent edge set). In some embodiments, for example, the error metric value can be an initial error metric value (e.g., a quadratic error metric) and / or can depend on the application using the mesh. For example, the edges can be sorted based on the error metric values ​​of the edges, and the edges with the lowest associated error metric values ​​are ranked first. In an example embodiment, when the edges of the input mesh are selected, the unblocked edges are added to form (or create) an independent edge set (e.g., a first independent edge set) and the edges near the edges that may be blocked are not considered for collapse in the current round. Edges may continue to be added to the independent edge set until all edges are blocked or the error metric is above a corresponding threshold.

[0030] For example, in some embodiments, Figure 3 As shown in , edge 302 can be collapsed without interference from other edges. However, edge 304 near edge 302 may be blocked from collapse by edge 302. Edge 304 blocked (e.g., blocked from collapse) by another edge (e.g., edge 302) is generally referred to as a blocked edge, and cannot be collapsed in the current round (e.g., when generating the current LOD). That is, edge 304 cannot be collapsed in the same round as edge 302. However, one or more edges 304 can be collapsed during edge collapse in a later round when generating another LOD.

[0031] Figure 4A An extraction mechanism 400 is illustrated according to at least one example embodiment.

[0032] like Figure 4A As shown in FIG. 4 , except for edge 402 (which may be similar to Figure 3 302), edge 422 can be collapsed without interference from other edges (e.g., edges 402, 412, 432). However, edge 432 near edge 422 can be blocked from collapse by edge 422. Edge 432 blocked from collapse by another edge (e.g., edge 422) can be referred to as a blocked edge and cannot be collapsed in the current round (e.g., when generating the current LOD). That is, edge 432 cannot be collapsed in the same round as edge 422. However, one or more of edges 432 can be collapsed during edge collapse in a later round to generate another LOD.

[0033] In one embodiment, for example, a full edge collapse operation (eg, as described above with reference to Figure 2A Detailed description) or half edge collapse operation (e.g., referenced above Figure 2B In some embodiments, a midpoint collapse operation may be used to collapse edges 402 and 422. In another embodiment, for example, a midpoint collapse operation may be used to collapse edges 402 and 422. In some other embodiments, one type of edge collapse operation (e.g., a half-edge or full-edge collapse operation) may be used to generate one LOD and / or another type of edge collapse operation (e.g., a full-edge or half-edge collapse operation) may be used to generate subsequent LODs to achieve a balance between quality (e.g., distortion) and cost (e.g., bit rate or bits per vertex). In some embodiments, a midpoint collapse may be used to collapse edges.

[0034] As a batch of edges is collapsed, a lower LOD (e.g., a lower resolution or coarser LOD) is generated along with additional information (e.g., vertex splitting information) that allows the decoder to recover a previous LOD (e.g., a higher resolution LOD). In some embodiments, the information generated during the generation of the LOD may include, for example, a header with initial information for the decoder (e.g., indicating whether a full edge or half edge operation is performed); information about how to split the encoded vertices into edges at the decoder; information about how to connect a vertex (e.g., a split vertex) to its surrounding vertices (neighbors of the split vertex); information necessary to recover the position of the split vertex; and / or texture coordinates or any other optional attributes. However, because the edge order provided by the error metric may not provide good (or efficient) packing of edges, the number of edges that can be collapsed in one pass (e.g., the density of edges) may vary. Therefore, it is desirable to have denser edge packing (or increase packing) so that more edges can be collapsed per pass (e.g., for each LOD) to achieve better compression rates.

[0035] Figure 4B A denser decimation mechanism 450 for improved progressive compression is illustrated in accordance with at least one example embodiment.

[0036] The present disclosure discloses a mechanism for increasing batch density, for example, increasing the number of edges collapsed in one round (e.g., the number of edges added to independent edge sets for collapse, the density of edges, etc.), which may affect the encoding of information associated with progressive mesh compression (e.g., vertex splitting information, etc.).

[0037] For example, in some embodiments, better compression of information related to the encoding of vertices (e.g., vertices that need to be split into edges during decoding) can be achieved. Better compression of information is possible because entropy coding can be improved due to the dense packing of edges. In some other embodiments, the increase in the number of edges collapsed (or extracted) in each round can allow more symbols to be encoded in each round, which can lead to better compression rates (e.g., encoding of information related to how a vertex (e.g., a split vertex) is connected to its surrounding vertices (neighbors of the split vertex)). In some more embodiments, information necessary to recover the position and / or texture coordinates or any other optional attributes of the split vertex can be better compressed. Therefore, based on the above, the entire progressive mesh compression process may require fewer rounds because more edges can be collapsed per round, and therefore fewer headers that need to be encoded are required.

[0038] For example, Figure 4B As shown in , edges 402, 452, 454, and 456 can be collapsed using adjusted priority values ​​to determine independent edge sets for collapse. In contrast, only edges 402 and 422 are eligible for collapse strictly based on priority values. This is possible because the proposed mechanism can slightly change the order of edges (e.g., priority values) so that edges that are closer to other edges that have been picked (e.g., selected) are advantageous. However, in scenarios where two edges have the same error metric value (e.g., based on comparisons in a priority queue), edges that block fewer other edges that have not yet been blocked are advantageous or selected for collapse. This approach tends to pack closer edges together and is more likely to obtain denser packing.

[0039] Figure 5A Flowchart 500 illustrates a method of increasing batch density for improved progressive mesh compression. For example, in one embodiment, the method may be performed by an encoder and may be based on increasing the number of edges collapsed in a pass to improve progressive mesh compression.

[0040] At block 510, the encoder may determine a priority value associated with a collapse of each edge in the plurality of edges, the priority value of the edge being determined based on an associated error metric value of the edge. For example, in one embodiment, the encoder may determine a priority value associated with a collapse of each edge in the plurality of edges (e.g., Figure 4B ) is shown in . The priority value of the edge can be determined, for example, based on a priority queue from the error metric value associated with the collapse of the edge. Once the encoder determines the error metric value of the edge, the encoder can, for example, use a priority queue to sort the edges, with the edge with the lowest error metric value ranked first. In other words, the encoder can sort the edges in order of increasing error metric value, with the edge with the lowest error metric value being at the first position in the order. In some embodiments, the lowest error metric value can correspond to the highest priority value.

[0041] At block 520, the encoder may select a first edge from the plurality of edges, the first edge being selected from the plurality of edges based on the first edge having a highest priority value among the plurality of edges. For example, in one embodiment, the encoder may select the first edge (e.g., edge 402) based on edge 402 having a highest priority value. In other words, edge 402 may be selected because edge 402 has a lowest error metric value associated with collapse of edge 402.

[0042] At block 530, the encoder may determine adjusted priority values ​​for edges near the selected first edge. For example, in one embodiment, the encoder may determine adjusted priority values ​​for edges near edge 402 after selecting a first edge (e.g., edge 402). In some embodiments, two edges may be considered to be near each other if they have one or more edges blocked in common or are in the same region. In some embodiments, the encoder may determine adjusted priority values ​​for edges (e.g., edges 452, 454, and / or 456) near the first selected edge (e.g., edge 402). For example, the adjusted priority values ​​for the edges may be determined based on the allowed variance of the priority values ​​associated with the edges, the actual number of edges blocked by the edges, and the maximum number of edges that may be blocked by the edges.

[0043] In some embodiments, the adjusted priority value can be determined by improving the priority values ​​associated with edges that are near (e.g., neighbors) the already selected edge. The adjustment to the priority value of an edge may be as high as X%. The greatest improvement can be achieved if a given edge does not block new edges. For example, the adjusted priority value (D') of edge e can be determined as follows: e ), where D eis the priority value associated with edge e (also referred to as the initial or original priority value), K is the maximum number of edges that edge e can block, and k is the actual number of edges that will be blocked if edge e is selected. For example, the adjusted priority value of edge e can be determined as follows:

[0044] D' e =D e *(1-X%(1-k / K))

[0045] In some implementations, the adjusted priority value provides an opportunity to determine whether there are any other edges that may be considered better candidates for collapsing to achieve denser edge packing in the current round.

[0046] At block 540, the encoder may select a second edge from the remaining edges of the plurality of edges after selecting the first edge, selecting the second edge based on the second edge having the highest adjusted priority value. For example, in one embodiment, the encoder may select edge 452 as the next edge for collapse. Edge 452 may be selected based on edge 452 having the highest adjusted priority value. In some embodiments, second edge 452 may be part of an independent edge set (along with edge 402) because second edge 452 does not block collapse of the first edge (e.g., edge 402).

[0047] At block 550, the encoder may repeat the determination of the adjusted priority values ​​for the remaining edges and the selection of edges for determining the independent edge set for collapse based on the newly determined adjusted priority values. For example, in one embodiment, the encoder may repeat the process of determining the adjusted priority values ​​(the adjusted priority values ​​determined from the priority values ​​determined at block 510) and selecting edges based on the determined adjusted priority values. That is, when selecting edge 452, the encoder may determine the adjusted priority values ​​of the edges near edge 452, and select edge 454 based on edge 454 having the highest adjusted priority value. After selecting edge 454, the encoder may determine the adjusted priority values ​​of the edges near edge 454, and select edge 456 based on edge 456 having the highest adjusted priority value, and so on. The encoder may continue this process until no more edges are available. The selected edges create or form an independent edge set that the encoder may use for collapse.

[0048] At box 560, the encoder can collapse the independent edge set determined for collapse and generate vertex splitting information based on the collapse of the independent edge set. In one embodiment, for example, the edges 402, 452, 454, 456, etc. included in the independent edge set can be collapsed to generate vertex splitting information (or the encoder can collapse the independent edge set determined for collapse so that the vertex splitting information is generated). In some embodiments, the vertex splitting information can be entropy encoded to achieve better compression rate. In some other embodiments, the vertex splitting information can be sent from the encoder to the decoder in response to a message from the decoder. The decoder uses the vertex splitting information to deconstruct the mesh. In other words, in response to a request from the decoder, the vertex splitting information can be entropy encoded, stored, and sent to the decoder.

[0049] Figure 5B Flowchart 570 illustrates a method of increasing batch density for improved progressive mesh compression. For example, in one embodiment, the method may be performed by an encoder and may be based on increasing the number of edges collapsed in a pass to improve progressive mesh compression.

[0050] The operations at blocks 572, 574, 576, and 578 may be similar to ( Figure 5A The operations at boxes 510, 520, 530 and 540 of FIG.

[0051] At box 580, the encoder can collapse the selected edges so that vertex splitting information is generated based on the collapse of the selected edges. In one embodiment, for example, the selected edges 402 and 452 (or 402, 452, 454, 456, etc.) can be collapsed to generate vertex splitting information. In some embodiments, the vertex splitting information can be entropy encoded to achieve better compression rate. In some other embodiments, the vertex splitting information can be sent from the encoder to the decoder in response to a message from the decoder. The decoder uses the vertex splitting information to deconstruct the mesh. In other words, the vertex splitting information can be entropy encoded, stored and sent to the decoder in response to a request from the decoder.

[0052] In one aspect, a method includes a computer-implemented method of progressive mesh compression. In an example implementation, the method may include: determining a priority value associated with a collapse of each of a plurality of edges, determining the priority value of the edge based on an associated error metric value of the edge, and selecting a first edge from the plurality of edges, selecting the first edge from the plurality of edges based on the first edge having a highest priority value among the plurality of edges. The method may further include: determining an adjusted priority value for edges near the selected first edge; after selecting the first edge, selecting a second edge from the remaining edges of the plurality of edges, selecting the second edge based on the second edge having the highest adjusted priority value; repeating the determination of the adjusted priority values ​​for the remaining edges and repeating the selection of edges for determining an independent edge set for collapse based on the newly determined adjusted priority values; and collapsing the independent edge set determined for collapse and generating vertex splitting information based on the collapse of the independent edge set. In some implementations, the method may further include entropy encoding the vertex splitting information.

[0053] In another aspect, an encoder includes a processor and a memory. The memory may include instructions configured to cause the processor to determine a priority value associated with the collapse of each of a plurality of edges, determine the priority value of the edge based on an associated error metric value of the edge; and select a first edge from the plurality of edges, selecting the first edge from the plurality of edges based on the first edge having the highest priority value among the plurality of edges. The memory may further include instructions to determine an adjusted priority value of an edge near the selected first edge; select a second edge from the remaining edges of the plurality of edges after selecting the first edge, selecting the second edge based on the second edge having the highest adjusted priority value; repeat the determination of the adjusted priority values ​​of the remaining edges and repeat the selection of edges for determining the independent edge set for collapse based on the newly determined adjusted priority values; and collapse the independent edge set determined for collapse and generate vertex splitting information based on the collapse of the independent edge set. In some embodiments, the method may further include entropy encoding the vertex splitting information.

[0054] In yet another additional aspect, a non-transitory computer-readable storage medium having computer executable program code stored thereon, when the computer executable program code is executed on a computer system, the computer executable program code causes the computer system to perform a method of progressive mesh compression. The method may include: determining a priority value associated with the collapse of each edge of a plurality of edges, determining the priority value of the edge based on the error metric value associated with the edge; and selecting a first edge from the plurality of edges, selecting the first edge from the plurality of edges based on the first edge having the highest priority value among the plurality of edges. The computer-readable storage medium may further include code for determining an adjusted priority value of an edge near the selected first edge; after selecting the first edge, selecting a second edge from the remaining edges of the plurality of edges, selecting the second edge based on the second edge having the highest adjusted priority value; repeating the determination of the adjusted priority values ​​of the remaining edges and repeating the selection of edges for determining the independent edge set for collapse based on the newly determined adjusted priority values; and collapsing the independent edge set determined for collapse and generating vertex splitting information based on the collapse of the independent edge set. In some embodiments, the method may further include entropy encoding the vertex splitting information.

[0055] Therefore, the encoder increases the batch density to improve progressive mesh compression and / or achieve better compression ratios.

[0056] Figure 6 Examples of computer device 600 and mobile computer device 650 that can be used with the techniques described herein are shown. Computing device 600 is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Computing device 650 is intended to represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, and other similar computing devices. The components shown here, their connections and relationships, and their functions are intended to be exemplary only and are not intended to limit the implementation of the inventions described and / or claimed in this document.

[0057] The computing device 600 includes a processor 602, a memory 604, a storage device 606, a high-speed interface 608 connected to the memory 604 and a high-speed expansion port 610, and a low-speed interface 612 connected to a low-speed expansion port 614 and the storage device 606. Each of the components 602, 604, 606, 608, 610, and 612 is interconnected using various buses and can be mounted on a common motherboard or otherwise installed as appropriate. The processor 602 can process instructions for execution within the computing device 600, including instructions stored in the memory 604 or on the storage device 606 to display graphical information for a GUI on an external input or output device such as a display 616 coupled to the high-speed interface 608. In other embodiments, multiple processors and / or multiple buses can be used together with multiple memories and multiple types of memories as appropriate. In addition, multiple computing devices 600 can be connected, each of which provides a portion of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system).

[0058] The memory 604 stores information within the computing device 600. In one embodiment, the memory 604 is one or more volatile memory units. In another embodiment, the memory 604 is one or more non-volatile memory units. The memory 604 may also be another form of computer-readable medium, such as a magnetic disk or optical disk.

[0059] Storage device 606 can provide mass storage for computing device 600. In one embodiment, storage device 606 can be or include computer readable media, such as a floppy disk device, a hard disk device, an optical disk device or a tape device, a flash memory or other similar solid-state storage device or array of devices, including devices in a storage area network or other configurations. A computer program product can be tangibly embodied in an information carrier. A computer program product can also include instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer readable medium or a machine readable medium, such as a memory 604, a storage device 606, or a memory on a processor 602.

[0060] The high-speed interface 608 manages bandwidth-intensive operations of the computing device 600, while the low-speed interface 612 manages less bandwidth-intensive operations. This allocation of functions is exemplary only. In one embodiment, the high-speed interface 608 is coupled to the memory 604, the display 616 (e.g., through a graphics processor or accelerator), and is coupled to a high-speed expansion port 610, which can accept various expansion cards (not shown). In this embodiment, the low-speed interface 612 is coupled to the storage device 606 and the low-speed expansion port 614. The low-speed expansion port, which can include various communication ports (e.g., USB, Bluetooth, Ethernet, wireless Ethernet), can be coupled to one or more input or output devices, such as a keyboard, a pointing device, a scanner, or a networking device such as a switch or a router, for example, through a network adapter.

[0061] As shown in the figure, computing device 600 can be implemented in many different forms. For example, it can be implemented as a standard server 620, or multiple times in a group of such servers. It can also be implemented as part of a rack server system 624. In addition, it can be implemented in a personal computer such as a laptop computer 622. Alternatively, components from computing device 600 can be combined with other components in a mobile device (not shown) such as device 650. Each of such devices can contain one or more of computing devices 600, 650, and the entire system can be composed of multiple computing devices 600, 650 that communicate with each other.

[0062] The computing device 650 includes a processor 652, a memory 664, an input or output device such as a display 654, a communication interface 666, and a transceiver 668, among other components. The device 650 may also be provided with a storage device, such as a microdrive or other device, to provide additional storage. Each of the components 650, 652, 654, 654, 666, and 668 are interconnected using various buses, and several components may be mounted on a common motherboard or otherwise as appropriate.

[0063] The processor 652 can execute instructions within the computing device 650, including instructions stored in the memory 664. The processor can be implemented as a chipset of chips that include separate and multiple analog and digital processors. The processor can, for example, provide coordination for other components of the device 650, such as control of a user interface, applications executed by the device 650, and wireless communications performed by the device 650.

[0064] The processor 652 can communicate with the user through a control interface 658 and a display interface 656 coupled to the display 654. The display 654 can be, for example, a TFT LCD (thin film transistor liquid crystal display) or an OLED (organic light emitting diode) display or other appropriate display technology. The display interface 656 may include appropriate circuits for driving the display 654 to present graphics and other information to the user. The control interface 658 may receive commands from the user and convert them for submission to the processor 652. In addition, an external interface 662 in communication with the processor 652 may be provided to enable near-area communication of the device 650 with other devices. The external interface 662 may be provided, for example, for wired communication in some embodiments, or for wireless communication in other embodiments, and multiple interfaces may also be used.

[0065] The memory 664 stores information within the computing device 650. The memory 664 may be implemented as one or more of one or more computer-readable media, one or more volatile memory units, or one or more non-volatile memory units. An expansion memory 674 may also be provided and connected to the device 650 via an expansion interface 672, which may include, for example, a SIMM (single in-line memory module) card interface. Such an expansion memory 674 may provide additional storage space for the device 650, or may also store applications or other information for the device 650. Specifically, the expansion memory 674 may include instructions for executing or supplementing the above-mentioned processes, and may also include security information. Therefore, for example, the expansion memory 674 may be provided as a security module for the device 650, and may be programmed with instructions that allow the secure use of the device 650. In addition, security applications and additional information may be provided via a SIMM card, such as placing identification information on a SIMM card in an unbreakable manner.

[0066] The memory may include, for example, flash memory and / or NVRAM memory, as discussed below. In one embodiment, a computer program product is tangibly embodied in an information carrier. The computer program product includes instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer or machine readable medium, such as memory 664, expansion memory 674, or memory on processor 652, which may be received, for example, via transceiver 668 or external interface 662.

[0067] Device 650 can communicate wirelessly via communication interface 666, which may include digital signal processing circuitry as necessary. Communication interface 666 may provide for communication under various modes or protocols, such as GSM voice calls, SMS, EMS or MMS messaging, CDMA, TDMA, PDC, WCDMA, CDMA2000 or GPRS. Such communication may occur, for example, via radio frequency transceiver 668. In addition, short-range communication may occur, such as using Bluetooth, WiFi or other such transceivers (not shown). In addition, GPS (global positioning system) receiver module 670 may provide additional navigation and location-related wireless data to device 650, which may be used by applications running on device 650 as appropriate.

[0068] Device 650 may also communicate audibly using audio codec 660, which may receive spoken information from a user and convert it into usable digital information. Audio codec 660 may likewise generate audible sounds for the user, such as through a speaker—for example, in a headset of device 650. Such sounds may include sounds from voice phone calls, may include recorded sounds (e.g., voice messages, music files, etc.), and may also include sounds generated by applications operating on device 650.

[0069] As shown in the figure, computing device 650 can be implemented in many different forms. For example, it can be implemented as a cellular phone 680. It can also be implemented as part of a smart phone 682, a personal digital assistant, or other similar mobile device.

[0070] Various embodiments of the systems and techniques described herein may be implemented using digital electronic circuits, integrated circuits, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include embodiments in one or more computer programs executable and / or interpretable on a programmable system, the programmable system including at least one programmable processor, which may be dedicated or general purpose, coupled to receive data and instructions from a storage system, at least one input device, and at least one output device, and to send data and instructions to a storage system, at least one input device, and at least one output device. Various embodiments of the systems and techniques described herein may be implemented as circuits, modules, blocks, or systems that can be combined in software and hardware and / or are generally referred to herein as circuits, modules, blocks, or systems that can be combined in software and hardware. For example, a module may include functions, behaviors, or computer program instructions executed on a processor (e.g., a processor formed on a silicon substrate, a GaAs substrate, etc.) or some other programmable data processing device.

[0071] Some of the above example embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the operations as sequential processes, many operations may be performed in parallel, concurrently, or simultaneously. In addition, the order of the operations may be rearranged. These processes may be terminated when their operations are completed, but may also have additional steps not included in the figure. These processes may correspond to methods, functions, programs, subroutines, subprograms, etc.

[0072] The methods discussed above, some of which are illustrated by flowcharts, may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, the program code or code segments for performing the necessary tasks may be stored in a machine or computer readable medium such as a storage medium. A processor may perform the necessary tasks.

[0073] The specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. Example embodiments are embodied in many alternate forms, however, and should not be construed as limited to only the embodiments set forth herein.

[0074] It should be understood that, although the terms first, second, etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element can be called the second element, and similarly, the second element can be called the first element without departing from the scope of the exemplary embodiment. As used herein, the terms and / or include any and all combinations of one or more of the related enumerated items.

[0075] It should be understood that when an element is referred to as being connected or coupled to another element, it may be directly connected or coupled to the other element or there may be intervening elements. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements. Other words used to describe the relationship between elements (e.g., between versus directly between, adjacent versus directly adjacent, etc.) should be interpreted in a similar manner.

[0076] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the exemplary embodiments. As used herein, unless the context clearly indicates otherwise, the singular forms a, an and the are also intended to include plural forms. It should be further understood that the terms contain, include, include and / or include when used in this article, specifying the features, integers, steps, operations, elements and / or components of the statement, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups.

[0077] It should also be noted that, in some alternative implementations, the functions or behaviors indicated may not occur in the order indicated in the figures. For example, depending on the functionality or behaviors involved, two figures shown in succession may actually be executed concurrently or may sometimes be executed in reverse order.

[0078] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It should be further understood that, unless explicitly defined as such herein, terms (e.g., those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0079] The various parts of the above-mentioned example embodiments and the corresponding detailed description are presented in terms of software or algorithms and symbolic representations of operations on data bits in a computer memory. These descriptions and representations are descriptions and representations used by those of ordinary skill in the art to effectively convey the essence of their work to other persons of ordinary skill in the art. An algorithm (when the term is used here, and when it is used generally) is considered to be a self-consistent sequence of steps leading to a desired result. These steps are those steps that require physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of optical, electrical or magnetic signals that can be stored, transferred, combined, compared and otherwise manipulated. Sometimes, mainly due to common reasons, it has proven to be convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0080] In the above illustrative embodiments, references to behaviors and symbolic representations of operations (e.g., in the form of flowcharts) that can be implemented as program modules or functional processes include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types and can be described and / or implemented using existing hardware at existing structural elements. Such existing hardware may include one or more central processing units (CPUs), digital signal processors (DSPs), application specific integrated circuits, field programmable gate arrays (FPGAs), computers, etc.

[0081] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specifically stated or as is apparent from the discussion, terms such as processing or computing or calculating or determining display refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical, electronic quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage, transmission or display devices.

[0082] Note also that the software-implemented aspects of the example embodiments are typically encoded on some form of non-transitory program storage medium or implemented on some type of transmission medium. The program storage medium may be magnetic (e.g., a floppy disk or hard drive) or optical (e.g., a compact disk read-only memory or CD ROM), and may be read-only or random access. Similarly, the transmission medium may be a twisted pair, a coaxial cable, an optical fiber, or some other suitable transmission medium known in the art. The example embodiments are not limited by these aspects of any given embodiment.

[0083] Finally, it should also be noted that although the appended claims set out particular combinations of features described herein, the scope of the present disclosure is not limited to the particular combinations thereafter claimed, but instead extends to include any combination of features or embodiments disclosed herein, regardless of whether the particular combination has been specifically enumerated in the appended claims at this time.

[0084] Although the example embodiments may include various modifications and alternative forms, their implementations are shown by way of example in the drawings and will be described in detail herein. However, it should be understood that there is no intention to limit the example embodiments to the specific forms disclosed, but on the contrary, the example embodiments will cover all modifications, equivalents, and alternative forms falling within the scope of the claims. Throughout the description of the drawings, the same reference numerals refer to the same elements.

Claims

1. A computer-implemented progressive grid compression method comprising: determining, by an encoder, a priority value associated with collapse of each edge of a plurality of edges, the priority value of an edge being determined based on an associated error metric value of the edge; selecting, by the encoder, a first edge from the plurality of edges, the first edge being selected from the plurality of edges based on the first edge having a highest priority value among the plurality of edges; determining, by the encoder, adjusted priority values ​​for edges proximate to the selected first edge; selecting, by the encoder after selecting the first edge, a second edge from remaining edges of the plurality of edges, the second edge being selected based on the second edge having a highest adjusted priority value, wherein selecting the second edge comprises adding the second edge to the independent edge set including edges when collapse of the second edge is not blocked by collapse of other edges already included in the independent edge set, and wherein the blocked edge interferes with the collapse of edges such that the blocked edge cannot be collapsed in the same round as the edge; and The independent edge sets are collapsed by the encoder such that vertex splitting information is generated based on the collapse of the independent edge sets.

2. The method according to claim 1, further comprising: The vertex splitting information is entropy encoded by the encoder.

3. The method according to claim 1, further comprising: The generated vertex splitting information is sent from the encoder to the decoder in response to the message received from the decoder.

4. The method according to claim 1, wherein: The adjusted priority value associated with the edge is determined based on an allowed variance of the priority value associated with the edge, an actual number of edges blocked by the edge, and a maximum number of edges that the edge can block.

5. The method according to claim 1, wherein: The collapse of the edge further comprises: Collapse the edge connecting two vertices using a full-edge or half-edge collapse operation.

6. The method according to any one of claims 1 to 5, wherein: The highest priority value corresponds to the lowest error metric value.

7. An encoder comprising: processor; and A memory comprising instructions configured to cause the processor to execute: determining a priority value associated with a collapse of each edge of a plurality of edges, the priority value of an edge being determined based on an associated error metric value of the edge; selecting a first edge from the plurality of edges, the first edge being selected from the plurality of edges based on the first edge having a highest priority value among the plurality of edges; determining adjusted priority values ​​for edges adjacent to the selected first edge; and, after selecting the first edge, selecting a second edge from the remaining edges of the plurality of edges, the second edge being selected based on the second edge having a highest adjusted priority value, wherein, to select the second edge, the instructions are configured to cause the processor to: add the second edge to the independent edge set including edges when collapse of the second edge is not blocked by collapse of other edges already included in the independent edge set, and wherein the blocked edge interferes with collapse of edges such that the blocked edge cannot be collapsed in the same round as the edge; and The independent edge set is collapsed so that vertex splitting information is generated based on the collapse of the independent edge set.

8. The encoder of claim 7, further comprising instructions for causing the processor to: The vertex splitting information is entropy encoded.

9. The encoder of claim 7, further comprising instructions for causing the processor to: In response to a message received from a decoder, the generated vertex splitting information is sent to the decoder.

10. The encoder according to claim 7, wherein: The adjusted priority value associated with the edge is determined based on an allowed variance of the priority value associated with the edge, an actual number of edges blocked by the edge, and a maximum number of edges that the edge can block.

11. The encoder according to any one of claims 7 to 10, wherein: The highest priority value corresponds to the lowest error metric value.

12. A non-transitory computer readable storage medium having computer executable program code stored thereon, the computer executable program code, when executed on a computer system, causing the computer system to perform a method of progressive mesh compression, the method comprising: determining, by an encoder, a priority value associated with collapse of each edge of a plurality of edges, the priority value of an edge being determined based on an associated error metric value of the edge; selecting, by the encoder, a first edge from the plurality of edges, the first edge being selected from the plurality of edges based on the first edge having a highest priority value among the plurality of edges; determining, by the encoder, adjusted priority values ​​for edges proximate to the selected first edge; selecting, by the encoder after selecting the first edge, a second edge from remaining edges of the plurality of edges, the second edge being selected based on the second edge having a highest adjusted priority value, wherein selecting the second edge comprises adding the second edge to the independent edge set including edges when collapse of the second edge is not blocked by collapse of other edges already included in the independent edge set, and wherein the blocked edge interferes with the collapse of edges such that the blocked edge cannot be collapsed in the same round as the edge; and The independent edge sets are collapsed by the encoder such that vertex splitting information is generated based on the collapse of the independent edge sets.

13. The computer-readable storage medium of claim 12, wherein the method further comprises: The vertex splitting information is entropy encoded by the encoder.

14. The computer-readable storage medium of claim 12, wherein the method further comprises: The generated vertex splitting information is sent from the encoder to the decoder in response to the message received from the decoder.

15. The computer-readable storage medium of claim 12, wherein: The adjusted priority value associated with the edge is determined based on an allowed variance of the priority value associated with the edge, an actual number of edges blocked by the edge, and a maximum number of edges that the edge can block.

16. The computer-readable storage medium of claim 12, wherein the method further comprises: Collapse the edge connecting two vertices using a full-edge or half-edge collapse operation.

17. The computer-readable storage medium according to any one of claims 12 to 16, wherein: The highest priority value corresponds to the lowest error metric value.

Images