Non-volatile memory device, method of operating the same, and memory system

Abstract

A non-volatile memory device, an operating method thereof, and a memory system are provided. The non-volatile memory device includes: a memory cell array including a plurality of memory cells configured to be respectively programmed as one of a plurality of states; a page buffer circuit including a plurality of page buffers configured to respectively store received data as state data, the state data indicating a target state of a corresponding memory cell of the plurality of memory cells, the page buffer circuit configured to perform a state data reordering operation of changing a first state data order to a second state data order during a programming operation performed on a selected memory cell of the plurality of memory cells; and a reordering control circuit configured to control the page buffer circuit to perform the state data reordering operation concurrently with the programming operation.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0040340, filed on April 5, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to memory devices, and more specifically, to non-volatile memory devices configured to store multi-bit data, methods of operating non-volatile memory devices, and / or memory systems including non-volatile memory devices. Background Technology

[0003] Memory devices used for storing data can be classified into volatile memory devices and non-volatile memory devices. Flash memory devices (an example of non-volatile memory devices) can be used in storage devices such as solid-state drives (SSDs), universal flash memory (UFS), and embedded multimedia cards (eMMC). In recent years, technologies for realizing high-capacity, low-power non-volatile memory devices that enable high-speed input / output (I / O) operations have been actively researched for the installation of non-volatile memory devices in mobile devices such as SSDs or smartphones. Summary of the Invention

[0004] The inventive concept provides a non-volatile memory device that can improve programming performance, a method for operating a non-volatile memory device, and / or a memory system including a non-volatile memory device.

[0005] According to one aspect of the inventive concept, a non-volatile memory device is provided, the non-volatile memory device comprising: a memory cell array including a plurality of memory cells, each memory cell being configured to be programmed into one of a plurality of states; a page buffer circuit including a plurality of page buffers, each page buffer being configured to store received data as state data, the state data indicating a target state of a corresponding memory cell among the plurality of memory cells, the page buffer circuit being configured to: perform a state data reordering operation during a programming operation on a selected memory cell among the plurality of memory cells, changing a first state data ordering to a second state data ordering, the first state data ordering indicating a reference mapping between a plurality of data values ​​of the state data and the plurality of states; and a reordering control circuit configured to control the page buffer circuit to perform the state data reordering operation simultaneously with the programming operation.

[0006] According to another aspect of the inventive concept, a method for operating a non-volatile memory device is provided. The method includes: receiving data; storing the data as state data in a plurality of page buffers connected to a memory cell array; programming a plurality of memory cells in the memory cell array based on the state data stored in the plurality of page buffers; and while programming the plurality of memory cells, changing the data value of the state data stored in each of the plurality of page buffers to reorder the state data.

[0007] According to another aspect of the inventive concept, a memory system is provided, the memory system comprising: a memory controller configured to transform data received from a host based on a first state data sorting to generate write data; and a non-volatile memory device configured to: store write data received from the memory controller as state data in each of a plurality of page buffers, program memory cells based on the state data, and simultaneously perform a state data reordering operation with the programming of the memory cells, the state data reordering operation comprising changing the value of the state data stored in each of the plurality of page buffers to change the first state data sorting to a second state data sorting, the second state data sorting being adapted to the programming sequence. Attached Figure Description

[0008] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] FIG. 1 This is a block diagram of a memory system according to some example embodiments;

[0010] FIG. 2A and FIG. 2B This shows an example of a state data reordering operation;

[0011] FIG. 3 This is a block diagram of a memory device according to some example embodiments;

[0012] FIG. 4 This illustrates some example embodiments. FIG. 3 A circuit diagram showing the connection between a memory block and a page buffer circuit;

[0013] FIG. 5 Based on some example embodiments FIG. 4 A diagram of the page buffer is shown below;

[0014] FIG. 6A and FIG. 6B This illustrates a sequence of states formed according to a programming algorithm of a memory device based on some example embodiments;

[0015] FIG. 7A and FIG. 7B It is a timing diagram of a sequence of programming operations performed according to a programming algorithm of a memory device, based on some example embodiments;

[0016] FIG. 8 The diagram illustrates the change in data values ​​of state data loaded into multiple page buffers due to a reordering operation of state data of a memory device, according to some example embodiments.

[0017] FIG. 9 These are timing diagrams of the operation of a memory device according to some example embodiments;

[0018] FIG. 10A and FIG. 10B This illustrates the relationship between the time spent on a state data reordering operation according to some example embodiments and a specific time period selected from multiple sub-time periods included in a programming time period;

[0019] FIG. 11A , FIG. 11B and FIG. 11C The illustration shows a period of time during which a state data reordering operation is performed in a memory device, according to some example embodiments;

[0020] FIG. 12 This illustrates the relationship between the time spent on a state data reordering operation according to some example embodiments and a specific time period selected from multiple sub-time periods included in a programming time period;

[0021] FIG. 13A A method is shown to divide a state data reordering operation into multiple sequences in a memory device, according to some example embodiments;

[0022] FIG. 13B The process of changing the order of state data by executing multiple sequences in a memory device, according to some example embodiments, is illustrated.

[0023] FIG. 14A , FIG. 14B and FIG. 14C The illustration shows a period of time during which a state data reordering operation is performed in a memory device, according to some example embodiments;

[0024] FIG. 15 This is a flowchart of the operation of a memory device according to some example embodiments;

[0025] FIG. 16A These are circuit diagrams of memory blocks according to some example embodiments; FIG. 16B yes FIG. 16A A 3D view of the memory block;

[0026] FIG. 17This is a block diagram of a memory controller according to some example embodiments; and

[0027] FIG. 18 This is a block diagram of a solid-state drive (SSD) system according to some example embodiments. Detailed Implementation

[0028] The embodiments will now be described more fully below with reference to the accompanying drawings.

[0029] FIG. 1 This is a block diagram of a memory system 10 according to some example embodiments.

[0030] Reference FIG. 1 The memory system 10 may include a memory device 100 and a memory controller 200. The memory device 100 may include a memory cell array 110, a page buffer circuit 120, and a reordering control circuit 130. The memory device 100 may include a non-volatile memory device.

[0031] Memory controller 200 can control memory device 100 to read or write data stored in or to write data to memory device 100 in response to read / write requests from a host. Memory controller 200 can be configured to communicate with an external source (e.g., a host) via at least one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), and Intelligent Drive Electronics (IDE)). Memory controller 200 can control programming (or writing), reading, and erasing operations on memory device 100 by providing address ADDR, command CMD, and control signal CTRL to memory device 100. Furthermore, data to be programmed (DATA) and data to be read (DATA) can be sent and received between memory controller 200 and memory device 100.

[0032] The memory controller 200 (and other circuitry, such as page buffer circuitry 120 and reordering control circuitry 130) may include processing circuitry, such as hardware including logic circuitry, hardware / software combinations (such as a processor executing software), or combinations thereof. More specifically, the processing circuitry may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0033] The memory cell array 110 may include a plurality of memory cells, each capable of storing one bit or more bits of data. For example, the plurality of memory cells may be flash memory cells. In the following description, embodiments will be described in detail assuming the plurality of memory cells are NAND flash memory cells. However, the inventive concept is not limited thereto, and the plurality of memory cells may be various types of non-volatile memory cells. In some example embodiments, the plurality of memory cells may be resistive memory cells (such as resistive RAM (ReRAM) cells), phase-change RAM (PRAM) cells, or magnetic RAM (MRAM) cells.

[0034] In some example embodiments, the memory cell array 110 may include a plurality of cell strings configured to share bit lines therebetween. Each of the plurality of cell strings may include a ground select transistor, a memory cell, and a string select transistor connected to a ground select line, a word line, and a string select line. The memory cell array 110 may be a two-dimensional (2D) memory array. Alternatively, the memory cell array 110 may be a three-dimensional (3D) memory array.

[0035] A 3D memory cell array is monolithically formed in at least one physical level of a memory cell array having active regions disposed on a silicon substrate and circuitry associated with the operation of the memory cells, wherein the associated circuitry may be on or within the silicon substrate. The term "monolithic" means that each layer of the 3D memory cell array is deposited directly on the layer of each layer below the 3D memory cell array.

[0036] In some example embodiments, the 3D memory cell array may include cell strings in which at least one memory cell is positioned vertically above another memory cell. At least one memory cell may include a charge trapping layer. Suitable configurations of 3D memory arrays configured in multiple layers and having word lines and / or bit lines shared between the multiple layers are disclosed by reference to the following patent documents incorporated herein by reference: U.S. Patents Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235, and U.S. Patent Publication No. 2011 / 0233648. Furthermore, U.S. Patent Publication No. 2014 / 0334232 and U.S. Patent No. 8,488,381 are incorporated herein by reference.

[0037] Page buffer circuit 120 may temporarily store data DATA received from memory controller 200 (i.e., data DATA to be written to memory cell array 110). Page buffer circuit 120 may store the data DATA to be written as state data corresponding to each memory cell (hereinafter, selected memory cell) connected to a selected word line of memory cell array 110. In some example embodiments, the state data may indicate one of several states (e.g., erase state and multiple programming states) to which the memory cell can be programmed based on data values. The mapping between the multiple data values ​​of the state data and the multiple states may be referred to as state data ordering. Page buffer circuit 120 may drive the selected memory cell based on the state data during operation on the memory cell (i.e., programming operation). Page buffer circuit 120 may perform a state data reordering operation concurrently with the programming operation to change the state data ordering.

[0038] The reordering control circuit 130 can control the page buffer circuit 120 to perform a state data reordering operation simultaneously with the programming operation. Furthermore, the reordering control circuit 130 can select a specific time period from the time period during which the programming operation is performed (e.g., the entire programming period), and control the page buffer circuit 120 to perform the state data reordering operation within the selected time period. For example, the entire programming period may include multiple sub-time periods (e.g., multiple programming voltage (or pulse) application periods, multiple programming recovery periods, and multiple verification periods); the reordering control circuit 130 can select at least one of the multiple sub-time periods, and control the page buffer circuit 120 to perform the state data reordering operation simultaneously with at least one programming operation (e.g., programming voltage application, recovery operation, and verification operation) configured to be performed within said at least one sub-time period in the selected at least one sub-time period.

[0039] In some example embodiments, the reordering control circuit 130 may divide (or segment) the state data reordering operation (i.e., the operation performed for the state data reordering operation) into multiple sequences and select multiple sub-time periods from multiple sub-time periods in which multiple sequences will be executed simultaneously. The page buffer circuit 120 may sequentially execute the multiple sequences of the state data reordering operation in the selected multiple sub-time periods. For example, the page buffer circuit 120 may divide the state data reordering operation into a first sequence and a second sequence. The page buffer circuit 120 may execute the operation corresponding to the first sequence of the state data reordering operation simultaneously with the corresponding programming operation in the selected first sub-time period, and then execute the operation corresponding to the second sequence of the state data reordering operation simultaneously with the corresponding programming operation in the selected second sub-time period.

[0040] When a write request and data to be written to memory device 100 are received from the host, memory controller 200 may transform the data to be written based on a first state data sort (e.g., default state data sort or reference state data sort) and provide the transformed data as write data to memory device 100. The first state data sort is set to take into account coupling effects and error rates (e.g., error rates in read operations of data written to memory cell array 110).

[0041] Page buffer circuit 120 can perform a state data reordering operation to change a first state data order to a second state data order, the second state data order being suitable for a programming algorithm (e.g., a programming pulse application algorithm and a verification algorithm) set for memory device 100. Reordering control circuit 130 can control the state data reordering operation of page buffer circuit 120 based on a reordering sequence configured to change the first state data order to the second state data order. Page buffer circuit 120 can change the data value of the state data stored in the page buffer circuit corresponding to each selected memory cell based on a reordering control signal provided by reordering control circuit 130. Because the state data reordering can be performed simultaneously with the programming operation as described above, page buffer circuit 120 can perform the state data reordering operation simultaneously with at least one programming operation corresponding to the state data reordering operation in at least one of a plurality of sub-periods included in the period during which the programming operation is performed.

[0042] As described above, the time required to program selected memory cells into multiple states can be reduced due to the state data reordering operation. The state data reordering operation can be performed concurrently with a specific programming operation. For example, the state data reordering operation can be performed as a background operation concurrently with the specific programming operation in at least one of multiple sub-times included in the programming time period. Therefore, no additional time is required for the state data reordering operation. Furthermore, the state data reordering operation can be divided into at least two sequences, which can be performed as background operations in at least two of the multiple sub-times included in the programming time period. Therefore, even if the total time spent on the state data reordering operation exceeds the time required to perform a single programming operation, no additional time is needed solely for the state data reordering operation. Therefore, the time spent programming selected memory cells with data can be reduced, thereby improving the programming performance of the memory device 100 and the input / output (I / O) speed of the memory system 10.

[0043] FIG. 2A and FIG. 2B This shows an example of a state data reordering operation. FIG. 2ASome example embodiments are shown where memory cells are programmed with 2 bits of data. FIG. 2B Some example embodiments are shown where memory cells are programmed with 3 bits of data. FIG. 2A and FIG. 2B In the diagram, the curve represents the distribution of the threshold voltage (Vth) of the programmed memory cell, and the data represents the sorting of state data.

[0044] Reference FIG. 2A Two bits of data can be stored in each memory cell. Each memory cell can be programmed into one of four states (i.e., erase state E and first programming states P1 through third programming states P3) based on the two bits of data corresponding to each memory cell. The two bits of data can correspond to the least significant bit (LSB) and the most significant bit (MSB), respectively. The two bits of data indicate the target state to which the corresponding memory cell in the four states will be programmed, and can be referred to as state data. The state data can have multiple two-bit data values ​​(i.e., "00", "01", "10", and "11"), and the mapping (or mapping relationship) between the four states and the multiple data values ​​of the state data can be referred to as state data sorting. Hereinafter, "state data sorting" can be simply referred to as "sorting".

[0045] The initial sorting of state data can be reordered (or changed) to a second sorting different from the initial sorting. The initial sorting can be... FIG. 2A The default sort (or initial sort), the second sort can be FIG. 2A The changed sort (or final sort).

[0046] According to the default sorting, the data values ​​"11", "01", "00", and "10" of the status data can be sequentially mapped to the erase state E and the first programming states P1 through the third programming states P3. The default sorting can be based on the memory controller (see [reference]). FIG. 1 The sorting is set in 200. Write data received from memory controller 200 may include status data about each memory cell according to the default sorting.

[0047] Can be applied to memory devices (see reference) FIG. 1 The programming algorithm of memory device 100 is used to set the changed sorting. For example, the changed sorting could be set to reduce the time spent on programming operations when memory device 100 performs programming operations based on the set programming algorithm.

[0048] Based on the changed sorting, the data values ​​“10”, “11”, “01” and “00” of the state data can be sequentially mapped to the erase state E and the first programming state P1 to the third programming state P3.

[0049] ReferenceFIG. 2B Three bits of data can be stored in each memory cell. Each memory cell can be programmed into one of eight states (i.e., erase state E and first programming states P1 to seventh programming states P7) based on the three bits of data corresponding to each memory cell. The three bits of data can correspond to the LSB, the middle significant bit (CSB), and the MSB, respectively. The three bits of data serving as state data indicate the target state to which the corresponding memory cell among the eight states will be programmed. The state data can have multiple three-bit data values ​​(i.e., "000", "001", "010", "011", "100", "101", "110", and "111"). The mapping (or mapping relationship) between the eight states and the multiple data values ​​of the state data can be referred to as state data sorting.

[0050] The state data sorting can be reordered (or changed) from a first sort to a second sort. The first sort can be... FIG. 2B The default sorting, the second sorting can be FIG. 2B The order of the changes. Based on the default order, the state data values ​​"111", "110", "100", "000", "010", "011", "001", and "101" can be mapped to the erase state E and the first programming states P1 through the seventh programming states P7, respectively. Based on the changed order, the state data values ​​"111", "110", "101", "100", "011", "010", "001", and "000" can be mapped to the erase state E and the first programming states P1 through the seventh programming states P7, respectively.

[0051] Although it has been referenced FIG. 2A and FIG. 2B The state data reordering operation has been described, but the inventive concept is not limited thereto. For example, the default sorting and the changed sorting can vary according to the data conversion algorithm of the memory controller 200 and the programming algorithm of the memory device 100. Furthermore, the state data reordering operation can be performed not only on 2-bit and 3-bit data, but also on the data values ​​of 4-bit or more bit state data.

[0052] FIG. 3 This is a block diagram of a memory device 100 according to some example embodiments.

[0053] Reference FIG. 3 The memory device 100 may include a memory cell array 110, a page buffer circuit 120, a row decoder 140, a pass / fail check circuit (PFC) 150, a data I / O circuit 160, a voltage generator 170, and control logic 180. The control logic 180 may include a reordering control circuit 130.

[0054] The memory cell array 110 may include multiple memory cells and be connected to word lines WL, serial select lines SSL, ground select lines GSL, and bit lines BL. For example, the memory cell array 110 may be connected to the row decoder 140 via word lines WL, serial select lines SSL, and ground select lines GSL, and to the page buffer circuit 120 via bit lines BL.

[0055] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz (where z is an integer greater than 2). Each of the memory blocks BLK1 to BLKz may have a 2D structure and / or a 3D structure (or a vertical structure). Memory blocks BLK1 to BLKz can be selected by a row decoder 140. For example, the row decoder 140 may select a memory block corresponding to a block address from among the memory blocks BLK1 to BLKz. At least one memory block among the memory blocks BLK1 to BLKz may include multiple cell strings configured to share bit lines with each other.

[0056] The memory cell array 110 may include at least one of the following: a single-layer cell block including single-layer cells, a multi-layer cell block including multiple layers of cells, a three-layer cell block including three layers of cells, and a four-layer cell block including four layers of cells. In some example embodiments, some of the plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 may be single-layer cell blocks, while other memory blocks may be multi-layer cell blocks, three-layer cell blocks, or four-layer cell blocks.

[0057] Page buffer circuit 120 is connected to memory cell array 110 via bit line BL and to data I / O circuit 160 via data line DL. Page buffer circuit 120 can operate in response to control of control logic 180. Page buffer circuit 120 can operate as a write driver or a sense amplifier depending on the operating mode. For example, during a write operation, page buffer circuit 120 can program data DATA received from data I / O circuit 160 into memory cell array 110 and perform a verification read operation to verify whether the programming operation has succeeded or failed. Furthermore, during a read operation, page buffer circuit 120 can read data DATA from memory cell array 110 and output data DATA to data I / O circuit 160.

[0058] In some embodiments, the page buffer circuit 120 may perform a state data reordering operation simultaneously with a programming operation. The page buffer circuit 120 may perform the state data reordering operation in response to a reordering control signal RCS provided by control logic 180. The page buffer circuit 120 may change a first state data order (e.g., default order) to a second state data order (e.g., final order).

[0059] During a read operation, the page buffer circuit 120 may perform the read operation based on the sorting of the state data to be changed (i.e., the first state data sorting).

[0060] The row decoder 140 can select some word lines from word lines WL in response to the row address X-ADDR received from control logic 180. For example, during a read operation, the row decoder 140 can apply a read voltage to the selected word lines and a read pass voltage (or read disable voltage) to the unselected word lines. Furthermore, during a programming operation, the row decoder 140 can apply a programming voltage and a verification voltage (or verification read voltage) to the selected word lines and apply a programming pass voltage (or programming disable voltage) to the unselected word lines. Additionally, the row decoder 140 can select some string select lines in the string select line SSL or some ground select lines in the ground select line GSL in response to the row address X-ADDR received from control logic 180.

[0061] PFC 150 can output a pass signal or a failure signal to control logic 180 based on the verification read results collected by page buffer circuit 120.

[0062] Data I / O circuit 160 can be connected to page buffer circuit 120 via data line DL. Data I / O circuit 160 can be operated under the control of control logic 180. Data I / O circuit 160 can be connected to external devices (e.g., ...). FIG. 1 The memory controller 200 exchanges data DATA. The data I / O circuit 160 can send data DATA received from the outside to the page buffer circuit 120, and output data received from the page buffer circuit 120 to the outside.

[0063] Voltage generator 170 can generate various voltages for performing programming, reading, and erasing operations on memory cell array 110 based on the voltage control signal CTRL_vol received from control logic 180. For example, voltage generator 170 can generate word line voltages (V_WL), such as programming voltage, read voltage, programming pass voltage, read pass voltage, erase verification voltage, and / or programming verification voltage. Furthermore, voltage generator 170 can generate serial select line voltage and ground select line voltage based on the voltage control signal CTRL_vol.

[0064] Control logic 180 can output various control signals for writing data DATA to memory cell array 110 and / or reading data DATA from memory cell array 110 based on commands CMD, address ADDR, and control signals CTRL received from memory controller 200. Therefore, control logic 180 can typically control various operations of memory device 100.

[0065] Various output signals from control logic 180 can be provided to voltage generator 170, line decoder 140, page buffer circuit 120, and data I / O circuit 160.

[0066] Control logic 180 can control the programming and verification read operations of page buffer circuit 120 during programming operations, and control the read operations of page buffer circuit 120 during read operations. Control logic 180 may include reordering control circuit 130, which can control the reordering operation of state data of page buffer circuit 120. Reordering control circuit 130 can provide a reordering control signal RCS to page buffer circuit 120 for controlling page buffer circuit 120 to change the state data order (i.e., perform a state data reordering operation). Reordering control circuit 130 can generate the reordering control signal RCS based on a reordering sequence configured to change a first state data order to a second state data order.

[0067] During programming operations, the page buffer circuit 120 can change the stored state data (i.e., the state data stored in each memory cell corresponding to each memory cell) in response to the reordering control signal RCS. The following will refer to... FIG. 4 to FIG. 15 The operation of the reordering control circuit 130 and the page buffer circuit 120 used for reordering state data is described in detail.

[0068] During a read operation, control logic 180 may control page buffer circuit 120 to perform a read operation based on the sorting of the state data to be changed (i.e., the first state data sorting).

[0069] As described above, according to the memory device 100 and the method of operating the memory device 100, the page buffer circuit 120 can perform a state data reordering operation, thereby reducing the time required for programming operations. Furthermore, the state data reordering operation can be performed simultaneously with the programming operation as a background operation, thereby improving the programming performance of the memory device 100.

[0070] FIG. 4 This illustrates some example embodiments. FIG. 3 A circuit diagram showing the connection between one of the memory blocks BLK1 to BLKz and the page buffer circuit 120.

[0071] Reference FIG. 4The memory block BLKa may include multiple string SRs. The multiple string SRs may be connected to multiple bit lines BL1 to BLn (where n is an integer greater than 3). Each string SR may include a ground select transistor GST, a memory cell MC, and a string select transistor SST. Optionally, although not shown, when the memory cell array 110 has a 3D structure, each of the bit lines BL1 to BLn may be connected to multiple string SRs connected to different string select lines SSL.

[0072] The ground select transistor GST of each string ST can be connected between the memory cell MC and the common source line CSL. The ground select transistors GST of multiple strings SR can be connected together to the common source line CSL. The string select transistor SST of each string SR can be connected between the memory cell MC and the bit line BL. The string select transistors SST of multiple strings SR can be connected to multiple bit lines BL1 to BLn respectively. In each string SR, multiple memory cells MC can be positioned between the ground select transistor GST and the string select transistor SST. In each string SR, multiple memory cells MC can be connected in series.

[0073] In multiple string SRs, memory cells MC arranged in the same order from the common source line CSL can be connected to a single word line. The memory cells MC of multiple string SRs can be connected to multiple word lines WL1 to WLm (where m is an integer greater than 3).

[0074] Programming and reading operations on memory cells (MCs) can be performed on a word line basis. Memory cells (MCs) connected to the same word line can be programmed or read simultaneously. Memory cells (MCs) that are programmed or read simultaneously are called physical pages. When a memory cell (MC) stores 2 bits or more of data, a physical page can include multiple logical pages. For example, in... FIG. 2A In this context, the LSB of the data corresponding to the memory cell MC may include a first logical page, and the MSB of the data corresponding to the memory cell MC may include a second logical page.

[0075] Erasing operations on memory cells (MCs) can be performed on a block-by-block basis. Memory cells (MCs) of a memory block (BLKa) can be erased simultaneously. In some example embodiments, erasing operations on memory cells (MCs) can be performed on a sub-block basis. A memory block (BLKa) can be divided into multiple sub-blocks, and memory cells (MCs) of a sub-block can be erased simultaneously.

[0076] Page buffer circuit 120 may include multiple page buffers PB1 to PBn. Page buffers PB1 to PBn may be connected to bit lines BL1 to BLn, respectively. Page buffer circuit 120 may temporarily store data DATA read from memory cell array 110, or temporarily store data DATA to be written to memory cell array 110. For example, each of page buffers PB1 to PBn may include multiple latches. The latches may temporarily store data DATA.

[0077] FIG. 5 Based on some example embodiments FIG. 4 The diagram shows a page buffer.

[0078] Reference FIG. 5 The page buffer PB may include a selection circuit 121, a precharge circuit 122, a sense latch (SL) 123, a data latch unit 124 including multiple data latches DL1 to DLd (here, d is an integer equal to or greater than 2), a cache latch (CL) 125, and a dump circuit 126.

[0079] Selection circuit 121 may be connected between bit line BL and sensing node SO, and connect bit line BL to sensing node SO in response to a received selection control signal. For example, selection circuit 121 may be implemented as at least one transistor configured to be turned on or off in response to a selection control signal.

[0080] The precharge circuit 122 can precharge the selected bit line BL during programming and reading operations (e.g., programming voltage application operation and verification read operation).

[0081] The sensing latch 123 can sense the voltage of the sensing node SO after a sensing operation and latch the sensed voltage to store the programmed data in the memory cell MC connected to the bit line BL.

[0082] During programming operations, multiple data latches DL1 to DLd included in data latch unit 124 can store state data indicating the state to which the memory unit MC will be programmed. For example, when programming the memory unit MC using 2 bits of data, the multiple data latches DL1 to DLd can be two data latches DL1 and DL2, and 2 bits of state data can be loaded into the two data latches DL1 and DL2. When programming the memory unit MC using 3 bits of data, the multiple data latches DL1 to DLd can be three data latches DL1 to DL3, and 3 bits of state data can be loaded into the three data latches DL1 to DL3. However, the inventive concept is not limited to this, and data latch unit 124 may also include at least one data latch for backup.

[0083] The high-speed buffer latch 125 can be based on bit-to-bit data I / O circuitry (see reference). FIG. 3 160) receives and loads data DATA, and sends the received data DATA to multiple data latches DL1 to DLd due to data dump operations.

[0084] Sensing latch 123, multiple data latches DL1 to DLd, and cache latch 125 can be connected to sensing node SO via dump circuit 126. Dump circuit 126 can set or reset at least one of the multiple data latches DL1 to DLd based on bits stored in cache latch 125. Therefore, data DATA loaded into cache latch 125 can be sent to the multiple data latches DL1 to DLd. Dump circuit 126 can set or reset sensing latch 123 based on bits loaded into multiple data latches DL1 to DLd, or it can set or reset at least one of the multiple data latches DL1 to DLd based on bits loaded into sensing latch 123. Furthermore, dump circuit 126 can set or reset at least one different latch based on at least one bit loaded into at least one of the multiple data latches DL1 to DLd. A dump operation (or data dump operation) can be performed based on setting or resetting operations of multiple data latches DL1 to DLd, sensing latch 123 and buffer latch 125.

[0085] During the state data reordering operation, the dump circuit 126 may respond to a reordering control signal (see reference). FIG. 3 The status data reordering operation may include multiple dump operations. Due to the dump operations on multiple data latches DL1 to DLd, the bits loaded into at least one of the multiple data latches DL1 to DLd can be changed (e.g., changed from "0" to "1" or from "1" to "0"). Therefore, the data value of the status data can be changed.

[0086] FIG. 6A and FIG. 6B The diagram illustrates a sequence of states formed according to a programming algorithm of a memory device based on some example embodiments.

[0087] Reference FIG. 6A and FIG. 6B A memory cell in erase state E can be programmed into erase state E and first programming states P1 through third programming states P3. In some example embodiments, the memory cell can be programmed in various sequences according to a programming algorithm.

[0088] For example, such asFIG. 6A As shown, some of the memory cells in the erase state E can be programmed to the initial programming state P0. A verification read operation can be performed based on the initial verification voltage Vvf0 to verify whether the programming operation in the initial programming state P0 has succeeded or failed.

[0089] Subsequently, some of the remaining memory cells in the erase state E can be programmed to the first programming state P1, some of the memory cells in the initial programming state P0 can be programmed to the second programming state P2, and some of the remaining memory cells in the initial programming state P0 can be programmed to the third programming state P3. A verification read operation can be performed based on the first verification voltage Vvf1, the second verification voltage Vvf2, and the third verification voltage Vvf3 to verify whether the programming operations in the first programming state P1, the second programming state P2, and the third programming state P3 have succeeded or failed.

[0090] In some example embodiments, such as FIG. 6B As shown, the remaining memory cells in the erase state E, except for those memory cells that are set to be programmed to erase state E (i.e., memory cells that will be kept in erase state E), can be programmed to the first programming state P1, and the verification read operation can be performed based on the first verification voltage Vvf1.

[0091] Subsequently, memory cells other than those programmed to erase state E and first programming state P1 (i.e., memory cells programmed to second programming state P2 and third programming state P3) can be programmed to second programming state P2, and the verification read operation can be performed based on the second verification voltage Vvf2. Finally, memory cells programmed to third programming state P3 can be programmed to third programming state P3.

[0092] For reference FIG. 6A and FIG. 6B As described, memory cells can be programmed into multiple programming states (e.g., first programming state P1 to third programming state P3) via intermediate states (e.g., initial programming state P0), or programmed into first programming state P1 to third programming state P3 in stages according to a programming algorithm. As mentioned above, the sequence (or process) forming multiple states (erase state and multiple programming states) can vary depending on various programming algorithms.

[0093] FIG. 7A and FIG. 7B This is a timing diagram showing the sequence of programming operations performed according to a programming algorithm of a memory device, based on some example embodiments. FIG. 7A and FIG. 7BIn the graph, the horizontal axis represents time, and the vertical axis represents the voltage level applied to the selected word line connected to the selected memory cell.

[0094] Reference FIG. 7A The programming operation may include multiple programming loops LOOP1 to LOOPj (where j is an integer greater than 3). In each of the multiple programming loops LOOP1 to LOOPj, a programming voltage Vpgm (or programming pulse) may be applied to the word line, and at least one of multiple verification voltages (e.g., Vvf1, Vvf2, and Vvf3) may subsequently be applied. The level of the second verification voltage Vvf2 may be higher than the level of the first verification voltage Vvf1, and the level of the third verification voltage Vvf3 may be higher than the level of the second verification voltage Vvf2. After the programming voltage Vpgm is applied and before the verification voltage is applied, a programming recovery operation in which ground is applied to the word line may be performed. According to the Incremental Step Pulse Programming (ISPP) method, the level of the programming voltage Vpgm applied in the multiple programming loops LOOP1 to LOOPj may be increased.

[0095] In the first programming loop (LOOP1) and the second programming loop (LOOP2), after the programming voltage Vpgm is applied, the second verification voltage Vvf2 can be applied. In the third programming loop (LOOP3), after the programming voltage Vpgm is applied, the second verification voltage Vvf2, the first verification voltage Vvf1, and the third verification voltage Vvf3 can be applied sequentially. In the final programming loop (LOOPj), after the programming voltage Vpgm is applied, the first verification voltage Vvf1 and the third verification voltage Vvf3 can be applied sequentially.

[0096] Reference FIG. 7B Programming operations can include multiple programming loops LOOP1 to LOOPk (where k is an integer greater than 3). (and) FIG. 7A The differences shown in FIG. 7B In the first programming loop (LOOP1) and the second programming loop (LOOP2), after the programming voltage Vpgm is applied, the first verification voltage Vvf1 can be applied. In the third programming loop (LOOP3), after the programming voltage Vpgm is applied, the first verification voltage Vvf1 and the second verification voltage Vvf2 can be applied sequentially. In the final programming loop (LOOPk), after the programming voltage Vpgm is applied, the third verification voltage Vvf3 can be applied.

[0097] For reference FIG. 7A and FIG. 7B The verification order can change during the programming operation depending on the programming algorithm.

[0098] For reference FIG. 6A to FIG. 7BThe programming method (e.g., the sorting and verification of programming states) can vary depending on the programming algorithm set, and the page buffer circuit (refer to...) FIG. 3 The number of dump operations and the time required for programming operations (120) can vary depending on the programming method.

[0099] For example, the time required to perform a programming operation based on a first programming algorithm and sorting the first state data may differ from the time required to perform a programming operation based on a first programming algorithm and sorting the second state data. Furthermore, the time required to perform a programming operation based on a first programming algorithm and sorting the first state data may differ from the time required to perform a programming operation based on a second programming algorithm and sorting the first state data. A memory device according to some example embodiments (see...) FIG. 1 and FIG. 3 The 100 in the middle can determine the optimized state data sorting, and perform the state data reordering operation as described above to change the state data sorting to the optimized state data sorting, which minimizes the time required for programming operations according to the set programming algorithm.

[0100] FIG. 8 This illustration shows the change in the data values ​​of state data loaded into multiple page buffers due to a reordering operation of the state data of the memory device, according to some example embodiments. For simplicity, first page buffers PB1 to fourth page buffers PB4 and first memory cells MC1 to fourth memory cells MC4 are shown. First memory cells MC1 to fourth memory cells MC4 can be respectively connected to a corresponding one of the first page buffers PB1 to fourth page buffers PB4 via first bit lines LB1 to fourth bit lines LB4. FIG. 8 An example embodiment is shown, for example, where the first page buffer PB1 to the fourth page buffer PB4 include pairs of data latches DL1-1 and DL2-1, DL1-2 and DL2-2, DL1-3 and DL2-3, and DL1-4 and DL2-4, respectively.

[0101] Before the state data reordering operation is performed, "1" can be loaded into each of the first data latches DL1-1 and DL2-1 in the first page buffer PB1. Therefore, the data value of the state data stored in the first page buffer PB1 can be "11". The data value of the state data stored in the second page buffer PB2 can be "01", the data value of the state data stored in the third page buffer PB3 can be "00", and the data value of the state data stored in the fourth page buffer PB4 can be "10". This can be based on a default sorting (e.g., ...). FIG. 2A(The default sorting) sets the first memory cell MC1 to the fourth memory cell MC4 to be programmed to erase state E and first programming state P1 to third programming state P3, respectively. In other words, the target states of the first memory cell MC1 to the fourth memory cell MC4 can be set to erase state E and first programming state P1 to third programming state P3, respectively.

[0102] During programming operations, the first page buffer PB1 through the fourth page buffer PB4 can simultaneously perform state data reordering operations. The state data can be sorted according to an optimized programming algorithm (i.e., a modified state data sorting, e.g., ...). FIG. 2A The sorting of the data is changed to alter the data values ​​of the state data from the first page buffer PB1 to the fourth page buffer PB4.

[0103] The data values ​​of the status data can be changed due to multiple dump operations of the data latches included in each of the first page buffers PB1 to the fourth page buffer PB4. The data value of the status data stored in the first page buffer PB1 can be changed to "10", the data value of the status data stored in the second page buffer PB2 can be changed to "11", the data value of the status data stored in the third page buffer PB3 can be changed to "01", and the data value of the status data stored in the fourth page buffer PB4 can be changed to "00". After performing a status data reordering operation, programming operations can be performed based on the changed status data order.

[0104] FIG. 9 It is a timing diagram of the operation of a memory device according to some example embodiments. FIG. 9 The operation can be performed by FIG. 1 and FIG. 3 The memory device 100 executes.

[0105] Reference FIG. 9 The memory device 100 can send a ready-busy signal RnBx to the memory controller 200, and when the ready-busy signal RnBx is at a first level (e.g., logic high), it can receive commands CMD, address ADDR, and data DATA from the memory controller 200 through the I / O channel DQ. The memory device 100 can receive commands CMD, address ADDR, and data DATA during a first time period T1.

[0106] The memory device 100 may set the ready-busy signal RnBx to a second level (e.g., logic low) during a second time period T2 and perform programming operations on the memory cell array.

[0107] The period during which the programming operation is performed (hereinafter referred to as the programming period) (i.e., the second period T2) may include multiple sub-periods. For example, the multiple sub-periods may include: multiple programming voltage application periods PGM during which programming voltage and / or programming pulses are applied, multiple programming recovery periods RV during which programming recovery operations are performed, and multiple verification periods VFY during which verification read operations are performed. The reordering control circuit 130 may select at least one sub-period from the multiple sub-periods and control the page buffer circuit 120 to perform a state data reordering operation in the selected at least one sub-period. When a programming operation is performed (e.g., when a programming pulse is applied, when a programming recovery operation is performed, and / or when a verification read operation is performed), the page buffer circuit 120 may perform a state data reordering operation as a background operation simultaneously with the above operations.

[0108] In some example embodiments, the reordering control circuit 130 can control the page buffer circuit 120 to perform a state data reordering operation during the period when an initial programming voltage is applied to the memory cell array (e.g., a selected word line).

[0109] FIG. 10A and FIG. 10B This illustrates the relationship between the time required for a state data reordering operation according to some example embodiments and a specific time period selected from multiple sub-time periods included in a programming time period.

[0110] Reference FIG. 10A The state data reordering operation may include multiple operations OP1 to OPm (where m is an integer equal to or greater than 4). For example, when the state data is 2 bits, state data reordering may include several operations. When the state data is 3 bits, state data reordering may include many operations. When the state data reordering operation is performed during the programming voltage application period PGM, the state data reordering operation may be performed simultaneously with the application of the programming voltage. The time required for the state data reordering operation (hereinafter referred to as the reordering time) Tr may be shorter than or equal to the time Ts1 corresponding to the programming voltage application period PGM.

[0111] Reference FIG. 10B The state data reordering operation can be performed concurrently with the verification read operation during the verification period VFY. The reordering time Tr can be shorter than or equal to the time Ts2 corresponding to the verification period VFY.

[0112] FIG. 11A , FIG. 11B and FIG. 11C This illustrates the time period during which a state data reordering operation is performed in a memory device, according to some example embodiments.

[0113] Reference FIG. 11A to FIG. 11C It allows you to perform a state data reordering operation in one of the multiple sub-times included in the programming time.

[0114] Reference FIG. 11A State data reordering can be performed during the period when the programming voltage Vpgm is first applied (i.e., the programming voltage application period of the first programming loop LOOP1). See reference... FIG. 11B The state data reordering operation can be performed during the period when the programming voltage Vpgm is applied for the second time (i.e., during the programming voltage application period of the second programming cycle LOOP2). See reference... FIG. 11A and FIG. 11B The state data reordering operation can be performed during one of the multiple programming voltage application periods of the applied programming voltage Vpgm. In some example embodiments, the reordering time may be shorter than or equal to the time required to apply the programming voltage Vpgm.

[0115] Reference FIG. 11C The state data reordering operation can be performed during the period when the verification read operation is performed. That is, the state data reordering operation can be performed simultaneously with the verification read operation. In some example embodiments, the reordering time may be shorter than or equal to the time required to apply the verification voltage (e.g., the time required to apply the first verification voltage Vvf1).

[0116] FIG. 12 This illustrates the relationship between the time required for a state data reordering operation according to some example embodiments and a specific time period selected from multiple sub-time periods included in a programming time period.

[0117] Reference FIG. 12 A state data reordering operation can be performed from a sub-period selected from multiple sub-periods included in the programming period (e.g., the programming voltage application period PGM). The reordering time Tr can be longer than the time Ts required for the selected sub-period.

[0118] like FIG. 12 As shown, when the reordering time Tr is longer than the time Ts required for the selected sub-period, the state data reordering operation can be divided into multiple sequences, and the multiple sequences can be executed separately in selected sub-periods among multiple sub-periods included in the programming period.

[0119] Reordering control circuit (refer to) FIG. 1 and FIG. 3The reordering control circuit 130 can compare the reordering time Tr with the time Ts required for the selected sub-period, and divide the state data reordering operation into (or split into) multiple sequences if the reordering time Tr is longer than the time Ts required for the selected sub-period. The reordering control circuit 130 can select multiple sub-periods from the multiple sub-periods included in the programming period, multiple sequences of which will be executed simultaneously with the corresponding programming operations. For example, the reordering control circuit 130 can reselect an already selected sub-period, and also select another sub-period.

[0120] FIG. 13A This illustrates a method for dividing a state data reordering operation into multiple sequences in a memory device, according to some example embodiments. FIG. 13B The process of changing the order of state data by executing multiple sequences in a memory device, according to some example embodiments, is illustrated.

[0121] Reference FIG. 13A The state data reordering operation may include multiple operations, such as first operation OP1 through eighth operation OP8. Furthermore, the time required to execute all first operations OP1 through eighth operations OP8 (i.e., the reordering time) may be longer than the first time Ts11, which is allocated to a first sub-time period selected from multiple sub-time periods of the programming period (e.g., the programming voltage application period PGM).

[0122] Reordering control circuit (refer to) FIG. 1 and FIG. 3 130) can divide the first operation OP1 to the eighth operation OP8 of the state data reordering operation into multiple reordering sequences (e.g., first reordering sequence SQ1 and second reordering sequence SQ2), and select multiple reordering sequences from multiple sub-times of the programming time period to be executed.

[0123] For example, in the first operations OP1 to the eighth operations OP8, the reordering control circuit 130 may classify the first operations OP1 to the fourth operations OP4 as a first reordering sequence SQ1 and classify the fifth operations OP5 to the eighth operations OP8 as a second reordering sequence SQ2. The reordering control circuit 130 may select at least one of the selected first sub-time period and subsequent other second sub-time periods (e.g., programming voltage application period PGM, programming recovery period RV, and verification period VFY). The time required for the first reordering sequence SQ1 (i.e., the time to execute the first operations OP1 to the fourth operations OP4) may be equal to or shorter than the first time Ts11 corresponding to the first sub-time period. The time required for the second reordering sequence SQ2 (i.e., the time to execute the fifth operations OP5 to the eighth operations OP8) may be equal to or shorter than the second time Ts12 corresponding to the second sub-time period.

[0124] The reordering control circuit 130 can control the page buffer circuit (see reference). FIG. 1 and FIG. 3 In step 120), multiple reordering sequences (e.g., first reordering sequence SQ1 and second reordering sequence SQ2) are executed in multiple selected sub-time periods.

[0125] Reference FIG. 13B The state data reordering operation can be divided into a first reordering sequence SQ1 and a second reordering sequence SQ2. The first reordering sequence SQ1 can be executed in the first sub-period, causing the state data sorting to be reordered (changed) from the default sorting to the intermediate changed sorting. The first sub-period is the earlier of two sub-periods selected from a plurality of sub-periods in the programming period. Subsequently, the second reordering sequence SQ2 can be executed in the second sub-period of the two selected sub-periods, causing the state data sorting to be reordered (changed) from the intermediate changed sorting to the final changed sorting.

[0126] When performing a phased reordering operation of state data, the programming method can be changed. After executing the first reordering sequence SQ, the memory device 100 can perform programming operations based on the intermediate reordering changes. Therefore, the control logic (refer to...) FIG. 3 (180) can change the programming algorithm to change the programming method based on the intermediate changed sorting, and perform programming operations based on the intermediate changed sorting and the changed programming method.

[0127] FIG. 14A , FIG. 14B and FIG. 14C This illustrates the time period during which a state data reordering operation is performed in a memory device, according to some example embodiments.

[0128] Reference FIG. 14A , FIG. 14B and FIG. 14C The state data reordering operation can be divided into multiple reordering sequences, which can be executed separately in a sub-time selected from multiple sub-times included in the programming time.

[0129] Reference FIG.14A The state data reordering operation can be divided into a first reordering sequence SQ1 and a second reordering sequence SQ2, which can be executed respectively during the time period when the programming voltage Vpgm of the first programming loop LOOP1 and the second programming loop LOOP2 is applied.

[0130] Reference FIG. 14B The state data reordering operation can be divided into a first reordering sequence SQ1, a second reordering sequence SQ2, and a third reordering sequence SQ3. The first reordering sequence SQ1, the second reordering sequence SQ2, and the third reordering sequence SQ3 can be executed respectively in the sub-periods when the programming voltage Vpgm of the first programming cycle LOOP1, the second programming cycle LOOP2, and the third programming cycle LOOP3 is applied.

[0131] For reference FIG. 14A and FIG. 14B The state data reordering operation can be performed in at least two of a plurality of programming periods during which the programming voltage Vpgm is applied. The reordering time can be longer than the unit time required to apply the programming voltage Vpgm. Therefore, the state data reordering operation can be divided into multiple sequences, which can be performed in at least two programming voltage application periods.

[0132] Reference FIG. 14C The state data reordering operation can be divided into a first reordering sequence SQ1 and a second reordering sequence SQ2. The first reordering sequence SQ1 can be executed during the sub-period when the programming voltage Vpgm is applied in the first programming loop LOOP1 (i.e., the programming voltage application period), and the second reordering sequence SQ2 can be executed during the sub-period when the first verification voltage Vvf1 is applied (i.e., the verification period). The reordering time can be longer than each of the programming voltage application period and the verification period. Therefore, the state data reordering operation can be divided into multiple sequences, which can be executed separately during the programming voltage application period and the verification period.

[0133] ​ This is a flowchart of the operation of a memory device 100 according to some example embodiments. ​ The operation can be performed by ​ and​ The memory device 100 performs the operation. Therefore, the above-described operation of the memory device 100 can be applied to the example embodiment.

[0134] Reference ​ The memory device 100 can receive data (S110). The memory device 100 can receive write data from the memory controller 200, and the write data can be data generated based on the sorting of the first state data.

[0135] The memory device 100 can store the received data as status data in multiple page buffers (S120). For example, when programming a memory cell using 2 bits of data, the status data can be stored in multiple page buffers based on 2 bits.

[0136] The memory device 100 can program multiple memory cells of the memory cell array based on state data (S130). The target state to which the memory cells will be programmed can be set based on the first state data sorting and the state data, and the memory device 100 can program the memory cells into the target state.

[0137] The memory device 100 can perform a state data reordering operation (S140) simultaneously with a programming operation. When performing a programming operation, the memory device 100 can perform a state data reordering operation as a background operation. Due to the state data reordering operation, a first state data order can be changed to a second state data order. The second state data order can be a state data order configured to reduce programming time based on a programming algorithm set for the memory device 100. When the first state data order is changed to the second state data order due to the state data reordering operation, the memory device 100 can perform subsequent programming operations based on the second state data order. In other words, when the data values ​​of state data stored in multiple page buffers are changed according to the second state data order, a programming operation can be performed based on the changed data values.

[0138] For reference ​ The memory device 100 can select at least one sub-time period from a plurality of sub-time periods included in the programming time period, and perform a state data reordering operation in the selected at least one sub-time period. When the time required for the state data reordering operation is longer than the length of a selected sub-time period, the memory device 100 can divide the state data reordering operation into multiple sequences and execute the multiple sequences in the multiple sub-time periods selected from the plurality of sub-time periods respectively.

[0139] ​ This is a circuit diagram of a memory block BLKb based on some example embodiments. ​ yes ​ A 3D view of the memory block BLKb.

[0140] Reference ​ The memory block BLKb can be a NAND flash memory with a vertical structure. ​ At least one of the memory blocks BLK1 to BLKz shown in the diagram can be as follows: ​ The ground shown is implemented as described. The memory block BLKb may include multiple NAND cell strings (e.g., NS11 to NS33), multiple word lines (e.g., WL1 to WL8), multiple bit lines (e.g., BL1 to BL3), multiple ground select lines (e.g., GSL1 to GSL3), multiple string select lines (e.g., SSL1 to SSL3), and a common source line CSL. The number of cell strings, word lines, bit lines, ground select lines, and string select lines may vary depending on the embodiment.

[0141] NAND cell strings NS11, NS21, and NS31 may be disposed between the first bit line BL1 and the common source line CSL; NAND cell strings NS12, NS22, and NS32 may be disposed between the second bit line BL2 and the common source line; and NAND cell strings NS13, NS23, and NS33 may be disposed between the third bit line BL3 and the common source line CSL. Each NAND cell string (e.g., NS11) may include a series-connected string select transistor SST, a plurality of memory cells MC1 to MC8, and a ground select transistor GST. In some example embodiments, dummy cells may be arranged between the string select transistor SST, the plurality of memory cells MC1 to MC8, and the ground select transistor GST. Hereinafter, for simplicity, the NAND cell string will be referred to as a cell string.

[0142] Serial select lines SSL1 to SSL3 can be isolated from each other, and the serial select transistor SST can be connected to the corresponding serial select line among SSL1 to SSL3. Ground select lines GSL1 to GSL3 can be isolated from each other, and the ground select transistor GST can be connected to the corresponding ground select line among GSL1 to GSL3. Serial select transistor SST can be connected to the corresponding bit line among BL1 to BL3, and select transistor GST can be connected to the common source line CSL.

[0143] Multiple memory cells MC1 to MC8 can be connected to multiple word lines WL1 to WL8 corresponding to the memory cells MC1 to MC8 respectively. Memory cells located at the same height from the substrate (or ground select transistor GST) can be connected to a single word line, while memory cells located at different heights can be connected to different word lines WL1 to WL8 respectively. For example, the first memory cell MC1 can be connected to the first word line WL1, and the second memory cell MC2 can be connected to the second word line WL2.

[0144] Reference ​ Memory blocks BLKb can be formed in a direction perpendicular to the substrate SUB. Although ​ The diagram shows some example embodiments of a memory block BLKb including two select lines GSL and SSL, eight word lines WL1 to WL8, and three bit lines BL1 to BL3. However, the number of select lines, word lines, and bit lines can actually be greater or less than these figures. ​ The number of selection lines, word lines, and bit lines in the code.

[0145] The substrate SUB may have a first conductivity type (e.g., p-type), and a common source line (CSL) may be disposed on the substrate SUB. The common source line (CSL) may extend in a first direction (e.g., the Y direction) and be doped with an impurity of a second conductivity type (e.g., n-type). A plurality of insulating films (ILs) may extend in the first direction and be sequentially disposed in a third direction (e.g., the Z direction) in a region between two adjacent common source lines (CSLs) of the substrate SUB. Furthermore, the plurality of insulating films (ILs) may be spaced apart from each other by a predetermined distance in the third direction. For example, the plurality of insulating films (ILs) may comprise an insulating material (e.g., silicon oxide).

[0146] Multiple pillars P may be sequentially arranged in a first direction and pass through multiple insulating films IL in a third direction. Each of the multiple pillars P may be disposed in the region between two adjacent common source lines CSL of the substrate SUB. For example, the multiple pillars P may pass through multiple insulating films IL and contact the substrate SUB. For example, the surface layer S of each pillar P may include a silicon material of a first conductivity type and serve as a channel region. Meanwhile, the inner layer I of each pillar P may include an insulating material (e.g., silicon oxide) and / or an air gap.

[0147] A charge storage layer CS may be disposed in the region between two adjacent common-source lines CSL along the exposed surfaces of the insulating film IL, pillar P, and substrate SUB. The charge storage layer CS may include a gate insulating layer (or "tunnel insulating layer"), a charge trapping layer, and a barrier insulating layer. For example, the charge storage layer CS may include an oxide-nitride-oxide (ONO) structure. Furthermore, gate electrodes GE, including select lines GSL and SSL and word lines WL1 to WL8, may be disposed in the region between two adjacent common-source lines CSL on the exposed surface of the charge storage layer CS.

[0148] The drain or drain contact DR may be disposed on a plurality of pillars P. For example, the drain or drain contact DR may comprise silicon material doped with impurities of a second conductivity type. Bit lines BL1 to BL3 may be disposed on the drain DR. Bit lines BL1 to BL3 may extend in a first direction and be spaced apart from each other by a predetermined distance in a second direction (e.g., the X direction).

[0149] ​This is a block diagram of a memory controller 200 according to some example embodiments.

[0150] Reference ​ The memory controller 200 may include a processor 210, a data converter 220, an error correction circuit (ECC) 230, a host interface 240, a buffer memory 250, and a memory interface 260. The processor 210, data converter 220, ECC 230, host interface 240, buffer memory 250, and memory interface 260 can send and receive data to each other via a bus 270.

[0151] Processor 210 can control the overall operation of memory controller 200 and perform logical operations. In some example embodiments, processor 210 may include processing circuitry, such as hardware including logic circuitry, a hardware / software combination (such as a processor executing software), or a combination thereof. More specifically, for example, processing circuitry may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0152] Data converter 220 can transform data received from an external host based on a first state data sorting (e.g., default state data sorting) that takes into account coupling effects and error rates. Furthermore, data converter 220 can also transform data received from a memory device (e.g., ...) based on the first state data sorting. ​ and ​ The memory device 100 receives data, converts it, and outputs the converted data to an external host.

[0153] ECC 230 can perform error correction operations. ECC 230 can perform error correction encoding operations based on data to be written to memory device 100 via memory interface 260. Data that has undergone error correction encoding operations can be sent to memory device 100 via memory interface 260. ECC 230 can perform error correction decoding operations on data received from memory device 100 via memory interface 260. For example, ECC 230 can be included as a component in memory interface 260.

[0154] The buffer memory 250 may temporarily store data to be written to or received from the memory device 100. Furthermore, the buffer memory 250 may temporarily store data required for the operation of the memory controller 200. In some example embodiments, the buffer memory 250 may be used as operational memory or cache memory.

[0155] The memory controller 200 can communicate with an external host via the host interface 240 and with the memory device 100 via the memory interface 260.

[0156] Host interface 240 can be configured to communicate with an external host via control of processor 210. Host interface 240 can be configured to communicate with an external host using at least one of various communication methods, such as USB, SATA, Serial Attached Small Computer System Interface (SCSI) (SAS), High-speed Interchip (HSIC), SCSI, Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Fast (NVMe), Universal Flash (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM)).

[0157] The memory interface 260 can be configured to communicate with the memory device 100 via control of the processor 210. The memory interface 260 can communicate commands, addresses, and data with the memory device 100 through I / O channels. The memory interface 260 can also communicate control signals with the memory device 100 through control channels.

[0158] ​ This is a block diagram of a solid-state drive (SSD) system 1000 according to some example embodiments.

[0159] Reference ​ The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 can send and receive signals to and from the host 1100 via a signal connector, and receives power (PWR) via a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and multiple flash memory devices (e.g., 1230, 1240, and 1250). In some example embodiments, the SSD controller 1210 can exchange data with multiple flash memory devices via channels Ch1, Ch2, ... Chn (where n is an integer equal to or greater than 3). In some example embodiments, ​ The memory system 10 can be applied to the SSD 1200. For example, ​ and ​The memory device 100 can be applied to at least one of a plurality of flash memory devices 1230 to 1250. At least one of the plurality of flash memory devices 1230 to 1250 can perform a state data reordering operation to reduce the time required for programming operations. At least one of the plurality of flash memory devices 1230 to 1250 can perform the state data reordering operation simultaneously with the programming operation. Therefore, programming performance can be improved, and the data input / output (I / O) speed of the SSD 1200 can be improved.

[0160] The memory device and memory system according to the embodiments can not only be installed in ​ The SSD 1200 shown in the image is on and / or applied to ​ The SSD 1200 shown herein can also be installed on and / or applied to memory card systems, computing systems, UFS, and eMMC. Furthermore, the methods for operating the memory device according to some example embodiments can be applied to various electronic systems equipped with non-volatile memory.

[0161] Although described with reference to specific examples and accompanying drawings, those skilled in the art can make modifications, additions, and substitutions to the exemplary embodiments differently based on the specification. For example, the described techniques and / or components such as the described systems, architectures, devices, circuits, etc., may be connected or combined in a different order than the methods described, or the results may be suitably achieved by other components or equivalents.

[0162] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made in the embodiments without departing from the spirit and scope of the claims.

Claims

1. A non-volatile memory device, comprising: A memory cell array comprising multiple memory cells, each memory cell being configured to be programmed into one of a variety of states; A page buffer circuit includes multiple page buffers, each configured to store received data as state data, the state data indicating a target state of a corresponding memory cell among the multiple memory cells, and the page buffer circuit is configured to perform a state data reordering operation during programming operations on selected memory cells among the multiple memory cells, changing a first state data ordering to a second state data ordering, the first state data ordering indicating a reference mapping between multiple data values ​​of the state data and the multiple states; as well as The reordering control circuit is configured to control the page buffer circuit to perform state data reordering operations simultaneously with the programming operation.

2. The non-volatile memory device according to claim 1, wherein, Each of the plurality of page buffers includes a data latch, which is configured to store bits of state data respectively; and The status data reordering operation includes multiple dump operations on the data latch.

3. The non-volatile memory device according to claim 1, wherein, The reordering control circuit is configured to control the page buffer circuit to change the data value of the state data stored in each of the plurality of page buffers based on a reordering sequence that is set to change the sorting of the first state data to the sorting of the second state data.

4. The non-volatile memory device according to claim 3, wherein, The second state data sorting is set to reduce the time required for the programming algorithm based on the settings to perform programming operations on the selected memory cells.

5. The non-volatile memory device according to claim 1, wherein, The page buffer circuit is configured to perform a state data reordering operation during at least one of the following periods: a programming voltage application period when a programming voltage is applied to a selected memory cell; a programming recovery period when a voltage is applied to a word line after the programming voltage is applied but before the verification read voltage is applied; and a verification period when a verification read operation is performed after the programming voltage is applied.

6. The non-volatile memory device according to claim 1, wherein, The page buffer circuit is configured to perform a state data reordering operation during the period when the programming voltage is initially applied to the selected memory cell.

7. The non-volatile memory device according to claim 1, wherein, The reordering control circuit is configured as follows: Based on at least one of the time when the programming voltage is applied to the selected memory cell and the time when the verification read operation is performed, the multiple operations included in the state data reordering operation are divided into at least two reordering sequences. as well as The at least two time periods from which the at least two reordering sequences will be executed are determined from a set of time periods including multiple programming voltage application periods, multiple programming recovery periods, and multiple verification periods.

8. The non-volatile memory device according to claim 7, wherein, The page buffer circuit is configured to sequentially execute the at least two reordering sequences during at least two of the plurality of programming voltage application periods.

9. The non-volatile memory device according to claim 7, wherein, The page buffer circuit is configured to sequentially execute the at least two reordering sequences in at least one of the plurality of programming voltage application periods and at least one of the plurality of verification periods.

10. The non-volatile memory device according to claim 7, wherein, Based on the execution of the first sequence of the at least two reordering sequences, the first state data sorting is changed to an intermediate state data sorting indicating the changed mapping; and After executing the first sequence, programming operations are performed based on a programming algorithm set according to the intermediate state data sorting settings.

11. A method of operating a non-volatile memory device, the method comprising: Receive data; The data is stored as state data in multiple page buffers connected to the memory cell array; Based on the state data stored in the multiple page buffers, multiple memory cells of the memory cell array are programmed; as well as While programming the plurality of memory cells, the data values ​​of the state data stored in each of the plurality of page buffers are changed to reorder the state data stored in the plurality of page buffers.

12. The method according to claim 11, wherein, The step of reordering the state data includes: performing multiple dump operations on multiple data latches included in each of the plurality of page buffers, and changing the first state data stored in the data latches to second state data.

13. The method according to claim 11, wherein, The programming operation period for programming the plurality of memory cells includes multiple sub-periods, namely a programming pulse application period, a programming recovery period, and a verification period. The step of reordering the state data is performed in at least one of the plurality of sub-time periods.

14. The method of claim 13, further comprising: Based on the fact that the time required to perform the step of reordering the state data exceeds the time required for the application of the programming pulse, the step of reordering the state data is divided into at least two reordering sequences; as well as Select at least two sub-times from the plurality of sub-times from which the at least two reordered sequences will be executed. The step of reordering the state data includes executing the at least two reordering sequences in at least two selected sub-time periods.

15. The method according to claim 14, wherein, The step of reordering the state data includes: executing the at least two reordering sequences simultaneously with programming operations corresponding to the at least two reordering sequences during at least two programming pulse application periods.

16. A memory system, comprising A memory controller is configured to transform data received from the host based on a first state data sorting to generate write data; and The non-volatile memory device is configured as follows: The write data received from the memory controller is stored as status data in each of multiple page buffers. The memory cells are programmed based on state data, and Simultaneously with the programming of the memory cells, a state data reordering operation is performed, which includes changing the value of state data stored in each of the plurality of page buffers to change a first state data order to a second state data order, the second state data order being suitable for the programming algorithm.

17. The memory system according to claim 16, wherein, The non-volatile memory device is configured such that during a read operation performed after programming of a memory cell, Data is read from the memory cell based on the first state data sorting, and The data read from the memory cell is output to the memory controller as read data.

18. The memory system according to claim 16, wherein, The non-volatile memory device is configured to perform a state data reordering operation during the programming period in which programming of the memory cell is performed, during the period in which a programming pulse is applied to the memory cell.

19. The memory system according to claim 16, wherein, The non-volatile memory device is configured such that the time required for a state data reordering operation exceeds the time it takes for the programming pulse to be applied. The state data reordering operation is divided into at least two sequences; and The at least two sequences are executed in at least two of the multiple sub-periods in which programming of the memory cells is performed.

20. The memory system of claim 19, wherein, The multiple sub-time periods include multiple programming pulse application time periods, multiple programming recovery time periods, and multiple verification time periods.

Images