Semiconductor devices and integrated circuits including standard cells

Abstract

A semiconductor device is disclosed, comprising: a first active region and a second active region extending in a first direction; a field region between the first active region and the second active region; a gate structure comprising an upper gate electrode and a lower gate electrode, the upper gate electrode overlapping the first active region and extending in a second direction crossing the first direction, the lower gate electrode overlapping the second active region, extending in the second direction, and being on the same line as the upper gate electrode; a gate isolation layer between the upper gate electrode and the lower gate electrode; a source / drain region on a respective side of the upper gate electrode; a contact jumper in the second active region crossing the upper gate electrode and electrically connecting the source / drain region; and a first upper contact extending in the second direction in the field region and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0038257, entitled "Integrated Circuits and Semiconductor Device Including Standard Cell," filed on April 2, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The embodiments relate to integrated circuits and semiconductor devices that include standard units. Background Technology

[0004] With the rapid development of the electronics industry, the performance of semiconductor devices has gradually improved. For example, semiconductor devices can exhibit high reliability, high speed, and / or multifunctionality. To meet these characteristics, the structure of semiconductor devices may become more complex, and semiconductor devices can be highly integrated. Summary of the Invention

[0005] An embodiment can be implemented by providing a semiconductor device comprising: a first active region extending in a first direction; a second active region extending in the first direction; a field region between the first active region and the second active region; a gate structure including an upper gate electrode and a lower gate electrode, the upper gate electrode overlapping the first active region and extending in a second direction intersecting the first direction, the lower gate electrode overlapping the second active region, extending in the second direction, and being on the same line as the upper gate electrode; a gate isolation layer between the upper gate electrode and the lower gate electrode; source / drain regions on corresponding sides of the upper gate electrode; a contact bridging wire in the second active region, the contact bridging wire intersecting the upper gate electrode and electrically connecting the source / drain regions; and a first upper contact extending in the field region in the second direction and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode.

[0006] Embodiments can be realized by providing an integrated circuit including a standard cell including a first active region and a second active region having different conductivity types and each extending in a first direction; a field region between the first active region and the second active region; a substrate; a first wire extending in a second direction crossing the first direction, the first wire being on the substrate in the first active region, the second active region, and the field region; an isolation insulating layer in the field region, the isolation insulating layer separating the first wire into a first upper wire and a first lower wire, and electrically insulating the first upper wire from the first lower wire from each other; a first lower contact in the field region and on the first lower wire; a first upper contact in the field region and on the first lower contact, the first upper contact extending in the second direction and overlapping the isolation insulating layer; and a contact jumper in the first active region, the contact jumper crossing the first upper wire, wherein the contact jumper is at a same or lower level than the first upper contact with respect to a main surface of the substrate.

[0007] Embodiments can be realized by providing an integrated circuit including a standard cell including a first active region and a second active region having different conductivity types and each extending in a first direction; a field region between the first active region and the second active region; an upper wire in the first active region, the upper wire extending in a second direction crossing the first direction; a lower wire in the second active region and the field region, the lower wire extending in the second direction, spaced apart from the upper wire in the second direction, and on a same line as the upper wire; an interconnect wire in the field region, the interconnect wire extending in the first direction and between the upper wire and the lower wire in a plan view; and an upper contact in the field region, the upper contact extending in the second direction and overlapping the interconnect wire and the lower wire, wherein the lower wire is electrically connected to the interconnect wire, and the upper wire is electrically insulated from the lower wire. BRIEF DESCRIPTION OF DRAWINGS

[0008] Features will become apparent to those of ordinary skill in the art upon examination of the following details. It is also intended that all such embodiments can be obtained and practiced within the scope of the application.

[0009] Figure 1 A layout view illustrating a partial configuration of an integrated circuit including a unidirectional standard cell according to an example embodiment is shown.

[0010] Figure 2 A cross-sectional view taken along line I-I’ of Figure 1 is shown.

[0011] Figure 3 A cross-sectional view taken along line II-II’ of Figure 1 is shown.

[0012] Figure 4a , Figure 5a and Figure 6a shows an enlarged view of a portion of the layout diagram of Figure 1 .

[0013] Figure 4b illustrates a cross-sectional view taken along line I-I' of Figure 4a .

[0014] Figure 5b illustrates a cross-sectional view taken along line I-I' of Figure 5a .

[0015] Figure 6b illustrates a cross-sectional view taken along line I-I' of Figure 6a .

[0016] Figure 7 illustrates a circuit diagram showing a cross-coupled structure XC according to an example embodiment.

[0017] Figure 8 illustrates a layout diagram of a portion of a unidirectional standard cell having a cross-coupled structure XC according to an example embodiment.

[0018] Figure 9 illustrates a circuit diagram showing a multiplexer including a cross-coupled structure XC according to an example embodiment.

[0019] Figure 10 illustrates a layout diagram of a portion of a unidirectional standard cell of a multiplexer having a cross-coupled structure XC according to an example embodiment.

[0020] Figure 11 illustrates a layout diagram of a portion of a unidirectional standard cell of a multiplexer having a cross-coupled structure XC according to an example embodiment. DETAILED DESCRIPTION

[0021] Figure 1 illustrates a layout diagram of a portion of a configuration of an integrated circuit including a unidirectional standard cell according to an example embodiment. Figure 2 illustrates a cross-sectional view taken along line I-I' of Figure 1 . Figure 3 illustrates a cross-sectional view taken along line II-II' of Figure 1 . Figure 2 and Figure 3 The semiconductor device shown in Figure 1 may be an example of a semiconductor device implemented according to a layout.

[0022] In Figure 1In the present embodiment, for ease of description, only a portion of the unidirectional standard cell is shown, and the unidirectional standard cell can be designed to further include other components. In one embodiment, as shown in FIG. 1A, the unidirectional standard cell can have an Ml interconnection structure having four tracks Tl, T2, T3, and T4. In one embodiment, the unidirectional standard cell can further include an M2 interconnection structure higher in level than the Ml interconnection structure. Figure 1

[0023] In the present specification, the term "Ml interconnection structure" can refer to an interconnection line formed at a level closest to a plurality of conductive lines among a plurality of interconnection lines formed in a plurality of layers. The plurality of interconnection lines constituting the "Ml interconnection structure" can be a plurality of unidirectional interconnection layers extending in parallel to each other in a direction crossing an extension direction of the plurality of conductive lines.

[0024] Referring to FIG. 1A, Figures 1 to 3 The integrated circuit 100a can include a substrate 101, a first active region ARl, a second active region AR2, a field region FR, active fins AF1 and AF2, first to third conductive lines CLa, CLb, and CLc, a source / drain contact CA, a contact jumper JP, a lower contact CB, an upper contact CM, a via V0, a gate isolation layer GI, and an interconnection line Ml. The integrated circuit 100a can be designed using a standard cell library, and the first active region ARl and the second active region AR2, the first to third conductive lines CLa, CLb, and CLc, the cut layer CT, and the contact jumper JP can be a portion of a standard cell.

[0025] The substrate 101 can be, for example, a semiconductor substrate. The substrate 101 can include, for example, silicon (Si), strained silicon, a silicon alloy, silicon carbide (SiC), silicon germanium (SiGe), silicon germanium carbide (SiGeC), germanium (Ge), a germanium alloy, gallium arsenide (GaAs), indium arsenide (InAs), a III-V semiconductor, a II-VI semiconductor, a combination thereof, or a laminate thereof. In one embodiment, the substrate 101 can be an organic plastic substrate rather than a semiconductor substrate. As used herein, the term "or" is not an exclusive term, for example, "A or B" can include A, B, or both A and B. Hereinafter, an embodiment in which the substrate 101 is made of silicon is described.

[0026] ​The first active region AR1 and the second active region AR2 can extend in a first direction (e.g., a longitudinal direction) and can be parallel to each other (e.g., and spaced apart) in a second direction substantially perpendicular to the first direction. The first active region AR1 and the second active region AR2 can have different conductivity types. In one embodiment, the first active region AR1 can be a p-channel metal-oxide-semiconductor (PMOS) region and the second active region AR2 can be an n-channel metal-oxide-semiconductor (NMOS) region. In one embodiment, the first active region AR1 can be an NMOS region and the second active region AR2 can be a PMOS region. The first active region AR1 and the second active region AR2 can be spaced apart from each other in the second direction and the field region FR can be between the first active region AR1 and the second active region AR2.

[0027] The first active fin AF1 and the second active fin AF2 can extend in the first direction and can be parallel to each other (e.g., and spaced apart) in the second direction. In one embodiment, the first active fin AF1 and the second active fin AF2 can be spaced apart from each other by a spacing. The first active fin AF1 can be in the first active region AR1 and the second active fin AF2 can be in the second active region AR2. According to example embodiments, the number of the first active fin AF1 and the second active fin AF2 in the integrated circuit 100a can be varied differently. In one embodiment, a dummy fin can be in the field region FR.

[0028] The device isolation layer 103 can be on the substrate 101 and can cover a portion of the first active fin AF1 and the second active fin AF2. The device isolation layer 103 can include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0029] The first to third conductive lines CLa, CLb, and CLc can cross the first active region AR1, the second active region AR2, and the field region FR in the second direction and can be parallel to each other and spaced apart in the first direction. The first to third conductive lines CLa, CLb, and CLc can be made of a suitable material having electrical conductivity and can include, for example, polysilicon, metal, metal alloy, etc. In one embodiment, the first to third conductive lines CLa, CLb, and CLc can correspond to gate electrodes or gate structures. In one embodiment, the first to third conductive lines CLa, CLb, and CLc can be any traces having electrical conductivity.

[0030] In the example embodiments shown, the first to third conductive lines CLa, CLb, and CLc can correspond to gate structures. The gate structures can include a gate insulating layer 111, gate electrodes 113 and 115, a gate spacer 117, and a gate capping layer 119. Figures 1 to 3 In the example embodiments shown, the first to third conductive lines CLa, CLb, and CLc can correspond to gate structures. The gate structures can include a gate insulating layer 111, gate electrodes 113 and 115, a gate spacer 117, and a gate capping layer 119.

[0031] The gate insulating layer 111 can be made of, for example, a silicon oxide film, a high-k dielectric film, or a combination thereof. The high-k dielectric film can be a material having a higher dielectric constant than a silicon oxide film. In one embodiment, the gate insulating layer 111 can include, for example, a metal oxide or a metal oxynitride having a dielectric constant of about 10 to 25. In one embodiment, the high-k dielectric film can include, for example, hafnium oxide.

[0032] The gate electrodes 113 and 115 can be formed in multiple layers. For example, the gate electrodes 113 and 115 can include a first gate electrode 113 and a second gate electrode 115. The first gate electrode 113 can include, for example, Ti, Ta, W, Ru, Nb, Mo, or Hf. The second gate electrode 115 can include, for example, W or Al. The gate structure can include a work function metal-containing layer. The work function metal-containing layer can include, for example, Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or P. The gate structure can include, for example, a TiAlC / TiN / W layer stack, a TiN / TaN / TiAlC / TiN / W layer stack, or a TiN / TaN / TiN / TiAlC / TiN / W layer stack.

[0033] The gate spacers 117 can be on both sidewalls of the gate insulating layer 111, the first gate electrode 113, and the second gate electrode 115. The gate spacers 117 can be made of, for example, a silicon nitride film, SiOCN, SiCN, or a combination thereof.

[0034] Between the gate spacers 117, a gate capping layer 119 can be on the gate insulating layer 111, the first gate electrode 113, and the second gate electrode 115. The gate capping layer 119 can include a nitride and can include, for example, SiN.

[0035] The cut layer CT can extend in the first direction between the first active region AR1 and the second active region AR2, and can cross the first conductive line CLa. In one embodiment, at least a portion of the cut layer CT can be in the first active region AR1. The cut layer CT can be a marker layer for cutting a portion of the first conductive line CLa. In the integrated circuit 100a manufactured according to the layout including the cut layer CT, the first conductive line CLa can be separated into an upper conductive line CLau (crossing the first active region AR1) and a lower conductive line CLad (crossing the second active region AR1) with respect to or through the cut layer CT. In one embodiment, the gate structure corresponding to the first conductive line CLa can include an upper gate structure and a lower gate structure extending substantially on or along the same line, e.g., along the line I-I'. The upper gate structure can include an upper gate electrode, an upper gate insulating layer, an upper gate spacer, and an upper gate capping layer, and the lower gate structure can include a lower gate electrode, a lower gate insulating layer, a lower gate spacer, and a lower gate capping layer.

[0036] A portion of the first conductive line CLa (e.g., the portion has been removed or does not exist in the region overlapping the cut layer CT) can be filled with a gate isolation layer GI. The gate isolation layer GI can be referred to as an isolation insulating layer. The gate isolation layer GI can be made of nitride and can include, for example, silicon nitride (SiN). In one embodiment, the gate isolation layer GI can be made of the same material as the first interlayer insulating layer 121 on the conductive lines CLa, CLb, and CLc. The upper conductive line CLau and the lower conductive line CLad can be electrically insulated from each other by the gate isolation layer GI. For example, the upper conductive line CLau can be in an electrically floating state, and can prevent unnecessary power consumption in the region where the jumper JP exists.

[0037] In one embodiment, a width of the gate isolation layer GI in the first direction can be greater than a width of the first conductive line CLa in the first direction. In one embodiment, the width of the gate isolation layer GI in the first direction can correspond to or be the same as the width of the first conductive line CLa.

[0038] The source / drain regions SD can be on the first and second active fins AF1, AF2. The source / drain regions SD can each be on both sides of the conductive lines CLa, CLb, and CLc. The source / drain regions SD in the PMOS region can include a compressive stress material. In one implementation, the compressive stress material can be a material having a lattice constant greater than that of Si, and can be, for example, SiGe. The compressive stress material can apply a compressive stress to the PMOS region, which can improve the mobility of the charge carriers in the channel region. The source / drain regions SD in the NMOS region can include a tensile stress material. In one implementation, when the substrate 101 is made of Si, the source / drain regions SD can include Si or can include a material having a lattice constant smaller than that of Si (e.g., SiC).

[0039] The source / drain contacts CA can extend in the second direction, and can each be in the first and second active regions AR1, AR2. Each of the source / drain contacts CA can be between two conductive lines adjacent to each other along the first direction. The source / drain contacts CA can be on the source / drain regions SD and can be electrically connected to the source / drain regions SD, respectively. The source / drain contacts CA can be referred to as a source / drain contact pattern or a source / drain contact plug. The source / drain contacts CA can include an electrically conductive material. The source / drain contacts CA can include, for example, polysilicon, a metal silicide compound, an electrically conductive metal nitride, or a metal. In one implementation, the source / drain contacts CA can include, for example, W.

[0040] The contact jumper JP can be in the first active region AR1. The contact jumper JP can refer to a conductor having a relatively short length for connecting any two points or two terminals in an integrated circuit, and can be referred to as a “jumper.”

[0041] The contact jumper JP can be above the upper conductive lines CLau to cross the upper conductive lines CLau in the first direction. The contact jumper JP can be above the upper conductive lines CLau. A lower (e.g., substrate-facing) surface of the contact jumper JP can be at or above a level of an upper (e.g., jumper-facing) surface of the gate structures or the gate cap layer 119 (e.g., a distance from a surface of the substrate 101 to the substrate-facing surface of the contact jumper JP can be greater than or equal to a distance from the surface of the substrate 101 to the jumper-facing surface of the gate structures or the gate cap layer 119). A width of the contact jumper JP in the second direction can correspond to (e.g., be equal to) or be greater than a width of the source / drain contacts CA in the first direction, and can correspond to (e.g., be equal to) or be less than a width of the source / drain contacts CA in the second direction.

[0042] The contact jumper JP can be connected to each of the source / drain contacts CA on both sides of the upper conductive line CLau. The contact jumper JP can electrically connect the regions on both sides of the upper conductive line CLau. Through the contact jumper JP, the potentials of the impurity regions on both sides of the upper conductive line CLau can be made equal to each other. The upper conductive line CLau can be a dummy conductive line, such as a jump line, rather than a real conductive line. In one embodiment, the upper gate electrode corresponding to the upper conductive line CLau can be a dummy gate electrode. In one embodiment, the contact jumper JP can include the same conductive material as the source / drain contacts CA.

[0043] The interlayer insulating layers 121, 123, and 125 can be in the first active region AR1 and the second active region AR2, and can cover the conductive lines CLa, CLb, and CLc, the lower contacts CB, the upper contacts CM, and the via V0. The first interlayer insulating layer 121 can be used for electrical insulation of the lower contacts CB. The second interlayer insulating layer 123 can be used for electrical insulation of the upper contacts CM. The first interlayer insulating layer 121 and / or the second interlayer insulating layer 123 can be used for electrical insulation of the contacts CB and CM and the jumper JP. The third interlayer insulating layer 125 can be used for electrical insulation of the via V0. In one embodiment, the first interlayer insulating layer 121 can be integrally formed with the gate isolation layer GI. For example, an insulating material can be formed to cover the conductive lines while filling the space corresponding to the cut layer CT between the upper conductive line CLau and the lower conductive line CLad, thereby forming the gate isolation layer GI and the first interlayer insulating layer 121. In one embodiment, the interlayer insulating layers 121, 123, and 125 can be formed using silicon oxide, such as borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), tetraethyl orthosilicate (TEOS) glass, high-density plasma chemical vapor deposition (HDP-CVD) glass, etc.

[0044] The interconnect lines Mla, Mlb, and Mlc can be above (e.g., relative to the substrate 101) the conductive lines CLa, CLb, and CLc to cross the conductive lines CLa, CLb, and CLc. The plurality of interconnect lines Mla, Mlb, and Mlc can be used for signal routing. The interconnect lines Mla, Mlb, and Mlc can have a unidirectional structure extending in a first direction, and can be coplanar. The interconnect lines Mla, Mlb, and Mlc can all have substantially the same width. The interconnect lines Mla, Mlb, and Mlc can correspond to a first level located at a lowermost portion of a back-end-of-line (BEOL) of the integrated circuit.

[0045] A standard cell having a low cell height can be implemented using an M1 interconnection structure extending in one direction in parallel, and a wide width of a power rail can be secured. Accordingly, the integration of the standard cell can be increased, and thus the standard cell can be applied to a miniaturization process.

[0046] The first interconnection line Mla can be arranged such that at least a portion thereof overlaps the gate isolation layer GI in a plan view. The first interconnection line Mla can be in the field region FR, and can be closer to the first active region AR1 than the second active region AR2. The first interconnection line Mla can be along the third trace T3. In a plan view, the first interconnection line Mla can be located in a position corresponding to a position of the first conductive line CLa in the second direction.

[0047] The second interconnection line Mlb can be above the second conductive line CLb, and the third interconnection line Mlc can be above the third conductive line CLc. The second interconnection line Mlb and the third interconnection line Mlc can extend in the first direction, which is the same as the extension direction of the first interconnection line Mla. The second interconnection line Mlb and the third interconnection line Mlc can be on or extend along the same line along the second trace T2, and can be spaced apart from each other in the first direction. In a plan view, the second interconnection line Mlb can be disposed on one side of the first upper contact CMa, and the third interconnection line Mlc can be on the other side of the first upper contact CMa. The second interconnection line Mlb and the third interconnection line Mlc can be spaced apart from the first interconnection line Mla in the second direction. The second interconnection line Mlb and the third interconnection line Mlc can be in the field region FR, and can be closer to the second active region AR2 than the first active region AR1. A distance from the second interconnection line Mlb or the third interconnection line Mlc to the contact jumper JP in the second direction can be greater than a distance from the first interconnection line Mla to the contact jumper JP in the second direction.

[0048] The first interconnection line Mla can be electrically connected to the lower conductive line CLad of the first conductive line CLa. The first interconnection line Mla can be electrically insulated from the upper conductive line CLau of the first conductive line CLa. The second interconnection line Mlb can be electrically connected to the second conductive line CLb. The third interconnection line Mlc can be electrically connected to the third conductive line CLc.

[0049] The electrical connection between each interconnection line Ml and the conductive lines CLa, CLb, and CLc can be through or via the lower contact CB, the upper contact CM, and the via V0. The lower contact CB can be on the conductive line CL, the upper contact CM can be on the lower contact CB, and the via V0 can be on the upper contact CM.

[0050] The lower contact CB can be in the field region FR between the first active region AR1 and the second active region AR2. By arranging the lower contact CB in the field region FR without arranging the lower contact CB in the second active region AR2, sufficient distance can be ensured between the lower contact CB and the source / drain contact CA. The first lower contact CBa can be on the lower wire CLad of the first wire CLa, the second contact CBb can be on the second wire CLb, and the third contact CBc can be on the third wire CLc. The first to third contacts CBa, CBb, and CBc can be substantially in line in the first direction.

[0051] In one embodiment, the first upper contact CMa can have a bar shape extending in the second direction on the second lower contact CBa. The first upper contact CMa can be referred to as a "bridge pattern". In a plan view, a lower portion of the first upper contact CMa can be between the second interconnect line Mlb and the third interconnect line Mlc, and in the plan view, the lower portion of the first upper contact CMa can extend in the second direction such that an upper portion of the first upper contact CMa can overlap the gate isolation layer GI and the first interconnect line Mla. In the plan view, the first upper contact CMa and the first interconnect line Mla can have extending directions perpendicular to each other. A width of the first upper contact CMa in the first direction can be smaller than a shortest distance between the second interconnect line Mlb and the third interconnect line Mlc in the first direction.

[0052] The first via V0a can be between and connected to each of the first upper contact CMa and the first interconnect line Mla. The first via V0a can electrically connect the first upper contact CMa to the first interconnect line Mla. In a plan view, the first via V0a can overlap the gate isolation layer GI, the first upper contact CMa, and the first interconnect line Mla.

[0053] The second upper contact CMb can be on the second lower contact CBb, and the second via V0b can be on the second upper contact CMb. The second lower contact CBb, the second upper contact CMb, the second via V0b, and the second interconnect line Mlb (hereinafter, referred to as a second structure) can overlap each other and can be electrically connected to each other in a plan view. The third lower contact CBc, the third upper contact CMc, the third via V0c, and the third interconnect line Mlc can also be configured in the same manner as the second structure. In one embodiment, the upper contact CM can be located at the same level as the jumper JP from or relative to a main surface of the substrate 101. In one embodiment, the upper contact CM can be located at a higher level than the jumper JP from or relative to a main surface of the substrate 101.

[0054] In one embodiment, the first lower contact CBa, the first upper contact CMa, the first via V0a, and the first interconnect line Mla can be electrically connected to a lower wire CLad (i.e., a lower gate electrode) of the first wire CLa, and can be electrically insulated from an upper wire CLau (i.e., an upper gate electrode) of the first wire CLa.

[0055] Figure 4a 、 Figure 5a and Figure 6a shows Figure 1 an enlarged view of a portion of a layout view. Figure 4b illustrates a cross-sectional view taken along line I-I’ of Figure 4a . Figure 5b illustrates a cross-sectional view taken along line I-I’ of Figure 5a . Figure 6b illustrates a cross-sectional view taken along line I-I’ of Figure 6a . In Figure 4a , Figure 5a and Figure 6a , for simplicity, the jumper, the interlayer insulating layer, and the gate cover layer are omitted. In Figures 1 to 6b , like reference numerals refer to like components, and for simplicity, the description of the like components can be omitted.

[0056] Referring to Figure 4a and Figure 4b , the unidirectional standard cell 100b can include a first lower contact CBa on a lower wire CLad of the first wire CLa, a first upper contact CMa on the first lower contact CBa, and a first interconnect line Mla on the first upper contact CMa. For example, a first via V0a between the first upper contact CMa and the first interconnect line Mla (see Figure 2 ) can be omitted, and an upper surface of the first upper contact CMa can be in direct contact with a lower surface of the first interconnect line Mla. A height (e.g., relative to a main surface of the substrate 101) of the first upper contact CMa can be less than or substantially equal to a sum of heights of the first upper contact CMa and the first via V0a of Figure 2 .

[0057] Referring to Figure 5a and Figure 5b , the unidirectional standard cell 100c can include a first upper contact CMa on a lower wire CLad of the first wire CLa and a gate isolation layer GI, and a first via V0a and a first interconnect line Mla on the first upper contact CMa. For example, a first lower contact CBa between the first upper contact CMa and the first wire CLa (see Figure 2), and the first upper contact CMa can be directly connected to a lower wire CLad (i.e., a lower gate electrode) of the first wire CLa. A lower surface of the first upper contact CMa can be in contact with the lower wire CLad. The lower surface of the first upper contact CMa can be in contact with the gate isolation layer GI. In one embodiment, the first upper contact CMa can be in contact with the gate cover layer. The first upper contact CMa can be spaced apart from an upper wire CLau (i.e., an upper gate electrode).

[0058] Referring to Figure 6a and Figure 6b , the unidirectional standard cell 100d can include a first upper contact CMa on a lower wire CLad of the first wire CLa and the gate isolation layer GI. For example, the first lower contact CBa and the first via VOa (see Figure 2 ) can be omitted, the first upper contact CMa can be connected to be in direct contact with the lower wire CLad, and the first upper contact CMa can be connected to be in direct contact with the first interconnection line Mla.

[0059] Figure 7 FIG. 13 illustrates a circuit diagram showing a cross-coupled structure XC according to an example embodiment.

[0060] Referring to Figure 7 , the cross-coupled structure XC can include a first PMOS transistor PM1 and a first NMOS transistor NM1 connected in series to each other, and a second PMOS transistor PM2 and a second NMOS transistor NM2 connected in series to each other. For example, the cross-coupled structure XC can be included in various standard cells including sequential logic cells such as latches, flip-flops, etc., or combinational logic cells such as multiplexers, adders, etc.

[0061] The first PMOS transistor PM1 can have a source connected to a first voltage terminal V1, a gate receiving a first control signal SO, and a drain connected to an output terminal Y. The first NMOS transistor NM1 can have a drain connected to the output terminal Y, a gate receiving a second control signal nSO, and a source connected to a second voltage terminal V2. The second PMOS transistor PM2 can have a source connected to a third voltage terminal V3, a gate receiving the second control signal nSO, and a drain connected to the output terminal Y. The second NMOS transistor NM2 can have a drain connected to the output terminal Y, a gate receiving the first control signal SO, and a source connected to a fourth voltage terminal V4.

[0062] In one embodiment, the gates of the first PMOS transistor PM1 and the second NMOS transistor NM2 can be electrically connected to each other to receive a first control signal SO. In one embodiment, the gates of the first NMOS transistor NM1 and the second PMOS transistor PM2 can be electrically connected to each other to receive a second control signal nSO. Thus, the first and second PMOS transistors PM1, PM2 and the first and second NMOS transistors NM1, NM2 can constitute a cross-coupled structure XC.

[0063] Figure 8 A layout diagram of a portion of a unidirectional standard cell having a cross-coupled structure XC is illustrated according to an example embodiment. According to Figure 8 the cross-coupled structure XC of a unidirectional standard cell of an example embodiment can correspond to Figure 7 the cross-coupled structure XC of a unidirectional standard cell of an example embodiment. In Figure 8 for ease of description, only a portion of a unidirectional standard cell is illustrated, and the unidirectional standard cell can be designed to further include other components. For example, the unidirectional standard cell can also include a second interconnect structure arranged at a higher level than the M1 interconnect from the main surface of the substrate.

[0064] Referring to Figure 8 , power rails can be respectively at the uppermost and lowermost portions of the unidirectional standard cell 200. Each respective power rail can be a power terminal VDD or a ground terminal VSS. In one embodiment, the power rail on the uppermost portion can be the ground terminal VDD, and the power rail on the lowermost portion can be the ground terminal VSS.

[0065] The unidirectional standard cell 200 can be defined by an upper boundary line (UBL) and a lower boundary line (LBL), and can further include different circuits at its left and right sides, respectively.

[0066] The unidirectional standard cell 200 can include first and second active regions AR1, AR2, conductive lines CL1, CL2, and CL3, source / drain contacts CA, jumper lines JP1 and JP2, lower contacts CB, upper contacts CM, cut layers CT, vias V0, and interconnect lines M1.

[0067] The first and second active regions AR1, AR2, the first and second conductive lines CL1, CL2, the first and second lower contacts CB1, CB2, the first and second upper contacts CM1, CM2, the first and second vias V01, V02, the first jumper line JP1, and the first cut layer CT1 can have the same configurations as those described with reference to Figures 1 to 3The structures corresponding to the first active region AR1 and the second active region AR2, the first and second conductive lines CLa and CLb, the first and second lower contacts CBa and CBb, the first and second upper contacts CM1 and CM2, the first and second vias V0a and V0b, the jumper JP, and the cut layer CT are described, and repetitive descriptions thereof can be omitted.

[0068] In the unidirectional standard cell 200, the third conductive line CL3, the second cut layer CT2, the third lower contact CB3, the third upper contact CM3, the third via V03, and the third interconnect line M13 can be on the (e.g., right) side of the second conductive line CL2. The region corresponding to the second cut layer CT2 can be removed so that the third conductive line CL3 can be separated into a second upper conductive line CL3u and a second lower conductive line CL3d. A gate isolation layer (or an isolation insulating layer) can be on the region corresponding to the second cut layer CT2.

[0069] The unidirectional standard cell 200 can include a second contact jumper JP2 connecting the source / drain contacts CA on both sides of the third conductive line CL3 to the source / drain contacts CA on both sides of the second lower conductive line CL3d.

[0070] The unidirectional standard cell 200 can include a fourth interconnect line M14 and a first output contact Ya in the first active region AR1, and a fifth interconnect line M15 and a second output contact Yb in the second active region AR2.

[0071] Referring to Figure 7 and Figure 8 the second conductive line CL2 and the source / drain regions on both sides of the second conductive line CL2 in the first active region AR1 can function as a first transistor PM1, and the third conductive line CL3 and the source / drain regions on both sides of the third conductive line CL3 in the first active region AR1 can function as a second transistor PM2. In one embodiment, the first transistor PM1 and the second transistor PM2 can be PMOS transistors.

[0072] The lower conductive line CL1d of the first conductive line CL1 and the source / drain regions on both sides of the lower conductive line CL1d in the second active region AR2 can function as a third transistor NM1, and the second conductive line CL2 and the source / drain regions on both sides (e.g., respective sides) of the second conductive line CL2 in the second active region AR2 can function as a fourth transistor NM2. In one embodiment, the third transistor NM1 and the fourth transistor NM2 can be NMOS transistors.

[0073] The second conductor CL2 can be gated by the first control signal SO, and the first conductor CL1 and the third conductor CL3 can be gated by the second control signal nSO. The drains of the first transistor PM1 and the second transistor PM2 can be connected to the first output contact Ya, and the drains of the third transistor NM1 and the fourth transistor NM2 can be connected to the second output contact Yb. The first output contact Ya can be connected to the fourth interconnect line M14, and the second output contact Yb can be connected to the fifth interconnect line M15. The first output contact Ya and the second output contact Yb can be electrically connected to the output terminal Y. The fourth interconnect line M14 and the fifth interconnect line M15 can be connected to the output terminal Y.

[0074] Figure 9 A circuit diagram illustrating a multiplexer including a cross-coupled structure XC according to an example embodiment is illustrated.

[0075] Referring to Figure 9 , the multiplexer can include a first tri-state inverter TIVTa and a second tri-state inverter TIVTb. The first tri-state inverter TIVTa and the second tri-state inverter TIVTb can share an output terminal Y with each other, and can be arranged to face each other. The multiplexer can be implemented as a standard cell. The cross-coupled structure XC can correspond to Figure 7 the cross-coupled structure XC of

[0076] The first tri-state inverter TIVTa can include a first PMOS transistor PM1 and a third PMOS transistor PM3, and a first NMOS transistor NM1 and a third NMOS transistor NM3. For example, the third PMOS transistor PM3 can include a source connected to a power terminal VDD, and a gate to which a data input signal D is applied, and the third NMOS transistor NM3 can include a source connected to a ground terminal VSS, and a gate to which the data input signal D is applied. The first PMOS transistor PM1 can include a source connected to a drain of the third PMOS transistor PM3, a gate to which a scan enable signal SE is applied, and a drain connected to the output terminal Y. The first NMOS transistor NM1 can include a drain connected to the first PMOS transistor PM1 and the output terminal Y, a gate to which an inverse scan enable signal NSE is applied, and a source connected to the third NMOS transistor NM3.

[0077] The second tri-state inverter TIVTb can include a second PMOS transistor PM2 and a fourth PMOS transistor PM4, and a second NMOS transistor NM2 and a fourth NMOS transistor NM4. For example, the fourth PMOS transistor PM4 can include a source connected to the power terminal VDD, and a gate to which the scan input signal SI is applied, and the fourth NMOS transistor NM4 can include a source connected to the ground terminal VSS, and a gate to which the scan input signal SI is applied. The second PMOS transistor PM2 can include a source connected to a drain of the fourth PMOS transistor PM4, a gate to which the inverse scan enable signal NSE is applied, and a drain connected to the output terminal Y. The second NMOS transistor NM2 can include a drain connected to the second PMOS transistor PM2 and the output terminal Y, a gate to which the scan enable signal SE is applied, and a source connected to the fourth NMOS transistor NM4.

[0078] As described above, according to an example embodiment, the scan enable signal SE can be applied to the gates of the first PMOS transistor PM1 and the second NMOS transistor NM2, and the inverse scan enable signal NSE can be applied to the gates of the first NMOS transistor NM1 and the second PMOS transistor PM2. For example, the first PMOS transistor PM1 and the second PMOS transistor PM2, and the first NMOS transistor NM1 and the second NMOS transistor NM2 can constitute a cross-coupled structure XC. According to an example embodiment, the cross-coupled structure XC can be implemented as a standard cell including Figure 8 According to an example embodiment, the multiplexer circuit can be implemented as a standard cell including Figures 1 to 6b described with reference to FIG. 1.

[0079] Figure 10 FIG. 2 illustrates a layout view of a portion of a unidirectional standard cell of a multiplexer having a cross-coupled structure XC according to an example embodiment. In Figure 8 and Figure 10 the same reference numerals denote the same components, and repeated description of the same components can be omitted for simplicity.

[0080] The unidirectional standard cell according to Figure 10 may correspond to the multiplexer according to Figure 9 In Figure 10 , for convenience of description, only a portion of the unidirectional standard cell is illustrated, and the unidirectional standard cell can be designed to further include other components. For example, the unidirectional standard cell can further include an interconnection structure arranged at a higher level than the M1 interconnection from the main surface of the substrate.

[0081] Referring to Figure 10In the unidirectional standard cell 300, the fourth conductive line CL4, the fourth lower contact CB4, the fourth upper contact CM4, the fourth via V04, and the sixth interconnect line M16 can be on the (e.g., right) side of the third conductive line CL3. In one embodiment, in the unidirectional standard cell 300, the fifth conductive line CL5, the fifth lower contact CB5, the fifth upper contact CM5, the fifth via V05, and the seventh interconnect line M17 can be on the (e.g., left) side of the first conductive line CL1. In one embodiment, a cross-sectional view taken along the line I-I’ of Figure 10 may correspond to the cross-sectional view of Figure 2 .

[0082] Referring to Figure 9 and Figure 10 , the second conductive line CL2 on the first active region AR1 and the source / drain regions on both sides of the second conductive line CL2 can function as a first transistor PM1, and the third conductive line CL3 in the first active region AR1 and the source / drain regions on both sides of the third conductive line CL3 can function as a second transistor PM2. In one embodiment, the first transistor PM1 and the second transistor PM2 can be PMOS transistors.

[0083] The fourth conductive line CL4 in the first active region AR1 and the source / drain regions on both sides of the fourth conductive line CL4 can function as a fourth transistor PM4, and the fifth conductive line CL5 in the first active region AR1 and the source / drain regions on both sides of the fifth conductive line CL5 can function as a third transistor PM3. In one embodiment, the third transistor NM3 and the fourth transistor NM4 can be PMOS transistors.

[0084] The lower conductive line CL1d of the first conductive line CL1 in the second active region AR2 and the source / drain regions on both sides of the lower conductive line CL1d can function as a fifth transistor NM1, and the second conductive line CL2 in the second active region AR2 and the source / drain regions on both sides of the second conductive line CL2 can function as a sixth transistor NM2. In one embodiment, the fifth transistor NM1 and the sixth transistor NM2 can be NMOS transistors.

[0085] The fourth conductive line CL4 in the second active region AR2 and the source / drain regions on both sides of the fourth conductive line CL4 can function as a seventh transistor NM4, and the fifth conductive line CL5 in the second active region AR2 and the source / drain regions on both sides of the fifth conductive line CL5 can function as an eighth transistor NM3. In one embodiment, the seventh transistor NM4 and the eighth transistor PM3 can be NMOS transistors.

[0086] The second conductive line CL2 can be gated by a scan enable signal SE, and the first conductive line CL1 and the third conductive line CL3 can be gated by a negative scan enable signal NSE. The fourth conductive line CL4 can be gated by a scan input signal SI, and the fifth conductive line CL5 can be gated by a data input signal D.

[0087] The drain of the first transistor PM1 and the second transistor PM2 can be electrically connected to a first output contact Ya, and the drain of the third transistor PM3 can be electrically connected to the source of the first transistor PM1. The drain of the fourth transistor PM4 can be electrically connected to the source of the second transistor PM2. The drains of the fifth transistor NM1 and the sixth transistor NM2 can be electrically connected to a second output contact Yb. The drain of the seventh transistor NM4 can be electrically connected to the source of the sixth transistor NM2, and the drain of the eighth transistor NM3 can be electrically connected to the source of the fifth transistor NM1.

[0088] The first output contact Ya can be connected to a fourth interconnect line M14, and the second output contact Yb can be connected to a fifth interconnect line M15. The first output contact Ya and the second output contact Yb can be electrically connected to an output terminal Y. The fourth interconnect line M14 and the fifth interconnect line M15 can be connected to the output terminal Y.

[0089] Figure 11 A layout view of a portion of a unidirectional standard cell of a multiplexer having a cross-coupled structure XC is illustrated, according to an example embodiment. For example, Figure 11 The unidirectional standard cell of can have an M1 interconnect structure having five traces T1, T2, T3, T4, and T5.

[0090] Figure 11 The unidirectional standard cell of can correspond to Figure 9 The unidirectional standard cell of a multiplexer. In Figure 11 In, for ease of description, only a portion of the unidirectional standard cell is shown, and the unidirectional standard cell can be designed to further include other components. For example, the unidirectional standard cell can also include an interconnect structure arranged at a higher level from the main surface of the substrate than the M1 interconnect structure.

[0091] Referring to Figure 11 The unidirectional standard cell 400 can include a first active region AR1 and a second active region AR2, conductive lines CL1, CL2, CL3, CL4, and CL5, a source / drain contact CA, a lower contact CB, an upper contact CM, a cut layer CT, a via V0, and an interconnect line M1.

[0092] The area corresponding to the first cut layer CT1 can be removed so that the first conductive line CL1 can be separated into a first upper conductive line CL1u and a first lower conductive line CL1d. The area corresponding to the second cut layer CT2 can be removed so that the third conductive line CL3 can be separated into a second upper conductive line CL3u and a second lower conductive line CL3d. A gate isolation layer (or an isolation insulating layer) can be on each area corresponding to the first cut layer CT1 and the second cut layer CT2. In one embodiment, the first cut layer CT1 can be adjacent to the first active region AR1 and can overlap the third trace T3 and / or the fourth trace T4. The second cut layer CT2 can be close to the second active region AR2 and can overlap the second trace T2 and / or the third trace T3.

[0093] The first to fifth interconnection lines M11, M12, M13, M14, and M15 can be on the first to fifth traces T1, T2, T3, T4, and T5, respectively, which extend in a first direction and are spaced apart from each other in a second direction. The first to fifth traces T1, T2, T3, T4, and T5 can be sequentially arranged from the second active region AR2 to the first active region AR1. The first trace T1 can be in the second active region AR2, the fifth trace T5 can be in the first active region AR1, and the second to fourth traces T2, T3, and T4 can be between the first active region AR1 and the second active region AR2. The second trace T2 can be adjacent to the second active region AR2, the fourth trace T4 can be adjacent to the first active region AR1, and the third trace T3 can be between the second trace T2 and the fourth trace T4.

[0094] In one embodiment, the first interconnection line M11 can be on the third trace T3, the second interconnection line M12 can be on the second trace T2, and the third interconnection line M13 can be on the fourth trace T4. The fourth interconnection line M14 can be on the fifth trace T5, and the fifth interconnection line M15 can be on the first trace T1.

[0095] In a plan view, at least a portion of the first interconnection line M11 can overlap the first cut layer CT1 (or the gate isolation layer). In the plan view, the first interconnection line M11 can be located at a position crossing the first conductive line CL1. In the plan view, the second interconnection line M12 can cross the second conductive line CL2, and the third interconnection line M13 can cross the third conductive line CL3.

[0096] The first interconnection line Ml1 can be electrically connected to the lower conductive line CL1d of the first conductive line CL1. The second interconnection line M12 can be electrically connected to the second conductive line CL2. The third interconnection line M13 can be electrically connected to the second lower conductive line CL3u of the third conductive line CL3.

[0097] The electrical connection between the respective interconnection line M1 and the respective conductive line CL can be implemented using the lower contact CB, the upper contact CM, and the via V0. The lower contact CB can be on the conductive line CL, the upper contact CM can be on the lower contact CB, and the via V0 can be on the upper contact CM.

[0098] In one embodiment, the first lower contact CB1 can be on an area substantially corresponding to the second trace T2 on the first lower conductive line CL1d. The first via V01 can be on the third trace T3 on the first lower conductive line CL1d. The first upper contact CM1 can extend to the first via V01 in the second direction on the first lower contact CB1. The first lower conductive line CL1d can be electrically connected to the first interconnection line M11 through the first lower contact CB1, the first upper contact CM1, and the first via V01.

[0099] In one embodiment, in the unidirectional standard cell 400, the fourth conductive line CL4, the fourth lower contact CB4, the fourth upper contact CM4, the fourth via V04, and the sixth interconnection line M16 can be on the (e.g., right) side of the third conductive line CL3. In the unidirectional standard cell 400, the fifth conductive line CL5, the fifth lower contact CB5, the fifth upper contact CM5, the fifth via V05, and the seventh interconnection line M17 can be on the (e.g., left) side of the third conductive line CL3. In one embodiment, the sixth interconnection line M16 can be on the second trace T2 or the fourth trace T4. The seventh interconnection line M17 can be on the second trace T2 or the third trace T3.

[0100] By summarizing and reviewing, various methods have been used to implement cross-gate connection circuits in cells such as multiplexers (MUXs) or flip-flops. Methods to improve the spatial efficiency of the overall layout according to the arrangement of gate contacts, source / drain contacts, and interconnections can be considered.

[0101] According to example embodiments, a unidirectional standard cell including a cross-coupling structure can include a jumper and a cut layer, and can improve power efficiency and operating performance while the integration of integrated circuits and semiconductor devices including the integrated cell is improved.

[0102] One or more embodiments can provide an integrated circuit having a layout for increasing power efficiency and integration.

[0103] One or more embodiments can provide a technology for improving spatial efficiency and integration of standard cells by increasing the degree of freedom of contact arrangement on conductive lines.

[0104] Example embodiments have been disclosed herein and, although a particular terminology is employed, it will be understood in context that the use of such terminology is only for descriptive purposes and is not intended to be limiting in any way. In some instances, features, attributes and / or benefits of embodiments described in connection with a particular embodiment can be used in combination with features, attributes and / or benefits of another embodiment, even though the subject embodiment is not explicitly described or shown. It will be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the application and are included within its spirit and scope.

Claims

1. A semiconductor device comprising: a substrate at a bottom of the semiconductor device, a first active region in the substrate, extending in a first direction; a second active region in the substrate, extending in the first direction; a field region in the substrate, between the first active region and the second active region; a gate structure comprising: an upper gate electrode overlapping the first active region and extending in a second direction crossing the first direction; and a lower gate electrode overlapping the second active region, extending in the second direction, and on a same line as the upper gate electrode; a gate isolation layer between the upper gate electrode and the lower gate electrode; a source / drain region on a respective side of the upper gate electrode; a contact jumper in the first active region, crossing the upper gate electrode and electrically connecting the source / drain region; and a first upper contact extending in the second direction in the field region and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode, and wherein the first upper contact and the contact jumper are at a same level relative to a major surface of the substrate and separated in the second direction by an interlayer insulating layer.

2. The semiconductor device of claim 1, wherein, the first upper contact is electrically connected to the lower gate electrode and electrically insulated from the upper gate electrode.

3. The semiconductor device of claim 1, further comprising: a first lower contact electrically connecting the lower gate electrode to the first upper contact in the field region.

4. The semiconductor device of claim 1, wherein, the first upper contact is spaced apart from the upper gate electrode.

5. The semiconductor device of claim 1, wherein, a lower surface of the first upper contact is in contact with the lower gate electrode and the gate isolation layer.

6. The semiconductor device of claim 1, further comprising: a first interconnect line overlapping the gate isolation layer and the first upper contact in the field region and extending in the first direction.

7. The semiconductor device of claim 6, further comprising: a first via electrically connecting the first upper contact to the first interconnect line in the field region.

8. The semiconductor device of claim 6, wherein, an upper surface of the first upper contact is in contact with the first interconnect line.

9. The semiconductor device of claim 6, further comprising: a second interconnect line and a third interconnect line in the field region, wherein the second interconnect line and the third interconnect line: extend in the first direction, are spaced apart from each other in the first direction, are at a same level relative to a major surface of the substrate as the first interconnect line, and are on respective sides of the first upper contact.

10. The semiconductor device of claim 9, wherein, a distance in the second direction from the second active region to the second interconnect line and the third interconnect line is less than a distance in the second direction from the second active region to the first interconnect line and the gate isolation layer.

11. An integrated circuit comprising standard cells, wherein, the standard cell comprises: a first active region and a second active region having different conductivity types and each extending in a first direction; a field region between the first active region and the second active region; a substrate; a first wire extending in a second direction crossing the first direction, the first wire being on the substrate in the first active region, the second active region, and the field region; an isolation insulating layer separating the first wire into a first upper wire and a first lower wire and electrically insulating the first upper wire from the first lower wire in the field region; a first lower contact in the field region and on the first lower wire; a first upper contact in the field region and on the first lower contact, the first upper contact extending in the second direction and overlapping the isolation insulating layer; and a contact jumper in the first active region, the contact jumper crossing the first upper wire, wherein the contact jumper and the first upper contact are at the same level relative to a main surface of the substrate and separated in the second direction by an interlayer insulating layer.

12. The integrated circuit of claim 11, wherein, the isolation insulating layer is in the field region and adjacent to the first active region.

13. The integrated circuit of claim 11, wherein, at least a portion of the isolation insulating layer is in the first active region.

14. The integrated circuit of claim 11, further comprising: a first via on the first upper contact and overlapping the isolation insulating layer.

15. The integrated circuit of claim 11, further comprising: a first interconnect wire extending in the first direction, crossing the first upper contact, and overlapping the isolation insulating layer.

16. The integrated circuit of claim 15, further comprising: second and third interconnect wires in the field region, wherein the second and third interconnect wires extend in the extension direction of the first interconnect wire and are on respective sides of the first upper contact in plan view, wherein a distance from the contact jumper to the second and third interconnect wires in the second direction is greater than a distance from the contact jumper to the first interconnect wire in the second direction.

17. The integrated circuit of claim 11, further comprising: source / drain regions in the first active region on respective sides of the first upper wire, wherein the contact jumper connects the source / drain regions.

18. An integrated circuit comprising standard cells, wherein, The standard cell comprises: a substrate; first and second active regions in the substrate, having different conductivity types and each extending in a first direction; a field region in the substrate between the first and second active regions; an upper wire in the first active region, the upper wire extending in a second direction crossing the first direction; a lower wire in the second active region and the field region, the lower wire extending in the second direction, spaced apart from the upper wire in the second direction, and on the same line as the upper wire; an interconnect wire in the field region, the interconnect wire extending in the first direction and between the upper wire and the lower wire in plan view; an upper contact in the field region, the upper contact extending in the second direction and overlapping the interconnect wire and the lower wire and not overlapping the upper wire; a contact jumper in the first active region, the contact jumper crossing the upper wire; and a first via disposed between and connecting the interconnect wire and the upper contact, the first via not overlapping the upper wire and the lower wire, wherein: the lower wire is electrically connected to the interconnect wire, The upper conductive lines are electrically insulated from the lower conductive lines, and wherein the upper contact and the contact jumper are at the same level with respect to a main surface of the substrate and separated in the second direction by an interlayer insulating layer.

19. The integrated circuit of claim 18, further comprising: source / drain regions on respective sides of the upper conductive lines, wherein the source / drain regions cross the upper conductive lines and are electrically connected to each other.

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