Method for manufacturing metal oxide array substrate, array substrate and display panel

Abstract

The present invention provides a method for manufacturing a metal oxide array substrate, an array substrate and a display panel. The method for manufacturing a metal oxide array substrate provided by the present invention includes depositing a gate metal layer on a base substrate, and forming a gate by a photolithography process; depositing a buffer layer on the gate metal layer, and depositing a semiconductor layer on the buffer layer, and forming a semiconductor pattern above the gate by a photolithography process; forming a source electrode and a drain electrode on the semiconductor pattern; forming a metal insulating layer on the buffer layer by atomic deposition, the metal insulating layer at least covering the semiconductor pattern; depositing a protective layer on the metal insulating layer, thereby preventing the metal electrode from being oxidized and preventing water or hydrogen from penetrating into the channel, thereby improving the performance of the TFT and the display quality of the display panel.

Description

Technical Field

[0001] The present invention relates to the technical field of display devices, and in particular to a method for manufacturing a metal oxide array substrate, an array substrate and a display panel. Background Art

[0002] Flat panel display devices have many advantages such as thin body, power saving, no radiation, etc., and have been widely used. Existing flat panel display devices mainly include liquid crystal display devices (Liquid Crystal Display, LCD) and organic light emitting diode display devices (Organic Light Emitting Display, OLED), and flat panel displays are usually formed by combining an upper substrate and a lower substrate, and the lower substrate is a thin film transistor (Thin Film Transistor, TFT) array substrate.

[0003] In the prior art, in order to reduce the number of photolithography times and reduce power consumption, the metal oxide TFT of the TFT array substrate generally adopts a back channel etching structure. Specifically, when preparing the metal oxide TFT, a metal layer is first deposited on the metal oxide semiconductor pattern, and then etched to form a metal electrode and a channel, wherein the metal electrode includes a metal source and a metal drain, and then a protective layer is further deposited thereon, which can play an insulating and protective role.

[0004] However, when the protective layer is deposited, water or hydrogen may penetrate into the channel, affecting the performance of the TFT. Summary of the invention

[0005] The present invention provides a method for manufacturing a metal oxide array substrate, an array substrate and a display panel, which prevent water or hydrogen from penetrating into a channel and improve the performance of a TFT.

[0006] In a first aspect, the present invention provides a method for manufacturing a metal oxide array substrate, comprising: forming a gate and a buffer layer on a base substrate; depositing a semiconductor layer on the buffer layer, and forming a semiconductor pattern on the semiconductor layer by a photolithography process; forming a source, a drain and a metal insulating layer on the semiconductor pattern, the metal insulating layer covering the semiconductor pattern, wherein the metal insulating layer is formed by depositing a metal layer by atomic deposition and then plasma oxidation; depositing a protective layer on the source, the drain and the metal insulating layer.

[0007] In a second aspect, the present invention provides an array substrate manufactured using the above-mentioned method for manufacturing a metal oxide array substrate.

[0008] In a third aspect, the present invention provides a display panel including the above-mentioned array substrate.

[0009] The manufacturing method of the metal oxide array substrate, the array substrate and the display panel provided by the present invention form a gate and a buffer layer on a base substrate; deposit a semiconductor layer on the buffer layer, and form a semiconductor pattern on the semiconductor layer by a photolithography process; form a source electrode, a drain electrode and a metal insulating layer on the semiconductor pattern, and the metal insulating layer covers the semiconductor pattern, wherein the metal insulating layer is formed by depositing a metal layer by atomic deposition and then plasma oxidation; deposit a protective layer on the source electrode, the drain electrode and the metal insulating layer, and the metal insulating layer is used to isolate and protect the metal electrode and the semiconductor pattern. During the deposition of the protective layer, water or hydrogen is prevented from penetrating into the channel, thereby improving the performance of the TFT and the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the present invention or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0011] Figure 1 A flow chart of a method for manufacturing a metal oxide array substrate provided in Embodiment 1 of the present invention;

[0012] Figure 2 A flow chart of forming a gate and a buffer layer on a base substrate in a method for manufacturing a metal oxide array substrate provided in Embodiment 1 of the present invention;

[0013] Figure 3 A schematic structural diagram of an array substrate in a first state in a method for manufacturing a metal oxide array substrate provided in Embodiment 1 of the present invention;

[0014] Figure 4 A schematic structural diagram of an array substrate in a second state in a method for manufacturing a metal oxide array substrate provided in Embodiment 1 of the present invention;

[0015] Figure 5 A flow chart of forming a source electrode, a drain electrode and a metal insulating layer on a semiconductor pattern in one of the methods for manufacturing a metal oxide array substrate provided in the first embodiment of the present invention;

[0016] Figure 6 A schematic structural diagram of an array substrate in a third state in the method for manufacturing a metal oxide array substrate provided in Embodiment 1 of the present invention;

[0017] Figure 7 Another flow chart of forming a source electrode, a drain electrode and a metal insulating layer on a semiconductor pattern in the method for manufacturing a metal oxide array substrate provided in the first embodiment of the present invention;

[0018] Figure 8 A schematic structural diagram of another array substrate in a third state in the method for manufacturing a metal oxide array substrate provided in the first embodiment of the present invention;

[0019] Fig. 9 A schematic structural diagram of an array substrate in a fourth state in the method for manufacturing a metal oxide array substrate provided in Embodiment 1 of the present invention;

[0020] Fig.10 This is a structural schematic diagram of an array substrate in a fifth state in the method for manufacturing a metal oxide array substrate provided in Embodiment 1 of the present invention.

[0021] Description of reference numerals:

[0022] 10 - substrate; 20 - gate; 30 - buffer layer; 40 - semiconductor pattern; 50 - source; 51 - drain; channel-53; 60 - metal insulating layer; 70 - protective layer; 80 - transparent conductive layer; contact via-90. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0024] First, those skilled in the art should understand that these embodiments are only used to explain the technical principles of the present invention and are not intended to limit the protection scope of the present invention. Those skilled in the art can make adjustments to them as needed to adapt to specific application scenarios.

[0025] Secondly, it should be noted that in the description of the present invention, terms such as "inside" and "outside" indicating directions or positional relationships are based on the directions or positional relationships shown in the drawings. This is only for the convenience of description and does not indicate or imply that the device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation on the present invention.

[0026] In addition, it should be noted that in the description of the present invention, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0028] Flat panel display devices have many advantages such as thin body, power saving, no radiation, etc., and have been widely used. Existing flat panel display devices mainly include liquid crystal display devices (Liquid Crystal Display, LCD) and organic light emitting diode display devices (Organic Light Emitting Display, OLED), and flat panel displays are usually formed by combining an upper substrate and a lower substrate, and the lower substrate is a thin film transistor (Thin Film Transistor, TFT) array substrate.

[0029] In the prior art, in order to reduce the number of photolithography times and reduce power consumption, the metal oxide TFT of the TFT array substrate generally adopts a back channel etching structure. Specifically, when preparing the metal oxide TFT, a metal layer is first deposited on the metal oxide semiconductor pattern, and then etched to form a metal electrode and a channel, wherein the metal electrode includes a metal source and a metal drain, and then a protective layer is further deposited thereon, which can play an insulating and protective role.

[0030] However, when depositing the protective layer, the metal electrode is easily oxidized, and water or hydrogen penetrates into the channel, affecting the performance of the TFT.

[0031] Specifically, when coating the organic protective layer, water will penetrate into the TFT through the channel during the coating process, causing the water to penetrate into the surface of the semiconductor layer. When depositing the inorganic protective layer, hydrogen plasma will penetrate into the channel to the surface of the semiconductor layer during the deposition gas reaction process, thereby affecting the performance of the TFT.

[0032] In order to solve the above problems, the embodiments of the present invention provide a method for manufacturing a metal oxide array substrate, an array substrate and a display panel, which avoid oxidation of the metal electrode and prevent water or hydrogen from penetrating into the channel, thereby improving the performance of the TFT and the display quality of the display panel.

[0033] It should be noted that the manufacturing method of the metal oxide array substrate, the array substrate and the display panel of the present invention have multiple display areas arranged in an array, and a thin film transistor is provided in each display area, so that each display area can realize the display function. The embodiments of the present invention will take the structure in a display area of ​​the array substrate as an example and combine its process to illustrate the innovation of the present invention.

[0034] Embodiment 1

[0035] Figure 1 A flow chart of a method for manufacturing a metal oxide array substrate provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the manufacturing method of the metal oxide array substrate provided in this embodiment includes:

[0036] S100, forming a gate and a buffer layer on a substrate.

[0037] Specifically, a gate 20 and a buffer layer 30 covering the gate 20 are formed on the base substrate 10. When the gate 20 is formed, a scan line of the array substrate is also formed, and the gate 20 is connected to the scan line. The array substrate manufactured by the manufacturing method of the metal oxide array substrate of this embodiment has a plurality of display areas arranged in an array, and a gate 20 is formed in each display area through the above steps.

[0038] Based on the above steps, a plasma enhanced chemical vapor deposition (PECVD) method is used to continuously deposit a thickness of A buffer layer 30 is formed, wherein the deposition material of the buffer layer 30 can be oxide, nitride or oxynitride.

[0039] Furthermore, the buffer layer 30 may be a silicon nitride film, a silicon oxide or a silicon oxynitride film, wherein the reaction gas when depositing the SiNx film is SiH4, NH3, N2 or SiH2Cl2, NH3, N2, and the reaction gas when depositing the SiNx film is SiH4, NH3, N2 or SiH2Cl2, NH3, N2. X O Y The reaction gases of the film are SiH4, NH3, N2O, N2, and the SiO X The reaction gases corresponding to the film are SiH4, N2O, and N2.

[0040] Optionally, the buffer layer 30 may be a single layer or a multi-layer, that is, the buffer layer 30 may be formed by stacking one or more of nitride or oxide. X and SiO X The double-layer film is composed of SiN X Layer, SiN XThe upper side of the layer, that is, the side away from the substrate 10, is SiO X Layer, SiO X The layer is in contact with the metal oxide semiconductor layer. To improve the performance of TFT devices, SiO X The thickness is

[0041]

[0042] Figure 2 A flow chart of forming a gate and a buffer layer on a base substrate in a method for manufacturing a metal oxide array substrate provided by an embodiment of the present invention, such as Figure 2 As shown, a gate and a buffer layer are formed on a substrate, specifically including:

[0043] S101, depositing a gate metal layer on a substrate, and forming a gate by a photolithography process.

[0044] Specifically, a layer of about 100 mm thick is deposited on the substrate 10 by sputtering or thermal evaporation. The gate metal layer may be formed on the substrate 10, and the base substrate 10 may be a glass substrate.

[0045] The gate metal layer can be made of Cr, W, Cu, Ti, Ta, Mo, or other metals or their alloys. A gate metal layer composed of multiple layers of metals can also meet the needs. Then, a common photolithography process is performed to form the gate 20.

[0046] S102 , depositing a first buffer layer on the gate metal layer, wherein the first buffer layer is made of silicon nitride.

[0047] Specifically, on the basis of the above steps, a first buffer layer is deposited and formed, and the first buffer layer covers the gate 20 .

[0048] S103 , depositing a second buffer layer made of silicon oxide on the first buffer layer.

[0049] Specifically, the second buffer layer covers the first buffer layer, and the thickness of the second buffer layer is Thereby, the performance of the thin film transistor can be improved.

[0050] Figure 3 A schematic structural diagram of an array substrate in a first state in a method for manufacturing a metal oxide array substrate provided by an embodiment of the present invention, as shown in FIG. Figure 3 As shown, a gate 20 is disposed on the base substrate 10 , and a buffer layer 30 formed by deposition covers the gate 20 .

[0051] S200, depositing a semiconductor layer on the buffer layer, and forming a semiconductor pattern on the semiconductor layer by a photolithography process.

[0052] Specifically, after the buffer layer 30 is deposited, a layer with a thickness of about 1000 nm is deposited on the buffer layer 30 by sputtering or thermal evaporation. The metal oxide semiconductor layer may be IGZO, or may be Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxides.

[0053] After the metal oxide semiconductor layer is deposited, a common photolithography process is performed to form a semiconductor pattern 40 , wherein the semiconductor pattern 40 is located above the gate 20 , with the buffer layer 30 interposed therebetween.

[0054] Figure 4 A schematic structural diagram of an array substrate in a second state in a method for manufacturing a metal oxide array substrate provided by an embodiment of the present invention, as shown in FIG. Figure 4 As shown, the semiconductor pattern 40 is located above the buffer layer 30 , and in the thickness direction of the array substrate, the projection of the semiconductor pattern 40 overlaps with the gate 20 .

[0055] S300, forming a source electrode, a drain electrode and a metal insulating layer on the semiconductor pattern, wherein the metal insulating layer covers the semiconductor pattern, wherein the metal insulating layer is formed by depositing a metal layer by atomic deposition and then undergoing plasma oxidation.

[0056] Specifically, the metal insulating layer 60 includes any one of aluminum oxide, tantalum oxide, molybdenum oxide, and titanium oxide, so that it can protect the semiconductor pattern 40 while insulating, thereby preventing water or hydrogen in subsequent processes from penetrating into the surface of the semiconductor pattern 40 and affecting the performance of the TFT.

[0057] The following will provide a detailed description of two specific structural arrangements and formation processes of the source 50 , the drain 51 and the metal insulating layer 60 .

[0058] As one of the optional methods, Figure 5 A flow chart of forming a source electrode, a drain electrode and a metal insulating layer on a semiconductor pattern in one of the methods for manufacturing a metal oxide array substrate provided in an embodiment of the present invention, such as Figure 5 As shown, a source electrode, a drain electrode and a metal insulating layer are formed on the semiconductor pattern, specifically including:

[0059] S301, forming a source and a drain on a semiconductor pattern.

[0060] Specifically, based on the above steps, sputtering or thermal evaporation is used to sequentially deposit a thickness of A metal layer is formed, and then a source electrode 50 and a drain electrode 51 are formed by a common photolithography process, wherein the source electrode 50 and the drain electrode 51 partially cover the semiconductor pattern 40 and contact the semiconductor pattern 40, and the source electrode 50 and the drain electrode 51 are respectively located on both sides of the semiconductor pattern 40, so that a channel 53 is formed between the two on the semiconductor pattern 40.

[0061] Optionally, the material of the metal layer is metal Cu, that is, the material of the source 50 and the drain 51 is metal Cu, so that it can have a smaller resistance. Since the data line of the array substrate is formed at the same time as the source 50 and the drain 51 are formed, using metal Cu as the material can reduce the delay of electrical signal transmission, so that each pixel area of ​​the array substrate can be fully charged, thereby ensuring the display quality.

[0062] S302 , forming a metal layer on the buffer layer by atomic deposition.

[0063] Specifically, based on the above steps, an atomic layer deposition (ALD) method can be used to deposit a single atomic film layer by layer on the surface with a thickness of about A metal layer, wherein the material of the metal layer can be metal such as aluminum (Al), tantalum (Ta), molybdenum (Mo), titanium (Ti), etc.

[0064] Preferably, the thickness of the metal layer is That is, a very thin metal layer of 2 to 15 atomic layers can have good light transmittance after a subsequent oxidation process to form a metal insulating layer 60. Without adding an additional photolithography process, the transmittance of the TFT pixel area is less affected, thereby ensuring the display quality.

[0065] S303, converting the metal layer into a metal insulating layer through plasma oxidation.

[0066] On the basis of the metal layer formed in the above steps, the deposited metal layer is transformed into the metal insulating layer 60 by plasma oxidation, so that the metal insulating layer 60 is insulated.

[0067] According to the metal material used for the metal layer, the corresponding metal insulating layer 60 can be composed of metal oxides such as aluminum oxide, tantalum oxide, molybdenum oxide, and titanium oxide. The plasma conditions for metal oxidation are: RF power of 5 to 30 Kw, oxygen flow rate of 500 to 5000 sccm, or N2O flow rate of 500 to 5000 sccm; substrate temperature of 20 to 300°C. Under the plasma conditions, oxygen or laughing gas ionizes oxygen free radicals, and under the action of oxygen free radicals, metals such as Al, Ta, Mo, and Ti are oxidized into an insulating layer, that is, a metal insulating layer 60 composed of one or more of aluminum oxide, tantalum oxide, molybdenum oxide, and titanium oxide.

[0068] It should be noted that the metal insulating layer 60 covers the source 50, the drain 51 and the semiconductor pattern 40, that is, the metal insulating layer 60 covers the surface of the entire thin film transistor, thereby preventing water and hydrogen adsorption and penetration in subsequent processes, and also preventing the metal electrode source 50 and the drain 51 from being oxidized in subsequent processes, thereby ensuring the overall performance of the thin film transistor.

[0069] Figure 6 A schematic structural diagram of an array substrate in a third state in a method for manufacturing a metal oxide array substrate provided by an embodiment of the present invention, such as Figure 6 As shown, the metal insulating layer 60 is relatively thin and covers both the source 50 and the drain 51. At the same time, since the semiconductor pattern 40 is exposed in the channel 53, the metal insulating layer 60 also covers the semiconductor pattern 40 when covering the channel 53, thereby providing a good protection for the thin film transistor.

[0070] As another alternative, Figure 7 Another flow chart of forming a source electrode, a drain electrode and a metal insulating layer on a semiconductor pattern in a method for manufacturing a metal oxide array substrate provided by an embodiment of the present invention is as follows: Figure 7 As shown, a source electrode, a drain electrode and a metal insulating layer are formed on the semiconductor pattern, specifically including:

[0071] S301', forming a metal layer on the semiconductor pattern by atomic deposition.

[0072] Specifically, a metal layer may be formed by atomic deposition, and the metal layer may be covered on the semiconductor pattern 40 , so that the semiconductor pattern 40 is isolated in subsequent processes.

[0073] S302', converting the metal layer into a metal insulating layer through plasma oxidation.

[0074] On the basis of the metal layer formed in the above steps, the deposited metal layer is transformed into a metal insulating layer 60 by plasma oxidation.

[0075] S303 ′, forming a source electrode and a drain electrode on the metal insulating layer.

[0076] Specifically, via holes are formed on the metal insulating layer 60 at positions corresponding to both sides of the semiconductor pattern 40, and then a source electrode 50 and a drain electrode 51 are formed thereon. The source electrode 50 and the drain electrode 51 are respectively in contact with the semiconductor pattern 40 through the via holes.

[0077] Figure 8 A schematic structural diagram of another array substrate in a third state in a method for manufacturing a metal oxide array substrate provided by an embodiment of the present invention, as shown in FIG. Figure 8 As shown, the metal insulating layer 60 covers the semiconductor pattern 40 , and the source 50 and the drain 51 are located above the metal insulating layer 60 .

[0078] It should be noted that the difference between the structures and process methods of the above-mentioned two types of source electrodes 50, drain electrodes 51 and metal insulating layer 60 lies in the different formation process sequences of each layer, that is, the stacked structures are different, while the process methods for forming the source electrode 50, drain electrode 51 and metal insulating layer 60 are consistent. The metal insulating layer 60 formed by both methods can prevent water or hydrogen in subsequent processes from penetrating into the semiconductor pattern 40, thereby ensuring the performance of the TFT.

[0079] S400, depositing a protection layer on the source electrode, the drain electrode and the metal insulating layer, and forming a contact via hole on the protection layer.

[0080] Specifically, a protective layer 70 is deposited on the source 50, the drain 51 and the metal insulating layer 60 by PECVD. The protective layer 70 covers the metal insulating layer 60. The protective layer 70 has a certain thickness and can insulate and protect the source 50, the drain 51 and the semiconductor pattern 40 of the thin film transistor thereunder.

[0081] Optionally, the protective layer 70 is an inorganic protective layer composed of silicon nitride, wherein the corresponding reaction gas for PECVD deposition is SiH4, NH3, N2 or SiH2Cl2, NH3, N2, and a layer having a thickness of 1000 nm is deposited thereon by a plasma enhanced chemical vapor deposition (PECVD) method. Thereafter, a contact via 90 is formed on the protective layer 70 by a photolithography process, and the contact via 90 is located at a position on the protective layer 70 corresponding to the drain electrode 51, so that the material of the transparent conductive layer 80 can enter the contact via 90 in the subsequent process, thereby being electrically connected to the drain electrode 51 through the contact via 90.

[0082] It should be noted that hydrogen plasma is generated during the PECVD vapor deposition process. The organic insulating layer 701 and the metal insulating layer 60 can effectively prevent the hydrogen plasma generated during the deposition process from penetrating to the surface of the channel 53, thereby improving the performance of the metal oxide TFT.

[0083] Fig. 9 A schematic structural diagram of an array substrate in a fourth state in a method for manufacturing a metal oxide array substrate provided by an embodiment of the present invention, as shown in FIG. Fig. 9 As shown, the protection layer 70 covers the source electrode 50, the drain electrode 51 and the metal insulating layer 60, and also forms a contact via 90, so that the drain electrode 51 can be exposed, which is convenient for electrical connection with the transparent conductive layer 80 in the subsequent process.

[0084] S500 , depositing a transparent conductive layer at a corresponding position of the display area of ​​the array substrate.

[0085] Specifically, the thickness of the layer is about 1000 nm and the thickness of the layer is continuously deposited by sputtering or thermal evaporation. The transparent conductive layer 80 may be made of ITO or IZO, or other transparent metal oxides, and a transparent pixel electrode is formed by a single photolithography process.

[0086] Optionally, the transparent pixel electrode is located in the display area of ​​the array substrate and is electrically connected to the drain electrode 51 through the contact via 90 .

[0087] Fig.10 A schematic structural diagram of an array substrate in a seventh state in a method for manufacturing a metal oxide array substrate provided by an embodiment of the present invention, as shown in FIG. Fig.10 As shown, the transparent conductive layer 80 covers the protection layer 70 and is electrically connected to the drain electrode 51 through the contact via 90 .

[0088] The manufacturing method of the metal oxide array substrate provided by the embodiment of the present invention forms a gate and a buffer layer on a base substrate; deposits a semiconductor layer on the buffer layer, and forms a semiconductor pattern on the semiconductor layer through a photolithography process; forms a source electrode, a drain electrode and a metal insulating layer on the semiconductor pattern, and the metal insulating layer covers the semiconductor pattern, wherein the metal insulating layer is formed by depositing a metal layer by atomic deposition and then plasma oxidation; deposits a protective layer on the source electrode, the drain electrode and the metal insulating layer, and utilizes the metal insulating layer to isolate and protect the metal electrode and the semiconductor pattern. During the deposition of the protective layer, water or hydrogen is prevented from penetrating into the channel, thereby improving the performance of the TFT and the display quality of the display panel.

[0089] Embodiment 2

[0090] This embodiment provides an array substrate, which is manufactured using the manufacturing method in the first embodiment, and has a structure as follows: Fig.10 shown.

[0091] The present invention provides an array substrate, including a base substrate 10 , a gate 20 , a buffer layer 30 , a semiconductor pattern 40 , a source electrode 50 , a drain electrode 51 , a metal insulating layer 60 and a protective layer 70 .

[0092] Among them, the gate 20, the buffer layer 30 and the semiconductor pattern 40 are stacked in sequence on the base substrate 10, the source 50 and the drain 51 are connected to the two sides of the semiconductor pattern 40, the metal insulating layer 60 covers the semiconductor pattern 40, and the protective layer 70 is stacked on the source 50, the drain 51 and the metal insulating layer 60. Through the isolation and protection of the metal insulating layer 60, water or hydrogen is prevented from penetrating into the channel, thereby improving the performance of the TFT and the display quality of the display panel.

[0093] As an optional manner, in the array substrate provided by the present invention, the metal insulating layer 60 is formed of any oxide of aluminum, tantalum, molybdenum, or titanium.

[0094] As an optional manner, in the array substrate provided by the present invention, the metal insulation layer 60 is stacked on the buffer layer 30 and covers the source electrode 50 , the drain electrode 51 and the semiconductor pattern 40 .

[0095] As an optional manner, in the array substrate provided by the present invention, the metal insulating layer 60 is a film structure formed by atomic deposition.

[0096] As an optional method, in the array substrate provided by the present invention, the thickness of the metal insulating layer 60 is

[0097] Furthermore, the thickness of the metal insulating layer 60 is In this way, it can have better light transmittance, and without adding additional photolithography processes, the transmittance of the TFT pixel area is less affected, thereby ensuring the display quality.

[0098] As an optional manner, in the array substrate provided by the present invention, the buffer layer 30 includes a first buffer layer and a second buffer layer which are arranged in sequence, the first buffer layer is a silicon nitride layer, and the second buffer layer is a silicon oxide layer.

[0099] The semiconductor pattern 40 is disposed on the second buffer layer.

[0100] As an optional manner, in the array substrate provided by the present invention, the protective layer 70 is an inorganic insulating layer, and the inorganic insulating layer is composed of silicon nitride.

[0101] As an optional manner, the array substrate provided by the present invention further includes a transparent conductive layer 80 , and a contact via 90 is provided on the protective layer 70 . The transparent conductive layer 80 is electrically connected to the drain electrode 51 through the contact via 90 .

[0102] The present invention provides a metal oxide array substrate and a display panel, wherein the metal oxide array substrate comprises a base substrate, a gate electrode, a buffer layer, a semiconductor pattern, a source electrode, a drain electrode, a metal insulating layer and a protective layer, wherein the gate electrode, the buffer layer and the semiconductor pattern are sequentially stacked on the base substrate, the source electrode and the drain electrode are connected to both sides of the semiconductor pattern, the metal insulating layer covers the semiconductor pattern, and the protective layer is stacked on the source electrode, the drain electrode and the metal insulating layer, and the isolation and protection effect of the metal insulating layer prevents water or hydrogen from penetrating into the channel, thereby improving the performance of the TFT and the display quality of the display panel.

[0103] Embodiment 3

[0104] This embodiment provides a display panel, including the array substrate in the second embodiment, wherein the specific structure and function of the array substrate have been described in detail in the second embodiment, and thus will not be described again here.

[0105] The display panel may be a liquid crystal display panel. In this case, the display panel includes a color filter substrate, a liquid crystal layer and the array substrate in the second embodiment. The liquid crystal layer is sandwiched between the color filter substrate and the array substrate.

[0106] The display panel may also be an organic light emitting diode display panel. In this case, the display panel includes the array substrate, the encapsulation layer and the organic layer in the second embodiment, wherein the organic layer is sandwiched between the array substrate and the encapsulation layer.

[0107] It should be noted that, whether it is a liquid crystal display panel or an organic light-emitting diode display panel, a metal insulating layer formed by atomic deposition is provided on the thin film transistor of its array substrate, which isolates and protects the thin film transistor. In this way, during the process of forming the protective layer, water or hydrogen is prevented from penetrating into the channel, thereby improving the performance of the thin film transistor and the display quality of the display panel.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a metal oxide array substrate, characterized in that: include: forming a gate and a buffer layer on a substrate; Depositing a semiconductor layer on the buffer layer, and forming a semiconductor pattern on the semiconductor layer by a photolithography process; A source electrode, a drain electrode and a metal insulating layer are formed on the semiconductor pattern, wherein the metal insulating layer covers the semiconductor pattern, wherein the metal insulating layer is formed by depositing a metal layer by atomic deposition and then plasma oxidation, the source electrode and the drain electrode are made of copper, and the thickness of the metal insulating layer is In the thickness direction of the array substrate, the projection of the semiconductor pattern is located within the projection range of the gate; Depositing a protective layer on the source electrode, the drain electrode and the metal insulating layer, and forming a contact via on the protective layer; A transparent conductive layer is deposited at a corresponding position of the display area of ​​the array substrate.

2. The method for manufacturing a metal oxide array substrate according to claim 1, characterized in that: The forming of a source electrode, a drain electrode and a metal insulating layer on the semiconductor pattern specifically includes: forming the source electrode and the drain electrode on the semiconductor pattern; forming the metal layer on the buffer layer by atomic deposition; The metal layer is converted into the metal insulating layer by plasma oxidation.

3. The method for manufacturing a metal oxide array substrate according to claim 1, characterized in that: The forming of a source electrode, a drain electrode and a metal insulating layer on the semiconductor pattern specifically includes: forming the metal layer on the semiconductor pattern by atomic deposition; converting the metal layer into the metal insulating layer by plasma oxidation; The source electrode and the drain electrode are formed on the metal insulating layer.

4. The method for manufacturing a metal oxide array substrate according to claim 2, characterized in that: The metal insulating layer includes any one of aluminum oxide, tantalum oxide, molybdenum oxide and titanium oxide.

5. The method for manufacturing a metal oxide array substrate according to any one of claims 1 to 4, characterized in that: The forming of a gate and a buffer layer on the substrate specifically includes: Depositing a gate metal layer on the substrate, and forming the gate by a photolithography process; Depositing a first buffer layer on the gate metal layer, wherein the first buffer layer is composed of silicon nitride; A second buffer layer is deposited on the first buffer layer, wherein the second buffer layer is made of silicon oxide.

6. The method for manufacturing a metal oxide array substrate according to any one of claims 1 to 4, characterized in that: The protective layer is an inorganic protective layer composed of silicon nitride.

7. The method for manufacturing a metal oxide array substrate according to any one of claims 1 to 4, characterized in that: The transparent conductive layer is electrically connected to the drain electrode through the contact via.

8. An array substrate, characterized in that: The method is manufactured by the manufacturing method according to any one of claims 1 to 7.

9. A display panel, characterized in that: Comprising the array substrate as claimed in claim 8.

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