A motor drive module

Abstract

The present invention relates to a motor drive module, comprising: a pulse circuit; an input circuit, the input circuit is connected to an external signal input device; a PWM circuit, the PWM circuit is electrically connected to the pulse circuit and the input protection circuit respectively; a power drive protection circuit, the power drive protection circuit is electrically connected to the PWM circuit; a power switch drive circuit, the power switch drive circuit is electrically connected to the power drive protection circuit. In the present invention, the pulse circuit can generate oscillations and there are only two transient states. The pulse circuit generates an oscillation signal, so there is no need to input an oscillation signal from an external device, and the input protection circuit and the power protection circuit can prevent excessive current, play a circuit protection role, and improve safety performance.

Description

Technical Field

[0001] The present invention relates to the technical field of motor modules, and in particular to a motor drive module. Background Art

[0002] A motor is an electromagnetic device that converts or transmits electrical energy based on the law of electromagnetic induction. With the continuous progress and development of society, motors have been integrated into various fields of human life. Motors can be divided into DC motors and AC motors, and can also be divided into single-phase motors and three-phase motors. Motors are often used in power tools, furniture, transportation equipment, etc.

[0003] However, many existing motors work in harsh environments, especially in the military field, and need to adapt to special environments, such as high temperature, high pressure or humid environments. Long-term harsh environments can easily damage the drive modules in the motors.

[0004] For example, the utility model patent with application number "CN201821152061.X" provides a motor drive circuit, including an external communication circuit, a control chip U1, a motor drive circuit and a power supply circuit; the external communication circuit communicates with an external device, and its output end is electrically connected to the control chip U1; the output end of the control chip U1 is electrically connected to the motor drive circuit; the power supply circuit is used to supply power to the entire motor drive circuit. The external communication circuit is connected to the external device to realize the communication between the external device and the control chip U1, and the control chip U1 drives the motor drive circuit to work, but the patent solution is not suitable for harsh environments, has low safety, and has high losses due to the large number of components. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a motor drive module to solve the problem that the existing motor drive module is easily damaged and has high loss.

[0006] The present invention solves the above technical problems through the following technical means:

[0007] A motor drive module, comprising:

[0008] Pulse circuit;

[0009] An input circuit, the input circuit being connected to an external signal input device;

[0010] A PWM circuit, wherein the PWM circuit is electrically connected to the pulse circuit and the input protection circuit respectively;

[0011] A power drive protection circuit, wherein the power drive protection circuit is electrically connected to one end of the PWM circuit;

[0012] A power switch driving circuit, wherein an input end of the power switch driving circuit is electrically connected to a PWM circuit, and an output end of the power switch driving circuit is electrically connected to another end of a power driving protection circuit.

[0013] The pulse circuit can generate oscillations and there are only two transient steady states. The pulse circuit generates an oscillation signal, so there is no need to input an oscillation signal from an external device. The input protection circuit and the power protection circuit can prevent excessive current, play a circuit protection role, and improve safety performance.

[0014] As a further solution of the present invention: the pulse circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R21, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a transistor VT2, a chip N1, a voltage regulator diode VD2, a diode D1, and a MOS tube Q1, wherein;

[0015] The seventh pin of the chip N1 is electrically connected to one end of the resistor R1, the resistor R2, and the resistor R3, the other end of the resistor R2 is grounded, the other end of the resistor R3 is electrically connected to the sixth pin and the second pin of the chip respectively, and is electrically connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded;

[0016] The first pin of the chip N1 is grounded, the fifth pin of the chip N1 is electrically connected to the capacitor C5, and the other end of the capacitor C5 is grounded;

[0017] The fourth pin and the eighth pin of the chip N1 are also electrically connected to one end of the capacitor C2 and the resistor R5. The fourth pin and the eighth pin of the chip N1 are also electrically connected to the drain of the MOS tube Q1. The other end of the capacitor C2 is grounded. The other end of the resistor R5 is electrically connected to the positive electrode of the diode D1. The source of the MOS tube Q1 is respectively connected to one end of the resistor R6 and the capacitor C3. The other end of the capacitor C3 is grounded. The other end of the resistor R6 is electrically connected to the gate of the MOS tube Q1. The gate of the MOS tube Q1 is also electrically connected to the negative electrode of the voltage regulator diode VD2. The positive electrode of the voltage regulator diode VD2 is grounded, and the voltage regulator diode VD2 is connected in parallel with the capacitor C4. The source of the MOS tube Q1 is electrically connected to the external power supply.

[0018] As a further solution of the present invention: the pulse circuit also includes a resistor R7, a transistor VT1, and a voltage-stabilizing diode VD1. The emitter of the transistor VT1 is electrically connected to the other end of the resistor R1, the base of the transistor VT1 is electrically connected to the negative electrode of the voltage-stabilizing diode VD1, the positive electrode of the voltage-stabilizing diode VD1 is grounded, the collector of the transistor VT1 is also electrically connected to one end of the resistor R7 and the source of the MOS tube Q1, and the other end of the resistor R7 is electrically connected to the negative electrode of the voltage-stabilizing diode.

[0019] As a further solution of the present invention: the input protection circuit includes resistors R8, R9, R10, R11, R12, R13, R22, R23, R24, R25, R26 and R27, wherein one end of the resistors R8, R9, R10, R11, R12 and R13 are respectively connected to input signals VINA, VINB, VINC, VIND, VINE and VINF;

[0020] One end of the resistor R22 is also connected to the input signal VINA, and the other end of the resistor R22 is grounded; one end of the resistor R23 is also connected to the input signal VINB, and the other end of the resistor R23 is grounded; one end of the resistor R24 ​​is also connected to the input signal VINC, and the other end of the resistor R24 ​​is grounded; one end of the resistor R25 is also connected to the input signal VIND, and the other end of the resistor R25 is grounded; one end of the resistor R26 is also connected to the input signal VINE, and the other end of the resistor R26 is grounded; one end of the resistor R27 is also connected to the input signal VINF, and the other end of the resistor R27 is grounded.

[0021] As a further solution of the present invention: the PWM circuit includes an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, and an operational amplifier U6, wherein the non-inverting input terminal of the operational amplifier U1 is electrically connected to the other end of the resistor R8, and the inverting input terminal of the operational amplifier U1 is electrically connected to the cathode of the diode D1;

[0022] The non-inverting input terminal of the operational amplifier U2 is electrically connected to the other end of the resistor R9, and the inverting input terminal of the operational amplifier U2 is electrically connected to the cathode of the diode D1;

[0023] The non-inverting input terminal of the operational amplifier U3 is electrically connected to the other end of the resistor R10, and the inverting input terminal of the operational amplifier U3 is electrically connected to the cathode of the diode D1;

[0024] The non-inverting input terminal of the operational amplifier U4 is electrically connected to the other end of the resistor R11, and the inverting input terminal of the operational amplifier U4 is electrically connected to the cathode of the diode D1;

[0025] The non-inverting input terminal of the operational amplifier U5 is electrically connected to the other end of the resistor R12, and the inverting input terminal of the operational amplifier U5 is electrically connected to the cathode of the diode D1;

[0026] The non-inverting input terminal of the operational amplifier U6 is electrically connected to the other end of the resistor R13, and the inverting input terminal of the operational amplifier U6 is electrically connected to the cathode of the diode D1; the output terminal of the operational amplifier U6 is electrically connected to the gate of the MOS tube Q7.

[0027] As a further solution of the present invention: the power drive protection circuit includes a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, an operational amplifier U7, a capacitor C4, and a diode D8, wherein the cathode of the diode D8 is electrically connected to the cathode of the diode D1, the cathode of the diode D8 is also electrically connected to one end of the resistor R15, the anode of the diode D8 is electrically connected to the output end of the operational amplifier U7, the other end of the resistor R15 is grounded, the in-phase input end of the operational amplifier U7 is electrically connected to one end of the resistor R6, and the other end of the resistor R6 is electrically connected to the positive power supply end of the operational amplifier U7;

[0028] The non-inverting input terminal of the operational amplifier U7 is also electrically connected to one end of a resistor R18, and the other end of the resistor R18 is grounded;

[0029] The inverting input terminal of the operational amplifier U7 is also electrically connected to one end of the resistor R17, the capacitor C4, and the resistor R19; the other ends of the capacitor C4 and the resistor R19 are grounded, the other end of the resistor R17 is electrically connected to the resistor R20, and the other end of the resistor R20 is grounded.

[0030] As a further solution of the present invention: the power switch driving circuit includes a diode D2, a diode D3, a diode D4, a diode D5, a diode D6, a diode D7, a MOS transistor Q2, a MOS transistor Q3, a MOS transistor Q4, a MOS transistor Q5, a MOS transistor Q6, and a MOS transistor Q7, wherein:

[0031] The anode of the diode D2 is electrically connected to the drain of the MOS transistor Q2, and the cathode of the diode D2 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U1 is electrically connected to the gate of the MOS transistor Q2;

[0032] The anode of the diode D3 is electrically connected to the drain of the MOS transistor Q3, and the cathode of the diode D3 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U2 is electrically connected to the gate of the MOS transistor Q3;

[0033] The anode of the diode D4 is electrically connected to the drain of the MOS transistor Q4, and the cathode of the diode D4 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U3 is electrically connected to the gate of the MOS transistor Q4;

[0034] The anode of the diode D5 is electrically connected to the drain of the MOS transistor Q5, and the cathode of the diode D5 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U4 is electrically connected to the gate of the MOS transistor Q5;

[0035] The anode of the diode D6 is electrically connected to the drain of the MOS transistor Q6, the cathode of the diode D6 is electrically connected to the source of the MOS transistor Q1, and the output end of the operational amplifier U5 is electrically connected to the gate of the MOS transistor Q6;

[0036] The anode of the diode D7 is electrically connected to the drain of the MOS transistor Q7, and the cathode of the diode D7 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U6 is electrically connected to the gate of the MOS transistor Q7;

[0037] The sources of the MOS transistors Q2 , Q3 , Q4 , Q5 , Q6 , and Q7 are also electrically connected to one end of the resistors R17 and R20 that are connected to each other.

[0038] As a further solution of the present invention: the operational amplifier U1, operational amplifier U2, operational amplifier U3, operational amplifier U4, operational amplifier U5, operational amplifier U6, and operational amplifier U7 are of model TL072.

[0039] As a further solution of the present invention: the model of the MOS tube Q1, MOS tube Q2, MOS tube Q3, MOS tube Q4, MOS tube Q5, MOS tube Q6, and MOS tube Q7 is IRFL4315PbF.

[0040] As a further solution of the present invention: the model of the chip N1 is NE555.

[0041] The advantages of the present invention are:

[0042] 1. In the present invention, the pulse circuit can generate an oscillation signal and there are only two transient steady states, so there is no need to connect to external equipment to provide a trigger signal. At the same time, the pulse circuit can generate the required oscillation signal, and fewer components are used, thereby reducing losses and increasing service life. The input protection circuit and the power protection circuit can prevent excessive current, play a circuit protection role, and improve safety performance.

[0043] 2. In the present invention, the transistor VT1, the voltage stabilizing diode VD1 and the resistor R17 form a voltage stabilizing circuit to provide a stable voltage to the resistors R1, R2, R3 and the capacitor C1. The ends of the resistors R17 and R20 connected to each other are also electrically connected to the sources of the MOS transistors Q2, Q3, Q4, Q5, Q6 and Q7. In this way, the power drive protection circuit can protect the MOS transistors Q2 to Q7 to prevent the components from being burned due to excessive current, so that the circuit can be applied to harsh environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of the structure of a motor drive module provided in an embodiment of the present invention.

[0045] Figure 2 A circuit schematic diagram of a pulse circuit provided in an embodiment of the present invention.

[0046] Figure 3 A circuit schematic diagram of an input protection circuit provided by an embodiment of the present invention.

[0047] Figure 4 A circuit schematic diagram of a PWM circuit provided in an embodiment of the present invention.

[0048] Figure 5 A circuit schematic diagram of a power drive protection circuit provided in an embodiment of the present invention.

[0049] Figure 6 A circuit schematic diagram of a power switch driving circuit provided in an embodiment of the present invention.

[0050] Figure 7 A schematic diagram of the structure of a chip N1 provided in an embodiment of the present invention.

[0051] Figure 8 A waveform diagram provided by an embodiment of the present invention.

[0052] Fig. 9 This is a schematic circuit diagram of the entire motor drive module provided in an embodiment of the present invention.

[0053] In the figure, 1-pulse circuit, 2-input protection circuit, 3-PWM circuit, 4-power drive protection circuit, 5-power switch drive circuit. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in combination with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] Example

[0056] like Figure 1 , Figure 1 A schematic diagram of the structure of a motor drive module provided by an embodiment of the present invention; a motor drive module, comprising:

[0057] Pulse circuit 1,

[0058] An input circuit 2, the input circuit is connected to an external signal input device to transmit an input signal;

[0059] A PWM circuit 3, wherein the PWM circuit 3 is electrically connected to the pulse circuit 1 and the input protection circuit 2 respectively.

[0060] A power drive protection circuit 4, one end of which is electrically connected to the PWM circuit 3;

[0061] The power switch driving circuit 5 has an input end electrically connected to the PWM circuit 3 , and an output end electrically connected to the other end of the power driving protection circuit 4 .

[0062] The pulse circuit 1 and the input circuit 2 respectively input signals to the PWM circuit 3, and the PWM circuit 3 sends a signal to drive the power switch driving circuit 5 to output a signal, and the power driving protection circuit 4 feeds back a signal to the PWM circuit 3 to adjust the output signal.

[0063] Further, such as Figure 2 and Fig. 9 , Figure 2 A circuit schematic diagram of a pulse circuit provided by an embodiment of the present invention; Fig. 9 The circuit schematic diagram of the motor drive module provided by the embodiment of the present invention; the pulse circuit 1 includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R21, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a transistor VT1, a transistor VT2, a chip N1, a voltage regulator diode VD1, a voltage regulator diode VD2, a diode D1, and a MOS tube Q1, wherein:

[0064] The seventh pin of the chip N1 is electrically connected to one end of the resistor R1, the resistor R2, and the resistor R3, the other end of the resistor R1 is electrically connected to the emitter of the transistor VT1, the other end of the resistor R2 is grounded, the other end of the resistor R3 is electrically connected to the sixth pin and the second pin of the chip respectively, and is electrically connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded;

[0065] The first pin of the chip N1 is grounded, the fifth pin of the chip N1 is electrically connected to the capacitor C5, and the other end of the capacitor C5 is grounded;

[0066] The eighth pin of the chip N1 is an external power supply. In this embodiment, the power supply voltage is preferably 30V, and the fourth pin and the eighth pin of the chip N1 are also electrically connected to the capacitor C2 and one end of the resistor R5. The fourth pin and the eighth pin of the chip N1 are also electrically connected to the drain of the MOS tube Q1. The other end of the capacitor C2 is grounded. The other end of the resistor R5 is electrically connected to the positive electrode of the diode D1. The source of the MOS tube Q1 is respectively connected to the resistor R6 and one end of the capacitor C3. The other end of the capacitor C3 is grounded. The other end of the resistor R6 is electrically connected to the gate of the MOS tube Q1. The gate of the MOS tube Q1 is also electrically connected to the negative electrode of the voltage regulator diode VD2. The positive electrode of the voltage regulator diode VD2 is grounded, and the voltage regulator diode VD2 is connected in parallel with the capacitor C4.

[0067] The base of the transistor VT1 is electrically connected to the negative electrode of the voltage zener diode VD1, the positive electrode of the voltage zener diode VD1 is grounded, the collector of the transistor VT1 is also electrically connected to one end of the resistor R7 and the source of the MOS tube Q1, the source of the MOS tube Q1 is electrically connected to the external power supply, and the other end of the resistor R7 is electrically connected to the negative electrode of the voltage zener diode.

[0068] Preferably, the chip N1 signal is NE555, such as Figure 7 As shown, Figure 7 The schematic diagram of the structure of the chip N1 provided in the embodiment of the present invention is that the chip N1 and the resistors R1, R2 and R3 form a multivibrator. In this way, the pulse circuit 1 has only two temporary stable states, so that the device as a whole does not need an external contact signal. At the same time, an external power supply is used to reversely charge the capacitor C1 through the resistors R1 and R2, and the capacitor C1 is discharged to the chip N1 (the 7th pin, i.e., the discharge terminal DIS) through the resistor R2, so that the circuit oscillates and provides an oscillation signal. In this way, there is no need for an external device to provide an oscillation signal. Figure 8 As shown, Figure 8A waveform diagram provided by an embodiment of the present invention; the capacitor C1 is charged and discharged between 2 / 3 VCC and 1 / 3 VCC, so that the capacitor C1 outputs a series of rectangular waves.

[0069] The time parameters of the output signal are:

[0070] T=tw1+tw2

[0071] tw1=0.7*(R1+R2)*C

[0072] tw2=0.7*R2*C

[0073] Wherein, C is the capacitance of capacitor C1; tw1 is the time required for the voltage to rise from 1 / 3 Vcc to 2 / 3 Vcc, tw2 is the time required for capacitor C1 to discharge, and tw1+tw2 equals one time period.

[0074] In the pulse circuit 1, it is required that both the resistor R1 and the resistor R2 should be no less than 1KΩ, but the sum of the two should not be greater than 3.3MΩ.

[0075] In addition, transistor VT1, voltage stabilizing diode VD1 and resistor R17 form a voltage stabilizing circuit, thereby ensuring the voltage output by capacitor C1 is stable.

[0076] like Figure 3 and Fig. 9 As shown, Figure 3 A circuit schematic diagram of an input protection circuit 2 provided in an embodiment of the present invention, wherein the input protection circuit 2 comprises a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, and a resistor R27, wherein one end of the resistor R8, the resistor R9, the resistor R10, the resistor R11, the resistor R12, and the resistor R13 are respectively connected to an input signal VINA, an input signal VINB, an input signal VINC, an input signal VIND, an input signal VINE, and an input signal VINF;

[0077] One end of the resistor R22 is also connected to the input signal VINA, and the other end of the resistor R22 is grounded; one end of the resistor R23 is also connected to the input signal VINB, and the other end of the resistor R23 is grounded; one end of the resistor R24 ​​is also connected to the input signal VINC, and the other end of the resistor R24 ​​is grounded; one end of the resistor R25 is also connected to the input signal VIND, and the other end of the resistor R25 is grounded; one end of the resistor R26 is also connected to the input signal VINE, and the other end of the resistor R26 is grounded; one end of the resistor R27 is also connected to the input signal VINF, and the other end of the resistor R27 is grounded.

[0078] like Figure 4 and Fig. 9 , Figure 4 A circuit schematic diagram of a PWM circuit 3 provided in an embodiment of the present invention, wherein the PWM circuit 3 includes an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, and an operational amplifier U6, wherein the non-inverting input terminal of the operational amplifier U1 is electrically connected to the other end of the resistor R8, and the inverting input terminal of the operational amplifier U1 is electrically connected to the cathode of the diode D1;

[0079] The non-inverting input terminal of the operational amplifier U2 is electrically connected to the other end of the resistor R9, and the inverting input terminal of the operational amplifier U2 is electrically connected to the cathode of the diode D1;

[0080] The non-inverting input terminal of the operational amplifier U3 is electrically connected to the other end of the resistor R10, and the inverting input terminal of the operational amplifier U3 is electrically connected to the cathode of the diode D1;

[0081] The non-inverting input terminal of the operational amplifier U4 is electrically connected to the other end of the resistor R11, and the inverting input terminal of the operational amplifier U4 is electrically connected to the cathode of the diode D1;

[0082] The non-inverting input terminal of the operational amplifier U5 is electrically connected to the other end of the resistor R12, and the inverting input terminal of the operational amplifier U5 is electrically connected to the cathode of the diode D1;

[0083] The non-inverting input terminal of the operational amplifier U6 is electrically connected to the other end of the resistor R13, and the inverting input terminal of the operational amplifier U6 is electrically connected to the cathode of the diode D1; the operational amplifiers U1-U6 output PWM waveforms;

[0084] like Figure 5 and Fig. 9 , Figure 5 A circuit schematic diagram of a power drive protection circuit 4 provided in an embodiment of the present invention; the power drive protection circuit 4 includes a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, an operational amplifier U7, a capacitor C4, and a diode D8, wherein the cathode of the diode D8 is electrically connected to the cathode of the diode D1, the cathode of the diode D8 is also electrically connected to one end of the resistor R15, the anode of the diode D8 is electrically connected to the output end of the operational amplifier U7, the other end of the resistor R15 is grounded, the in-phase input end of the operational amplifier U7 is electrically connected to one end of the resistor R6, and the other end of the resistor R6 is electrically connected to the positive power supply end of the operational amplifier U7;

[0085] The non-inverting input terminal of the operational amplifier U7 is also electrically connected to one end of a resistor R18, and the other end of the resistor R18 is grounded;

[0086] The inverting input terminal of the operational amplifier U7 is also electrically connected to one end of the resistor R17, the capacitor C4, and the resistor R19; the other ends of the capacitor C4 and the resistor R19 are grounded, the other end of the resistor R17 is electrically connected to the resistor R20, and the other end of the resistor R20 is grounded;

[0087] like Figure 6 and Fig. 9 , Figure 6 A circuit schematic diagram of a power switch driving circuit 5 provided in an embodiment of the present invention, wherein the power switch driving circuit 5 includes a diode D2, a diode D3, a diode D4, a diode D5, a diode D6, a diode D7, a MOS transistor Q2, a MOS transistor Q3, a MOS transistor Q4, a MOS transistor Q5, a MOS transistor Q6, and a MOS transistor Q7, wherein the anode of the diode D2 is electrically connected to the drain of the MOS transistor Q2, and the cathode of the diode D2 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U1 is electrically connected to the gate of the MOS transistor Q2;

[0088] The anode of the diode D3 is electrically connected to the drain of the MOS transistor Q3, and the cathode of the diode D3 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U2 is electrically connected to the gate of the MOS transistor Q3;

[0089] The anode of the diode D4 is electrically connected to the drain of the MOS transistor Q4, and the cathode of the diode D4 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U3 is electrically connected to the gate of the MOS transistor Q4;

[0090] The anode of the diode D5 is electrically connected to the drain of the MOS transistor Q5, and the cathode of the diode D5 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U4 is electrically connected to the gate of the MOS transistor Q5;

[0091] The anode of the diode D6 is electrically connected to the drain of the MOS transistor Q6, the cathode of the diode D6 is electrically connected to the source of the MOS transistor Q1, and the output end of the operational amplifier U5 is electrically connected to the gate of the MOS transistor Q6;

[0092] The anode of the diode D7 is electrically connected to the drain of the MOS transistor Q7, and the cathode of the diode D7 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U6 is electrically connected to the gate of the MOS transistor Q7;

[0093] The sources of the MOS transistors Q2 , Q3 , Q4 , Q5 , Q6 , and Q7 are also electrically connected to one end of the resistors R17 and R20 that are connected to each other.

[0094] The PWM waveform is used to drive the switch MOS tubes Q2-Q7 respectively; the positive electrodes of the diodes D2, D3, D4, D5, D6 and D7 output control signals A, B, C, D, E and F, so that the power drive protection circuit 4 can protect the MOS tubes Q2-Q7 to prevent the components from being burned due to excessive current; the diodes D2, D3, D4, D5, D6 and D7 are used to eliminate the reverse electromotive force generated by the motor to prevent the reverse electromotive force from causing reverse breakdown of the MOS tubes Q1-Q7.

[0095] Preferably, in this embodiment, the operational amplifier U1, operational amplifier U2, operational amplifier U3, operational amplifier U4, operational amplifier U5, operational amplifier U6, and operational amplifier U7 are of model TL072, and the MOS tube Q1, MOS tube Q2, MOS tube Q3, MOS tube Q4, MOS tube Q5, MOS tube Q6, and MOS tube Q7 are of model IRFL4315PbF.

[0096] Working principle: an oscillation signal is generated by resistors R1, R2, R3 and chip N1 in the pulse circuit 1, so there is no need to connect to external equipment to provide an oscillation signal, which reduces losses. The input protection circuit 2 includes multiple resistors for protection. The diodes D2, D3, D4, D5, D6 and D7 are used to eliminate the reverse electromotive force generated by the motor to avoid reverse breakdown of the MOS tubes Q1 to Q7 by the reverse electromotive force, thereby improving the overall safety performance.

[0097] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A motor drive module, characterized in that: include; A pulse circuit (1); the pulse circuit generates an oscillation signal; An input protection circuit (2), wherein the input protection circuit (2) is connected to an external signal input device; A PWM circuit (3), the PWM circuit (3) being electrically connected to the pulse circuit (1) and the input protection circuit (2) respectively; A power drive protection circuit (4), one end of the power drive protection circuit (4) being electrically connected to the PWM circuit (3); A power switch driving circuit (5), wherein an input end of the power switch driving circuit (5) is electrically connected to the PWM circuit (3), and an output end of the power switch driving circuit (5) is electrically connected to the other end of the power drive protection circuit (4); The pulse circuit (1) generates an oscillation signal which is input into the PWM circuit (3), and the input protection circuit (2) prevents excessive current from inputting an external input signal into the PWM circuit (3). The PWM circuit (3) sends a signal to drive the power switch drive circuit (5) to output a signal, and the power drive protection circuit (4) feeds back a signal to the PWM circuit (3) to adjust the output signal. The pulse circuit (1) comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R21, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a transistor VT2, a chip N1, a voltage regulator diode VD2, a diode D1, and a MOS tube Q1, wherein; The seventh pin of the chip N1 is electrically connected to one end of the resistor R1, the resistor R2, and the resistor R3, the other end of the resistor R2 is grounded, the other end of the resistor R3 is electrically connected to the sixth pin and the second pin of the chip respectively, and is electrically connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded; The first pin of the chip N1 is grounded, the fifth pin of the chip N1 is electrically connected to the capacitor C5, and the other end of the capacitor C5 is grounded; The fourth pin and the eighth pin of the chip N1 are also electrically connected to one end of the capacitor C2 and the resistor R5, the fourth pin and the eighth pin of the chip N1 are also electrically connected to the drain of the MOS tube Q1, the other end of the capacitor C2 is grounded, the other end of the resistor R5 is electrically connected to the positive electrode of the diode D1, the source of the MOS tube Q1 is respectively connected to one end of the resistor R6 and the capacitor C3, the other end of the capacitor C3 is grounded, the other end of the resistor R6 is electrically connected to the gate of the MOS tube Q1, the gate of the MOS tube Q1 is also electrically connected to the negative electrode of the voltage-stabilizing diode VD2, the source of the MOS tube Q1 is electrically connected to an external power supply, the positive electrode of the voltage-stabilizing diode VD2 is grounded, and the voltage-stabilizing diode VD2 is connected in parallel with the capacitor C4; One end of the resistor R4 is electrically connected to the third pin of the chip N1, and the other end is connected to the base of the transistor VT2; One end of the resistor R21 is electrically connected to the emitter of the transistor VT2, and the other end is grounded; The cathode of the diode D1 is the output end of the pulse circuit (1); The pulse circuit (1) further comprises a resistor R7, a transistor VT1, and a voltage-stabilizing diode VD1. The emitter of the transistor VT1 is electrically connected to the other end of the resistor R1, the base of the transistor VT1 is electrically connected to the negative electrode of the voltage-stabilizing diode VD1, the positive electrode of the voltage-stabilizing diode VD1 is grounded, the collector of the transistor VT1 is electrically connected to one end of the resistor R7 and the source of the MOS tube Q1, respectively, and the other end of the resistor R7 is electrically connected to the negative electrode of the voltage-stabilizing diode VD1.

2. The motor drive module according to claim 1, characterized in that: The input protection circuit (2) comprises a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, and a resistor R27, wherein one end of the resistor R8, the resistor R9, the resistor R10, the resistor R11, the resistor R12, and the resistor R13 are respectively connected to an input signal VINA, an input signal VINB, an input signal VINC, an input signal VIND, an input signal VINE, and an input signal VINF; One end of the resistor R22 is also connected to the input signal VINA, and the other end of the resistor R22 is grounded; one end of the resistor R23 is also connected to the input signal VINB, and the other end of the resistor R23 is grounded; one end of the resistor R24 ​​is also connected to the input signal VINC, and the other end of the resistor R24 ​​is grounded; one end of the resistor R25 is also connected to the input signal VIND, and the other end of the resistor R25 is grounded; one end of the resistor R26 is also connected to the input signal VINE, and the other end of the resistor R26 is grounded; one end of the resistor R27 is also connected to the input signal VINF, and the other end of the resistor R27 is grounded; The PWM circuit (3) comprises an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, an operational amplifier U4, an operational amplifier U5 and an operational amplifier U6, wherein the non-inverting input terminal of the operational amplifier U1 is electrically connected to the other end of the resistor R8, and the inverting input terminal of the operational amplifier U1 is electrically connected to the cathode of the diode D1; The non-inverting input terminal of the operational amplifier U2 is electrically connected to the other end of the resistor R9, and the inverting input terminal of the operational amplifier U2 is electrically connected to the cathode of the diode D1; The non-inverting input terminal of the operational amplifier U3 is electrically connected to the other end of the resistor R10, and the inverting input terminal of the operational amplifier U3 is electrically connected to the cathode of the diode D1; The non-inverting input terminal of the operational amplifier U4 is electrically connected to the other end of the resistor R11, and the inverting input terminal of the operational amplifier U4 is electrically connected to the cathode of the diode D1; The non-inverting input terminal of the operational amplifier U5 is electrically connected to the other end of the resistor R12, and the inverting input terminal of the operational amplifier U5 is electrically connected to the cathode of the diode D1; The non-inverting input terminal of the operational amplifier U6 is electrically connected to the other end of the resistor R13, and the inverting input terminal of the operational amplifier U6 is electrically connected to the cathode of the diode D1; the output terminals of the operational amplifiers U1-U6 are electrically connected to the power switch driving circuit.

3. The motor drive module according to claim 2, characterized in that: The power drive protection circuit (4) comprises a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, an operational amplifier U7, a capacitor C4, and a diode D8, wherein the cathode of the diode D8 is electrically connected to the cathode of the diode D1, the cathode of the diode D8 is also electrically connected to one end of the resistor R15, the anode of the diode D8 is electrically connected to the output end of the operational amplifier U7, the other end of the resistor R15 is grounded, the in-phase input end of the operational amplifier U7 is electrically connected to one end of the resistor R6, and the other end of the resistor R6 is electrically connected to the positive power supply end of the operational amplifier U7; The non-inverting input terminal of the operational amplifier U7 is also electrically connected to one end of a resistor R18, and the other end of the resistor R18 is grounded; The inverting input terminal of the operational amplifier U7 is also electrically connected to one end of the resistor R17, the capacitor C4, and the resistor R19; the other ends of the capacitor C4 and the resistor R19 are grounded, the other end of the resistor R17 is electrically connected to the resistor R20, and the other end of the resistor R20 is grounded; The cathode of the diode D8 is the output end of the power drive protection circuit (4); The power switch driving circuit (5) comprises: Diode D2, diode D3, diode D4, diode D5, diode D6, diode D7, MOS transistor Q2, MOS transistor Q3, MOS transistor Q4, MOS transistor Q5, MOS transistor Q6, MOS transistor Q7, among which, The anode of the diode D2 is electrically connected to the drain of the MOS transistor Q2, and the cathode of the diode D2 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U1 is electrically connected to the gate of the MOS transistor Q2; The anode of the diode D3 is electrically connected to the drain of the MOS transistor Q3, and the cathode of the diode D3 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U2 is electrically connected to the gate of the MOS transistor Q3; The anode of the diode D4 is electrically connected to the drain of the MOS transistor Q4, and the cathode of the diode D4 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U3 is electrically connected to the gate of the MOS transistor Q4; The anode of the diode D5 is electrically connected to the drain of the MOS transistor Q5, and the cathode of the diode D5 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U4 is electrically connected to the gate of the MOS transistor Q5; The anode of the diode D6 is electrically connected to the drain of the MOS transistor Q6, the cathode of the diode D6 is electrically connected to the source of the MOS transistor Q1, and the output end of the operational amplifier U5 is electrically connected to the gate of the MOS transistor Q6; The anode of the diode D7 is electrically connected to the drain of the MOS transistor Q7, and the cathode of the diode D7 is electrically connected to the source of the MOS transistor Q1; the output end of the operational amplifier U6 is electrically connected to the gate of the MOS transistor Q7; The sources of the MOS transistors Q2 , Q3 , Q4 , Q5 , Q6 , and Q7 are also electrically connected to one end of the resistors R17 and R20 that are connected to each other.

4. The motor drive module according to claim 3, characterized in that: The operational amplifier U1, operational amplifier U2, operational amplifier U3, operational amplifier U4, operational amplifier U5, operational amplifier U6 and operational amplifier U7 are of model TL072.

5. The motor drive module according to claim 3, characterized in that: The model of the MOS tube Q1, MOS tube Q2, MOS tube Q3, MOS tube Q4, MOS tube Q5, MOS tube Q6 and MOS tube Q7 is IRFL4315PbF.

6. The motor drive module according to claim 1, characterized in that: The model of the chip N1 is NE555.

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