Clock fractional divider module, image and / or video processing module, and device

Abstract

The present invention relates to a clock fractional divider module (100) formed as, including or integrating a dual-core lockstep unit (10; 20; 30) therein, wherein the dual-core lockstep unit (10; 20; 30) is configured to enable a clock fractional division device, mechanism or process with error detection, identification and / or correction means, mechanisms or processes attached thereto.

Description

Technical Field

[0001] The invention relates to a clock fractional frequency divider module, an image and / or video processing module and a device, in particular a vehicle. Background Art

[0002] Given the limitations of hardware design complexity, cost, and power consumption, many technical areas involving integrated circuit design involve clock fractional divider modules to establish compliance with required system processing performance. However, in such architectures, the handling of errors or failures that are common causes of major system failures is often still not completely satisfactory. Summary of the invention

[0003] The clock fractional frequency divider module according to the present invention has the advantage of more reliably detecting, identifying and / or correcting possible errors. This is achieved by providing a clock fractional frequency divider module, which is formed as, includes and / or integrates a dual-core lockstep unit, wherein the dual-core lockstep unit is configured to be able to implement a clock fractional frequency division device, mechanism and / or process with an error detection, identification and / or correction device. With such a configuration, possible errors can be more reliably detected, identified and / or corrected.

[0004] The dependent claims contain advantageous embodiments of the invention.

[0005] According to a preferred embodiment of the present invention, the proposed clock fractional divider module may include or integrate a master clock fractional divider module core unit as a first component.

[0006] The master clock fractional frequency divider module core unit may preferably be configured to be able to implement a corresponding underlying clock fractional frequency division process, in particular in a usual or common manner.

[0007] In this regard, in a clock fractional divider module formed according to a preferred embodiment of the present invention, the master clock fractional divider module core unit can be configured to be able to generate corresponding clock enable signals to select and / or enable the input reference clock and / or generate the output clock accordingly.

[0008] Additionally or alternatively, the fractional frequency divider module according to the present invention may include or integrate a checker clock fractional frequency divider module core unit as a second component.

[0009] The checker clock fractional divider module core unit may be configured to enable corresponding error detection, identification and / or correction.

[0010] In such a case, the checker clock fractional divider module core unit may additionally be configured to be able to generate a clock enable signal or a specific clock enable signal, in particular to be compared with a corresponding master core clock enable signal.

[0011] The fractional clock divider module according to the present invention may include or integrate a lockstep comparison unit as a third component.

[0012] The corresponding checker clock fractional divider module core unit may be configured to enable corresponding error identification, detection and / or detection in cooperation with the lockstep comparison unit.

[0013] The lockstep comparison unit may be configured to enable at least one of the following:

[0014] - comparing core clock enable signals of or assigned to the master clock fractional divider module core unit and the checker clock fractional divider module core unit, and in particular generating an error signal if these enable signals differ, and

[0015] - comparing the enable signals of or assigned to the master clock fractional divider module core unit and the checker clock fractional divider module core unit as a master enable signal and a checker enable signal, in particular generating an error signal if these enable signals are different,

[0016] - In particular, both by means of the XOR logical operation.

[0017] According to another preferred embodiment of the present invention, the clock fractional divider module of the present invention can be implemented in whole or in part, in particular one or more of its components or parts of its components, as at least one of a software component and a hardware component or by at least one of a software component and a hardware component, in particular based on one or more semiconductor modules and / or ASICs.

[0018] The invention further relates to an image and / or video processing module comprising and / or having a clock fractional divider module formed and / or configured according to the invention functionally and / or physically connected to the image and / or video processing module.

[0019] Furthermore, the present invention also relates to a device, in particular a vehicle, which comprises an image and / or video processing module designed according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In the following section, embodiments of the present invention are disclosed with reference to the accompanying drawings.

[0021] Figure 1 is a schematic block diagram showing a preferred embodiment of a clock fractional divider module according to a preferred embodiment of the present invention.

[0022] Figure 2 is a schematic block diagram illustrating an alternative preferred embodiment of a fractional clock divider module according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0023] In the following, by reference to the attached Figure 1 and attached Figure 2 The embodiments and technical background of the present invention are described in detail. The same or equivalent elements and the elements that function the same or equivalently are represented by the same reference numerals. The detailed description of the elements and components is not repeated in every case where the elements and components appear.

[0024] The depicted and described features and other characteristics of the embodiments of the present invention may be arbitrarily separated and recombined without departing from the gist of the present invention.

[0025] By reference, but not limited to Figure 1 and Figure 2 , the key aspects of the present invention as outlined above and other features thereof as well as the nature and advantages of the present invention will be further discussed hereinafter.

[0026] The figures show, by means of schematic block diagrams, a preferred embodiment of a fractional clock divider module 100 according to the invention.

[0027] In these embodiments, the clock fractional divider module 100 is generally formed by a master clock fractional divider module core unit 10 as a first component, a checker clock fractional divider module core unit 20 as a second component, and a lockstep comparison unit 30 as a third unit. These units are connected with other components by means of a wiring pattern 150.

[0028] Each of the components, a group of components or the fractional clock divider module 100 itself may be formed partly or completely as hardware, for example as an ASIC component, and / or as a programming structure or as a software entity within a programmable structure.

[0029] (1) The present invention proposes, inter alia, improvements to the clock fractional divider module 100 or CFDM, and, inter alia, corresponding improved operation and / or control methods.

[0030] (2) According to a particular view of one of the main points of the present invention, a potential key aspect of the present invention is to provide and thereby integrate a dual-core lockstep scheme method and / or architecture, module and / or device - that is, or for example, within a common clock fractional divider module 100 or CFDM and method, in particular, so as to achieve an error identification / correction mechanism with an improved and / or increased error identification / correction rate.

[0031] (3) The dual-core configuration 10; 20; 30 - in the corresponding CFD module 100 and / or method - includes a main CFDM core 10 as a first component and a checker CFDM core 20 as a second component.

[0032] (4) The main CFDM core 10 implements the usual and / or well-known fractional clock division process.

[0033] (5) Checker The CFDM core 20 is configured to be capable of being used for error detection or in combination with error detection, in particular in cooperation with a third component that implements a lockstep comparison unit 30 or processing, which is further provided as other additional or optional key components of the concept of the present invention.

[0034] (6) Figure 1 and 2 An embodiment of the configuration of the present invention is explained.

[0035] (7) According to certain additional or alternative aspects of the gist of the present invention, a potential key aspect of the present invention lies in providing - that is, in addition to the usual and / or well-known fractional clock division processing and / or mapping module implemented by the above-mentioned main CFDM core component 10 and / or processing - an additional checker core unit 20 and / or lock-step comparison unit 30 as a module component and / or as a processing component.

[0036] (8) Still according to other additional or alternative aspects of the gist of the present invention, when starting from an embodiment of the configuration of the present invention, roughly speaking, the known or prior art configuration is obtained by omitting only the checker core unit and the lockstep comparison unit. Technical Background

[0038] Fractional clock division is often employed in common integrated circuit designs to meet required system processing performance while limiting hardware design complexity, cost, and power consumption.There are several techniques that are widely described in the open literature and are generally known to those of ordinary skill in the art.

[0039] Failures in clock generation and clock control generally represent common cause error sources and can lead to major system failures.

[0040] There are systems and applications such as safety-critical systems that require specific error detection and control mechanisms to prevent and mitigate the effects of clock failures.

[0041] There are some clock monitoring techniques to detect clock errors. Most of them are designed to be able to detect clock errors at a given stage of the clock tree by relying on a dual clock scheme in which a fast clock signal is monitored with reference to a reference slow clock signal. An error is detected when the difference between the number of fast clock cycles within one cycle of the slow reference clock is greater than a predetermined threshold (which depends on the expected relative jitter between the two clock signals).

[0042] In such an approach, the independence of the two clock sources is critical to preventing common cause failures.

[0043] The invention solves inter alia the problem in which the generation of the corresponding clock signal is instead monitored at the source and under the assumption that the input reference clock is correct.

[0044] In particular and according to a particular definition of the present invention, a programmable or programmed clock-fractional divider module (CFDM) 100 and / or process embeds a dual-core lock step (DCLS) error detection mechanism that enables high clock fault detection capabilities.

[0045] Detailed aspects of the invention

[0046] The CFDM 100 is configured to be operable as a direct digital synthesizer that takes a reference clock as input and generates an output clock signal by gating the input clock based on a programmable preload counter value that determines a clock division factor.

[0047] According to a specific embodiment and in order to simplify the description of the invention, it may be assumed that the DCLS-CFDM 100 can be programmed or programmed by a corresponding system via a suitable register interface 120 , 40 , for example based on the well-known AMBA APB (ARM-Peripheral-Bus) protocol.

[0048] The CFDM 100 described herein is characterized in particular by having a dual core lockstep (DCLS) architecture 10; 20; 30, which is capable of and is configured to detect errors in the generated output clock, and includes a master clock fractional divider module core unit 10 as a first component, a checker clock fractional divider module core unit 20 as a second component, and a lockstep comparison unit 30 as a third component.

[0049] Therefore, the dual core lock-step (DCLS) CFDM architecture 10; 20; 30 can be composed of or include a main CFDM core 10, a checker CFDM core 20 and / or a lock-step comparison unit (LCSU) 30.

[0050] The fractional clock divider 100 and the DCLS architecture 10; 20; 30 will be described below together with an error detection mechanism according to a preferred embodiment of the present invention.

[0051] Fractional Clock Divider

[0052] The master CFDM core unit 10 , hereinafter referred to as the master core, may be configured to be able to perform the actual function of fractional clock division, while the checker core unit 20 together with the lockstep comparison unit 30 supports clock error detection.

[0053] Fractional clock division is performed based on a multi-phase representation of the input clock signal and relies on a preloaded N-bit phase reference value and an N-bit adder with carry.

[0054] Figure 1 and Figure 2 A block diagram of a DCLS CFDM according to an embodiment of the present invention is shown, wherein in this particular embodiment, the case of N=8 bits is considered.

[0055] N-bit precision allows the input clock signal to be represented as a multi-phase signal with K equal to 2 to the Nth power phases and a period that is K times the input clock period.

[0056] Let fc_in, Tc_in=1 / fc_in, Tc_polyphase=K×Tc_in represent the input clock frequency, input clock period and multi-phase input clock signal period respectively.

[0057] The preload counter reference value determines which phases of the input clock from the K phases of each period Tc_polyphase are enabled and which are gated. To implement clock gating control, the preload value of the reference phase is added to the phase count value, and if the N-bit adder result is greater than (K-1), a carry signal is issued (i.e., the carry bit is set to "1"). The carry signal is connected to the clock enable input port of the clock gating unit to release the clock gating when it is issued.

[0058] The described mechanism generates an output clock signal consisting of a series of clock pulses that may satisfy one or more of the following properties:

[0059] - Each clock pulse lasts for the time span of Tc_in.

[0060] - Successive clock pulses are usually spaced at variable time intervals, but always at integer multiples of the time span of Tc_in.

[0061] - The complete sequence of clock pulses is periodic, having a period at least equal to the time period of Tc_polyphase.

[0062] The number of clock pulses per period Tc_polyphase is equal to the preloaded phase reference value mst_phase_ref, where mst_phase_ref may range from 0 to (K-1).

[0063] - The average output clock frequency is given by fc_out = fc_in x mst_phase_ref / K, so that the clock frequency ratio fc_out / fc_in ranges from 0, 1 / K, 2 / K, ..., (K-1) / K.

[0064] Dual-core lock-step CFDM

[0065] The clock error detection mechanism is now described. The DCLS CFDM architecture supports or is configured to support one or more of the following aspects:

[0066] - Transient and permanent error or fault detection in the master and / or checker CFDM logic units 10 and 20.

[0067] - Detection of wrong phase reference values ​​due to corruption of register contents.

[0068] - Detection of wrong phase reference values ​​due to register address corruption which may occur when the system programs the reference values.

[0069] -Detection of erroneous CFDM enable and / or bypass control due to corrupted register contents.

[0070] Clock Enable Error Detection

[0071] In the DCLS architecture, the master core 10 is monitored by means of a checker CFDM core 20, hereinafter referred to as the checker core 20, which includes the same phase counter and clock enable logic, receives the same input signals, and generates the same clock enable / select signal under normal operating conditions.

[0072] The master clock enable / strobe signal and the checker clock enable / strobe signal are continuously compared at each input clock cycle by the LSCU 30. When the two signals are different, an error signal clk_err_pulse is generated.

[0073] In practice, the clock enable error detected by the dedicated LSCU 30 results in fast successive pulses at the same speed as the input clock, so it is difficult to observe. Therefore, for easy observation, the clk_err_pulse pulse signal is converted to a level-based output error signal clk_err by means of suitable glue logic.

[0074] Once the master-checker clock is enabled and the LSCU detects the first error pulse, the clk_err signal is issued and its state remains unchanged regardless of subsequent error pulses until the corresponding reset signal is issued (i.e., soft reset rst_func_soft or full HW reset preset_n).

[0075] Additionally, to provide robust resilience to common cause faults, the checker core input signal is delayed by two clock cycles, while the master core clock enable signal is delayed by two clock cycles to ensure synchronous lock-step comparison of the master clock enable signal and the checker clock enable signal.

[0076] Phase reference error detection

[0077] To prevent common cause failures due to corrupted phase reference values, the CFDM main core phase reference value and the checker core phase reference value may be programmed via two different registers mapped to different addresses.

[0078] This mechanism has two advantages:

[0079] (1) Ensure that the fault phase reference value is not shared by both the master core phase counter and the checker core phase counter. Otherwise, the same fault clock enable signal will be generated by both the master core 10 and the checker core 20, respectively, and it will not be observed by the LSCU 30.

[0080] (2) When the system programs the reference value, different addresses are used to provide effective end-to-end address protection.

[0081] Main and checker cores enable error detection

[0082] To prevent common cause failures due to faulty CFDM enable / bypass control caused by corruption of the control register contents, dedicated master enable and checker enable signals (mst_enable and chk_enable, respectively) may be used and mapped on separate bits into a single control register as described in the register address mapping table.

[0083] The mst_enable and chk_enable bit signals are compared by the LCSU (ie, via an XOR operation), and if they are different, an error signal ctrl_err_pulse is generated. For the clk_err_pulse signal, for ease of viewing, the ctrl_err_pulse pulse signal is converted to a level-based output error signal clk_err by means of appropriate glue logic.

[0084] Once the main core 10 and the checker core 20 respectively enable signals and the LSCU detects the first error pulse, the clk_err signal is issued, and its state remains unchanged regardless of subsequent error pulses until the corresponding reset signal is issued (ie, soft reset rst_func_soft or full HW reset preset_n).

[0085] To reduce design complexity, a unique enable signal is internally generated at the input of both the master core 10 and the checker core 20. The internal enable signal is issued in the case where the master enable signal and the checker enable signal are issued by programming the corresponding control register bits. This mechanism ensures timely detection of a single-event-upset that may cause a single bit in the enable control register to flip.

[0086] However, if the respective enable signals of the main core 10 or the checker core 20 fail due to incorrect programming of the control register or HW random failure, the CFDM will be set to bypass mode so that the output clock will be equal to the input clock. In these cases, the system safety state can be ensured based on the ctrl_err error signal and by reading back the contents of the control register.

[0087] Figure 1 One specific embodiment of a dual-core lock-step CFDM block diagram is shown.

[0088] In this particular embodiment, the registers and system register interface are located in a dedicated clock domain represented by pclk represented by 101, while the rest of the logic is located in the clk_in clock domain represented by 102. Such an architecture allows for improved hardware design flexibility and separation between configuration and actual clock division logic.

[0089] Reference Figure 1According to a preferred embodiment of the present invention, one or more of the following aspects can be implemented by the embodiment of the present invention:

[0090] - A CFDM master core 10 configured to be able to generate a clock enable signal to gate or enable an input reference clock and generate an output clock accordingly.

[0091] - A CFDM checker core 20 configured to be able to generate a clock enable signal to be compared with the master core clock enable signal.

[0092] - A LSCU or lockstep comparison unit 30 configured to be able to perform, in particular by means of an XOR logic operation, a comparison of the master CFDM core clock enable signal and the checker CFDM core clock enable signal and, if they are different, to generate an error signal denoted clk_err_pulse.

[0093] - The LSCU may alternatively or additionally perform - for example by means of an XOR logic operation - a comparison of the main enable signal and the checker enable signal and, if they are different, generate an error signal denoted ctrl_err_pulse.

[0094] - A glue pulse to level conversion logic configured to generate output signals clk_err and ctrl_err (belonging to clk_in and pclk clock domains, respectively) capable of generating clk_err_pulse and ctrl_err_pulse, respectively.

[0095] An output port, which is related to the clk_err error signal and the ctrl_err error signal, to be connected to the error control module 104 .

[0096] - Clock input port, which is used to input reference clocks clk_in and pclk.

[0097] - Reset input port, which is used for external reset control signal preset_n of pclk clock domain. Figure 2 In the particular embodiment shown in , for simplicity, the clk_in clock domain reset is generated internally by the resynchronization signal preset_n, although a separate reset signal may also be used.

[0098] - An output clock port, corresponding to the CFDM output clock signal clk_out, for being connected to a corresponding clock domain.

[0099] - Output port that reports the master CFDM clock gating status (ie, whether the output clock is fully gated).

[0100] - Glue synchronization logic (which is used for clock domain crossing).

[0101] - A register system interface connected to a set of registers including the master CFDM reference phase values ​​and the checker CFDM reference phase values ​​required for the clock division and lockstep comparison operations.

[0102] - Control registers for master CFDM core enable / bypass control and checker CFDM core enable / bypass control.

[0103] - Register for soft reset control soft_reset.

[0104] - Test mode enable and test bypass reset input ports for connection to a test controller.

[0105] The present invention can be used in a general video processing acceleration module and the like as well as in their respective application programs.

[0106] like Figure 1 and Figure 2 As shown in , the present invention particularly includes the following components:

[0107] 10 first component, master clock fractional divider module core unit, 11 internal master core, 12 components of the internal master core, 13 components of the external master core, 20 second component, checker clock fractional divider module core unit, 21 internal checker core, 22 components of the internal checker core, 23 components of the external checker core located on the output side, 24 components of the external checker core located on the input side, 30 third component, lockstep comparison unit, 40 control register unit, 41 components of the control register unit, 50 glue synchronization logic unit, 51 components of the glue synchronization logic unit, 60 clock enable lockstep comparison unit, 61 components of the lockstep comparison unit 60, 70 pulse to level glue logic unit, 71 components of the pulse to level glue logic unit, 100 clock fractional divider module, 101 pclk clock domain unit, 102 clk_in clock domain unit, 103 pulse to level glue logic unit, 104 error control unit, 105 output, clock domain, clock domain output, 110 port unit, 111 port for WDRU, 112 port for CGU, 113 port for DFT CTRL, 114 port for other partitions, 120 system interface, 150 wiring, wiring pattern.

Claims

1. A clock fractional divider module (100), - The clock fractional divider module (100) integrates a dual-core lockstep unit (10; 20; 30), - The dual-core lockstep unit (10; 20; 30) is configured to be capable of performing clock fractional division processing with error detection, identification, and / or correction processing attached, - The clock fractional divider module (100) integrates a main clock fractional divider module core unit (10) as a first component, - The main clock fractional divider module core unit (10) is configured to be capable of performing corresponding clock fractional division processing, Wherein, The main clock fractional divider module core unit (10) is configured to be capable of generating a corresponding clock enable signal to gate and / or enable an input reference clock and / or correspondingly generate an output clock.

2. The clock fractional divider module (100) according to claim 1, Wherein, - The clock fractional divider module (100) integrates an inspector clock fractional divider module core unit (20) as a second component, - Wherein, the inspector clock fractional divider module core unit (20) is configured to be capable of performing corresponding error detection, identification, and / or correction.

3. The clock fractional divider module (100) according to claim 2, Wherein, The inspector clock fractional divider module core unit (20) is configured to be capable of generating a corresponding clock enable signal.

4. The clock fractional divider module (100) according to claim 3, Wherein, The clock enable signal is used to compare with a corresponding main core clock enable signal.

5. The clock fractional divider module (100) according to any one of the preceding claims, - The clock fractional divider module (100) includes or integrates a lockstep comparison unit (30) as a third component, - Wherein, The corresponding inspector clock fractional divider module core unit (20) is configured to be capable of performing corresponding error identification, detection, and / or collaborative detection with the lockstep comparison unit (30).

6. The clock fractional divider module (100) according to claim 5, Wherein, The lockstep comparison unit (30) is configured to be capable of performing at least one of the following: - Comparing the core clock enable signals of the main clock fractional divider module core unit (10) and the inspector clock fractional divider module core unit (20) or assigned to the main clock fractional divider module core unit (10) and the inspector clock fractional divider module core unit (20), and if these enable signals are different, generating an error signal, and - Comparing the enable signals of the main clock fractional divider module core unit (10) and the inspector clock fractional divider module core unit (20) or assigned to the main clock fractional divider module core unit (10) and the inspector clock fractional divider module core unit (20) as the main enable signal and the inspector enable signal, and if these enable signals are different, generating an error signal, - Both by means of XOR logic operation.

7. The clock fractional divider module (100) according to any one of claims 1-4 and 6, which is implemented in whole or in part as at least one of a software component and a hardware component or is implemented by at least one of a software component and a hardware component.

8. The clock fractional divider module (100) according to claim 7, which is implemented in whole or in part based on one or more semiconductor modules and / or ASICs.

9. An image and / or video processing module (1), the image and / or video processing module (1) comprising: The clock fractional divider module (100) according to any one of the preceding claims, which is functionally and / or physically connected to the image and / or video processing module (1).

10. A device comprising the image and / or video processing module (1) according to claim 9.

11. The device according to claim 10, wherein, the device is formed as a vehicle.

Images