Reliability Testing System for Laser Chips

Abstract

The present invention discloses a reliability test system for a laser chip, which includes a substrate, a carrier board and a first PCB. A chip slot is formed on the carrier board, and chip probes are provided on the first PCB. A TEC is installed between the substrate and the carrier board, and a heat insulation plate is installed between the substrate and the first PCB. A heat insulation through slot is formed in this heat insulation plate; a connection contact, a test contact, a welding contact and a power supply contact are provided on a second PCB. The first PCB and a backing plate are installed on the substrate through a fixing screw. A limiting rod is further provided on the substrate, and a limiting spring is sleeved on this limiting rod. A limiting hole for the limiting rod to be inserted into is formed on the backing plate, and a strip-shaped guiding hole is communicated and opened on the backing plate on one side of this limiting hole, and this strip-shaped guiding hole is located on the side of the backing plate close to the chip; the welding contact is located on the bottom surface of the second PCB, and a welding through hole corresponding to the welding contact is formed on the bottom surface of the substrate. The present invention can not only improve the temperature control accuracy, but also test multiple chips at a time, effectively improving the test efficiency.

Description

Technical Field

[0001] The present invention relates to a reliability test system for a laser chip, belonging to the technical field of chip processing. Background Art

[0002] Chip aging test is an electrical stress test method that uses voltage and high temperature to accelerate the electrical failures of devices. Among them, the aging process basically simulates the entire life of the chip because the electrical excitation applied during the aging process reflects the worst-case scenario of the chip's operation.

[0003] Aging tests can be used as a detection of device reliability or as a production window to discover early failures of devices. Generally, the device used for chip aging tests works together with an external circuit board through a test socket. In the existing aging test fixtures, the heat source that provides temperature is far from the chip, the temperature control accuracy is poor, and only one chip can be tested at a time, which is very troublesome. Summary of the Invention

[0004] The purpose of the present invention is to provide a reliability test system for a laser chip, which can not only improve the temperature control accuracy but also test multiple chips at a time, effectively improving the test efficiency.

[0005] To achieve the above object, the technical solution adopted by the present invention is: a reliability test system for a laser chip, including a substrate, a carrier board mounted on the substrate, and a first PCB mounted on the carrier board. A chip slot for embedding the chip is opened on the carrier board. Chip probes corresponding to the chip slot are provided on the first PCB. A plurality of TECs are installed between the substrate and the carrier board, and these TECs are located directly below the chip slot. A heat insulation plate is installed between the substrate and the first PCB, and a heat insulation through slot for embedding the TEC is opened in this heat insulation plate;

[0006] The first PCB is mounted on the heat insulation plate. A second PCB is mounted on the substrate. The second PCB has connection contacts, test contacts communicated with the connection contacts, welding contacts, and power supply contacts communicated with the welding contacts. Connection probes corresponding to the connection contacts are provided on the first PCB. The test contacts are used to connect external devices. The power connection pins of the TECs are welded to the welding contacts;

[0007] A spacer is installed between the first PCB and the heat insulation plate. Probe through holes for the chip probes and the connection probes to pass through are opened on this spacer. The first PCB and the spacer are installed on the substrate through a fixing screw. A limiting rod is also provided on the substrate. A limiting spring located between the spacer and the carrier board is sleeved on this limiting rod. A limiting hole for the limiting rod to be embedded is opened on the spacer. A strip-shaped guiding hole is also communicated and opened on the spacer on one side of the limiting hole, and this strip-shaped guiding hole is located on the side of the spacer close to the chip;

[0008] The solder contact points are located on the bottom surface of the second PCB, and welding through-holes corresponding to the solder contact points are formed in the bottom surface of the substrate.

[0009] The further improved solutions in the above technical solutions are as follows:

[0010] 1. In the above solution, an installation groove for embedding the TEC is formed in the top surface of the substrate.

[0011] 2. In the above solution, two installation grooves are spaced apart, and two carrier plates are provided and are respectively located in the two installation grooves.

[0012] 3. In the above solution, the number of TECs in one of the installation grooves is four, and two of the chip grooves correspond to one TEC.

[0013] 4. In the above solution, a heat insulation groove for embedding a heat insulation plate is formed at the side edge of the top surface of the substrate, and the installation groove is formed at the bottom of the heat insulation groove.

[0014] 5. In the above solution, an arc-shaped opening is formed at the corner of the heat insulation groove.

[0015] 6. In the above solution, a stepped groove for embedding a carrier plate is formed at the side edge of the top surface of the heat insulation plate.

[0016] 7. In the above solution, a positioning rod is provided on the substrate, and positioning holes for embedding the positioning rod are formed in the heat insulation plate, the carrier plate and the backing plate.

[0017] Due to the application of the above technical solutions, the present invention has the following advantages compared with the prior art:

[0018] 1. In the reliability test system for laser chips of the present invention, a plurality of TECs are installed between the substrate and the carrier plate. The TECs are located directly below the chip grooves. By installing a TEC, i.e., a semiconductor cooler, between the substrate and the PCB, and installing a carrier plate for placing chips on the TEC, the chips are directly placed on the TEC for heating and temperature control. The TEC can directly heat the chips, which not only has a fast heating speed and high efficiency, but also has a high temperature control accuracy. The test results of each chip are less affected by temperature fluctuations. A heat insulation plate is installed between the substrate and the first PCB. A heat insulation through-groove for embedding the TEC is formed in the heat insulation plate. By installing the TEC into the heat insulation through-groove of the heat insulation plate with heat insulation function, on the one hand, the heat generated by the TEC can be prevented from dissipating to the surroundings through the heat insulation plate, improving the heating efficiency. On the other hand, through the setting of the heat insulation through-groove, the heating effect of the TEC is limited to the chip grooves of the carrier plate, making the temperature control accuracy of the TEC higher, and reducing the temperature fluctuation amplitude caused by the energy dissipating to the surroundings, further reducing the influence of temperature fluctuation on the test accuracy.

[0019] 2. For the reliability test system for laser chips of the present invention, the first PCB is installed on a heat insulation board, and a second PCB is installed on the substrate. The second PCB has connection contacts, test contacts communicating with the connection contacts, welding contacts, and power supply contacts communicating with the welding contacts. The first PCB has connection probes corresponding to the connection contacts. The test contacts are used to connect external devices. The power connection pins of the TEC are welded to the welding contacts. Since the TEC component needs an external power supply, the PCB not only needs to be connected to the TEC to achieve integrated power supply, but also needs to be connected to the chip during use to facilitate chip testing by the staff. However, when disassembling and assembling the chip, it is necessary to move to release the contact between the PCB probe and the chip. On the one hand, it is required that the PCB connected to the chip can move relative to the substrate. On the other hand, it is required that the PCB welded and fixed to the TEC cannot move to avoid affecting the heating and temperature control function of the TEC. Therefore, by modularizing the PCB into a first PCB with chip probes and connection probes and a second PCB with connection contacts, test contacts, welding contacts, and power supply contacts, the connection and disconnection with the chip are realized by using the movable first PCB, and then the testing of the chip is realized by the connection between the first PCB and the second PCB, thereby meeting multiple requirements such as power supply, testing, disassembly, and assembly, which is very convenient.

[0020] 3. For the reliability test system for laser chips of the present invention, the first PCB and the backing plate are installed on the substrate through a fixing screw. A limiting rod is also provided on the substrate, and a limiting spring located between the backing plate and the carrier plate is sleeved on the limiting rod. A limiting hole for the limiting rod to be inserted into is opened on the backing plate, and a strip-shaped guiding hole is also communicated and opened on the backing plate on one side of the limiting hole, and this strip-shaped guiding hole is located on the side of the backing plate close to the chip. Through the setting of the fixing screw, the first PCB can be stably connected to the chip. And the limiting spring still has a certain thickness after being compressed, so that the carrier plate and the backing plate are isolated by the compressed limiting spring to form a light passing gap, which is convenient for the laser chip to complete optoelectronic testing. At the same time, after the fixing screw is loosened, the limiting spring can automatically lift the backing plate to separate the chip probe of the first PCB from the chip, which is convenient for the staff to operate the chip in the chip slot. And the limiting rod inserted into the limiting hole can slide along the strip-shaped guiding hole communicated with the limiting hole, so that the backing plate and the first PCB board are far away from the chip slot, avoiding the chip probe, the backing plate and the first PCB from affecting the disassembly and assembly of the chip.

[0021] 4. The reliability test system for the laser chip of the present invention has solder joints located on the bottom surface of the second PCB. Welding through-holes corresponding to the solder joints are opened on the bottom surface of the substrate. Since the power connection pins of the TEC need to be soldered to the solder joints of the second PCB, in order to avoid problems with poor quality during the TEC soldering process, after the TEC is soldered, it is difficult for each TEC to maintain in the same reference plane, resulting in different sizes of gaps between the carrier board installed on multiple TECs and the TECs, making it difficult to fit completely. This will not only affect the installation of the carrier board but also, due to the existence of different sizes of gaps, cause the chips corresponding to different TECs to be in different temperature ranges, with poor test accuracy for a single chip and large differences in the test results of the same batch of chips, thus affecting the use of the fixture. Therefore, the welding through-holes on the substrate expose the solder joints, and the heat insulation plate, carrier board, and TEC are pre-assembled into one body and installed in the heat insulation groove. The staff can not only directly realize the soldering of the power connection pins and the solder joints but also avoid the offset of the TEC due to the soldering work, thereby ensuring the uniformity of TEC heating and temperature control.

[0022] 5. The reliability test system for the laser chip of the present invention has two installation grooves spaced apart. The carrier boards are provided in two and are respectively located in these two installation grooves. The number of TECs in one installation groove is four, and two chip grooves correspond to one TEC. By setting multiple TECs in the installation grooves, the heating efficiency and density of the heat source are further increased, so that more chip grooves can be opened on the carrier board, and the connection and testing of each chip are integrated by the cooperation of the first PCB and the second PCB, thereby improving the test efficiency of the chips and reducing the test cost. Description of the Drawings

[0023] Att Figure 1 is the overall structure schematic diagram of the reliability test system for the laser chip of the present invention;

[0024] Att Figure 2 is the partial exploded view of the reliability test system for the laser chip;

[0025] Att Figure 3 is for Att Figure 2 the exploded view of part A in

[0026] Att Figure 4 is the partial exploded view of another perspective of the reliability test system for the laser chip;

[0027] Att Figure 5 is the bottom structure schematic diagram of the reliability test system for the laser chip;

[0028] Att Figure 6 is the exploded structure schematic diagram of the backing plate and the first PCB part.

[0029] In the above drawings: 1. Substrate; 11. Limiting rod; 12. Limiting spring; 16. Welding through-hole; 101. Installation groove; 106. Positioning rod; 107. Positioning hole; 108. Heat insulation groove; 109. Arc-shaped opening; 2. Carrier board; 201. Chip slot; 3. First PCB; 31. Chip probe; 32. Connecting probe; 4. TEC; 41. Power connection pin; 5. Heat insulation board; 51. Heat insulation through-channel; 501. Step groove; 6. Second PCB; 61. Connecting contact; 62. Testing contact; 63. Welding contact; 64. Power supply contact; 7. Pad; 71. Fixing screw; 72. Limiting hole; 73. Strip-shaped guiding hole; 701. Probe through-hole. Detailed implementation mode

[0030] Embodiment 1: A reliability test system for a laser chip, referring to the attached Figures 1-6 drawings, which includes a substrate 1, a carrier board 2 mounted on the substrate 1, and a first PCB 3 mounted on the carrier board 2. A chip slot 201 for a chip to be embedded is formed on the carrier board 2. Chip probes 31 corresponding to the chip slot 201 are provided on the first PCB 3. A plurality of TECs 4 are installed between the substrate 1 and the carrier board 2, and these TECs 4 are located directly below the chip slot 201. A heat insulation board 5 is installed between the substrate 1 and the first PCB 3, and a heat insulation through-channel 51 for the TEC 4 to be embedded is formed in this heat insulation board 5;

[0031] The first PCB 3 is mounted on the heat insulation board 5. A second PCB 6 is mounted on the substrate 1. Connecting contacts 61, testing contacts 62 communicating with the connecting contacts 61, welding contacts 63, and power supply contacts 63 communicating with the welding contacts 63 are provided on this second PCB 6. Connecting probes 32 corresponding to the connecting contacts 61 are provided on the first PCB 3. The testing contacts 62 are used to connect external devices. The power connection pins 41 of the TEC 4 are welded to the welding contacts 63;

[0032] A pad 7 is installed between the first PCB 3 and the heat insulation board 5. A probe through-hole 701 for the chip probes 31 and the connecting probes 32 to pass through is formed on this pad 7. The first PCB 3 and the pad 7 are mounted on the substrate 1 through a fixing screw 71. A limiting rod 11 is also provided on the substrate 1. A limiting spring 12 located between the pad 7 and the carrier board 2 is sleeved on this limiting rod 11. A limiting hole 72 for the limiting rod 11 to be embedded is formed on the pad 7. A strip-shaped guiding hole 73 is also communicated and opened on the pad 7 on one side of the limiting hole 72, and this strip-shaped guiding hole 73 is located on the side of the pad 7 close to the chip;

[0033] The welding contacts 63 are located on the bottom surface of the second PCB 6. Welding through-holes 16 corresponding to the welding contacts 63 are formed on the bottom surface of the substrate 1.

[0034] The top surface of the above-mentioned substrate 1 is provided with mounting grooves 101 for embedding the TEC 4; there are two mounting grooves 101 spaced apart, and the carrier plates 2 are provided in two and are respectively located in these two mounting grooves 101; the number of TEC 4 in one of the mounting grooves is four, and two of the chip grooves 201 correspond to one TEC 4.

[0035] At the side edge of the top surface of the above-mentioned substrate 1, there is a heat insulation groove 108 for embedding the heat insulation plate 5, and the mounting groove 101 is opened at the bottom of the heat insulation groove 108; an arc-shaped opening 109 is opened at the corner of the heat insulation groove 108.

[0036] At the side edge of the top surface of the above-mentioned heat insulation plate 5, there is a stepped groove 501 for embedding the carrier plate 2; there is a positioning rod 106 on the above-mentioned substrate 1, and positioning holes 107 for embedding the positioning rod 106 are opened on the heat insulation plate 5, the carrier plate 2 and the spacer plate 7.

[0037] Embodiment 2: A reliability test system for a laser chip, referring to the attached Figures 1-6 , including a substrate 1, a carrier plate 2 mounted on the substrate 1, and a first PCB 3 mounted on the carrier plate 2. The carrier plate 2 is provided with chip grooves 201 for embedding chips. The first PCB 3 is provided with chip probes 31 corresponding to the chip grooves 201. A plurality of TEC 4 are installed between the substrate 1 and the carrier plate 2, and the TEC 4 is located directly below the chip grooves 201. A heat insulation plate 5 is installed between the substrate 1 and the first PCB 3, and a heat insulation through groove 51 for embedding the TEC 4 is opened in the heat insulation plate 5;

[0038] The first PCB 3 is mounted on the heat insulation plate 5. A second PCB 6 is mounted on the substrate 1. The second PCB 6 is provided with connection contacts 61, test contacts 62 communicated with the connection contacts 61, welding contacts 63, and power supply contacts 63 communicated with the welding contacts 63. The first PCB 3 is provided with connection probes 32 corresponding to the connection contacts 61. The test contacts 62 are used to connect external devices, and the power connection pins 41 of the TEC 4 are welded on the welding contacts 63;

[0039] A spacer plate 7 is installed between the first PCB 3 and the heat insulation plate 5. The spacer plate 7 is provided with probe through holes 701 for the chip probes 31 and the connection probes 32 to pass through. The first PCB 3 and the spacer plate 7 are mounted on the substrate 1 through a fixing screw 71. A limiting rod 11 is further provided on the substrate 1. A limiting spring 12 located between the spacer plate 7 and the carrier plate 2 is sleeved on the limiting rod 11. The spacer plate 7 is provided with a limiting hole 72 for the limiting rod 11 to be embedded. A strip-shaped guiding hole 73 is further communicated and opened on the spacer plate 7 on one side of the limiting hole 72, and the strip-shaped guiding hole 73 is located on the side of the spacer plate 7 close to the chip;

[0040] The solder contact point 63 is located on the bottom surface of the second PCB 6, and a soldering through hole 16 corresponding to the solder contact point 63 is formed on the bottom surface of the substrate 1.

[0041] An installation groove 101 for embedding the TEC 4 is formed on the top surface of the substrate 1; there are two installation grooves 101 spaced apart; the carrier plates 2 are provided in two and are respectively located in the two installation grooves 101; the number of TECs 4 in one installation groove is four, and two chip grooves 201 correspond to one TEC 4.

[0042] A heat insulation groove 108 for embedding the heat insulation plate 5 is formed at the side edge of the top surface of the substrate 1, and the installation groove 101 is formed at the bottom of the heat insulation groove 108; an arc-shaped opening 109 is formed at the corner of the heat insulation groove 108. A stepped groove 501 for embedding the carrier plate 2 is formed at the side edge of the top surface of the heat insulation plate 5.

[0043] When the above-mentioned reliability test system for laser chips is adopted, by installing a TEC, i.e., a semiconductor refrigerator, between the substrate and the PCB, and installing a carrier plate for placing the chips on the TEC, the chips are directly placed on the TEC for heating and temperature control. The TEC can directly heat the chips, which not only has a fast heating speed and high efficiency, but also has high temperature control accuracy, and the test results of each chip are less affected by temperature fluctuations; by installing the TEC into the heat insulation through groove of the heat insulation plate with heat insulation function, on the one hand, the heat generated by the TEC can be blocked from dissipating to the surrounding by the heat insulation plate, improving the heating efficiency, on the other hand, the heating effect of the TEC is limited at the chip groove of the carrier plate through the setting of the heat insulation through groove, making the temperature control accuracy of the TEC higher, and reducing the temperature fluctuation amplitude caused by the energy dissipating to the surrounding, further reducing the influence of temperature fluctuation on the test accuracy.

[0044] In addition, since the TEC component needs to be externally powered, the PCB not only needs to be connected to the TEC to achieve integrated power supply, but also needs to be connected to the chips during use to facilitate the staff to test the chips. However, when disassembling and assembling the chips, it is necessary to move and release the contact between the PCB probe and the chips. On the one hand, it is required that the PCB connected to the chips can move relative to the substrate, and on the other hand, it is required that the PCB welded and fixed to the TEC cannot move to avoid affecting the heating and temperature control function of the TEC. Therefore, by modularizing the PCB into a first PCB with chip probes and connection probes and a second PCB with connection contacts, test contacts, solder contact points and power supply contacts, the connection and disconnection with the chips can be realized by using the movable first PCB, and then the test of the chips can be realized by the connection between the first PCB and the second PCB, thus meeting multiple requirements such as power supply, test, disassembly and assembly, which is very convenient.

[0045] In addition, through the setting of the fixing screws, the first PCB can be stably connected to the chip. The limiting spring still has a certain thickness after being compressed. Thus, the carrier plate and the backing plate are isolated by the compressed limiting spring to form a light passing gap, which is convenient for the laser chip to complete optoelectronic testing. At the same time, after the fixing screws are loosened, the limiting spring can automatically lift the backing plate, so that the chip probe of the first PCB is separated from the chip, which is convenient for the staff to operate the chip in the chip slot. Moreover, the limiting rod inserted in the limiting hole can slide along the strip-shaped guiding hole communicated with the limiting hole, so that the backing plate and the first PCB board are far away from the chip slot, avoiding the chip probe, the backing plate and the first PCB from affecting the disassembly and assembly of the chip.

[0046] In addition, since the power connection pins of the TEC need to be welded to the solder contact points of the second PCB, in order to avoid poor quality problems during the welding of the TEC, after the TEC is welded, it is difficult for each TEC to maintain in the same reference plane, resulting in different sizes of gaps between the carrier plate installed on multiple TECs and the TECs, and it is difficult to fit completely. This will not only affect the installation of the carrier plate, but also due to the existence of different sizes of gaps, the chips corresponding to different TECs are in different temperature ranges, the test accuracy of a single chip is poor, and the test results of the same batch of chips vary greatly, thus affecting the use of the fixture. Therefore, the welding through holes on the substrate expose the solder contact points, and the heat insulation plate, the carrier plate and the TEC are pre-assembled into one body and installed in the heat insulation groove. The staff can not only directly realize the welding of the power connection pins and the solder contact points, but also avoid the TEC from shifting due to the welding work, thereby ensuring the uniformity of TEC heating and temperature control.

[0047] In addition, through the setting of multiple TECs in the installation groove, the heating efficiency and density of the heat source are further increased, so that more chip slots can be opened on the carrier plate, and the connection and testing of each chip are integrated by the cooperation of the first PCB and the second PCB, thereby improving the test efficiency of the chip and reducing the test cost.

[0048] The above embodiments are only used to illustrate the technical concept and characteristics of the present invention, and their purpose is to enable those who are familiar with this technology to understand the content of the present invention and implement it accordingly, and should not be used to limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the protection scope of the present invention.

Claims

1. A reliability test system for a laser chip, characterized in that: It includes a substrate (1), a carrier board (2) mounted on the substrate (1), and a first PCB (3) mounted on the carrier board (2). A chip slot (201) for chip embedding is formed on the carrier board (2). Chip probes (31) corresponding to the chip slot (201) are provided on the first PCB (3). A plurality of TECs (4) are installed between the substrate (1) and the carrier board (2), and this TEC (4) is located directly below the chip slot (201). A heat insulation plate (5) is installed between the substrate (1) and the first PCB (3), and a heat insulation through slot (51) for the TEC (4) to be embedded is formed in this heat insulation plate (5); The first PCB (3) is mounted on the heat insulation plate (5). A second PCB (6) is mounted on the substrate (1). Connection contacts (61), test contacts (62) communicating with the connection contacts (61), welding contacts (63), and power supply contacts (63) communicating with the welding contacts (63) are provided on this second PCB (6). Connection probes (32) corresponding to the connection contacts (61) are provided on the first PCB (3). The test contacts (62) are used to connect external devices. The power connection pins (41) of the TEC (4) are welded to the welding contacts (63); A spacer plate (7) is installed between the first PCB (3) and the heat insulation plate (5). Probe through holes (701) for the chip probes (31) and connection probes (32) to pass through are formed on this spacer plate (7). The first PCB (3) and the spacer plate (7) are mounted on the substrate (1) through a fixing screw (71). A limiting rod (11) is also provided on the substrate (1). A limiting spring (12) located between the spacer plate (7) and the carrier board (2) is sleeved on this limiting rod (11). A limiting hole (72) for the limiting rod (11) to be embedded is formed on the spacer plate (7). A strip-shaped guiding hole (73) is also communicated and opened on the spacer plate (7) on one side of this limiting hole (72), and this strip-shaped guiding hole (73) is located on the side of the spacer plate (7) close to the chip; The welding contacts (63) are located on the bottom surface of the second PCB (6). Welding through holes (16) corresponding to the welding contacts (63) are formed on the bottom surface of the substrate (1).

2. The reliability test system for a laser chip according to claim 1, wherein: Mounting grooves (101) for the TEC (4) to be embedded are formed on the top surface of the substrate (1).

3. The reliability test system for a laser chip according to claim 2, characterized in that: There are two mounting grooves (101) spaced apart. The carrier board (2) is provided in two and is respectively located in these two mounting grooves (101).

4. The reliability test system for a laser chip according to claim 3, wherein: The number of TECs (4) in one of the mounting grooves is four, and two chip slots (201) correspond to one TEC (4).

5. The reliability test system for a laser chip according to claim 2, wherein: Heat insulation grooves (108) for the heat insulation plate (5) to be embedded are formed at the side edges of the top surface of the substrate (1). The mounting grooves (101) are formed at the bottom of this heat insulation groove (108).

6. The reliability test system for a laser chip according to claim 5, wherein: Arc-shaped openings (109) are formed at the corners of the heat insulation groove (108).

7. The reliability test system for a laser chip according to claim 1, wherein: Step grooves (501) for the carrier board (2) to be embedded are formed at the side edges of the top surface of the heat insulation plate (5).

8. The reliability test system for a laser chip according to claim 1, characterized in that: The substrate (1) is provided with a positioning rod (106), and positioning holes (107) for the positioning rod (106) to be inserted are formed in the heat insulation plate (5), the carrier plate (2) and the backing plate (7).

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