A high performance CMOS voltage reference with negative feedback

Abstract

The application discloses a high-performance CMOS voltage reference source with negative feedback, comprising a start-up circuit module, a current source module and an active load module connected in sequence; the start-up circuit module is used for keeping the circuit at a proper working point and ensuring that the circuit can always reach a stable state; the current source module is used for generating a bias current proportional to electron mobility and temperature square without using special devices, and the bias current is small, so that the power consumption of the current is small; in the application, the active load module generates an output reference voltage with low voltage linearity and high power supply rejection ratio by introducing negative feedback, and simultaneously has the advantages of low temperature coefficient, low voltage linearity, high power supply rejection ratio, low power consumption and good process compatibility.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a high-performance CMOS voltage reference source with negative feedback. BACKGROUND

[0002] As an important component of contemporary analog integrated circuits, voltage reference sources are widely used in the fields of Internet of Things, wearable devices and power management. As the most commonly used modules in power management modules, low-dropout linear regulators and direct-current voltage stabilizers both need to use voltage reference sources to generate a reference voltage independent of process, power voltage and temperature variation, and the precision of the reference voltage output by the voltage reference source will directly affect the performance of these modules.

[0003] Several indicators commonly used to measure voltage reference sources include temperature coefficient, voltage linearity, power supply rejection ratio, power consumption and temperature coefficient. The temperature coefficient and voltage linearity are respectively used to measure the influence of temperature and voltage reference source variation on the reference voltage; the power supply rejection ratio is used to measure the ability of the circuit to suppress power noise; the power consumption is a performance parameter for measuring the power loss of the circuit; and the coefficient of variation is used to measure the degree of process affecting the performance of the circuit.

[0004] In the design process of voltage reference source, in order to obtain a temperature independent output reference voltage, it is usually necessary to obtain the output reference voltage with temperature compensation by adding the positive and negative temperature coefficients. The conventional voltage reference source mainly uses the negative temperature coefficient of the base-emitter voltage of the bipolar transistor (BJT) and the positive temperature coefficient of the thermoelectric potential to linearly add to achieve zero temperature coefficient, so as to obtain a reference voltage of about 1.2V. This makes the power supply voltage higher than 1.2V, which is difficult to realize low power consumption. In addition, since the conventional voltage reference source uses resistors and bipolar transistors, the chip area is greatly increased. Therefore, the CMOS voltage reference source has been widely developed due to its low power consumption and low process sensitivity. The CMOS voltage reference source based on resistance uses the positive temperature coefficient of the gate-source voltage difference of the MOS tube and the negative temperature coefficient of the threshold voltage to linearly add to obtain zero temperature coefficient. The circuit uses the subthreshold characteristics of the MOS tube to reduce the power consumption of the circuit, but since the circuit uses resistors, the chip area is still large. In order to further reduce the chip area, the CMOS voltage reference source based on high threshold voltage is proposed. The voltage reference source uses the negative temperature coefficient of the threshold voltage difference of the high threshold MOS tube and the standard MOS tube and the positive temperature coefficient of the thermoelectric potential to linearly add. Since no resistor is used, the chip area is small, but since the high threshold MOS tube is used, the process compatibility of the circuit is poor and the cost is high. In order to obtain better temperature stability and process compatibility, the CMOS voltage reference source using only standard threshold voltage MOS tube is proposed. Since only standard MOS tubes are used, the circuit has good process compatibility, but the voltage linearity of the circuit is still poor.

[0005] Based on the above analysis, in the design and research process of the voltage reference source, it is difficult to cover all the key characteristics of the voltage reference source. SUMMARY

[0006] The purpose of the present application is to overcome the defects that the above-mentioned voltage reference source cannot cover all the key performances, and a CMOS voltage reference source with negative feedback is proposed, which has the advantages of low temperature coefficient, low voltage linearity, high power supply rejection ratio, low power consumption and good process compatibility.

[0007] The technical scheme adopted by the present application is as follows: a high-performance CMOS voltage reference source with negative feedback, comprising a start-up circuit module, a current source module and an active load module, the start-up circuit module, the current source module and the active load module are connected in sequence.

[0008] The start-up circuit module is used to keep the circuit at a proper operating point and ensure that the circuit can always reach a stable state.

[0009] The current source module is used to generate a bias current proportional to electron mobility and temperature square without using special devices, and the bias current is small, so that the power consumption of the current is small.

[0010] The active load module generates an output reference voltage with low voltage linearity and high power supply rejection ratio by introducing negative feedback.

[0011] The start-up circuit module includes PMOS tube M14, NMOS tubes M15, M16 and M17, the drain and source of M14 in the start-up circuit are connected to the power supply voltage, the gate of M14 is connected to the gates of M15 and M16, the drains of M15 and M16 are connected, and a first output end of the start-up circuit is connected to the current source module to provide a start-up signal, the sources of M15 and M16 are connected to the second and third output ends of the start-up circuit to provide start-up signals, the drain of M17 is connected to the gate of M14, the gate of M17 is connected to the output reference voltage VREF, and the source of M17 is grounded.

[0012] The current source module includes an operational amplifier, PMOS tubes M9, M10, M11, NMOS tubes M1, M2, M3 and M4, M9, M10 and M11 constitute a current mirror, the drain and gate of M9 are connected, the sources of M9, M10 and M11 are connected to the power supply voltage, the gates of M9, M10 and M11 are connected, and are connected to the operational amplifier OP-AMP, and are connected to the first output end of the start-up circuit and are led out to the active load module, M1, M2 and M4 are diode-connected, that is, the gate and drain of each of M1, M2 and M4 are connected together, the drain of M1 is connected to the drain of M9, the source of M1 is connected to the drain of M2, the gate of M2 is connected to the drain of M1, the source of M2 is grounded, the source of M3 is connected to the drain of M2, the gate of M3 is connected to the positive input end of the operational amplifier OP-AMP, the drain of M3 is connected to the second output end of the start-up circuit, the gate of M4 is connected to the negative input end of the operational amplifier OP-AMP and is connected to the third output end of the start-up circuit, the drain of M4 is connected to the drain of M11, and the source of M4 is grounded.

[0013] In the current source module, M2, M4, M9, M10 and M11 work in the sub-threshold region, and M1 and M3 work in the saturation region.

[0014] The active load module comprises PMOS tubes M12 and M13, NMOS tubes M5, M6, M7 and M8, M12 and M13 are connected with the gate of M9, M10 and M11 in the current source module as the output end of the active load module, and constitute a current mirror, the source of M12 and M13 is connected with the power supply voltage, the drain of M12 is connected with the drain of M5, the drain of M13 is connected with the drain of M7, the gate of M5 is connected with the gate of M7, the source of M5 is connected with the drain of M6, the source of M6 is grounded, M6 and M7 are diode-connected, i.e. the drain and the gate of M6 and M7 are connected together, the source of M7 is connected with the drain of M8, and is also the output end VREF of the whole voltage reference source, the gate of M8 is connected with the gate of M6, and the source of M8 is grounded.

[0015] The PMOS tubes M12 and M13, the NMOS tubes M5, M6, M7 and M8 in the active load module all work in the sub-threshold region.

[0016] The power supply voltage ranges from 0.95V to 3V.

[0017] In summary, due to the adoption of the above technical scheme, the application has the following advantages:

[0018] In the application, a high-performance CMOS voltage reference source with negative feedback is provided, which comprises a start-up circuit module, a current source module and an active load module connected in sequence; the start-up circuit module is used for keeping the circuit at a proper working point and ensuring that the circuit can always reach a stable state; the current source module is used for generating a bias current proportional to the electron mobility and the square of temperature without using special devices, and the bias current is small, so that the power consumption is small. The active load module generates an output reference voltage with low voltage linearity and high power supply rejection ratio by introducing negative feedback. The application has the advantages of low temperature coefficient, low voltage linearity, high power supply rejection ratio, low power consumption and good process compatibility. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 FIG. 1 is a circuit diagram of the high-performance CMOS voltage reference source with negative feedback of the application;

[0020] Figure 2 FIG. 3 is a small signal diagram of the active load module of the high-performance CMOS voltage reference source with negative feedback of the application. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical scheme and advantages of the application clearer, the application will be further described in detail below with reference to the drawings and examples. It should be understood that the specific examples described herein are only used to explain the application, and are not used to limit the application.

[0022] Embodiment one, as shown in the accompanying drawings Figures 1-2 The embodiment of the present application provides a high-performance CMOS voltage reference source with negative feedback, which comprises a start-up circuit module, a current source module and an active load module in sequence.

[0023] The start-up circuit module is used for maintaining the circuit at a proper operating point and ensuring that the circuit can always reach a steady state.

[0024] The current source module is used for generating a bias current which is proportional to the electron mobility and the square of temperature without using special devices, and the bias current is small, so that the power consumption is small.

[0025] The active load module generates an output reference voltage with low voltage linearity and high power supply rejection ratio by introducing negative feedback while realizing zero temperature coefficient.

[0026] The threshold voltage of the MOS transistor is negatively related to temperature, that is, the threshold voltage is negatively temperature-coefficient, and its expression is as follows:

[0027] VTH = V TH0 - α T (T-T0) (1)

[0028] Wherein, V TH0 represents the threshold voltage of the MOS transistor at room temperature, α T represents the temperature coefficient of the threshold voltage, T represents the temperature of the circuit working environment, and T0 represents the room temperature.

[0029] When the voltage between the source and the substrate of the MOS transistor is not zero, the body effect will be introduced, so that the threshold voltage of the MOS transistor changes, and the threshold voltage considering the body effect can be expressed as:

[0030]

[0031] Wherein, η is a sub-threshold slope factor, V SB is the voltage between the source and the substrate of the MOS transistor

[0032] When the NMOS transistor works in the saturation region, the expressions of the drain-source current and the gate-source voltage are as follows:

[0033]

[0034]

[0035] When the NMOS transistor works in the sub-threshold, the expressions of the drain-source current and the gate-source voltage are as follows:

[0036]

[0037]

[0038] where μ and C OX are the electron mobility and the oxide capacitance under the gate, K is the width-to-length ratio of the MOS, V GS is the voltage between the gate and the source, V T is the thermal voltage, and V T has a positive temperature coefficient with temperature.

[0039] In the present application, the power supply voltage range in which the circuit can normally work is 0.95V-3V, and the high-performance CMOS voltage reference source realizes low temperature coefficient and low voltage linearity without using special threshold MOS and resistor, so that the process compatibility and chip area of the circuit are greatly improved.

[0040] Further, the starting circuit module comprises PMOS M14 and NMOS M15, M16 and M17; the drain and source of M14 in the starting circuit are connected to the power supply voltage, the gate of M14 is connected to the gates of M15 and M16, the drains of M15 and M16 are connected, and the first output end of the starting circuit is led out as a starting signal for the current source module. The sources of M15 and M16 are connected to the second and third output ends as starting signals, and the current source module is connected. The drain of M17 is connected to the gate of M14, the gate of M17 is connected to the output reference voltage VREF, and the source of M17 is grounded.

[0041] Further, the current source module comprises an operational amplifier, PMOS M9, M10 and M11, and NMOS M1, M2, M3 and M4. M9, M10 and M11 constitute a current mirror, i.e. the drain and gate of M9 are connected, the sources of M9, M10 and M11 are connected to the power supply voltage, the gates of M9, M10 and M11 are connected, and are connected to the operational amplifier OP-AMP, at the same time connected to the first output end of the starting circuit, and led out to the active load module. M1, M2 and M4 are diode-connected, i.e. the gate and drain of each of M1, M2 and M4 are connected together, the drain of M1 is connected to the drain of M9, the source of M1 is connected to the drain of M2, the gate of M2 is connected to the drain of M1, the source of M2 is grounded, the source of M3 is connected to the drain of M2, the gate of M3 is connected to the positive input end of the operational amplifier OP-AMP, the drain of M3 is connected to the second output end of the starting circuit, the gate of M4 is connected to the negative input end of the operational amplifier OP-AMP, and is connected to the third output end of the starting circuit, the drain of M4 is connected to the drain of M11, and the source of M4 is grounded.

[0042] Further, the PMOS transistors M12 and M13 and the NMOS transistors M5, M6, M7 and M8 in the active load module work in the sub-threshold region.

[0043] The start-up circuit module is connected with the current source module, so that the CMOS power reference source can be started up quickly, and the power consumption can be ignored after the CMOS power reference source is successfully started up and enters the normal state, and meanwhile, the other performances of the circuit are not affected.

[0044] The transistors M2, M4, M9, M10 and M11 in the current source module work in the sub-threshold region, and the transistors M1 and M3 work in the saturation region, and according to the connection relationship of the transistors M1, M2, M3 and M4, the following equation can be obtained:

[0045]

[0046] In the equation, VGS represents the gate-source voltage of the transistors M1 and M3, and VGS represents the gate-source voltage of the transistors M2 and M4. And In the equation, VGS represents the gate-source voltage of the transistors M1 and M3, and VGS represents the gate-source voltage of the transistors M2 and M4. The equation (7) can be obtained by substituting the equations (2), (4) and (6) into the equation (7).

[0047]

[0048]

[0049] In the equation, α, β and γ are the ratios of the currents. The equation (8) can be simplified to obtain the expression of the current generated by the current source as follows:

[0050]

[0051] Further, the active load module includes the PMOS transistors M12 and M13 and the NMOS transistors M5, M6, M7 and M8; the transistors M12 and M13 as the output end of the active load module are connected with the gate electrodes of the transistors M9, M10 and M11 in the current source module to form a current mirror, the source electrodes of the transistors M12 and M13 are connected with the power supply voltage, the drain electrode of the transistor M12 is connected with the drain electrode of the transistor M5, the drain electrode of the transistor M13 is connected with the drain electrode of the transistor M7, the gate electrode of the transistor M5 is connected with the gate electrode of the transistor M7, the source electrode of the transistor M5 is connected with the drain electrode of the transistor M6, the source electrode of the transistor M6 is connected with the ground, the transistors M6 and M7 are diode-connected, i.e., the drain electrode and the gate electrode of each of the transistors M6 and M7 are connected together, the source electrode of the transistor M7 is connected with the drain electrode of the transistor M8, and the transistor M8 is also the output end of the active load module and the output end VREF of the entire voltage reference source, the gate electrode of the transistor M8 is connected with the gate electrode of the transistor M6, and the source electrode of the transistor M8 is connected with the ground.

[0052] Further, in the active load module, M7, M5, M6 and M8 form a negative feedback loop in sequence. By pushing the main pole of the circuit far away, the low frequency power supply rejection ratio (PSRR) of the circuit is improved, and by introducing a conjugate complex pole, the high frequency PSRR of the circuit is improved. The current generated by the current source is mirrored by the current mirror and injected into the active load module. The active load module is used to generate a reference voltage independent of the power supply voltage and temperature. According to M5, M6, M7 and M8, the expression of the output reference voltage can be obtained as follows:

[0053]

[0054] Substituting equations (2), (4) and (6) into equation (7), the expression of the output reference voltage can be expressed as:

[0055]

[0056] In order to obtain a temperature-compensated reference voltage, the following conditions must be met:

[0057]

[0058] By adjusting the width-length ratio of the relevant MOS transistors in the expression, a zero-temperature-coefficient output reference voltage can be obtained.

[0059] Further, in the active load module, M7, M5, M6 and M8 form a negative feedback loop in sequence. If the voltage at node Z increases with the change of the power supply voltage, the voltage at node Y will rise, and then the output reference voltage VREF will decrease. Because the gain of the negative feedback loop composed of M7, M5, M6 and M8 is greater than the gain of the positive feedback loop composed of M7, the output reference voltage VREF will eventually decrease, and vice versa. The existence of the negative feedback loop further improves the accuracy of the reference voltage, making the voltage reference source achieve a low voltage linearity. As shown in FIG. 4, it is a small signal diagram of the active load module of the high-performance CMOS voltage reference source with negative feedback. According to the small signal analysis, the calculated PSRR expression is as follows: Figure 2

[0060]

[0061] wherein the expression of δ is as follows:

[0062]

[0063] wherein g mi and r oi represent the transconductance and output resistance of MOS transistor M i , respectively; g oi is the derivative of r oi ; A dc ​is the DC gain of the operational amplifier. The active load with negative feedback proposed in this invention indeed improves the PSRR of the circuit, and the main reasons are as follows. First, pushing the dominant pole z0far away improves the low frequency PSRR of the circuit. Second, introducing the complex conjugate pole p cp and the complex conjugate pole p cp is designed to be much smaller than the complex conjugate zero z cz to improve the high frequency PSRR of the circuit.

[0064] The present invention provides a high performance CMOS voltage reference with negative feedback, comprising a start-up circuit module, a current source module and an active load module connected in sequence; the start-up circuit module is used to keep the circuit at an appropriate operating point and ensure that the circuit can always reach a steady state. The current source module is used to generate a bias current proportional to the electron mobility and the square of the temperature without using special devices, and the bias current is small, so that the power consumption of the current is small. The active load module generates an output reference voltage with low voltage linearity and high power supply rejection ratio by introducing negative feedback. At the same time, it has the advantages of low temperature coefficient, low voltage linearity, high power supply rejection ratio, low power consumption and good process compatibility.

[0065] The above description is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modification, equivalent replacement and improvement made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A high performance CMOS voltage reference with negative feedback, comprising a start-up circuit module, a current source module and an active load module, characterized in that: The start-up circuit module, the current source module and the active load module are connected in sequence; the start-up circuit module is used for keeping the circuit at a proper working point and ensuring that the circuit can reach a steady state at all times; the current source module is used for generating a bias current proportional to the electron mobility and the square of the temperature without using special devices; the active load module generates an output reference voltage with low voltage linearity and high power supply rejection ratio by introducing negative feedback; the start-up circuit module comprises PMOS tubes M14, NMOS tubes M15, M16 and M17, the drain and the source of M14 in the start-up circuit are connected with a power supply voltage, the gate of M14 is connected with the gates of M15 and M16, the drains of M15 and M16 are connected, and a first output end of the start-up circuit is led out to provide a start-up signal for the current source module, the sources of M15 and M16 are connected with a second and a third output end led out as start-up signals and connected with the current source module, the drain of M17 is connected with the gate of M14, the gate of M17 is connected with an output reference voltage VREF, and the source of M17 is grounded; the current source module comprises an operational amplifier, PMOS tubes M9, M10, M11, NMOS tubes M1, M2, M3 and M4, M9, M10 and M11 constitute a current mirror, that is, the drain and the gate of M9 are connected, the sources of M9, M10 and M11 are connected with a power supply voltage, the gates of M9, M10 and M11 are connected and connected with the operational amplifier OP-AMP, and are connected with the first output end of the start-up circuit and led out to the active load module, M1, M3 and M4 are diode-connected, that is, the gate and the drain of each of M1, M3 and M4 are connected together, the drain of M1 is connected with the drain of M9, the source of M1 is connected with the drain of M2, the gate of M2 is connected with the drain of M1, the source of M2 is grounded, the source of M3 is connected with the drain of M2, the gate of M3 is connected with the positive input end of the operational amplifier OP-AMP, the drain of M3 is connected with the second output end of the start-up circuit, the gate of M4 is connected with the negative input end of the operational amplifier OP-AMP and connected with the third output end of the start-up circuit, the drain of M4 is connected with the drain of M11, and the source of M4 is grounded.The active load module comprises PMOS tubes M12 and M13, NMOS tubes M5, M6, M7 and M8, M12 and M13 are connected with the gates of M9, M10 and M11 in the current source module as the output end of the active load module, to form a current mirror, the source of M12 and M13 is connected with the power supply voltage, the drain of M12 is connected with the drain of M5, the drain of M13 is connected with the drain of M7, the gate of M5 is connected with the gate of M7, the source of M5 is connected with the drain of M6, the source of M6 is grounded, M6 and M7 are both diode-connected, that is, the drain and the gate of M6 and M7 are connected together, the source of M7 is connected with the drain of M8, and is also the output end VREF of the whole voltage reference source, the gate of M8 is connected with the gate of M6, and the source of M8 is grounded.

2. A high performance CMOS voltage reference with negative feedback as defined in claim 1, characterized in that: M2, M4, M9, M10 and M11 in the current source module work in sub-threshold region, and M1 and M3 work in saturation region.

3. A high performance CMOS voltage reference with negative feedback as defined in claim 2, characterized in that: PMOS M12 and M13, and NMOS M5, M6, M7 and M8 in the active load module all work in sub-threshold region.

4. A high performance CMOS voltage reference with negative feedback as defined in claim 3, characterized in that: The range of the power supply voltage is 0.95V-3V.

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