A crystal oscillator with low phase noise and a control method thereof

Abstract

The present invention discloses a crystal oscillator with low phase noise, which includes an oscillation circuit, an amplitude detection circuit and a voltage control circuit; the amplitude detection circuit is connected to the output end of the oscillation circuit and is used for detecting whether the amplitude of the output signal of the oscillation circuit exceeds a preset amplitude threshold; the voltage control circuit is connected to the output end of the amplitude detection circuit and is used for determining the input voltage of the oscillation circuit according to the output signal of the amplitude detection circuit. By adding the amplitude detection circuit and the voltage control circuit, the present invention realizes that when the amplitude of the oscillation circuit exceeds the threshold, the working voltage of the oscillation circuit is automatically reduced, achieving the purpose of controlling the oscillation amplitude, and greatly reducing its power consumption and the phase noise of the output signal. The present invention also provides an electronic timer with the above beneficial effects, as well as a control method, device, equipment and computer-readable storage medium of the crystal oscillator.

Description

Technical Field

[0001] The present invention relates to the field of crystal oscillator control, and particularly to a crystal oscillator with low phase noise, an electronic timer, and a control method, device, equipment, and computer-readable storage medium for a crystal oscillator. Background Art

[0002] Clocks are used in many fields of today's society, especially in fields such as communication and control. As a key circuit for clock generation, the crystal oscillator is used to amplify the local oscillator signal of the quartz crystal and generate a reference clock that can be used by modules such as phase-locked loops. Since it is used as a reference clock, its performance is particularly important. If the noise of the reference clock generated by the crystal oscillator is not small enough, the phase-locked loop that relies on the reference clock cannot obtain a high-performance output clock; if the power consumption is not low enough, then it will inevitably put higher requirements on the power supply capacity of the upper-level power management chip.

[0003] Once the crystal oscillator starts to oscillate, its amplitude will become larger and larger until the amplitude reaches the amplitude of the supply voltage. At this time, the transconductance MOS (metal oxide semiconductor) transistor that provides the oscillation energy enters the linear region due to the too large amplitude. At this time, the generated oscillation signal is a signal containing many harmonic components, with large phase noise and large power consumption, and cannot be used as an ideal reference clock to be provided to clock generation modules such as phase-locked loops that require low jitter. Moreover, a large oscillation amplitude may even burn out the quartz crystal.

[0004] Therefore, how to reduce power consumption while ensuring that the crystal oscillator has few harmonic components and low phase noise is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0005] The object of the present invention is to provide a crystal oscillator with low phase noise, an electronic timer, and a control method, device, equipment, and computer-readable storage medium for a crystal oscillator, so as to solve the problems of many harmonic components, large phase noise, and large power consumption in the oscillation signal of the prior art.

[0006] To solve the above technical problems, the present invention provides a crystal oscillator with low phase noise, including an oscillation circuit, an amplitude detection circuit, and a voltage control circuit;

[0007] The amplitude detection circuit is connected to the output end of the oscillation circuit and is used to detect whether the amplitude of the output signal of the oscillation circuit exceeds a preset amplitude threshold;

[0008] The voltage control circuit is connected to the output end of the amplitude detection circuit and is used to determine the input voltage of the oscillation circuit according to the output signal of the amplitude detection circuit.

[0009] Optionally, in the crystal oscillator with low phase noise, the voltage control circuit includes an amplitude management circuit, a release decision circuit, and a voltage regulation circuit;

[0010] The input end of the amplitude management circuit is connected to the output end of the oscillation circuit, and is used to obtain a voltage adjustment signal through the output signal of the oscillation circuit;

[0011] The input end of the release decision circuit is connected to the output ends of the amplitude detection circuit and the amplitude detection circuit, and is used to determine whether to output the voltage adjustment signal according to the output signal of the amplitude detection circuit;

[0012] The input end of the voltage regulation circuit is connected to the output end of the release decision circuit, and is used to determine the input voltage of the oscillation circuit according to the voltage adjustment signal.

[0013] Optionally, in the crystal oscillator with low phase noise, the amplitude detection circuit includes a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, and an eighteenth PMOS transistor, a fifth capacitor and a sixth capacitor, and a fourth resistor;

[0014] The gates of the sixteenth PMOS transistor and the eighteenth PMOS transistor are connected to a first positive power supply, and the drain of the sixteenth PMOS transistor is respectively connected to the gates of the fifteenth PMOS transistor and the seventeenth PMOS transistor. The sources of the fifteenth PMOS transistor and the seventeenth PMOS transistor are connected to VDD. The drain of the fifteenth PMOS transistor is connected to the source of the sixteenth PMOS transistor, and the drain of the seventeenth PMOS transistor is connected to the source of the eighteenth PMOS transistor;

[0015] The gates of the thirteenth NMOS transistor and the fifteenth NMOS transistor are connected to a first negative power supply. The drain of the thirteenth NMOS transistor is connected to the drain of the sixteenth PMOS transistor, and the drain of the fifteenth NMOS transistor is connected to the drain of the eighteenth PMOS transistor. And the drain of the fifteenth NMOS transistor and the drain of the eighteenth PMOS transistor are grounded through a fifth capacitor;

[0016] The gates of the sixteenth NMOS transistor and the seventeenth NMOS transistor are connected to a third negative power supply. And the drain of the sixteenth NMOS transistor is connected to the source of the fifteenth NMOS transistor. The source of the sixteenth NMOS transistor is connected to the drain of the seventeenth NMOS transistor, and the source of the seventeenth NMOS transistor is grounded;

[0017] The output terminal of the oscillation circuit is connected to the gate of the fourteenth NMOS transistor through the sixth capacitor, and the gate of the fourteenth NMOS transistor is connected to the fourth reverse power supply through the fourth resistor. The source of the fourteenth NMOS transistor is grounded, and the drain of the fourteenth NMOS transistor is connected to the source of the thirteenth NMOS transistor.

[0018] Optionally, in the crystal oscillator with low phase noise, the amplitude management circuit includes an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor, a third resistor, a zero capacitor, and a third capacitor;

[0019] The gates of the twelfth PMOS transistor, the fourteenth PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are connected to the first positive power supply, and the sources of the eighth PMOS transistor, the eleventh PMOS transistor, and the thirteenth PMOS transistor are connected to VDD. The drain of the thirteenth PMOS transistor is connected to the source of the fourteenth PMOS transistor, the drain of the eleventh PMOS transistor is connected to the source of the twelfth PMOS transistor, the drain of the eighth PMOS transistor is connected to the source of the ninth PMOS transistor, and the drain of the fourteenth PMOS transistor is connected to the gates of the thirteenth PMOS transistor and the eleventh PMOS transistor respectively;

[0020] The gates of the eighth NMOS transistor and the ninth NMOS transistor are connected to the first reverse power supply. The drain of the eighth NMOS transistor is connected to the drain of the fourteenth PMOS transistor, and the drain of the ninth NMOS transistor is connected to the drain of the twelfth PMOS transistor. The drain of the twelfth PMOS transistor is connected to the gate of the tenth PMOS transistor, and the connection between the drain of the twelfth PMOS transistor and the gate of the tenth PMOS transistor is grounded through the zero capacitor. The drain of the tenth PMOS transistor is the output terminal of the amplitude management circuit;

[0021] The gates of the tenth NMOS transistor and the eleventh NMOS transistor are connected to the third reverse power supply. The drain of the eleventh NMOS transistor is connected to the source of the tenth NMOS transistor, the drain of the tenth NMOS transistor is connected to the source of the ninth NMOS transistor, and the source of the eleventh NMOS transistor is grounded;

[0022] The output terminal of the oscillation circuit is connected to the gate of the twelfth NMOS transistor through the third capacitor, and the gate of the twelfth NMOS transistor is connected to the fourth reverse power supply through the third resistor. The source of the twelfth NMOS transistor is grounded, and the drain of the twelfth NMOS transistor is connected to the source of the eighth NMOS transistor.

[0023] Optionally, in the crystal oscillator with low phase noise, the release decision circuit and the amplitude detection circuit are connected through a Schmitt trigger;

[0024] The release decision circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor, a first resistor and a second resistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor;

[0025] The sources of the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, and the drain of the seventh PMOS transistor are connected to the VDD. The drain of the sixth PMOS transistor is grounded through the first resistor and the second resistor in sequence, and the gate of the sixth PMOS transistor is connected to the output terminal of the amplitude detection circuit;

[0026] The gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the fourth PMOS transistor, and the drain of the fifth NMOS transistor respectively. The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the seventh PMOS transistor, and the drain of the tenth PMOS transistor;

[0027] The source of the seventh PMOS transistor is connected to the drain of the seventh NMOS transistor. The source of the seventh NMOS transistor is grounded, and the gate of the seventh NMOS transistor is connected to the first reverse power supply;

[0028] The gate of the sixth NMOS transistor is connected to the first reverse power supply. The source of the sixth NMOS transistor is grounded, and the drain of the sixth NMOS transistor is connected to the source of the fourth NMOS transistor. The gate of the fourth NMOS transistor is connected to the source of the seventh PMOS transistor;

[0029] The source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, and the gate of the fifth NMOS transistor is connected between the first resistor and the second resistor.

[0030] An electronic timer, the electronic timer includes the crystal oscillator with low phase noise as described in any one of the above.

[0031] A control method for a crystal oscillator, including:

[0032] Receive a voltage oscillation signal;

[0033] Determine amplitude information according to the voltage oscillation signal;

[0034] Judge whether the amplitude information exceeds an amplitude threshold;

[0035] When the amplitude information exceeds the amplitude threshold, reduce the operating voltage of the crystal oscillator so that the crystal oscillator operates in a low-amplitude state.

[0036] A control device for a crystal oscillator, comprising:

[0037] A receiving module, configured to receive a voltage oscillation signal;

[0038] An amplitude determination module, configured to determine the amplitude information according to the voltage oscillation signal;

[0039] A judgment module, configured to judge whether the amplitude information exceeds an amplitude threshold;

[0040] A voltage reduction module, configured to reduce the operating voltage of the crystal oscillator when the amplitude information exceeds the amplitude threshold so that the crystal oscillator operates in a low-amplitude state.

[0041] An instantaneous residual voltage detection device, comprising:

[0042] A memory, configured to store a computer program;

[0043] A processor, configured to implement the steps of the control method for the crystal oscillator as described when executing the computer program.

[0044] A computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the control method for the crystal oscillator as described are implemented.

[0045] The crystal oscillator with low phase noise provided by the present invention includes an oscillation circuit, an amplitude detection circuit, and a voltage control circuit; the amplitude detection circuit is connected to the output end of the oscillation circuit and is used to detect whether the amplitude of the output signal of the oscillation circuit exceeds a preset amplitude threshold; the voltage control circuit is connected to the output end of the amplitude detection circuit and is used to determine the input voltage of the oscillation circuit according to the output signal of the amplitude detection circuit. By adding the amplitude detection circuit and the voltage control circuit, when the amplitude of the oscillation circuit exceeds the threshold, the present invention automatically reduces the working voltage of the oscillation circuit, achieving the control of the oscillation amplitude and enabling the cross - conductance MOS transistor of the oscillation circuit to always work in the saturation region. In this way, the oscillation circuit can not only output a single - frequency sine wave, but also greatly reduce its power consumption and the phase noise of the output signal. The present invention also provides an electronic timer, as well as a control method, device, equipment, and computer - readable storage medium having the above - mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following - described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0047] Figure 1 It is a schematic structural diagram of a specific embodiment of the crystal oscillator with low phase noise provided by the present invention;

[0048] Figure 2 It is a schematic structural diagram of another specific embodiment of the crystal oscillator with low phase noise provided by the present invention;

[0049] Figure 3 It is a schematic structural diagram of the oscillation circuit of a specific embodiment of the crystal oscillator with low phase noise provided by the present invention;

[0050] Figure 4 It is the equivalent circuit of the quartz crystal of the oscillation circuit of a specific embodiment of the crystal oscillator with low phase noise provided by the present invention;

[0051] Figure 5 It is a schematic structural diagram of the amplitude detection circuit of a specific embodiment of the crystal oscillator with low phase noise provided by the present invention;

[0052] Figure 6 It is a schematic structural diagram of the voltage control circuit of a specific embodiment of the crystal oscillator with low phase noise provided by the present invention;

[0053] Figure 7 Schematic diagram of the shaping circuit of a specific embodiment of the crystal oscillator with low phase noise provided by the present invention;

[0054] Figure 8 Flow chart of a specific embodiment of the control method of the crystal oscillator provided by the present invention;

[0055] Figure 9 Schematic diagram of the structure of a specific embodiment of the control device of the crystal oscillator provided by the present invention;

[0056] Figure 10 Transient waveform at point XA in a specific embodiment of the crystal oscillator with low phase noise provided by the present invention;

[0057] Figure 11 Transient waveform at point XB in a specific embodiment of the crystal oscillator with low phase noise provided by the present invention. Specific embodiment

[0058] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0059] It should be pre - explained that in the specification of the present invention, circuit elements are sometimes represented by circuit diagram markings. For example, MN represents an NMOS transistor, MP represents a PMOS transistor, R represents a resistor, C represents a capacitor, and a serial number is added after the circuit diagram marking. For example, MN12 represents the twelfth NMOS transistor MN12, MP7 represents the seventh PMOS transistor MP7, R4 represents the fourth resistor R4, etc.

[0060] The core of the present invention is to provide a crystal oscillator with low phase noise. The schematic diagram of a specific embodiment thereof is as Figure 1 shown, which is called specific embodiment one, and includes an oscillation circuit 01, an amplitude detection circuit 02, and a voltage control circuit 03;

[0061] The amplitude detection circuit 02 is connected to the output end of the oscillation circuit 01 and is used to detect whether the amplitude of the output signal of the oscillation circuit 01 exceeds a preset amplitude threshold;

[0062] The voltage control circuit 03 is connected to the output end of the amplitude detection circuit 02 and is used to determine the input voltage of the oscillation circuit 01 according to the output signal of the amplitude detection circuit 02.

[0063] The oscillation circuit 01 consists of an oscillation core circuit and a bias circuit, as Figure 3 shown. The supply voltage of this circuit is provided by the source VDD_2nd of the controlled MN2. Figure 3 It also includes an off-chip quartz crystal and a load circuit. The oscillation core circuit includes transistors MP1 and MN1 that generate a transconductance Gm, a feedback resistor Rf, and DC-blocking capacitors C1 and C2.

[0064] Figure 4 is the equivalent circuit of the quartz crystal, where Ls, Cs, and Rs represent the equivalent series inductance, series capacitance, and series resistance (internal resistance) of the crystal; Cp represents the capacitance paralleled across the crystal, including package capacitance and parasitic capacitance on the PCB (printed circuit board), etc.

[0065] Except for Ls, Cs, and Rs, the equivalent small-signal AC impedance between points XA and XB is:

[0066]

[0067] where Gm is the sum of the transconductance Gmn1 of MN1 and the transconductance Gmp1 of MP1, and

[0068]

[0069]

[0070] In the above two equations, I d is the current flowing through MN1 and MP1; k N and k P are the process parameters of the NMOS and PMOS transistors; and are the ratios of the gate length to the gate width of the NMOS and PMOS transistors, respectively.

[0071] The equivalent AC impedance is a function of the variable Gm, and its real part is:

[0072]

[0073] Because the internal resistance Rs of the quartz crystal is positive and it consumes energy, in order to start oscillation and maintain oscillation, the real part of the above equation should be negative resistance and its absolute value must be greater than or equal to Rs. Let the following equation hold:

[0074] Re[Zeq] = -Rs;

[0075] Since in practice the external load capacitances CL1 and CL2 are much larger than the parasitic capacitance Cp, the critical transconductance is approximately:

[0076] Gm (critical) = ω 2·Rs·(CL1 + C1 + C2) 2 ;

[0077] Taking the derivative of the expression of the equivalent impedance with respect to Gm, the maximum transconductance can be obtained as:

[0078]

[0079] According to Gm (maximum), and by selecting appropriate and values, the maximum current I required for startup can be obtained d .

[0080] Preferably, it further includes a shaping circuit;

[0081] The shaping circuit is connected to the output end of the oscillation circuit 01;

[0082] The crystal oscillator is connected to an external circuit through the shaping circuit.

[0083] In addition, the shaping circuit further includes a second buffer;

[0084] The shaping circuit is connected to an external circuit through the second buffer.

[0085] A schematic diagram of the circuit structure of a specific embodiment of the shaping circuit is as shown in Figure 7 The shaping circuit consists of three parts, namely a high-pass filter, a comparator, and an output buffer. The high-pass filter is composed of C7 and R5 to ensure that the oscillation signal passes through. The comparator consists of a tail current bias transistor MN28, differential input transistors MN24, MN23, first-stage load transistors MP23, MP24, second-stage output transistors MP26, MN26, MP25, MN25. The buffer consists of a first-stage inverter MP27, MN27 and a second-stage inverter MP28, MN28, aiming to provide appropriate driving ability to the subsequent stage.

[0086] VBN5 determines the tail current of the comparator input stage. The common-mode voltage VB of the positive input terminal VIP of the comparator is provided by a bias circuit and transmitted to the negative input terminal VIN of the comparator through a large resistor R5. In this way, the positive and negative input terminals of the comparator have the same common-mode voltage. When the oscillation signal XA reaches VIN through the DC-blocking capacitor C7, the sine wave signal just oscillates centered on the common-mode voltage, and the comparator outputs a 50% square wave. Of course, waveforms with other duty cycles can also be output, which can be adjusted according to actual needs; after adding the shaping circuit, the output signal of the oscillation circuit 01 can be adjusted according to actual needs, improving the versatility of the crystal oscillator.

[0087] The crystal oscillator with low phase noise provided by the present invention includes an oscillation circuit 01, an amplitude detection circuit 02, and a voltage control circuit 03. The amplitude detection circuit 02 is connected to the output end of the oscillation circuit 01 and is used to detect whether the amplitude of the output signal of the oscillation circuit 01 exceeds a preset amplitude threshold. The voltage control circuit 03 is connected to the output end of the amplitude detection circuit 02 and is used to determine the input voltage of the oscillation circuit 01 according to the output signal of the amplitude detection circuit 02. By adding the amplitude detection circuit 02 and the voltage control circuit 03, the present invention realizes that when the amplitude of the oscillation circuit 01 exceeds the threshold, the working voltage of the oscillation circuit 01 is automatically reduced, achieving the control of the oscillation amplitude and enabling the transconductance MOS transistor of the oscillation circuit 01 to always operate in the saturation region. In this way, the oscillation circuit 01 can not only output a single-frequency sine wave, but also greatly reduce its power consumption and the phase noise of the output signal.

[0088] On the basis of the above specific implementation manner, the voltage control circuit 03 is further improved to obtain the second specific implementation manner, and its structural schematic diagram is as Figure 2 shown, including an oscillation circuit 01, an amplitude detection circuit 02, and a voltage control circuit 03;

[0089] The amplitude detection circuit 02 is connected to the output end of the oscillation circuit 01 and is used to detect whether the amplitude of the output signal of the oscillation circuit 01 exceeds a preset amplitude threshold;

[0090] The voltage control circuit 03 is connected to the output end of the amplitude detection circuit 02 and is used to determine the input voltage of the oscillation circuit 01 according to the output signal of the amplitude detection circuit 02;

[0091] The voltage control circuit 03 includes an amplitude management circuit 031, a release decision circuit 032, and a voltage regulation circuit 033;

[0092] The input end of the amplitude management circuit 031 is connected to the output end of the oscillation circuit 01 and is used to obtain a voltage adjustment signal through the output signal of the oscillation circuit 01;

[0093] The input end of the release decision circuit 032 is connected to the output end of the amplitude detection circuit 02 and the output end of the amplitude detection circuit 02, and is used to determine whether to output the voltage adjustment signal according to the output signal of the amplitude detection circuit 02;

[0094] The input end of the voltage regulation circuit 033 is connected to the output end of the release decision circuit 032 and is used to determine the input voltage of the oscillation circuit 01 according to the voltage adjustment signal.

[0095] The difference between this specific embodiment and the above specific embodiment is that the specific structure of the voltage control circuit 03 is defined in this specific embodiment, and the rest of the structures are the same as those in the above specific embodiment, so they will not be elaborated here.

[0096] As a specific embodiment, the voltage regulating circuit 033 is an amplifying circuit. Specifically, the amplifying circuit is a triode amplifying circuit, and the voltage adjustment signal is amplified by the amplifying circuit and then used as the operating voltage of the oscillation circuit 01.

[0097] As a preferred embodiment, the amplitude detection circuit 02 includes a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, a sixteenth NMOS transistor MN16, a seventeenth NMOS transistor MN17, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, and an eighteenth PMOS transistor MP18, a fifth capacitor C5 and a sixth capacitor C6, and a fourth resistor R4. The schematic diagram of its specific structure is as Figure 5 shown;

[0098] The gates of the sixteenth PMOS transistor MP16 and the eighteenth PMOS transistor MP18 are connected to the first positive power supply, and the drain of the sixteenth PMOS transistor MP16 is respectively connected to the gates of the fifteenth PMOS transistor MP15 and the seventeenth PMOS transistor MP17. The sources of the fifteenth PMOS transistor MP15 and the seventeenth PMOS transistor MP17 are connected to VDD. The drain of the fifteenth PMOS transistor MP15 is connected to the source of the sixteenth PMOS transistor MP16, and the drain of the seventeenth PMOS transistor MP17 is connected to the source of the eighteenth PMOS transistor MP18;

[0099] The gates of the thirteenth NMOS transistor MN13 and the fifteenth NMOS transistor MN15 are connected to the first negative power supply. The drain of the thirteenth NMOS transistor MN13 is connected to the drain of the sixteenth PMOS transistor MP16, and the drain of the fifteenth NMOS transistor MN15 is connected to the drain of the eighteenth PMOS transistor MP18. And the drain of the fifteenth NMOS transistor MN15 and the drain of the eighteenth PMOS transistor MP18 are grounded through the fifth capacitor C5;

[0100] The gates of the sixteenth NMOS transistor MN16 and the seventeenth NMOS transistor MN17 are connected to a third reverse power supply. The drain of the sixteenth NMOS transistor MN16 is connected to the source of the fifteenth NMOS transistor MN15, the source of the sixteenth NMOS transistor MN16 is connected to the drain of the seventeenth NMOS transistor MN17, and the source of the seventeenth NMOS transistor MN17 is grounded.

[0101] The output terminal of the oscillation circuit 01 is connected to the gate of the fourteenth NMOS transistor MN14 through the sixth capacitor C6. The gate of the fourteenth NMOS transistor MN14 is connected to a fourth reverse power supply through the fourth resistor R4. The source of the fourteenth NMOS transistor MN14 is grounded, and the drain of the fourteenth NMOS transistor MN14 is connected to the source of the thirteenth NMOS transistor MN13.

[0102] Figure 5 In the amplitude detection circuit 02 in [], a Schmitt trigger is additionally provided after the above structure to convert the high voltage at the Q point into a low voltage during output. Please read in combination with the specific structure of the following voltage control circuit 03.

[0103] Preferably, Figure 5 the amplitude detection circuit 02 in [] further includes a first buffer;

[0104] The amplitude detection circuit 02 is connected to the voltage control circuit 03 through the first buffer.

[0105] Figure 5 The amplitude detection circuit 02 in [] includes MOS transistors MN13, MN14, MN15, MN16, MN17, MP15, MP16, MP17, MP18, resistor R4, and capacitors C6, C5. MOS transistors MP19, MP20, MN19, MN20, MP40, MN40 form a Schmitt trigger. The purpose of introducing the Schmitt trigger is to prevent output errors caused by ripples at the Q point. MP21, MN21 form the first inverter of the buffer, and MP22, MN22 form the second inverter of the buffer.

[0106] The bias voltages VBP1, VBN1, VBN3, and VBN4 are provided by the first positive power supply, the first negative power supply, the third negative power supply, and the fourth negative power supply, respectively. The output signal of the oscillation circuit 01 enters from the XA terminal and is transmitted to the gate XA_INT of MN14 through the DC-blocking capacitor C6. The bias voltage at the XA_INT point is provided by VBN2 through a large resistor R4, and MN14 and MN17 are biased in the subthreshold region. Therefore, when there is no oscillation, a relatively large voltage is output at point P, while a low voltage is output at point Q, and a high voltage is output at STARTUP_OUT, controlling the amplitude management circuit 031 to output a high voltage.

[0107] As the oscillation amplitude increases, the voltage amplitude at point P gradually increases. Since it operates in the subthreshold region, the increase in amplitude causes the DC level at this point to gradually decrease, resulting in the voltage at point Q rising until it approaches the power supply voltage VDD. Due to the presence of the filtering capacitor C5, only the DC component exists at point Q. Finally, a low voltage is output at STARTUP_OUT, controlling the amplitude management circuit 031 to output a preset lower voltage.

[0108] There are certain timing requirements for the startup detection and amplitude management circuit 031, that is, the time when the voltage at point Q in the startup detection circuit becomes high must be earlier than the time when the voltage at point B in the amplitude management circuit 031 becomes high.

[0109] As a preferred embodiment, the circuit structure schematic diagram of the voltage control circuit 03 is as Figure 6 shown, including the amplitude management circuit 031 and the release decision circuit 032.

[0110] The amplitude management circuit 031 includes the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the fourteenth PMOS transistor MP14, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, and the twelfth NMOS transistor MN12, the third resistor R3, the zero capacitor C0, and the third capacitor C3;

[0111] The gates of the twelfth PMOS transistor MP12, the fourteenth PMOS transistor MP14, the eighth PMOS transistor MP8, and the ninth PMOS transistor MP9 are connected to the first positive power supply. Also, the sources of the eighth PMOS transistor MP8, the eleventh PMOS transistor MP11, and the thirteenth PMOS transistor MP13 are connected to VDD. The drain of the thirteenth PMOS transistor MP13 is connected to the source of the fourteenth PMOS transistor MP14. The drain of the eleventh PMOS transistor MP11 is connected to the source of the twelfth PMOS transistor MP12. The drain of the eighth PMOS transistor MP8 is connected to the source of the ninth PMOS transistor MP9. The drain of the fourteenth PMOS transistor MP14 is connected to the gates of the thirteenth PMOS transistor MP13 and the eleventh PMOS transistor MP11 respectively;

[0112] The gates of the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are connected to the first negative power supply. The drain of the eighth NMOS transistor MN8 is connected to the drain of the fourteenth PMOS transistor MP14. The drain of the ninth NMOS transistor MN9 is connected to the drain of the twelfth PMOS transistor MP12. Also, the drain of the twelfth PMOS transistor MP12 is connected to the gate of the tenth PMOS transistor MP10. A ground connection is made between the drain of the twelfth PMOS transistor MP12 and the gate of the tenth PMOS transistor MP10 through the zero capacitor C0. The drain of the tenth PMOS transistor MP10 is the output terminal of the amplitude management circuit 031;

[0113] The gates of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are connected to the third negative power supply. Also, the drain of the eleventh NMOS transistor MN11 is connected to the source of the tenth NMOS transistor MN10. The drain of the tenth NMOS transistor MN10 is connected to the source of the ninth NMOS transistor MN9. The source of the eleventh NMOS transistor MN11 is grounded;

[0114] The output terminal of the oscillation circuit 01 is connected to the gate of the twelfth NMOS transistor MN12 through the third capacitor C3. Also, the gate of the twelfth NMOS transistor MN12 is connected to the fourth negative power supply through the third resistor R3. The source of the twelfth NMOS transistor MN12 is grounded. The drain of the twelfth NMOS transistor MN12 is connected to the source of the eighth NMOS transistor MN8.

[0115] The release decision circuit 032 and the amplitude detection circuit 02 are connected through a Schmitt trigger;

[0116] The release decision circuit 032 includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, and a seventh PMOS transistor MP7, a first resistor R1 and a second resistor R2, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a seventh NMOS transistor MN7;

[0117] The source of the fourth PMOS transistor MP4, the source of the fifth PMOS transistor MP5, the source of the sixth PMOS transistor MP6, and the drain of the seventh PMOS transistor MP7 are connected to the VDD. The drain of the sixth PMOS transistor MP6 is grounded through the first resistor R1 and the second resistor R2 in sequence, and the gate of the sixth PMOS transistor MP6 is connected to the output terminal of the amplitude detection circuit 02;

[0118] The gate of the fifth PMOS transistor MP5 is connected to the drain of the fifth PMOS transistor MP5, the gate of the fourth PMOS transistor MP4, and the drain of the fifth NMOS transistor MN5. The drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4, the gate of the seventh PMOS transistor MP7, and the drain of the tenth PMOS transistor MP10;

[0119] The source of the seventh PMOS transistor MP7 is connected to the drain of the seventh NMOS transistor MN7. The source of the seventh NMOS transistor MN7 is grounded, and the gate of the seventh NMOS transistor MN7 is connected to the first reverse power supply;

[0120] The gate of the sixth NMOS transistor MN6 is connected to the first reverse power supply. The source of the sixth NMOS transistor MN6 is grounded. The drain of the sixth NMOS transistor MN6 is connected to the source of the fourth NMOS transistor MN4, and the gate of the fourth NMOS transistor MN4 is connected to the source of the seventh PMOS transistor MP7;

[0121] The source of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6, and the gate of the fifth NMOS transistor MN5 is connected between the first resistor R1 and the second resistor R2.

[0122] Figure 6In this case, the output signal of the oscillation circuit 01 enters from the XB terminal and is transmitted to the gate XB_INT of MN12 through the DC-blocking capacitor C3. The bias voltage of the XB_INT point is provided by VBN2 through a large resistor R3, and MN12 and MN11 are biased in the subthreshold region. Therefore, when there is no oscillation, a relatively large voltage is output at point A, while the output at point B is a low voltage, so that MP10 is fully turned on. Since the output STARTUP_OUT of the startup detection circuit outputs a high voltage at this time, the gate voltage VREF of MN5 is 0, causing MN5, MP5, MP4, MP7, and MN4 to all turn off. In this way, the voltage of MN2 is controlled, and AMP_REG approaches the power supply voltage VDD because of the conduction of MP8, MP9, and MP10.

[0123] As the oscillation amplitude increases, the voltage amplitude at point A gradually increases. Since it operates in the subthreshold region, the increase in amplitude causes the DC level at this point to gradually decrease, and the voltage at point B begins to rise. Due to the presence of the filter capacitor C0 at point B, the oscillation amplitude at this point is approximately 0. When the oscillation amplitude increases to a certain value, point B will rapidly increase to approach the power supply voltage VDD, thereby turning off MP10. On the other hand, the output STARTUP_OUT of the startup detection circuit outputs a low voltage, and VREF becomes the value divided by R1 and R2. A two-stage operational transconductance amplifier composed of MN5, MP5, MP4, MP7, MN4, MN7, and MN6 is established. The voltage at point C is equal to VREF, and the voltage at the AMP_REG point is thus determined. This node is the voltage to be adjusted, which controls the amplitude of the oscillator.

[0124] Preferably, the amplitude management circuit 031 further includes a filter capacitor C4, which functions to filter out the glitches at the AMP_REG point.

[0125] In this specific embodiment, the voltage control circuit 03 does not require an external power supply, but obtains the voltage adjustment signal from the output signal of the oscillation circuit 01, which simplifies the structure of the crystal oscillator and saves the power consumption of the crystal oscillator.

[0126] Figure 10 is the transient waveform of point XA, Figure 11 is the transient waveform of point XB, Figure 10 、 11 The turning points in are formed by the bias of the oscillation circuit 01 controlled by the voltage control circuit 03.

[0127] The present invention also provides an electronic timer, and the electronic timer includes the crystal oscillator with low phase noise as described in any one of the above. The crystal oscillator with low phase noise provided by the present invention includes an oscillation circuit 01, an amplitude detection circuit 02 and a voltage control circuit 03; the amplitude detection circuit 02 is connected to the output end of the oscillation circuit 01 and is used for detecting whether the amplitude of the output signal of the oscillation circuit 01 exceeds a preset amplitude threshold value; the voltage control circuit 03 is connected to the output end of the amplitude detection circuit 02 and is used for determining the input voltage of the oscillation circuit 01 according to the output signal of the amplitude detection circuit 02. By adding the amplitude detection circuit 02 and the voltage control circuit 03, the present invention realizes that when the amplitude of the oscillation circuit 01 exceeds the threshold value, the working voltage of the oscillation circuit 01 is automatically reduced, so as to control the oscillation amplitude and make the cross - conductance MOS transistor of the oscillation circuit 01 always work in the saturation region. In this way, the oscillation circuit 01 can not only output a single - frequency sine wave, but also greatly reduce its power consumption and the phase noise of the output signal.

[0128] The present invention also provides a control method for a crystal oscillator. The schematic flow chart of a specific embodiment is as Figure 8 shown, which is called the third specific embodiment and includes:

[0129] S301: Receive a voltage oscillation signal.

[0130] S302: Determine amplitude information according to the voltage oscillation signal.

[0131] S303: Judge whether the amplitude information exceeds an amplitude threshold value.

[0132] S304: When the amplitude information exceeds the amplitude threshold value, reduce the working voltage of the crystal oscillator to make the crystal oscillator work in a low - amplitude state.

[0133] As a preferred embodiment, the step S303 specifically includes:

[0134] Judge whether the amplitude information exceeds an amplitude threshold value and a working threshold value.

[0135] Correspondingly, the S304 includes:

[0136] S3041: When the amplitude information exceeds the working threshold value, obtain a voltage adjustment signal according to the voltage oscillation signal.

[0137] S3042: When the amplitude information exceeds the amplitude threshold value, send the voltage adjustment signal to a voltage regulation circuit 033 to make the voltage regulation circuit 033 reduce the working voltage of the crystal oscillator according to the voltage adjustment signal, so as to realize that the crystal oscillator works in a low - amplitude state.

[0138] The control method of the crystal oscillator provided by the present invention includes receiving a voltage oscillation signal; determining amplitude information according to the voltage oscillation signal; judging whether the amplitude information exceeds an amplitude threshold; when the amplitude information exceeds the amplitude threshold, reducing the operating voltage of the crystal oscillator to make the crystal oscillator operate in a low-amplitude state. By monitoring the amplitude information of the voltage oscillation signal, the present invention realizes that after the amplitude of the oscillation circuit 01 exceeds the threshold, the operating voltage of the oscillation circuit 01 is automatically reduced, achieving the control of the oscillation amplitude and making the transconductance MOS transistor of the oscillation circuit 01 always operate in the saturation region. In this way, the oscillation circuit 01 can not only output a single-frequency sine wave, but also greatly reduce its power consumption and the phase noise of the output signal.

[0139] The control device of the crystal oscillator provided by the embodiments of the present invention will be introduced below. The control device of the crystal oscillator described below can be correspondingly referred to the control method of the crystal oscillator described above.

[0140] Figure 9 It is a structural block diagram of the control device of the crystal oscillator provided by the embodiments of the present invention, which is called the fourth specific implementation manner. Refer to Figure 9 The control device of the crystal oscillator may include:

[0141] A receiving module 100, configured to receive a voltage oscillation signal;

[0142] An amplitude determining module 200, configured to determine the amplitude information according to the voltage oscillation signal;

[0143] A judging module 300, configured to judge whether the amplitude information exceeds an amplitude threshold;

[0144] A voltage reducing module 400, configured to reduce the operating voltage of the crystal oscillator when the amplitude information exceeds the amplitude threshold, so that the crystal oscillator operates in a low-amplitude state.

[0145] As a preferred implementation manner, the judging module 300 includes a dual-threshold judging unit, configured to judge whether the amplitude information exceeds an amplitude threshold and an operating threshold.

[0146] As a preferred implementation manner, the voltage reducing module 400 includes:

[0147] A low-voltage unit, configured to obtain a voltage adjustment signal according to the voltage oscillation signal when the amplitude information exceeds the operating threshold.

[0148] A transmitting unit, configured to transmit the voltage adjustment signal to a voltage regulation circuit 033 when the amplitude information exceeds the amplitude threshold, so that the voltage regulation circuit 033 reduces the operating voltage of the crystal oscillator according to the voltage adjustment signal, and enables the crystal oscillator to operate in a low-amplitude state.

[0149] The control device for a crystal oscillator provided by the present invention includes a receiving module 100, configured to receive a voltage oscillation signal; an amplitude determination module 200, configured to determine the amplitude information according to the voltage oscillation signal; a judgment module 300, configured to judge whether the amplitude information exceeds an amplitude threshold; and a voltage reduction module 400, configured to reduce the operating voltage of the crystal oscillator when the amplitude information exceeds the amplitude threshold, so that the crystal oscillator operates in a low-amplitude state. By monitoring the amplitude information of the voltage oscillation signal, the present invention automatically reduces the operating voltage of the oscillation circuit 01 after the amplitude of the oscillation circuit 01 exceeds the threshold, achieving control of the oscillation amplitude and enabling the transconductance MOS transistor of the oscillation circuit 01 to always operate in the saturation region. In this way, the oscillation circuit 01 can not only output a single-frequency sine wave, but also greatly reduce its power consumption and the phase noise of the output signal.

[0150] The control device for a crystal oscillator in this embodiment is used to implement the foregoing control method for a crystal oscillator. Therefore, the specific implementation manners in the control device for a crystal oscillator can be seen in the embodiment part of the control method for a crystal oscillator in the foregoing text. For example, the receiving module 100, the amplitude determination module 200, the judgment module 300, and the voltage reduction module 400 are respectively configured to implement steps S101, S102, S103, and S104 in the foregoing control method for a crystal oscillator. Therefore, the specific implementation manners can refer to the descriptions of the corresponding individual embodiments and will not be elaborated herein.

[0151] The present invention further provides an instantaneous residual voltage detection device having the above beneficial effects, including:

[0152] A memory, configured to store a computer program;

[0153] A processor, which is configured to implement the steps of the control method of the crystal oscillator as described when executing the computer program. The control method of the crystal oscillator provided by the present invention includes receiving a voltage oscillation signal; determining amplitude information according to the voltage oscillation signal; judging whether the amplitude information exceeds an amplitude threshold; when the amplitude information exceeds the amplitude threshold, reducing the operating voltage of the crystal oscillator to make the crystal oscillator operate in a low-amplitude state. By monitoring the amplitude information of the voltage oscillation signal, the present invention realizes automatically reducing the operating voltage of the oscillation circuit 01 after the amplitude of the oscillation circuit 01 exceeds the threshold, achieving the control of the oscillation amplitude and making the transconductance MOS transistor of the oscillation circuit 01 always operate in the saturation region. In this way, the oscillation circuit 01 can not only output a single-frequency sine wave, but also greatly reduce its power consumption and the phase noise of the output signal.

[0154] The present invention also provides a computer-readable storage medium having the above beneficial effects. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements the steps of the control method of the crystal oscillator as described. The control method of the crystal oscillator provided by the present invention includes receiving a voltage oscillation signal; determining amplitude information according to the voltage oscillation signal; judging whether the amplitude information exceeds an amplitude threshold; when the amplitude information exceeds the amplitude threshold, reducing the operating voltage of the crystal oscillator to make the crystal oscillator operate in a low-amplitude state. By monitoring the amplitude information of the voltage oscillation signal, the present invention realizes automatically reducing the operating voltage of the oscillation circuit 01 after the amplitude of the oscillation circuit 01 exceeds the threshold, achieving the control of the oscillation amplitude and making the transconductance MOS transistor of the oscillation circuit 01 always operate in the saturation region. In this way, the oscillation circuit 01 can not only output a single-frequency sine wave, but also greatly reduce its power consumption and the phase noise of the output signal.

[0155] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and reference can be made to the description in the method part for related parts.

[0156] It should be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0157] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0158] The steps of the methods or algorithms described in combination with the embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0159] The low-phase-noise crystal oscillator, electronic timer, and a control method, device, equipment, and computer-readable storage medium provided by the present invention have been introduced in detail above. Specific examples are used herein to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A crystal oscillator with low phase noise, characterized in that, It includes an oscillation circuit, an amplitude detection circuit, and a voltage control circuit; The amplitude detection circuit is connected to the output terminal of the oscillation circuit and is used to detect whether the amplitude of the output signal of the oscillation circuit exceeds a preset amplitude threshold; The voltage control circuit is connected to the output terminal of the amplitude detection circuit and is used to determine the input voltage of the oscillation circuit according to the output signal of the amplitude detection circuit; The voltage control circuit includes an amplitude management circuit, a release decision circuit, and a voltage regulation circuit; The input terminal of the amplitude management circuit is connected to the output terminal of the oscillation circuit and is used to obtain a voltage adjustment signal through the output signal of the oscillation circuit; The input terminal of the release decision circuit is connected to the output terminal of the amplitude detection circuit and the output terminal of the amplitude management circuit and is used to determine whether to output the voltage adjustment signal according to the output signal of the amplitude detection circuit; The input terminal of the voltage regulation circuit is connected to the output terminal of the release decision circuit and is used to determine the input voltage of the oscillation circuit according to the voltage adjustment signal; The amplitude detection circuit includes a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, and an eighteenth PMOS transistor, a fifth capacitor, a sixth capacitor, and a fourth resistor; The gates of the sixteenth PMOS transistor and the eighteenth PMOS transistor are connected to a first positive power supply, and the drain of the sixteenth PMOS transistor is respectively connected to the gates of the fifteenth PMOS transistor and the seventeenth PMOS transistor. The sources of the fifteenth PMOS transistor and the seventeenth PMOS transistor are connected to VDD. The drain of the fifteenth PMOS transistor is connected to the source of the sixteenth PMOS transistor. The drain of the seventeenth PMOS transistor is connected to the source of the eighteenth PMOS transistor; The gates of the thirteenth NMOS transistor and the fifteenth NMOS transistor are connected to a first negative power supply. The drain of the thirteenth NMOS transistor is connected to the drain of the sixteenth PMOS transistor. The drain of the fifteenth NMOS transistor is connected to the drain of the eighteenth PMOS transistor, and the drain of the fifteenth NMOS transistor and the drain of the eighteenth PMOS transistor are grounded through a fifth capacitor; The gates of the sixteenth NMOS transistor and the seventeenth NMOS transistor are connected to a third negative power supply. The drain of the sixteenth NMOS transistor is connected to the source of the fifteenth NMOS transistor. The source of the sixteenth NMOS transistor is connected to the drain of the seventeenth NMOS transistor. The source of the seventeenth NMOS transistor is grounded; The output terminal of the oscillation circuit is connected to the gate of the fourteenth NMOS transistor through the sixth capacitor, and the gate of the fourteenth NMOS transistor is connected to a fourth negative power supply through the fourth resistor. The source of the fourteenth NMOS transistor is grounded, and the drain of the fourteenth NMOS transistor is connected to the source of the thirteenth NMOS transistor.

2. The crystal oscillator with low phase noise according to claim 1, characterized in that, The amplitude management circuit includes an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor, a third resistor, a zero capacitor, and a third capacitor; The gates of the twelfth PMOS transistor, the fourteenth PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are connected to the first positive power supply, and the sources of the eighth PMOS transistor, the eleventh PMOS transistor, and the thirteenth PMOS transistor are connected to VDD. The drain of the thirteenth PMOS transistor is connected to the source of the fourteenth PMOS transistor, the drain of the eleventh PMOS transistor is connected to the source of the twelfth PMOS transistor, the drain of the eighth PMOS transistor is connected to the source of the ninth PMOS transistor, and the drain of the fourteenth PMOS transistor is connected to the gates of the thirteenth PMOS transistor and the eleventh PMOS transistor respectively; The gates of the eighth NMOS transistor and the ninth NMOS transistor are connected to the first negative power supply. The drain of the eighth NMOS transistor is connected to the drain of the fourteenth PMOS transistor, and the drain of the ninth NMOS transistor is connected to the drain of the twelfth PMOS transistor. The drain of the twelfth PMOS transistor is connected to the gate of the tenth PMOS transistor, and the connection between the drain of the twelfth PMOS transistor and the gate of the tenth PMOS transistor is grounded through the zero capacitor. The drain of the tenth PMOS transistor is the output terminal of the amplitude management circuit; The gates of the tenth NMOS transistor and the eleventh NMOS transistor are connected to the third negative power supply, and the drain of the eleventh NMOS transistor is connected to the source of the tenth NMOS transistor. The drain of the tenth NMOS transistor is connected to the source of the ninth NMOS transistor, and the source of the eleventh NMOS transistor is grounded; The output terminal of the oscillation circuit is connected to the gate of the twelfth NMOS transistor through the third capacitor, and the gate of the twelfth NMOS transistor is connected to the fourth negative power supply through the third resistor. The source of the twelfth NMOS transistor is grounded, and the drain of the twelfth NMOS transistor is connected to the source of the eighth NMOS transistor.

3. The crystal oscillator with low phase noise according to claim 2, wherein The release decision circuit and the amplitude detection circuit are connected through a Schmitt trigger; The release decision circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor, a first resistor and a second resistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; The source of the fourth PMOS transistor, the source of the fifth PMOS transistor, the source of the sixth PMOS transistor, and the drain of the seventh PMOS transistor are connected to the VDD. The drain of the sixth PMOS transistor is grounded through the first resistor and the second resistor in sequence. The gate of the sixth PMOS transistor is connected to the output terminal of the amplitude detection circuit; The gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor, the gate of the fourth PMOS transistor, and the drain of the fifth NMOS transistor respectively. The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the seventh PMOS transistor, and the drain of the tenth PMOS transistor; The source of the seventh PMOS transistor is connected to the drain of the seventh NMOS transistor. The source of the seventh NMOS transistor is grounded. The gate of the seventh NMOS transistor is connected to the first reverse power supply; The gate of the sixth NMOS transistor is connected to the first reverse power supply. The source of the sixth NMOS transistor is grounded. The drain of the sixth NMOS transistor is connected to the source of the fourth NMOS transistor. The gate of the fourth NMOS transistor is connected to the source of the seventh PMOS transistor; The source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor. The gate of the fifth NMOS transistor is connected between the first resistor and the second resistor.

4. An electronic timer, characterized in that, The electronic timer includes the crystal oscillator with low phase noise as described in any one of claims 1 to 3.

5. A control method for a crystal oscillator, characterized in that, The control method of the crystal oscillator is used to control the crystal oscillator with low phase noise as described in any one of claims 1 to 3, and includes: Receiving a voltage oscillation signal; Determining amplitude information according to the voltage oscillation signal; Judging whether the amplitude information exceeds an amplitude threshold; When the amplitude information exceeds the amplitude threshold, reducing the operating voltage of the crystal oscillator to make the crystal oscillator operate in a low-amplitude state.

6. A control device for a crystal oscillator, characterized in that, The control device of the crystal oscillator corresponds to the crystal oscillator with low phase noise as described in any one of claims 1 to 3, and includes: A receiving module for receiving a voltage oscillation signal; An amplitude determining module for determining amplitude information according to the voltage oscillation signal; A judging module for judging whether the amplitude information exceeds an amplitude threshold; A voltage reduction module for reducing the operating voltage of the crystal oscillator when the amplitude information exceeds the amplitude threshold to make the crystal oscillator operate in a low-amplitude state.

7. A transient residual voltage detection device, characterized in that, Including: A memory for storing a computer program; A processor for implementing the steps of the control method of the crystal oscillator as described in claim 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the control method of the crystal oscillator as described in claim 5 are implemented.

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