Low-noise ring oscillator

Abstract

The invention relates to the field of electronic oscillation circuits, and discloses a low-noise ring oscillator. The ring oscillator comprises an oscillation loop formed by connecting 2N + 1 stages of delay unit modules end to end, each stage of delay unit module comprises a complementary MOS tube and a source electrode degeneration resistor, one end of the source electrode degeneration resistor is connected with a source electrode of the complementary MOS tube, the other end of the source electrode degeneration resistor is connected with a common potential, and the source electrode degeneration resistor is made of a low-noise polycrystalline silicon resistor. By introducing the source electrode degeneration resistor into the delay unit module and utilizing the characteristic that a resistor element has lower noise compared with an MOS (Metal Oxide Semiconductor) device, the proportion of an MOS tube in the integral noise contribution is effectively reduced, so that the phase noise performance of the ring oscillator is improved, and the ring oscillator is particularly suitable for an electronic circuit system needing a high-quality clock signal.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to a low-noise ring oscillator technology. Background Art

[0002] Ring oscillators are widely used in various clock generation circuits due to their advantages, such as small size, insensitivity to electromagnetic noise, ability to provide multi-phase output clock signals, and wide frequency tuning range. However, a major drawback of ring oscillators is their typically poor phase noise. Phase noise in ring oscillators primarily stems from two factors: low-frequency phase noise is dominated by device flicker noise, while high-frequency phase noise is dominated by device white noise.

[0003] Traditional solutions for reducing ring oscillator phase noise typically include selecting device types with favorable noise characteristics, such as MOSFETs with low flicker noise and low thermal noise, and increasing MOSFET size to reduce its noise contribution. However, these approaches have limitations in practical applications. First, optimizing noise performance often comes at the expense of other performance metrics, such as increased power consumption and area overhead, or reduced speed. Second, traditional noise reduction methods are highly dependent on process parameters, limiting the scope for optimization. Particularly at advanced process nodes, the deteriorating noise characteristics of MOSFETs make it increasingly difficult to meet ring oscillator noise specifications through device selection and sizing.

[0004] Therefore, there is an urgent need for a novel ring oscillator design scheme that can effectively reduce the phase noise of the oscillator without relying on device parameter adjustment, while taking into account other performance indicators such as power consumption, area, and speed, so as to meet the needs of low-noise clock signals in different application scenarios. Summary of the Invention

[0005] The purpose of this application is to provide a low-noise ring oscillator to solve the problems raised in the above background technology.

[0006] The present application discloses a low-noise ring oscillator, comprising:

[0007] A ring oscillator unit, wherein the ring oscillator unit is formed by connecting 2N+1 delay unit modules end to end to form an oscillation loop, where N is a positive integer;

[0008] Wherein, each level of the delay unit module includes:

[0009] At least one pair of complementary MOS transistors, wherein the gates of the complementary MOS transistors serve as the input terminals of the delay unit module, and the drains serve as the output terminals of the delay unit module;

[0010] Two source degeneration resistors, one end of each of the two source degeneration resistors is connected to the source of the complementary MOS transistor, and the other end is connected to two common potentials. The source degeneration resistors are used to reduce the phase noise of the ring oscillator.

[0011] In a preferred example, two adjacent delay unit modules of the ring oscillator unit are connected via an inter-stage coupling circuit, and the output end of the previous delay unit module is connected to the input end of the next delay unit module.

[0012] In a preferred embodiment, the ring oscillator unit includes:

[0013] The first PMOS tube (PM D1 ) and the second PMOS tube (PM D2 ), whose gates are respectively used to receive the first input terminal (inp) and the second input terminal (inn) of the differential input signal, and whose drains are respectively connected to the first output terminal (outn) and the second output terminal (outp);

[0014] The first NMOS tube (NM D1 ) and the second NMOS tube (NM D2 ), whose gates are respectively used to receive the first input terminal (inp) and the second input terminal (inn) of the differential input signal, and whose drains are respectively connected to the first output terminal (outn) and the second output terminal (outp);

[0015] The first cross-coupling pair includes a first cross-coupling PMOS transistor (PM CP1 ) and the second cross-coupled PMOS tube (PM CP2 ), whose gates are connected to the second output terminal (outp) and the first output terminal (outn), and whose drains are connected to the first output terminal (outn) and the second output terminal (outp);

[0016] The second cross-coupling pair includes a first cross-coupling NMOS transistor (NM CP1 ) and the second cross-coupled NMOS tube (NM CP2 ), whose gates are connected to the second output terminal (outp) and the first output terminal (outn), and whose drains are connected to the first output terminal (outn) and the second output terminal (outp);

[0017] The first source degeneration resistor (RS D1 ), one end of which is connected to the power supply voltage, and the other end is connected to the first PMOS tube (PM D1 ) source, the second PMOS tube (PM D2 ) source, the first cross-coupled PMOS tube (PM CP1) source, the second cross-coupled PMOS tube (PM CP2 ) between the source and the power supply;

[0018] The second source degeneration resistor (RS D2 ), one end of which is grounded, and the other end is connected to the first NMOS tube (NM D1 ) source, the second NMOS tube (NM D2 ) source, the first cross-coupled NMOS tube (NM CP1 ) source and the second cross-coupled NMOS tube (NM CP2 ) source.

[0019] In a preferred embodiment, the two source degeneration resistors are made of low-noise polysilicon resistors; the noise of the source degeneration resistors is lower than the noise of the MOS transistor.

[0020] In a preferred embodiment, the two common potentials are respectively a power supply voltage and a ground.

[0021] In a preferred embodiment, the two source degeneration resistors are switch resistor arrays, which are used to adjust the oscillation frequency of the ring oscillator by configuring the resistance values of the switch resistor arrays.

[0022] In a preferred embodiment, a load capacitor is connected between the output end of each stage of the delay unit module and the ground.

[0023] In a preferred example, the load capacitor is a varactor, which is used to adjust the oscillation frequency of the ring oscillator by configuring the capacitance value of the varactor.

[0024] In a preferred example, the load capacitor is a switched capacitor array, which is used to adjust the oscillation frequency of the ring oscillator by configuring the capacitance value of the switched capacitor array.

[0025] In a preferred embodiment, a power supply voltage tuning device is further included, which is used to adjust the voltage value of the power supply voltage to adjust the oscillation frequency of the ring oscillator.

[0026] The embodiment of the present application can effectively reduce the phase noise of the ring oscillator by introducing a source degeneration resistor into each delay unit module of the ring oscillator, one end of which is connected to the source of the MOS tube and the other end is connected to the common potential. This design takes advantage of the fact that the resistor has lower noise than the MOS tube device, and introduces a low-noise resistor into the signal path of the ring oscillator, thereby reducing the proportion of the MOS tube in the overall noise contribution. Compared with the traditional method of simply increasing the MOS size or selecting a low-noise MOS tube type, this solution can more effectively reduce the flicker noise and thermal noise of the ring oscillator without significantly increasing power consumption and area. In particular, when the noise performance of the MOS tube deteriorates in advanced processes, this technology provides a more reliable noise reduction solution.

[0027] Furthermore, by introducing differential and cross-coupled circuit designs, the working relationship between the MOS transistors in the differential pair and the low-noise source degeneration resistors is optimized. While maintaining low-noise characteristics, the trade-off between speed and power consumption is balanced, providing better frequency stability and phase noise performance for the ring oscillator. The shared design of the source degeneration resistors reduces the circuit area and improves the integration density, making it particularly suitable for high-performance integrated circuit applications that require multi-phase low-noise clock signals.

[0028] Furthermore, by using low-noise polysilicon resistors to make source degeneration resistors, the impact of noise sources can be further reduced. Since the noise of polysilicon resistors is significantly lower than that of MOS tubes, this material selection can effectively exert the noise reduction effect of source degeneration technology.

[0029] Furthermore, by designing the source degeneration resistor as a switch resistor array, the oscillation frequency of the ring oscillator can be adjusted by configuring different resistance values, thereby realizing a frequency-adjustable low-noise ring oscillator and enhancing the application flexibility of the circuit.

[0030] Furthermore, by connecting a load capacitor between the output of each delay unit module and ground, the signal propagation delay can be controlled, providing another means for adjusting the frequency of the ring oscillator and enriching the frequency control scheme. By using a varactor as the load capacitor, the ring oscillator's oscillation frequency can be continuously and finely adjusted by adjusting the varactor's capacitance value, improving the accuracy and range of frequency adjustment. By designing the load capacitor as a switched capacitor array, the ring oscillator's oscillation frequency can be discretely adjusted by configuring different capacitance values, providing more frequency options to meet the needs of different application scenarios.

[0031] Furthermore, by adding a power supply voltage tuning device to adjust the voltage value of the power supply voltage, another way of adjusting the oscillation frequency of the ring oscillator can be achieved, which complements other frequency modulation methods and constructs a more comprehensive frequency tuning system.

[0032] The specification of this application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too lengthy. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be technically combined with feature C. Then, the solution of A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution of A+B+C+E should be considered as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 FIG. 1 is a schematic diagram of the basic architecture of a low-noise ring oscillator according to the first embodiment of the present application.

[0034] Figure 2 3 is a schematic diagram of the core circuit structure of each delay unit module in the ring oscillator structure according to the first embodiment of the present application.

[0035] Figure 3 3 is a schematic diagram of the circuit structure of a differential delay unit module according to the second embodiment of the present application. DETAILED DESCRIPTION

[0036] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0037] Description of some concepts:

[0038] Ring oscillator: An oscillator circuit consisting of an odd number of delay cells connected end to end in a closed loop. Ring oscillators have advantages such as small size, insensitivity to electromagnetic noise, multi-phase output clock signals, and a wide frequency tuning range.

[0039] Delay unit module: the basic unit circuit that makes up the ring oscillator loop. In this application, the ring oscillator unit is composed of 2N+1 delay unit modules connected end to end to form an oscillation loop.

[0040] Source degeneration resistor: A resistor connected between the source of the MOS transistor and the common potential. This application uses the source degeneration resistor to reduce the noise contribution of the MOS transistor, thereby reducing the phase noise of the ring oscillator.

[0041] Complementary MOS transistor: A structure composed of N-type and P-type MOS transistors. In the delay unit, the gate of the complementary MOS transistor serves as the input of the delay unit module, and the drain serves as the output of the delay unit module.

[0042] Differential structure: The differential delay unit module provided in this application includes a differential input end and a differential output end, and two pairs of complementary MOS transistors correspond to the two branches of the differential signal respectively.

[0043] Frequency tuning circuit: A circuit used to adjust the oscillation frequency of a ring oscillator. This application includes methods such as switching array control of the source degeneration resistor, tuning of the load capacitor using a varactor and switched capacitor array, tuning of the power supply voltage, and tuning of the MOS transistor in the delay unit.

[0044] Phase noise: One of the performance indicators of a ring oscillator. The ring oscillator of this application improves its performance by improving its phase noise characteristics. At low frequencies, the phase noise is mainly dominated by the device's flicker noise, while at high frequencies, the white noise of the device is mainly dominant.

[0045] The following is a summary of some of the innovative features of this application:

[0046] In general, to address the deteriorating noise performance issues faced by ring oscillators at advanced process nodes, this application proposes a novel technical solution that utilizes source degeneration resistors to reduce the noise contribution of MOS transistors in delay cells. This solution cleverly utilizes the physical property of resistors (particularly polysilicon resistors) that have lower noise than MOS devices themselves. By introducing source degeneration resistors into the delay cell module, the MOS transistor's contribution to the overall noise contribution is effectively reduced, thereby optimizing the phase noise performance of the ring oscillator.

[0047] The technical solution of this application takes a different approach to solving the phase noise problem of ring oscillators, providing a method that does not rely on process parameter adjustments. Traditional noise reduction methods rely primarily on increasing MOS transistor size or selecting the appropriate MOS transistor type, but the optimization space for these methods is very limited at advanced process nodes. However, this application utilizes a source degeneration resistor to adjust the noise contribution ratio of active and passive devices in the delay unit, avoiding the limitations of device selection and sizing, and has wider applicability.

[0048] The following describes the physical mechanism by which the technical solution of this application reduces noise. The source degeneration resistor provides local negative feedback. When the source-drain current of the MOS transistor fluctuates due to noise, the current flowing through the source degeneration resistor generates a voltage change. This voltage change has a counteracting effect on the gate-source voltage (Vgs), reducing the current fluctuation caused by the original noise. Mathematically, negative feedback reduces the noise to 1 / (1 + gm × Rs) times the original value, where Rs is the value of the source degeneration resistor. Furthermore, the source degeneration resistor reduces the effective transconductance of the MOS transistor. This reduction in transconductance directly leads to a reduction in noise power, especially for suppressing flicker noise. Furthermore, the source degeneration structure fundamentally changes the distribution of noise power in the circuit. The total noise power at the output can be decomposed into two components: MOS transistor noise and resistor noise. Resistor noise (especially polysilicon resistors) is typically an order of magnitude lower than the noise in the MOS transistor. By properly designing the Rs value, the proportion of low-noise components (resistors) in the overall circuit noise is increased, while the proportion of high-noise components (MOS transistors) is reduced.

[0049] This application also provides circuit implementations for both single-ended and differential delay unit modules. The differential structure, by introducing a cross-coupled MOS transistor pair and a shared source degeneration resistor, minimizes the area overhead associated with the additional resistor while ensuring good noise suppression, thus balancing the design requirements of low ring oscillation noise and a small footprint.

[0050] The low-noise ring oscillator of this application can be easily combined with a variety of frequency tuning circuits, such as a switch array for controlling the source degeneration resistor value, an adjustable capacitor unit, and a bias voltage adjustment unit. This provides multiple possibilities for flexible adjustment of the oscillation frequency in different application scenarios, expanding the application range of this low-noise ring oscillator architecture.

[0051] In summary, the low-noise ring oscillator proposed in this application demonstrates a high level of creativity in both architectural design and circuit implementation. The novel design concept of using source degeneration resistors to adjust the noise contribution ratio overcomes the limitations of traditional noise reduction solutions. The carefully designed differential delay unit further enhances circuit performance while balancing noise and area. Flexible and diverse frequency tuning methods lay the foundation for the application of this architecture in various fields. The ingenious combination of these features constitutes a complete technical solution for a low-noise ring oscillator that breaks through existing technology.

[0052] In summary, the present application has made systematic innovations in key technical aspects such as noise suppression, signal integrity, frequency adaptability, low power consumption and high integration, and through the synergy between various innovative points, it has finally formed a high-efficiency, low-noise, tunable ring oscillator architecture. Compared with the existing technology, the present application not only significantly reduces the phase noise of the oscillation signal, but also improves the frequency tuning capability, optimizes power consumption and area, and provides a new solution for high-precision clock signal generation. Especially in application scenarios such as on-chip clock generation, radar detection, navigation positioning and high-speed data communication, which have extremely high requirements for clock signal purity and stability, the present application has demonstrated obvious technical advantages and industrialization potential. Therefore, the technical solution of the present application has outstanding creativity and meets the basic conditions for patent authorization.

[0053] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0054] Example 1: Single-ended delay unit module

[0055] like Figure 1 As shown, a first embodiment provides a low-noise ring oscillator, including a ring oscillator unit formed by connecting 2N+1 delay unit modules end to end. Where N is a positive integer. In some embodiments, N can be flexibly set based on the performance requirements of the ring oscillator to obtain desired frequency and phase characteristics.

[0056] The ring-shaped connection of the ring oscillator units enables cyclic propagation and phase iteration of the clock signal between the delay unit modules, generating stable oscillations. The signal phase at the output of each ring oscillator unit can be different, and the output of one or more ring oscillator units can be selected as the output of the ring oscillator as needed.

[0057] In the low-noise ring oscillator of this application, each delay unit module includes at least one pair of complementary MOS transistors and a source degeneration resistor used to reduce the noise contribution of the MOS transistors. The source degeneration resistor is connected to the source of the MOS transistor and its other end is connected to a common potential. Optionally, by using a low-noise polysilicon resistor as the source degeneration resistor, the phase noise of the ring oscillator can be effectively reduced.

[0058] It is worth noting that the introduction of source degeneration resistors in this application differs from the traditional noise reduction method of adjusting the size and type of MOS transistors, providing a novel approach to noise suppression. By using source degeneration resistors to shunt the MOS transistor noise current, the noise performance of the ring oscillator can be effectively optimized without increasing power consumption or area.

[0059] Further, Figure 2The structure of a single-ended delay unit module in a specific embodiment of the low-noise ring oscillator of the first embodiment is shown. As shown, the delay unit module includes a pair of complementary MOS transistors: an NMOS transistor NM1 and a PMOS transistor PM1. The gates of NM1 and PM1 are connected together, serving as the input terminal inp of the delay unit module. The drains of NM1 and PM1 are connected together, serving as the output terminal outn of the delay unit module.

[0060] In order to reduce the influence of MOS tube noise on the phase noise of the ring oscillator, a first source degeneration resistor R is connected between the source of NM1 and the ground terminal. S2 , connect the second source degeneration resistor R between the source of PM1 and the power supply terminal S1 It should be emphasized that R S1 and R S2 Low-noise polysilicon resistors are preferred. Compared to MOS transistors, polysilicon resistors have lower noise characteristics. By using source degeneration resistor technology, the noise contribution of MOS transistors can be reduced, effectively improving the noise performance of the delay unit module and even the entire ring oscillator.

[0061] Working principle:

[0062] In this embodiment, the single-ended delay unit module operates as follows: When an input signal is input through the inp terminal, the complementary structure formed by NM1 and PM1 inverts the signal and generates a delay, with the output signal being output through the outn terminal. Multiple such delay unit modules are connected end to end in a ring oscillator to form a loop. When the oscillation conditions are met, a stable oscillation signal is generated.

[0063] By introducing a source degeneration resistor at the source of the MOS transistor, the noise in the MOS transistor can be degraded. Polysilicon resistors have lower noise characteristics than MOS transistors. This source degeneration structure takes advantage of the low noise characteristics of polysilicon resistors, thereby reducing the contribution of the MOS transistor to the overall noise and effectively improving the phase noise performance of the ring oscillator.

[0064] The single-ended delay unit module in this embodiment performs source degeneration on the noise in the MOS transistor and uses low-noise polysilicon resistors to reduce the noise contribution of the MOS transistor, thereby achieving the design goal of a low-noise ring oscillator.

[0065] Example 2: Differential Delay Unit Module

[0066] Figure 3 FIG. 1 shows the structure of the differential delay unit module in another specific embodiment of the low noise ring oscillator of the present application. Figure 2Compared with the single-ended delay unit module shown in FIG, the differential delay unit module adopts a differential signal transmission method, which has the advantages of common mode suppression and power supply noise suppression.

[0067] As shown in the figure, the differential delay unit module is configured with differential input terminals inp and inn and corresponding differential output terminals outp and outn. The differential input signal and the differential output signal are a pair of complementary signals, where inp and outp are positive phase signals, and inn and outn are negative phase signals.

[0068] The differential delay unit module includes two pairs of complementary MOS tubes, namely NMOS tube NM D1 、NM D2 and PMOS tube PM D1 、PM D2 Among them, NM D1 and PM D1 The gates of the two terminals are connected to the differential input terminals inp, NM D2 and PM D2 The gates of NM are connected to the differential input terminal inn. D1 and PM D1 The drains are connected to the differential output terminals outn, NM D2 and PM D2 The drains of the two complementary MOS transistors are connected to the differential output terminal outp. The two pairs of complementary MOS transistors correspond to the two branches of the differential signal respectively.

[0069] In order to further enhance the amplification and anti-interference capabilities of the differential delay unit module, a pair of cross-coupled MOS tubes, namely NMOS tubes NM, are set between the two pairs of complementary MOS tubes. CP1 、NM CP2 and PMOS tube PM CP1 、PM CP2 .

[0070] Among them, NM CP1 The gate and drain of NM are connected to outn and outp respectively. CP2 The gate and drain of the PM are connected to outp and outn respectively. CP1 The gate and drain of the PM are connected to outn and outp respectively. CP2 The gate and drain of the delay unit are connected to outp and outn, respectively. This cross-coupling forms a positive feedback path, which accelerates the conversion speed of the differential output signal and improves the driving force and bandwidth of the delay unit module.

[0071] It is worth mentioning that in the differential structure, each MOS tube can share the source degeneration resistor. Figure 3 As shown, NM D1 、NM D2 、NMCP1 and NM CP2 The sources of the D2 One end, RS D2 The other end of PM is connected to the ground terminal; D1 、PM D2 、PM CP1 and PM CP2 The sources of the D1 One end, RS D1 Connect the other end of the power supply to the power supply. Figure 2 Similar to the single-ended structure, RS D1 and RS D2 Low-noise polysilicon resistors are preferably used. Sharing the source degeneration resistor not only reduces the circuit area but also ensures the matching and symmetry of the differential path, thereby achieving better noise suppression.

[0072] Working principle:

[0073] In this embodiment, the differential delay unit module operates as follows: a differential input signal is input through the inp and inn terminals. After processing by two pairs of complementary MOS transistors and a cross-coupled MOS transistor, a differential output signal is output through the outp and outn terminals. When multiple such differential delay unit modules are connected end-to-end to form a ring oscillator, a stable differential oscillation signal can be generated.

[0074] Similar to Example 1, this embodiment also uses source degeneration technology to reduce the noise contribution of MOS tube. In the differential structure, the source degeneration resistor RS D1 and RS D2 The use of low-noise polysilicon resistors effectively reduces the contribution of MOS tube noise to the overall noise, thereby improving the phase noise performance of the ring oscillator. The differential structure's shared source degeneration resistor design further reduces circuit area and improves integration.

[0075] In summary, the differential delay unit module in this embodiment inherits the low-noise characteristics of the single-ended structure and further introduces differential transmission and cross-coupling technology. It can achieve high-speed and stable oscillation output in harsh noise environments while taking into account layout area and power consumption considerations. It is suitable for occasions with high requirements on ring oscillator performance.

[0076] It should be noted that in practical applications, the output frequency of the ring oscillator often needs to be tuned to adapt to different operating conditions and performance requirements. This application provides a variety of optional frequency tuning schemes that can be flexibly combined with the aforementioned low-noise delay unit module to achieve control of the oscillation frequency.

[0077] One frequency tuning solution is to control the resistance of the source degeneration resistor through a switch array. Specifically, the source degeneration resistor in the delay unit module (such as Figure 2 and Figure 3 R in S1 、R S2 、RS D1 and RS D2 ) is a switching electronic array. Its control terminal can be used to control the switching resistor array, changing its resistance value, thereby changing the equivalent source degeneration resistor value. This change in the source degeneration resistor value affects the characteristics of the delay unit module, thereby adjusting the oscillation frequency of the ring oscillator.

[0078] Another frequency tuning solution involves connecting an adjustable capacitor to the output of the delay unit module. This adjustable capacitor can be implemented using a varactor or a switched capacitor array. By varying the equivalent capacitance of the adjustable capacitor by a control signal, the characteristics of the delay unit module can be adjusted, thereby varying the oscillation frequency. For example, connecting an adjustable capacitor to the output of the delay unit module can achieve frequency tuning.

[0079] The third frequency tuning solution is to adjust the power supply voltage of the delay unit module. Changing the power supply voltage of the delay unit module through the voltage adjustment unit can affect the characteristics of the MOS tube, thereby adjusting the delay time and oscillation frequency.

[0080] A fourth frequency tuning scheme involves tuning the MOS transistors in the delay cell. This involves adjusting the electrical characteristics of the MOS transistors to control the time required for the signal to pass through the delay cell, thereby affecting the overall oscillation frequency of the ring oscillator. For example, bias current can be controlled by using an additional control transistor to limit the current flowing through the MOS transistors in the delay cell. This changes the charge and discharge time of the load capacitor, thereby adjusting the delay time. Another example is the use of transistor array switches, which involve arranging multiple transistors with different width-to-length ratios (W / L) in parallel. These transistors can be selectively enabled or disabled via digital control signals, changing the effective transistor size in the delay cell and thus adjusting its drive capability and delay characteristics. Another example is body bias tuning, which involves adjusting the body voltage of the MOS transistors and utilizing the body effect to change their threshold voltage. This change in threshold voltage affects the switching speed of the transistors.

[0081] In summary, the frequency tuning solutions provided in this application include multiple implementations. These tuning solutions can be used individually or in combination. They can be designed for ring oscillators in different application scenarios, ensuring low noise characteristics while meeting frequency tunability requirements.

[0082] It should be noted that in this patent application, relational terms such as first and second, etc., are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element specified by the phrase "comprising a" does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element. In this patent application, reference to performing an action in accordance with an element means performing the action in accordance with at least that element, including two situations: performing the action in accordance with that element alone, and performing the action in accordance with that element and other elements. Expressions such as "plurality," "multiple times," and "many" include "two," "twice," "two kinds," and "more than two," "more than two times," and "more than two kinds."

[0083] All documents mentioned in this application are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art may make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A low-noise ring oscillator, characterized in that: include: A ring oscillator unit, wherein the ring oscillator unit is formed by connecting 2N+1 delay unit modules end to end to form an oscillation loop, where N is a positive integer; Wherein, each level of the delay unit module includes: At least one pair of complementary MOS transistors, wherein the gates of the complementary MOS transistors serve as the input terminals of the delay unit module, and the drains serve as the output terminals of the delay unit module; Two source degeneration resistors, one end of each of the two source degeneration resistors is connected to the source of the complementary MOS transistor, and the other end is connected to two common potentials. The source degeneration resistors are used to reduce the phase noise of the ring oscillator.

2. The low-noise ring oscillator according to claim 1, wherein: Two adjacent delay unit modules of the ring oscillator unit are connected via an inter-stage coupling circuit, and the output end of the previous delay unit module is connected to the input end of the next delay unit module.

3. The low-noise ring oscillator according to claim 1, wherein: The ring oscillator unit comprises: The first PMOS tube (PM D1 ) and the second PMOS tube (PM D2 ), whose gates are respectively used to receive the first input terminal (inp) and the second input terminal (inn) of the differential input signal, and whose drains are respectively connected to the first output terminal (outn) and the second output terminal (outp); The first NMOS tube (NM D1 ) and the second NMOS tube (NM D2 ), whose gates are respectively used to receive the first input terminal (inp) and the second input terminal (inn) of the differential input signal, and whose drains are respectively connected to the first output terminal (outn) and the second output terminal (outp); The first cross-coupling pair includes a first cross-coupling PMOS transistor (PM CP1 ) and the second cross-coupled PMOS tube (PM CP2 ), whose gates are connected to the second output terminal (outp) and the first output terminal (outn), and whose drains are connected to the first output terminal (outn) and the second output terminal (outp); The second cross-coupling pair includes a first cross-coupling NMOS transistor (NM CP1 ) and the second cross-coupled NMOS tube (NM CP2 ), whose gates are connected to the second output terminal (outp) and the first output terminal (outn), and whose drains are connected to the first output terminal (outn) and the second output terminal (outp); The first source degeneration resistor (RS D1 ), one end of which is connected to the power supply voltage, and the other end is connected to the first PMOS tube (PM D1 ) source, the second PMOS tube (PM D2 ) source, the first cross-coupled PMOS tube (PM CP1 ) source, the second cross-coupled PMOS tube (PM CP2 ) between the source and the power supply; The second source degeneration resistor (RS D2 ), one end of which is grounded, and the other end is connected to the first NMOS tube (NM D1 ) source, the second NMOS tube (NM D2 ) source, the first cross-coupled NMOS tube (NM CP1 ) source and the second cross-coupled NMOS tube (NM CP2 ) source.

4. The low-noise ring oscillator according to claim 1, wherein: The two common potentials are respectively a power supply voltage and a ground.

5. The low-noise ring oscillator according to any one of claims 1 to 4, wherein: The two source degeneration resistors are made of low-noise polysilicon resistors; the noise of the source degeneration resistors is lower than the noise of the MOS tube.

6. The low-noise ring oscillator according to any one of claims 1 to 4, wherein: The two source degeneration resistors are a switch resistor array, which is used to adjust the oscillation frequency of the ring oscillator by configuring the resistance value of the switch resistor array.

7. The low-noise ring oscillator according to any one of claims 3 or 4, characterized in that: A load capacitor is connected between the output end of each delay unit module and the ground.

8. The low-noise ring oscillator according to claim 7, wherein: The load capacitor is a varactor, which is used to adjust the oscillation frequency of the ring oscillator by configuring the capacitance value of the varactor.

9. The low-noise ring oscillator according to claim 7, wherein: The load capacitor is a switched capacitor array, which is used to adjust the oscillation frequency of the ring oscillator by configuring the capacitance value of the switched capacitor array.

10. The low-noise ring oscillator according to claim 5, wherein: It also includes a power supply voltage tuning device for adjusting the voltage value of the power supply voltage to adjust the oscillation frequency of the ring oscillator.

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