Saving and restoring the scoreboard

Abstract

Disclosed are systems, devices, and methods for tracking updates to configuration status registers using a scoreboard. A system includes one or more processing nodes, one or more memory devices, a plurality of configuration status registers, and a communication structure coupled to the one or more processing units and the one or more memory devices. The system uses a scoreboard to track updates to the configuration status registers during operation. Before a node enters a power-gated state, the system stores only those configuration status registers that have changed. This reduces the amount of data written to memory at each transition to a power-gated state and increases the amount of time the node can spend in the power-gated state. Furthermore, the configuration status registers are grouped together to match the memory access granularity, and each configuration status register group has a corresponding scoreboard entry.

Description

[0001] background

[0002] Description of Related Technology

[0003] Computing systems increasingly integrate a large number of different types of components on a single chip module or on a multi-chip module. The complexity and power consumption of the system increase with the number of different types of components. Power management is an important aspect of the design and operation of integrated circuits, especially for those circuits integrated in mobile devices. Mobile devices typically rely on battery power, and reducing the power consumption in the integrated circuit can increase the life of the battery and reduce the heat generated by the integrated circuit. In order to achieve reduced power consumption, various components within the integrated circuit can enter a power reduction state or a power gated state. As used herein, a "power gated state" refers to a power reduction state when a component operates in a mode in which the component consumes less power than in a normal operating mode. For example, a "power gated state" may involve turning off the power of a given component or removing the power of a given component. Alternatively, a "power gated state" may involve reducing the power supply voltage and / or reducing the clock frequency supplied to a given component. It should be noted that a "power-gated state" may also be referred to as a "power-gated state" or a "power-gated mode". In various embodiments, a power-gated state refers to a power reduced state in which the current state of a device or component is not maintained (ie, power that would normally be used to maintain such a state is removed in order to consume less power).

[0004] Some computing systems save the configuration register state to a memory (e.g., a dynamic random access memory (DRAM)) before entering a power-gated state. After power gating is exited, the configuration register state is restored. As used herein, "configuration register state" is defined as the value of a plurality of configuration registers that identify a given component of a computing system, define various features of a given component, and allow system software to interface with a given component and / or control the operation of a given component. It should be noted that configuration registers may also be referred to as control state registers (CSRs) or model-specific registers (MSRs). "Configuration register state" may also be referred to as "configuration space". Configuration registers may be internal registers of a device of a component such as a communication fabric, a memory controller, a central processing unit (CPU), a graphics processing unit (GPU), or other components. Operating systems, device drivers, and diagnostic software typically access the configuration space during operation of a given component.

[0005] Saving the configuration register state to memory each time the system enters a power-gated state results in a delay that reduces the total amount of time spent in the power-gated state. Furthermore, writing the entire configuration register state to memory incurs a power usage penalty. Therefore, there is a need for improved techniques for managing configuration register states when transitioning between different power states. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The advantages of the methods and mechanisms described herein may be better understood by referring to the following description in conjunction with the accompanying drawings, in which:

[0007] Figure 1 is a block diagram of one embodiment of a computing system.

[0008] Figure 2 is a block diagram of another embodiment of a computing system.

[0009] Figure 3 is a block diagram of another embodiment of a computing system.

[0010] Figure 4 is a diagram of one implementation for splicing the configuration status register address into the linear address space.

[0011] Figure 5 is a generalized flow diagram illustrating one embodiment of a method for tracking configuration status register writes using a scoreboard.

[0012] Figure 6 is a generalized flow chart illustrating one embodiment of a method for performing configuration status register address stitching.

[0013] Figure 7 is a generalized flow diagram illustrating one embodiment of a method for matching scoreboard entry tracking with memory access granularity. DETAILED DESCRIPTION

[0014] In the following description, numerous specific details are set forth to provide a thorough understanding of the methods and mechanisms presented herein. However, those skilled in the art will recognize that various embodiments may be practiced without these specific details. In some cases, well-known structures, components, signals, computer program instructions, and techniques have not been shown in detail to avoid obscuring the methods described herein. It will be appreciated that for simplicity and clarity of description, the elements shown in the figures are not necessarily drawn to scale. For example, the sizes of some elements may be exaggerated relative to other elements.

[0015] Various systems, devices, methods, and computer-readable media for implementing a scoreboard to track register writes are disclosed herein. In one embodiment, a system includes at least one or more processing units, a communication structure, a scoreboard, and a memory. The system uses a scoreboard to track configuration register writes so that those configuration registers that have not been updated since a previous transition to a power-gated state will not trigger a save operation to the memory. Typically, the configuration state does not change during operation, so it is expected that filtering implemented by the scoreboard will effectively reduce writes to the memory at each transition to a power-gated state.

[0016] In one embodiment, the memory for the system is implemented as one or more dynamic random access memory (DRAM) devices. In certain DRAM types, write power is greater than read power, and thus avoiding writes to the DRAM can reduce the DRAM power of the configuration state save operation by more than half. In one embodiment, the scoreboard is implemented at the same access granularity as the DRAM device. In this embodiment, registers saved to a DRAM channel will have the same access granularity as the DRAM channel and are tracked collectively by the same scoreboard entry.

[0017] In one embodiment, configuration register addressing is sparsely distributed within the address space. For example, register addressing may be implemented over a larger Peripheral Component Interconnect Express (PCIe) address space range. In one embodiment, an addressing scheme is used to avoid unnecessary save and restore addressing holes between registers. This addressing scheme involves splicing configuration registers together into contiguous addresses for save and restore operations associated with power gating. This contiguous address space can then help determine which DRAM access block a register for scoreboard manipulation belongs to.

[0018] View now Figure 1, a block diagram of one embodiment of a computing system 100 is shown. In one embodiment, computing system 100 includes at least core complexes 105A-N, input / output (I / O) interface 120, bus 125, one or more memory controllers 130, network interface 135, and power management unit 145. In other embodiments, computing system 100 may include other components and / or computing system 100 may be arranged differently. In one embodiment, each core complex 105A-N includes one or more general-purpose processors, such as central processing units (CPUs). It should be noted that a "core complex" may also be referred to as a "processing node" or "CPU" herein. In some embodiments, one or more core complexes 105A-N may include a data parallel processor with a highly parallel architecture. Examples of data parallel processors include graphics processing units (GPUs), digital signal processors (DSPs), etc. In one embodiment, each processor core within core complex 105A-N includes a cache subsystem having one or more levels of cache.

[0019] The one or more memory controllers 130 represent any number and type of memory controllers accessible by the core complexes 105A-N. The one or more memory controllers 130 are coupled to any number and type of memory devices (not shown). For example, the type of memory in the one or more memory devices coupled to the one or more memory controllers 130 may include dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), or other memory. The I / O interface 120 represents any number and type of I / O interface (e.g., peripheral component interconnect (PCI) bus, PCI extension (PCI-X), PCIE (PCI Express) bus, Gigabit Ethernet (GBE) bus, universal serial bus (USB)). Various types of peripheral devices may be coupled to the I / O interface 120. Such peripheral devices include (but are not limited to) a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc. Power management unit 145 manages power consumption of various components of system 100 by changing the power states of these components. For example, power management unit 145 may place a component in a power-gated mode to reduce power consumption of system 100 when the component has been idle for a threshold amount of time.

[0020] In various embodiments, computing system 100 may be any of a server, a computer, a laptop, a mobile device, a game console, a streaming device, a wearable device, or a variety of other types of computing systems or devices. It should be noted that the number of components of computing system 100 may vary between embodiments. For example, there may be more than one component in FIG. Figure 1 It should also be noted that computing system 100 may include a greater or lesser number of each component shown. Figure 1 Other components not shown in FIG. In addition, in other embodiments, Figure 1 The computing system 100 may be constructed in other ways different from the one shown in FIG.

[0021] Now turn to Figure 2 , a block diagram of another embodiment of a computing system 200 is shown. In one embodiment, the computing system 200 includes at least a processing unit 210, a fabric 215, a power management unit 220, a memory controller 230, and one or more memory devices 240. In other embodiments, the computing system 200 may include other components and / or the computing system 200 may be arranged differently. In addition, although in Figure 2 An example of components is shown in FIG. 2 , but it should be understood that in other embodiments, system 200 may include Figure 2 For example, in another embodiment, computing system 200 may include additional processing units, memory controllers, etc.

[0022] Processing unit 210 represents any number and type of processing units. Processing unit 210 may include any number of cores, each of which includes any number of execution units for executing software instructions and a cache subsystem for caching data used by the core. Processing unit 210 also includes a configuration status register 245A for storing the state of processing unit 210. When power management unit 220 detects a condition for placing processing unit 210 in power gating mode, the value of configuration status register 245A is stored to one or more memory devices 240. The stored version of configuration status register 245A is shown as configuration status register 245B in one or more memory devices 240. One or more memory devices 240 represent any number and type of memory devices included in system 200. For example, in one embodiment, one or more memory devices 240 are implemented using DRAM devices. In other embodiments, one or more memory devices 240 may be implemented using other types of memory devices (e.g., static random access memory (SRAM), non-volatile RAM, etc.).

[0023] As used herein, the term "low power mode" may be defined as a reduced power state for operating a component or device. In one embodiment, a "low power mode" involves removing power to a component or device (i.e., power gating). In another embodiment, a "low power mode" involves placing a component or device in a lower power state in order to reduce the power consumption of the component or device. For example, the component / device may be placed in a lower power state by reducing the voltage and / or clock frequency supplied to the component / device.

[0024] Rather than writing the configuration state register 245A in its entirety to the one or more memory devices 240 each time the processing unit 210 enters a power gated mode, a scoreboard 250 may be used to track which registers have been updated since the last time the processing unit 210 entered a power gated mode. Subsequently, the next time the processing unit 210 is to enter a power gated mode, only the subset of registers that have been updated will be written to the one or more memory devices 240. Other registers that have not yet been updated will have their existing values ​​stored in the configuration state register 245B in the one or more memory devices 240. The scoreboard 250 may be implemented using any suitable structure. For example, in one embodiment, the scoreboard 250 is implemented using a flip-flop. In other embodiments, the scoreboard 250 may be implemented using other types of storage elements. Although the scoreboard 250 is shown as being stored within the fabric 215, it should be noted that in other embodiments, the scoreboard 250 may be stored in other locations. Using the scoreboard 250 helps to reduce the amount of data written to the one or more memory devices 240 when transitioning to a power gated mode. Use of scoreboard 250 also helps reduce latency in transitioning to power-gated mode, which increases the overall amount of time processing unit 210 can spend in power-gated mode.

[0025] The structure 215 represents any type of communication structure, bus and / or other control and interface logic. The structure 215 represents any communication interconnection and can use any protocol to communicate between the components of the system 200. The structure 215 provides data paths, switches, routers and other logic that connect the processing unit 210, the power management unit 220, the memory controller 230 and other components to each other. The structure 215 handles request, response and data services and detection services to promote consistency. The structure 215 also handles interrupt request routing and configuration access paths to various components of the system 200. In addition, the structure 215 handles configuration requests, responses and configuration data services. The structure 215 can be based on a bus, including a shared bus configuration, a crossbar configuration and a layered bus with a bridge. The structure 215 can also be based on packets and can be layered with bridges, crossbars, point-to-point or other interconnects.

[0026] In one embodiment, the fabric 215 has a configuration space represented by configuration state registers 255A. These configuration state registers 255A may include any number and type of registers, such as routing tables, address mappings, configuration data, buffer allocation information, etc. When the power management unit 220 detects an idle condition of the fabric 215, the power management unit 220 may place the fabric 215 in a power gated mode to save power. Before the fabric 215 enters the power gated mode, the configuration state registers 255A are saved to one or more memory devices 240 because these values ​​will be lost when the fabric 215 enters the power gated mode. When the configuration state registers 255A are written to the one or more memory devices 240, these values ​​are shown as configuration state registers 255B in the one or more memory devices 240. In order to avoid having to write all values ​​of the configuration state registers 255A back to the one or more memory devices 240 each time a transition to the power gated mode occurs, a scoreboard 250 may be used to track which configuration state registers in the configuration state registers 255A have changed. Alternatively, different scoreboards may be used to track updates to configuration status registers 255A. Depending on the embodiment, a single scoreboard 250 may track multiple sets of configuration status registers for multiple components, or a separate scoreboard 250 may be used for each individual component whose configuration status registers are tracked. In either case, only those of configuration status registers 255A that have been updated since fabric 215 was previously transitioned to power-gated mode are written back to one or more memory devices 240. This helps increase the efficiency of the process by which fabric 215 enters power-gated mode. It should be noted that any number of other components of system 200 may also include configuration status registers that are tracked by scoreboard 250 (or another scoreboard structure) for determining which registers have been updated and need to be written to one or more memory devices 240 after a component is transitioned to power-gated mode.

[0027] In one embodiment, the power management unit 220 manages power gating of different components of the system 200. As used herein, the term "power gating" is defined as reducing the power consumption of one or more components. The term "power gating" may also be defined as placing a component in a low power state. A "low power state" as defined herein may be a state in which the voltage supplied to the component is reduced from its maximum value; the frequency of a clock signal is reduced from its maximum value; the clock signal to the component is suppressed (clock gating); power to the component is removed; or a combination of any of the previous states. In order to cause a given component to leave the power gating mode, the power management unit 220 may increase or turn on the supply voltage and / or clock supplied to the given component. The power management unit 220 may receive control signals from one or more other units, such as timers, interrupt units, processing units, etc., for determining when to transition between different power states of various components.

[0028] View now Figure 3 , a block diagram of another embodiment of a computing system 300 is shown. The computing system 300 includes at least a component 310, a structure 320, a memory controller 330, and one or more memory devices 340. It should be noted that except for Figure 3 300. In addition to the components shown in FIG. 300, system 300 may include any number of other components. It should also be noted that system 300 may be any of the previously listed types of computing systems, depending on the implementation. Component 310 represents any type of component that may be included in system 300. Depending on the implementation, component 310 may be a processing unit, a processing core, a processing node, an I / O or peripheral device, a fabric component, a fabric area, or other type of component or device.

[0029] In one embodiment, component 310 includes a plurality of configuration state registers 315A. These configuration state registers 315A may include any number and type of storage elements for storing values ​​representing the configuration state of component 310. When component 310 enters power-gated mode, only those registers 315A that have changed since the previous transition to power-gated mode are written to one or more memory devices 340. In one embodiment, scoreboard 325 is used to track which registers 315A have been updated recently. Although scoreboard 325 is shown as being stored in configuration 320, it should be understood that in other embodiments, scoreboard 325 may be stored in other locations. In addition, scoreboard 325 is coupled to control unit 327, and control unit 327 manages entries of scoreboard 325 and determines which registers 315A are written back to one or more memory devices 340 when component 310 transitions to power-gated mode. Control unit 327 may be implemented using any suitable combination of software and / or hardware.

[0030] Scoreboard 325 may include any number of entries, wherein the number of entries is different between embodiments. Although scoreboard 325 is shown as including eight entries, it should be understood that this only indicates one embodiment. In other embodiments, scoreboard 325 may include other number of entries. In one embodiment, each entry of scoreboard 325 is used to track multiple registers from configuration status register 315A. In one embodiment, the granularity tracked by each entry of scoreboard 325 matches the access granularity to one or more memory devices 340. In other words, each entry of scoreboard 325 tracks the amount of data that can be written to one or more memory devices 340 in a single access. For example, if the access granularity to one or more memory devices 340 is 64 bytes (in one embodiment), each entry of scoreboard 325 tracks a register equivalent to 64 bytes.

[0031] like Figure 3 , scoreboard 325 includes eight entries labeled 00-07. In one embodiment, each entry of scoreboard 325 includes an entry ID, a register ID or address of a tracked register, and an update indication to specify whether any register in the tracked register group has been updated since component 310 was previously converted to power-gated mode. As indicated by scoreboard 325, the register groups corresponding to entries 01 and 05 have been updated, while other register groups corresponding to other entries have not been updated. Therefore, if a condition is detected for component 310 to enter power-gated mode, only those register groups corresponding to entries 01 and 05 will be written to the configuration status register 315B in one or more memory devices 340.

[0032] In addition, when component 310 enters power gated mode, the entries of scoreboard 325 are reset. Alternatively, when component 310 exits power gated mode, the entries of scoreboard 325 may be reset. In either case, after component 310 exits power gated mode, all entries of scoreboard 325 will indicate that configuration status register 315A has not changed. After exiting from power gated mode, only changes to configuration status register 315A after component 310 is powered on again will be reflected in scoreboard 325. It should be noted that configuration 320 may also include any number of other scoreboards to track updates to configuration status registers for any number of other components.

[0033] Now turn to Figure 4 , shows one embodiment of splicing configuration status register addresses into linear address space 435. In one embodiment, a set of configuration status registers (for a given component) includes registers 410, 415, 420, and 425. Registers 410, 415, 420, and 425 represent any number and type of registers that define the configuration space for a given component. In one embodiment, registers 410, 415, 420, and 425 are distributed throughout sparsely populated address space 405. In other words, there are large gaps between the addresses of registers 410, 415, 420, and 425 in sparsely populated address space 405.

[0034] Instead of attempting to track and store registers 410, 415, 420, and 425 from sparsely populated address space 405, translation unit 430 maps registers 410, 415, 420, and 425 from sparsely populated address space 405 into linear address space 435. It should be noted that translation unit 430 may also be referred to as a control unit. Figure 4As shown on the right side of FIG, registers 410, 415, 420, and 425 are remapped so that they now occupy contiguous addresses in linear address space 435. When the computing system tracks updates to registers 410, 415, 420, and 425, the computing system uses a scoreboard implemented in linear address space 435. Therefore, when the computing system needs to write register values ​​to memory when a given component enters a power-gated mode, the computing system uses the addresses of registers 410, 415, 420, and 425 from linear address space 435 to reduce the amount of data that needs to be stored to memory.

[0035] View now Figure 5 , shows one embodiment of a method 500 for tracking configuration status register writes using a scoreboard. For discussion purposes, this embodiment and Figure 6 to Figure 7 However, it should be noted that in various embodiments of the described method, one or more of the described elements are performed simultaneously, in an order different from the order shown, or the elements are omitted entirely. Other additional elements are also performed when necessary. Any of the various systems or devices described herein can implement method 500.

[0036] When a component first enters power-gated mode, the component writes all configuration status registers to memory (e.g., DRAM) (block 505). Depending on the implementation, the component may be a processing node, a processing unit, a processor core, a fabric, a portion of a fabric, or another type of component or computing device. Next, after exiting from power-gated mode, the component uses a scoreboard to track updates made to the configuration status registers (block 510). If the component detects a condition to enter power-gated mode (conditional block 515, "yes" branch), the component writes only those configuration status registers that are marked by the scoreboard as having changed to memory (e.g., DRAM), after which the component enters power-gated mode (block 520). In one embodiment, the condition to enter power-gated mode includes detecting that the component has been idle for a threshold amount of time. In addition, the scoreboard is reset to clear any entries that are marked (block 525). Next, the component enters power-gated mode (block 530). If the component does not detect conditions to enter a power-gated mode (conditional block 515 , “no” branch), method 500 returns to block 510 .

[0037] After block 530, if the component detects a condition to exit the power gated mode (conditional block 535, "yes" branch), the component exits the power gated mode and restores the configuration state register according to the stored value in the memory (block 540). In one embodiment, the condition to exit the power gated mode includes an interrupt generated to wake up the component. After block 540, method 500 returns to block 510. If the component does not detect a condition to exit the power gated mode (conditional block 535, "no" branch), the component remains in the power gated mode (block 545). After block 545, method 500 returns to conditional block 535. It should be noted that multiple instances of method 500 can be performed in parallel for multiple components of a computing system.

[0038] Now turn to Figure 6 , shows one embodiment of a method 600 for performing configuration status register address stitching. A control unit identifies the addresses of a set of configuration status registers storing the configuration state of a given component (block 605). In one embodiment, the configuration status registers are sparsely mapped within the physical address space of the host computing system, with large gaps between the individual registers.

[0039] Next, the control unit maps the addresses of the set of configuration status registers to contiguous addresses within the linear address space (block 610). Subsequently, the given component uses a scoreboard entry to track the group of the set of configuration status registers mapped to contiguous locations in the linear address space (block 615). Furthermore, the system maps addresses in the linear address space to memory locations to store and restore configuration status registers after entering and exiting the power-gated mode (block 620). After block 620, the method 600 ends.

[0040] View now Figure 7 , one embodiment of a method 700 for matching scoreboard entry tracking with memory access granularity is shown. A control unit identifies a memory access granularity for a computing system (block 705). In one embodiment, a register or other storage element may store an indication of the memory access granularity. In another embodiment, the control unit performs a memory access to determine the memory access granularity. Next, the control unit groups configuration status registers together into groups that match the memory access granularity (block 710). For example, in one embodiment, the memory access granularity is 64 bytes, and the control unit groups the configuration status registers into 64-byte groups. The control unit may perform these steps for a single component of the computing system or for multiple components of the computing system. In some cases, more than one control unit within the computing system may perform the steps of method 700 for different components of the computing system.

[0041] Furthermore, the control unit tracks each configuration state register group using a single scoreboard entry (block 715). Subsequently, the control unit tracks updates to the configuration state registers using the scoreboard (block 720). The system marks a given scoreboard entry in response to any of the configuration state registers in a given register group being updated to indicate that the given group should be saved at the next transition to power gating mode (block 725). After block 725, the method 700 ends.

[0042] In various embodiments, the method and / or mechanism described herein are implemented using the program instructions of the software application. For example, it is expected that the program instructions can be executed by a general or special processor. In various embodiments, such program instructions can be represented by a high-level programming language. In other embodiments, the program instructions can be compiled into binary, intermediate or other forms by a high-level programming language. Alternatively, program instructions describing the behavior or design of hardware can be written. Such program instructions can be represented by high-level programming languages ​​such as C. Alternatively, hardware design languages ​​(HDL) such as Verilog can be used. In various embodiments, the program instructions are stored on any one of a variety of non-temporary computer-readable storage media. The storage medium can be accessed by a computing system during use to provide program instructions to the computing system for program execution. In general, such computing systems at least include one or more memories and one or more processors that can execute program instructions.

[0043] It should be emphasized that the above embodiments are only non-limiting examples of implementations. Once the above disclosure is fully understood, numerous changes and modifications will become apparent to those skilled in the art. It is expected that the following claims will be understood to include all such changes and modifications.

Claims

1. A system, comprising: one or more processing nodes; Memory; as well as Multiple configuration status registers; The system is configured as follows: maintaining a scoreboard to track which of the plurality of configuration state registers have been updated since a given processing node previously transitioned to a power-gated state, wherein the scoreboard includes one or more entries, the one or more entries including a register configuration identification and an indication of whether the register configuration has been updated since the given processing node previously transitioned to the power-gated state; as well as In response to detecting a condition for the given processing node to transition to the power-gated state, only a subset of the plurality of configuration state registers are written to the memory, wherein the subset is indicated by the scoreboard.

2. The system of claim 1, wherein the system is further configured to maintain entries in the scoreboard at a granularity matching a memory access granularity.

3. The system of claim 1, wherein: A plurality of configuration status registers are collectively tracked by a single scoreboard entry; and A combined size of the plurality of configuration status registers matches the memory access granularity.

4. The system of claim 1, wherein the system is further configured to map the configuration status register to a contiguous address of a linear address space.

5. The system of claim 4, wherein the system is further configured to map addresses in the linear address space to addresses in the memory for storing and restoring the configuration status register.

6. The system of claim 1, wherein the system is further configured to reset the scoreboard in response to the given processing node transitioning to the power-gated state.

7. The system of claim 1, wherein the system is further configured to restore the plurality of configuration state registers according to the stored values ​​in the memory in response to the given processing node exiting the power-gated state.

8. A method comprising: maintaining, by the control unit, a scoreboard to track which of a plurality of configuration status registers have been updated since a given component previously transitioned to a power-gated state, wherein the scoreboard includes one or more entries, the one or more entries including a register configuration identification and an indication of whether the register configuration has been updated since a given processing node previously transitioned to a power-gated state; responsive to detecting an update to a given configuration status register, storing, by the control unit, an indication in a corresponding entry in the scoreboard; as well as In response to detecting a condition for the given component to transition to the power-gated state, a subset of the plurality of configuration state registers is written to a memory by the given component, wherein the subset is indicated by the scoreboard.

9. The method of claim 8, further comprising maintaining entries in the scoreboard at a granularity matching a memory access granularity.

10. The method of claim 8, wherein: A plurality of configuration status registers are collectively tracked by a single scoreboard entry; and A combined size of the plurality of configuration status registers matches the memory access granularity.

11. The method of claim 8, further comprising mapping the configuration status register to a contiguous address of the linear address space.

12. The method of claim 11, further comprising mapping addresses in the linear address space to addresses in the memory for storing and restoring the configuration status register.

13. The method of claim 8, further comprising resetting the scoreboard in response to the given component transitioning to the power-gated state.

14. The method of claim 8, further comprising restoring the plurality of configuration state registers according to the stored values ​​in the memory in response to the given component exiting the power-gated state.

15. A device, comprising: Processing nodes; Control unit; as well as Memory; The control unit is configured as follows: maintaining a scoreboard to track which of a plurality of configuration state registers have been updated since a given processing node previously transitioned to a power-gated state, wherein the scoreboard includes one or more entries, the one or more entries including a register configuration identification and an indication of whether the register configuration has been updated since the given processing node previously transitioned to the power-gated state; In response to detecting a condition for the given processing node to transition to the power-gated state, only a subset of the plurality of configuration state registers are written to the memory, wherein the subset is indicated by the scoreboard.

16. The apparatus of claim 15, wherein the control unit is further configured to maintain entries in the scoreboard at a granularity matching a memory access granularity.

17. The apparatus of claim 15, wherein: A plurality of configuration status registers are collectively tracked by a single scoreboard entry; and A combined size of the plurality of configuration status registers matches the memory access granularity.

18. The apparatus of claim 15, wherein the control unit is further configured to map the configuration status register to a contiguous address of a linear address space.

19. The apparatus of claim 18, wherein the control unit is further configured to map addresses in the linear address space to addresses in the memory for storing and restoring the configuration status register.

20. The apparatus of claim 15, wherein the control unit is further configured to reset the scoreboard in response to the given processing node transitioning to the power-gated state.

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