Substrate processing method and substrate processing apparatus

Abstract

The present invention relates to a substrate processing method and a substrate processing apparatus. [Problem] To contract a base film of a mask without blocking an opening of the mask. [Solution] Provided is a substrate processing method including the following steps: a step of preparing a substrate having a first film which is a silicon-containing film and a second film formed on the first film and having a second opening; a control step of controlling the temperature of the substrate to -30° or lower; and an etching step of etching the first film through the second opening, wherein in the step of etching the first film, a plasma of a first processing gas containing a fluorocarbon gas is used to form the first film into a tapered shape such that as etching progresses, the shape of a cross section of a first opening formed in the first film becomes smaller.

Description

Technical Field

[0001] The present disclosure relates to a substrate processing method and a substrate processing apparatus. Background Art

[0002] With the miniaturization of wafer processing, there is a tendency for the line width of wirings formed on a wafer, the diameter of contact holes, etc. to become smaller. Therefore, a plasma etching method has been proposed that can etch an etching target film into a finer line width and contact hole pattern.

[0003] For example, Patent Document 1 proposes the following: When etching an intermediate layer that is a silicon oxide film, by making the size of the opening at the bottom of the intermediate layer smaller than the size of the corresponding pattern opening formed by the resist layer on the upper layer of the intermediate layer, the organic film layer under the intermediate layer is etched thinner.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2007-005377 Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] However, when transferring a mask pattern to an etching target film that is a base film, when using a processing gas having a depositing precursor and etching while depositing a deposit on the pattern, there is a concern that the front of the opening of the mask may be blocked due to the deposit attached to the upper part of the opening of the mask.

[0009] The present disclosure can shrink the base film of the mask without blocking the opening of the mask.

[0010] Solutions for Solving the Problems

[0011] According to one aspect of the present disclosure, there is provided a substrate processing method including the following steps: a step of preparing a substrate having a first film that is a silicon-containing film and a second film formed on the first film and having a second opening; a control step of controlling the temperature of the substrate to -30° or lower; and an etching step of etching the first film through the second opening, and in the step of etching the first film, using a plasma of a first processing gas containing a fluorocarbon gas, and forming the first film into a tapered shape in such a manner that the shape of the cross section of the first opening formed in the first film becomes smaller as the etching progresses.

[0012] Effects of the Invention

[0013] According to one aspect, the width of the opening can be reduced without blocking the opening of the film formed by etching. Brief Description of the Drawings

[0014] Figure 1 A cross-sectional schematic view showing an example of a substrate processing apparatus according to an embodiment.

[0015] Figure 2 A diagram showing an outline of an etching process for a stacked structure 1 according to an embodiment.

[0016] Figure 3 A diagram showing the etching processes of the respective layers of a stacked structure 1 according to an embodiment in sequence.

[0017] Figure 4 A diagram showing a comparison of an example of the result of an etching process according to an embodiment with a comparative example.

[0018] Figure 5 A diagram showing the relationship between the addition amount of H2 and the opening blockage in an etching process according to an embodiment.

[0019] Figure 6 A diagram schematically showing the types of gases used and the deposition state in an etching process according to an embodiment.

[0020] Figure 7 A diagram for explaining the surface reaction in an etching process according to an embodiment.

[0021] Figure 8 A flowchart showing an example of a substrate processing method according to an embodiment.

[0022] Figure 9 A diagram showing the etching processes of the respective layers of a stacked structure 2 according to an embodiment in sequence.

[0023] Figure 10 A diagram showing the etching processes of the respective layers of a stacked structure 3 according to an embodiment in sequence.

[0024] Explanation of Reference Numerals

[0025] W substrate

[0026] 1 Substrate processing apparatus

[0027] 10 Processing container

[0028] 10s Internal space

[0029] 14 Mounting table

[0030] 30 Upper electrode

[0031] 32 Component

[0032] 34 Top plate

[0033] 36 Support

[0034] 38 Gas supply pipe

[0035] 40 Gas source group

[0036] 42 Valve group

[0037] 44 Flow controller group

[0038] 46 Shield

[0039] 48 Baffle

[0040] 80 Control unit

[0041] 92 Silicon oxide film

[0042] 93 Organic film

[0043] 94 Silicon-containing antireflection film

[0044] 95 Photoresist film

[0045] 96, 105, 124 Second opening

[0046] 97 First opening

[0047] 110 Deposit Detailed implementation manners

[0048] Hereinafter, with reference to the accompanying drawings, the manners for implementing the present disclosure will be described. In each of the accompanying drawings, the same reference numerals are assigned to the same components, and repeated descriptions may be omitted sometimes.

[0049] [Substrate processing apparatus]

[0050] For a substrate processing apparatus 1 of an embodiment, it will be described with Figure 1 reference to the drawings. Figure 1 FIG. is a cross-sectional schematic view showing an example of a substrate processing apparatus 1 of an embodiment.

[0051] The substrate processing apparatus 1 includes a processing container 10. The processing container 10 provides an internal space 10s therein. The processing container 10 includes a processing container main body 12. The processing container main body 12 has a substantially cylindrical shape. The processing container main body 12 is formed of, for example, aluminum. A film having corrosion resistance is provided on the inner wall surface of the processing container main body 12. The film may be a ceramic such as alumina or yttria.

[0052] A passage 12p is formed in the side wall of the processing container main body 12. The substrate W is transported between the internal space 10s and the outside of the processing container 10 through the passage 12p. The passage 12p is opened and closed by a gate valve 12g provided along the side wall of the processing container main body 12.

[0053] A support portion 13 is provided on the bottom of the processing container main body 12. The support portion 13 is formed of an insulating material. The support portion 13 has a substantially cylindrical shape. The support portion 13 extends upward from the bottom of the processing container main body 12 in the internal space 10s. The support portion 13 has a mounting table 14 at the upper part. The mounting table 14 is configured to support the substrate W in the internal space 10s.

[0054] The mounting table 14 has a lower electrode 18 and an electrostatic chuck 20. The mounting table 14 may further have an electrode plate 16. The electrode plate 16 is formed of a conductor such as aluminum and has a substantially disc shape. The lower electrode 18 is provided on the electrode plate 16. The lower electrode 18 is formed of a conductor such as aluminum and has a substantially disc shape. The lower electrode 18 is electrically connected to the electrode plate 16.

[0055] The electrostatic chuck 20 is provided on the lower electrode 18. The substrate W is placed on the upper surface of the electrostatic chuck 20. The electrostatic chuck 20 has a main body and an electrode. The main body of the electrostatic chuck 20 has a substantially disc shape and is formed of a dielectric. The electrode of the electrostatic chuck 20 is a film-like electrode provided inside the main body of the electrostatic chuck 20. The electrode of the electrostatic chuck 20 is connected to a DC power supply 20p via a switch 20s. When a DC voltage from the DC power supply 20p is applied to the electrode of the electrostatic chuck 20, an electrostatic attraction is generated between the electrostatic chuck 20 and the substrate W. By this electrostatic attraction, the substrate W is held on the electrostatic chuck 20.

[0056] On the peripheral portion of the lower electrode 18, an edge ring 25 is arranged so as to surround the edge of the substrate W. The edge ring 25 is also called a focus ring. The edge ring 25 is used to improve the in-plane uniformity of the plasma processing of the substrate W. The edge ring 25 can be formed of silicon, silicon carbide, quartz, or the like.

[0057] A flow path 18f is provided inside the lower electrode 18. In the flow path 18f, a cooling medium is supplied from a cooling unit (not shown) provided outside the processing container 10 via a pipe 22a. The cooling medium such as brine supplied in the flow path 18f returns to the cooling unit via a pipe 22b. In the substrate processing apparatus 1, the temperature of the substrate W placed on the electrostatic chuck 20 is adjusted by the heat exchange between the cooling medium and the lower electrode 18. It should be noted that the cooling medium supplied by the cooling unit not only cools the lower electrode 18 but also functions as a medium for adjusting the temperature for heating the lower electrode 18. In addition, the temperature of the cooling medium (temperature adjusting medium) is adjusted by the cooling unit so that the value of a temperature sensor (not shown) provided on the electrostatic chuck 20 (or the lower electrode 18) becomes a specified temperature.

[0058] In the substrate processing apparatus 1, a gas supply pipeline 24 is provided. The gas supply pipeline 24 is used to supply a heat transfer gas (such as He gas) from the heat transfer gas supply mechanism to between the upper surface of the electrostatic chuck 20 and the back surface of the substrate W.

[0059] The substrate processing apparatus 1 further includes an upper electrode 30. The upper electrode 30 is disposed above the mounting table 14. The upper electrode 30 is supported by the upper part of the processing container main body 12 via a member 32. The member 32 is formed of an insulating material. The upper electrode 30 and the member 32 close the upper opening of the processing container main body 12.

[0060] The upper electrode 30 can include a top plate 34 and a support body 36. The lower surface of the top plate 34 is the lower surface on the side of the internal space 10s, defining the internal space 10s. The top plate 34 can be formed of a low-resistance conductor or semiconductor that generates less Joule heat. The top plate 34 has a plurality of gas discharge holes 34a penetrating through the top plate 34 in its plate thickness direction.

[0061] The support body 36 detachably supports the top plate 34. The support body 36 is formed of a conductive material such as aluminum. A gas diffusion chamber 36a is provided inside the support body 36. The support body 36 has a plurality of gas holes 36b extending downward from the gas diffusion chamber 36a. The plurality of gas holes 36b communicate with the plurality of gas discharge holes 34a respectively. A gas inlet 36c is formed on the support body 36. The gas inlet 36c is connected to the gas diffusion chamber 36a. A gas supply pipe 38 is connected to the gas inlet 36c.

[0062] A valve group 42, a flow controller group 44, and a gas source group 40 are connected to the gas supply pipe 38. The gas source group 40, the valve group 42, and the flow controller group 44 constitute a gas supply unit. The gas source group 40 includes a plurality of gas sources. The valve group 42 includes a plurality of on-off valves. The flow controller group 44 includes a plurality of flow controllers. The plurality of flow controllers in the flow controller group 44 are respectively mass flow controllers or pressure-controlled flow controllers. The plurality of gas sources in the gas source group 40 are respectively connected to the gas supply pipe 38 via the corresponding on-off valves in the valve group 42 and the corresponding flow controllers in the flow controller group 44.

[0063] In the substrate processing apparatus 1, a shield 46 is detachably provided along the inner wall surface of the processing container main body 12 and the outer periphery of the support portion 13. The shield 46 is used to prevent reaction products from adhering to the processing container main body 12. The shield 46 is formed, for example, by forming a corrosion-resistant film on the surface of a base material made of aluminum. The corrosion-resistant film can be formed of a ceramic such as yttrium oxide.

[0064] A baffle plate 48 is provided between the support portion 13 and the side wall of the processing container main body 12. The baffle plate 48 is formed, for example, by forming a corrosion-resistant film (such as a yttrium oxide film) on the surface of a base material made of aluminum. A plurality of through holes are formed in the baffle plate 48. An exhaust port 12e is provided below the baffle plate 48 and at the bottom of the processing container main body 12. An exhaust device 50 is connected to the exhaust port 12e via an exhaust pipe 52. The exhaust device 50 includes a pressure regulating valve and a vacuum pump such as a turbo molecular pump.

[0065] The substrate processing apparatus 1 includes a first high-frequency power supply 62 and a second high-frequency power supply 64. The first high-frequency power supply 62 is a power supply that generates first high-frequency power (hereinafter, also referred to as "HF power"). The first high-frequency power has a frequency suitable for plasma generation. The frequency of the first high-frequency power is in the range of 27 MHz to 100 MHz, and can be, for example, 40 MHz. The first high-frequency power supply 62 is connected to the lower electrode 18 via an integrator 66 and an electrode plate 16. The integrator 66 has a circuit for integrating the output impedance of the first high-frequency power supply 62 and the impedance on the load side (lower electrode 18 side). It should be noted that the first high-frequency power supply 62 can be connected to the upper electrode 30 via the integrator 66. The first high-frequency power supply 62 constitutes an example of a plasma generation unit.

[0066] The second high-frequency power supply 64 is a power supply that generates second high-frequency power (hereinafter, also referred to as "LF power"). The second high-frequency power has a frequency lower than that of the first high-frequency power. When the second high-frequency power is used together with the first high-frequency power, the second high-frequency power is used as high-frequency power for a bias voltage for introducing ions into the substrate W. The frequency of the second high-frequency power is, for example, in the range of 400 kHz to 13.56 MHz, and can be, for example, 13.56 MHz. The second high-frequency power supply 64 is connected to the lower electrode 18 via an integrator 68 and an electrode plate 16. The integrator 68 has a circuit for integrating the output impedance of the second high-frequency power supply 64 and the impedance on the load side (lower electrode 18 side).

[0067] It should be noted that the second high-frequency power can be used without using the first high-frequency power, that is, plasma can be generated using only a single high-frequency power. In the above case, the frequency of the second high-frequency power can be a frequency greater than 13.56 MHz, such as 40 MHz. Additionally, in the above case, the second high-frequency power supply 64 constitutes an example of a plasma generation unit, and the substrate processing apparatus 1 can include the first high-frequency power supply 62 and the integrator 66.

[0068] In the substrate processing apparatus 1, gas is supplied from a gas supply unit to an internal space 10s to generate plasma. In addition, by supplying the first high-frequency power and / or the second high-frequency power, a high-frequency electric field is generated between the upper electrode 30 and the lower electrode 18. The generated high-frequency electric field generates plasma from the gas.

[0069] The substrate processing apparatus 1 includes a power supply 70. The power supply 70 is connected to the upper electrode 30. The power supply 70 applies a DC voltage for introducing positive ions existing in the internal space 10s into the top plate 34 to the upper electrode 30. The DC voltage applied to the upper electrode 30 is -1000 V or more and 0 V or less.

[0070] The substrate processing apparatus 1 may further include a control unit 80. The control unit 80 can be a computer including a processor, a storage unit such as a memory, an input device, a display device, an input / output interface for signals, etc. The control unit 80 controls each part of the substrate processing apparatus 1. In the control unit 80, an input device can be used, and an operator can perform an input operation of commands for managing the substrate processing apparatus 1. In addition, in the control unit 80, the operation status of the substrate processing apparatus 1 can be visualized and displayed through the display device. Further, in the storage unit, a control program and process data are stored. The control program is executed by the processor to perform various processes in the substrate processing apparatus 1. The processor executes the control program and controls each part of the substrate processing apparatus 1 according to the process data.

[0071] [Etching a wafer having a stacked structure 1]

[0072] Next, the etching process of the wafer W using the substrate processing apparatus 1 having the above configuration will be described with reference to Figure 2 and Figure 3 will be described. Figure 2 FIG. is a diagram showing an outline when an etching process of one embodiment is performed on the stacked structure 1. Figure 3 FIG. is a diagram showing an example of the etching process of each layer of the stacked structure 1 shown in (a) of Figure 2 .

[0073] Figure 2 In (a) of Figure 3 and (a) of Figure 2 , the stacked structure 1 on the wafer W on which the etching process is performed is shown. The stacked structure 1 is an example of a structure of multiple films formed on the wafer W. As shown in (a) of Figure 3 , in the stacked structure 1, a silicon nitride film 91, a silicon oxide film 92, an organic film 93, a silicon-containing antireflection film 94, and a photoresist film 95 are sequentially stacked from below on a silicon substrate 90.

[0074] The photoresist film 95, the silicon-containing antireflection film 94, and the organic film 93 can function as masks. The photoresist film 95 has a second opening 96. The second openings 96 are regularly arranged when observed from the upper surface of the photoresist film 95 and are patterned through a photolithography process. The silicon-containing antireflection film 94 is etched using the photoresist film 95 as a mask, whereby a first opening 97 is formed in the silicon-containing antireflection film 94. The silicon-containing antireflection film 94 is an example of a first film that is a silicon-containing film. The photoresist film 95 is an example of a second film formed on the first film and having a second opening.

[0075] As an example of the silicon-containing film that is the first film, it can be a silicon oxide film containing organic substances such as hydrocarbons. Additionally, it can be a silicon oxynitride film such as SiON. They are used as antireflection film materials when forming the second opening 96 as an exposure pattern on the photoresist film 95 in the photolithography process.

[0076] The organic film 93 is a coating film formed on the silicon oxide film 92 by spin on carbon. Additionally, the organic film 93 can be amorphous carbon deposited on the silicon oxide film 92 by a chemical vapor deposition (CVD) method. The organic film 93, the silicon-containing antireflection film 94, and the photoresist film 95 function as masks, and when etching the silicon oxide film 92, the silicon oxide film 92 is etched until the silicon nitride film 91 is exposed at the bottom of the etched recess.

[0077] First, the silicon-containing antireflection film 94 is etched through the second opening 96 of the photoresist film 95. The process conditions during the etching of the silicon-containing antireflection film 94 are shown below.

[0078] <Process conditions during the etching of the silicon-containing antireflection film 94>

[0079] Pressure 50 mT (6.67 Pa)

[0080] HF power / LF power 300 W / 300 W

[0081] Gas types CF4, H2 (Three types were experimented with: no H2 added, and H2 added at a ratio of CF4:H2 = 25:3 or 25:6)

[0082] Wafer temperature variable

[0083] It should be noted that the supplied CF4 gas and the mixed gas of CF4 gas and H2 gas are examples of a first processing gas. A fluorine-containing gas such as SF6 gas or NF3 gas can be added to the CF4 gas.

[0084] Note that the temperature of the wafer can be adjusted as follows: The temperature of the electrostatic chuck 20 adjusted to a specified temperature by the cooling unit is transferred to the wafer through the surface of the electrostatic chuck 20 and the heat transfer gas, so that it can be adjusted. However, the wafer is exposed to the plasma generated by the first high-frequency power for plasma excitation, and the ions introduced by the light from the plasma and the second high-frequency power for the bias voltage are irradiated onto the wafer. Therefore, the temperature of the wafer, especially the surface temperature of the wafer facing the plasma, sometimes becomes higher than the temperature of the adjusted electrostatic chuck 20. In addition, the temperature of the wafer sometimes also rises due to the radiant heat from the temperature-adjusted counter electrode and the chamber side wall. Therefore, if the actual temperature of the wafer during the etching process can be measured, or the temperature difference between the adjusted temperature of the electrostatic chuck 20 and the actual surface temperature of the wafer can be inferred from the process conditions, the temperature of the wafer can be adjusted within a preset temperature range. Therefore, the set value of the adjusted temperature of the electrostatic chuck 20 can be reduced. Note that if it is inferred that the temperature difference between the adjusted temperature of the electrostatic chuck 20 and the actual surface temperature of the wafer is small under conditions such as small output of the first high-frequency power and the second high-frequency power, the wafer temperature can be regarded as equal to the temperature of the electrostatic chuck 20.

[0085] After the silicon-containing antireflection film 94 is etched, the organic film 93 is etched using the silicon-containing antireflection film 94 as a mask. The process conditions during the etching of the organic film 93 are shown below.

[0086] <Process conditions during the etching of the organic film 93>

[0087] Pressure 15 mT (2.00 Pa)

[0088] HF power / LF power 100 W / 750 W

[0089] Gas types N2, H2

[0090] Wafer temperature variable

[0091] Note that in the following description, "extremely low temperature" means a temperature of -30°C or lower, and "normal temperature" means a temperature of 0°C or higher. In addition, the mixed gas of the supplied N2 gas and H2 gas is an example of the second processing gas. As another example of the second processing gas, an O2 gas, a mixed gas of an O2 gas and a CO2 gas, a mixed gas of an O2 gas and a SO2 gas, a mixed gas of an O2 gas and a COS gas, etc. can be used.

[0092] The etching of the organic film 93 does not necessarily have to be carried out at extremely low temperatures and can also be carried out at room temperature. However, by creating an extremely low temperature environment, it is possible to obtain the effects of mass productivity and shrinkage of the CD value during further etching. Therefore, the wafer temperature is preferably controlled to be extremely low. It should be noted that the gas type during the etching of the organic film 93 is not limited to the mixed gas of N2 gas and H2 gas, and a mixed gas of O2 gas and CO2 gas, a mixed gas of O2 gas and SO2 gas, a mixed gas of O2 gas and COS gas, etc. can be used.

[0093] After the organic film 93 is etched, the silicon oxide film 92 is etched using the organic film 93 as a mask. The following shows the process conditions during the etching of the silicon oxide film 92.

[0094] <Process conditions during the etching of the silicon oxide film 92>

[0095] Pressure 25 mT (3.33 Pa)

[0096] HF power / LF power 0 W / 800 W

[0097] Gas type CF4, H2

[0098] Wafer temperature -45 °C

[0099] The etching of the silicon oxide film 92 does not necessarily have to be carried out at extremely low temperatures and can also be carried out at room temperature. However, by creating an extremely low temperature environment, it is possible to obtain the protective effect generated by the reaction products produced during etching adhering to the inner wall of the etched silicon oxide film 92, and the etching on the sidewalls of the silicon oxide film 92 can be suppressed. Therefore, the wafer temperature is preferably controlled to be extremely low. It is easy to maintain the etching shape of the silicon oxide film 92 in a vertical shape. Therefore, the effect of shrinkage of the etching shape can be obtained, and thus, it is preferably carried out at an extremely low temperature. It should be noted that the gas type during the etching of the silicon oxide film 92 is not limited to this, and a mixed gas of C4F6 gas, O2 gas, and Ar gas, a mixed gas of C4F8 gas, O2 gas, and Ar gas, etc. can be used.

[0100] Based on the above process conditions, an example of the result of etching in the order of the silicon-containing antireflection film 94 → organic film 93 → silicon oxide film 92 is shown in Figure 2 of (b). Figure 2 The horizontal axis of (b) in shows the wafer temperature during the etching of the silicon-containing antireflection film 94 and the organic film 93. Figure 2 The vertical axis of (b) in shows the CD (hereinafter also referred to as "TOP CD") value of the amplitude of the opening at the upper end of the silicon oxide film 92 shown within the frame after the silicon oxide film 92 is etched until the silicon nitride film 91 is exposed and then the organic film 93 is further removed by ashing (refer to Figure 2 of (a)).

[0101] Figure 2 A shown in (b) represents the TOP CD value when only CF4 gas is supplied and H2 gas is not added during the etching process of the silicon-containing antireflection film 94. B represents the TOP CD value when H2 gas is added to the CF4 gas at a ratio of CF4:H2 = 25:3 during the etching of the silicon-containing antireflection film 94. C represents the TOP CD value when H2 gas is added to the CF4 gas at a ratio of CF4:H2 = 25:6 during the etching of the silicon-containing antireflection film 94.

[0102] According to Figure 2 the result shown in (b), in the region below -30°C (hereinafter also referred to as the "extremely low temperature region") within the frame S indicated by the dashed line, the CD value becomes approximately 13 nm or less, and the TOP CD value shrinks compared to when etching is performed at room temperature. Specifically, as Figure 2 shown in (a), the width of the second opening 96 of the photoresist film 95, i.e., the CD value, is 28 nm, while the TOP CD value becomes 13.5 nm or less in the case where H2 is not added to CF4 as shown by A. That is, in the etching process of the silicon-containing antireflection film 94, by supplying a gas containing CF4 gas (hereinafter also referred to as the "first processing gas") in the extremely low temperature region, the TOP CD value can be shrunk.

[0103] Furthermore, in the case of adding H2 to CF4 as shown by B, the TOP CD value becomes less than 10 nm in the extremely low temperature region. From the above, it can be seen that compared with the case where H2 is not added to CF4 in the etching process of the silicon-containing antireflection film 94, the TOP CD value can be significantly shrunk when H2 is added to CF4.

[0104] Thus, from Figure 3 the initial state in (a) to Figure 3 the process of etching the silicon-containing antireflection film 94 shown in (b), the plasma of the first processing gas containing CF4 gas is used to control the wafer temperature to -30°C or less. Then, the silicon-containing antireflection film 94 is etched through the second opening 96.

[0105] Thus, as Figure 3As shown in (b) thereof, the cross-section of the silicon-containing antireflection film 94 is formed in a tapered shape such that as etching progresses, the CD value of the first opening 97 formed in the silicon-containing antireflection film 94 decreases. That is, the cross-section of the silicon-containing antireflection film 94 is formed in a tapered shape so that the size of the first opening 97 of the silicon-containing antireflection film 94 on the side opposite to the photoresist film 95 becomes smaller than the size of the first opening 97 on the photoresist film 95 side. Thereby, the TOP CD value in the etching of the silicon oxide film 92 can be shrunk to less than half of the CD value of the second opening 26 of the photoresist film 95, and a small contact can be formed in the shrunk concave portion. Further, the first processing gas is supplied containing H2 gas, so that compared with the case where H2 is not added to CF4, the inclination of the cross-section of the first opening 97 of the silicon-containing antireflection film 94 can be further increased, and the effect of shrinking the TOP CD value can be further improved.

[0106] In addition, in the case where H2 is not added to CF4 during the etching of the silicon-containing antireflection film 94 and in the case where H2 is added to CF4 at a ratio of CF4:H2 = 25:3, as shown in Figure 3 (c) thereof, the first opening 97 of the silicon-containing antireflection film 94 is not blocked. Further, through the opening 98 formed in the organic film 93, in the process of etching the silicon oxide film 92 shown in Figure 3 (d) thereof, the silicon oxide film 92 can be etched until the silicon nitride film 91 is exposed without blocking the front surface of the opening 98. However, in the case where H2 is added to CF4 at a ratio of CF4:H2 = 25:6, the CD value changes significantly in the direction of decreasing in an extremely low temperature environment, and an opening is not formed at the upper end of the silicon oxide film 92. Therefore, Figure 2 the CD value in the extremely low temperature environment cannot be shown in (b) thereof.

[0107] Figure 4 It is a diagram showing a comparison of an example of the result of an etching process of one embodiment with a comparative example. Figure 4 (a) shows an example of an upper surface view of the hole 99 formed in the silicon oxide film 92 after performing each etching process of the present embodiment of the stacked structure 1 and removing the organic film 93 shown in Figure 3 (d) thereof by ashing. Figure 4 (b) shows an example of an upper surface view of the hole 109 formed in the silicon oxide film 92 by performing each etching process of the comparative example of the stacked structure 1.

[0108] In the etching process of the silicon-containing antireflection film 94 of the stacked structure 1 of the comparative example, the wafer temperature was controlled to -45°C, 0°C, and 30°C, respectively, and CHF3 gas and CF4 gas were supplied. At this point, it is different from the present embodiment in which CF4 gas or a mixture of CF4 gas and H2 gas is supplied. The process conditions in the etching processes of the organic film 93 and the silicon oxide film 92 are the same as those in the corresponding etching processes of the organic film 93 and the silicon oxide film 92 of the present embodiment.

[0109] The etching process of the comparative example was performed. As a result, when the wafer temperature was 0°C and 30°C, although the TOP CD value of the silicon oxide film 92 could be shrunk to about 10 nm, the openings of the holes 109 were not regularly arranged, and it was found that some of the holes 109 could not be formed in the shape of the silicon oxide film 92 (blind holes). That is, it means that the silicon oxide film 92 on the resist mask 95 was not etched into the same pattern as the patterned second opening. It is considered that this is because a part of the mask was blocked by the reaction products generated during the etching of the silicon-containing antireflection film 94. In addition, when the wafer temperature was -45°C, the amount of reaction products generated during etching further increased, resulting in a state where the holes 109 that should have been formed on the silicon oxide film 92 were completely absent.

[0110] On the other hand, when the etching process of the present embodiment was performed, as a result, when the wafer temperature was 0°C and 30°C, the openings of the holes 99 were regularly arranged and no blind holes were observed. However, even when H2 gas was added to CF4 gas, the TOP CD value did not become less than 10 nm, and there was a limit to the shrinkage amount. On the other hand, when the wafer temperature was -45°C, blind holes of the holes 99 could be avoided, the TOP CD value of the silicon oxide film 92 could be made smaller than 10 nm, and the silicon oxide film 92 could be etched into the same pattern as the patterned second opening on the resist mask 95.

[0111] From the above, in order to shrink the silicon-containing antireflection film 94 without blocking the second opening 96 of the photoresist film 95, in the process of etching the silicon-containing antireflection film 94, the wafer temperature must be controlled to an extremely low temperature of -30°C or lower. On the other hand, in the process of etching the organic film 93 and the process of etching the silicon oxide film 92, it is not necessary to make the wafer temperature an extremely low temperature. It can be an extremely low temperature of -30°C or lower, or it can be higher than -30°C. However, as described above, in the process of etching the organic film 93 and the process of etching the silicon oxide film 92, it is also preferable to control the wafer temperature to an extremely low temperature.

[0112] [Addition amount of H2]

[0113] Next, the addition amount of H2 gas will be described with reference to Figure 5 while. Figure 5A graph showing the relationship between the addition amount of H2 and the blocking of the front side of the opening in the etching process of an embodiment. Figure 5 The horizontal axis represents the wafer temperature, Figure 5 The vertical axis represents the flow ratio of H2 gas to the total flow of CF4 gas and H2 gas in the etching process of the silicon-containing antireflection film 94.

[0114] Figure 5 E represents the case of no CD shrinkage and blind holes, that is, it represents the state in which the holes 99 with the shrunk CD in the silicon oxide film 92 are regularly arranged. On the other hand, Figure 5 F represents the case of CD shrinkage and blind holes, that is, in the silicon oxide film 92, there are holes 99 with shrunk CD and they are not regularly arranged, there is a part where one or more holes 99 are not formed, or the state where holes 99 are not formed on the entire surface.

[0115] According to Figure 5 the results shown, when the flow ratio of H2 gas to the total flow of CF4 gas and H2 gas (the total flow of the first processing gas), that is, the partial pressure ratio of H2 gas, is set as y (%), and the wafer temperature is set as x, the first processing gas contains H2 gas with a flow rate that satisfies the following relational expression (1). 0 ≤ y ≤ 0.0078 × x 2 -0.3938 × x + 11.877 ··· (1)

[0116] Thus, by gradually adding H2 gas to the first processing gas, the effect of CD shrinkage can be assisted, and no part or the entire surface where no formation occurs is generated in the silicon oxide film 92, and regularly arranged holes 99 identical to the second opening patterned on the resist mask 95 can be formed.

[0117] [Gas and deposition state]

[0118] Next, regarding the relationship between the types of gases used in the etching process of an embodiment and the deposition state of deposits in the etching process, with reference to Figure 6 and Figure 7 it will be described. Figure 6 A graph schematically showing the relationship between the types of gases used in the etching process of an embodiment and the deposition state of deposits. Figure 7 A graph for explaining the surface reaction in the etching process of an embodiment.

[0119] First, if referring to Figure 6 , for the case of CF4 gas in the upper section and the case of CHF3 gas in the lower section, the deposition state of reaction products generated by etching is shown by distinguishing between the extremely low temperature of -45 °C and the normal temperature of 0 °C.

[0120] Generally, starting from the one with lower stacking property as CH x F y gas, it is considered that CF4 < CHF3 < CH2F2 < CH3F. What determines this sequence is the dissociation mode of each molecule and the attachment coefficient of the radicals generated by dissociation to the target film.

[0121] As an example, the energy required to generate CF x radicals by dissociation of CF4 gas and CHF3 gas is as described below.

[0122] When generating CF radicals, CF2 radicals, and CF3 radicals from CF4 gas, 22 eV, 19 eV, and 14.6 eV are required respectively. On the other hand, when generating CF radicals, CF2 radicals, and CF3 radicals from CHF3 gas, 17 eV, 14 eV, and 13.8 eV are required respectively. That is, it can be seen that under the condition of applying the same HF power and LF power, when using CF4 gas, the ratio of CF radicals in the generated radicals becomes smaller.

[0123] Therefore, compared with the case of using CF4 gas, when using CHF3 gas, the ratio of CF radicals becomes higher. The attachment probability of CF radicals is more than one order of magnitude larger than that of CF2 radicals and CF3 radicals. Therefore, as Figure 6 shown in the lower part below, when using CHF3 gas at room temperature, the deposit 110 is also likely to attach to the upper part of the film. In the extremely low temperature region, the amount of reaction products further increases. Therefore, the amount of the deposit 110 on the upper part of the film increases, and the risk of blocking occurs. On the contrary, compared with the case of using CHF3 gas, when using CF4 gas, the ratio of CF radicals becomes lower. Therefore, the deposit 110 is not likely to attach to the upper part of the film, and it is not easy to generate blocking.

[0124] From the above, the attachment coefficient of CF4 gas is small. When using CF4 gas at room temperature, only radicals that are not conducive to stacking are generated in the plasma. Therefore, as Figure 6 shown in the upper part above, when using CF4 gas at room temperature, the reaction products hardly attach to the film. On the other hand, when using CF4 gas at an extremely low temperature of -45 °C, the reaction products barely start to stack, and the deposit 110 stacks conformally and thinly on the inner wall of the second opening 96 and the upper part of the film. At this time, a gas with a small attachment coefficient such as CF4 gas is less likely to attach to the upper part of the film and is more likely to attach to the bottom. Therefore, it is not easy to generate blocking.

[0125] Thus, for a single gas of CF4 gas, the stacking property of the reaction product is small. Therefore, in the etching of the silicon-containing antireflection film 94 of the present embodiment, it is preferable to add H2 gas to the CF4 gas to improve the stacking property. As a result, the gas properties are close to those of CHF3 gas. As a result, Figure 6 Similar to the case of etching with CHF3 gas shown in the lower part of

[0126] However, when the amount of H2 gas added in the extremely low temperature region becomes excessive, as shown in Figure 5 , a state where CD shrinkage NG occurs ( Figure 5 F), that is, the risk of obstruction becomes high. As a result, as shown in the shape of the deposit 110 in the extremely low temperature column in the lower part of Figure 6 , the risk of pore blockage becomes high.

[0127] Next, the deposit 110 deposited on the side wall of the silicon-containing antireflection film 94 will be described with reference to Figure 7 . Figure 7 The side surface of the silicon-containing antireflection film 94 shown in Figure 7 becomes tapered due to the deposition of deposits 110 such as reaction products generated during etching. More specifically, the deposit 110 shown in Figure 7 contains: reaction products generated during etching and free radicals contained in the plasma. The accumulation of these two substances can promote the tapered etching of the side wall of the silicon-containing antireflection film 94 into a tapered shape. However, tapered etching is promoted when the deposit 110 accumulates on the silicon-containing antireflection film 94, and is not promoted when it volatilizes. Moreover, whether the deposit 110 accumulates on the silicon-containing antireflection film 94 or volatilizes is determined by the vapor pressure curve of each gas type that is favorable for etching and depends on the temperature.

[0128] When generating plasma from the first processing gas containing CF4 gas, CF2 * (radical), CF2 + (ion) in the plasma can promote the etching of the silicon-containing antireflection film 94. The chemical reaction formula at this time is as follows.

[0129] SiO2 + 2×CF2 → SiF4 + 2CO

[0130] SiO-R + CF2 → SiFx-R + CO

[0131] Here, SiO-R is an example of a silicon-containing film containing an organic substance, and SiFx-R is an example of a reaction product when etching a silicon-containing film containing an organic substance.

[0132] As a result of the above chemical reaction, the reaction product SiFx-R adheres to the sidewalls to form a deposit 110. According to the vapor pressure curve, Figure 7 as shown on the right of Figure 7 , SiFx-R volatilizes at normal temperature, or Figure 7 as shown on the left of Figure 7 , SiFx-R accumulates at extremely low temperatures. SiF4 and CO volatilize at both normal temperature and extremely low temperatures.

[0133] From the above, when etching the silicon-containing antireflection film 94 by supplying the first processing gas containing CF4 gas, in order to form the silicon-containing antireflection film 94 into a tapered shape, an extremely low temperature of -30°C or lower is required. Thus, the deposit 110 can be accumulated on the sidewalls of the silicon-containing film.

[0134] As described above, in the process of etching the silicon-containing antireflection film 94, as the first processing gas to be supplied, a CF4 gas or a mixed gas of CF4 gas and H2 gas is exemplified for description. However, the first processing gas is not limited to this, and any gas containing a fluorocarbon gas is acceptable. Further, the first processing gas preferably contains a fluorocarbon gas and hydrogen gas.

[0135] The fluorocarbon gas can be a C x F y gas that satisfies y / x > 3. In addition, the fluorocarbon gas is preferably a gas in which the production amount of CF2 as a precursor becomes larger than the production amounts of other precursors when dissociated by plasma. The fluorocarbon gas can be any one of C2F4 gas, C3F4 gas, and C2F6 gas, or can also be CF4 gas.

[0136] In addition, in the present embodiment, as an example of the first film that is a silicon-containing film, the silicon-containing antireflection film 94 is exemplified, but it is not limited thereto. The first film can further contain an organic substance, or can be an organic silicon oxide film.

[0137] [Etching Process]

[0138] Regarding the substrate processing method including the etching process of the present embodiment described above, it will be described while referring to Figure 8 and Figure 8 FIG. is a flowchart showing an example of a substrate processing method including an etching process of an embodiment. This processing is controlled by the control unit 80.

[0139] First, the control unit 80 prepares a wafer W in which a silicon oxide film 92 as an example of an etching target film (fourth film), an organic film 93 as an example of a third film, a silicon-containing film 94 as an example of a first film, and a photoresist film 95 as an example of a second film are stacked in order from below. That is, the above wafer W is carried into the processing container 10 and adsorbed and held by the electrostatic chuck 20 for preparation (step S1). The second film (photoresist film 95), the first film (silicon-containing film 94), and the first film (organic film 93) function as masks.

[0140] Next, the control unit 80 sets the wafer temperature to -30°C or lower (step S2). The wafer temperature is as follows: The temperature of the cooling medium flowing in the flow path 18f is controlled from the cooling unit via the piping 22a and 22b shown, and set to a specified temperature of -30°C or lower. Figure 1 Next, the control unit 80 supplies a mixed gas of CF4 gas and H2 gas into the processing container 10 (step S3). The flow rate of the H2 gas is determined by Equation (1). Next, the control unit 80 applies HF power and LF power to the lower electrode 18, and etches the first film through the second opening 96 of the second film using the plasma generated by the plasma generation unit (step S4). In the present embodiment, the silicon-containing film 94 is etched into a tapered shape through the second opening 96 of the photoresist film 95.

[0141] Next, after the control unit 80 finishes etching the first film, it supplies a mixed gas of N2 gas and H2 gas into the processing container 10 (step S5).

[0142] Next, the control unit 80 applies HF power and LF power to the lower electrode 18, and etches the third film through the first opening 97 formed in the first film using the plasma generated by the plasma generation unit (step S6). In the present embodiment, the organic film 93 is etched through the first opening 97 formed in the silicon-containing film 94.

[0143] Next, after the control unit 80 finishes etching the first film, it supplies a mixed gas of CF4 gas and H2 gas into the processing container 10 (step S7). Then, it applies HF power and LF power to the lower electrode 18, and etches the fourth film through the opening 98 formed in the third film using the plasma generated by the plasma generation unit (step S8). In the present embodiment, the silicon oxide film 92 serving as the base film is etched through the opening 98 formed in the organic film 93.

[0144] Next, the control unit 80 ashes the third film (step S9). As a result, the organic film 93 that functions as a mask when etching the silicon oxide film 92 is removed. Next, a metal is buried in the hole formed in the silicon oxide film 92 (step S10). As a result, a metal is buried in the hole with the CD value shrunk through the first opening 97 of the silicon-containing film 94, so that a small contact with a CD value of less than 10 nm, for example, about 6 nm can be formed.

[0145] [Etching a wafer having a stacked structure 2]

[0146] Next, for an example in which the substrate processing method including the etching process of the present embodiment is used for the wafer W having the stacked structure 2, while referring to

[0147] Next, for an example in which the substrate processing method including the etching process of the present embodiment is used for the wafer W having the stacked structure 2, while referring toFigure 9 will be described below. Figure 9 FIG. is a diagram showing the etching processes of the respective layers of the stacked structure 2 of one embodiment in sequence.

[0148] For the wafer W having the stacked structure 2, the etching process of this embodiment is performed Figure 9 (b) to Figure 9 (f). After that, a process of burying a metal wiring in the holes shrunk by the above etching process is performed. The state of the result of all the processes of the substrate processing method including the etching process of this embodiment is shown in Figure 9 (g).

[0149] For Figure 9 (b) to Figure 9 (f), the etching processes will be specifically described. As shown in Figure 9 (b), an impurity layer 101 doped with impurities is formed on the silicon substrate 100 of the stacked structure 2, and a gate 102 is formed adjacent to the impurity layer 101. A silicon nitride film 103 that functions as a protective film is coated on the impurity layer 101 and the gate 102. On the upper part of the silicon nitride film 103, a silicon oxide film 104b and a silicon oxide film 104a are formed with the silicon nitride film 107 of the intermediate layer sandwiched therebetween. A mask layer 106 is formed on the silicon oxide film 104a. A second opening 105 is formed on the uppermost layer of the mask layer 106.

[0150] Figure 9 In the initial state of the stacked structure 2 shown in (b), the silicon nitride film 107 is an example of the first film that is a silicon-containing film. The silicon oxide film 104a and the mask layer 106 are examples of the second film formed on the first film and having the second opening 105. The silicon oxide film 104b under the silicon nitride film 107 is an example of the third film formed under the first film.

[0151] In the case of the stacked structure 2, Figure 8 at the start of the substrate processing method of one embodiment shown, the control unit 80 prepares a wafer W having the first to third films of the stacked structure 2. Next, as shown in Figure 9 (c) and (d), the control unit 80 supplies a mixed gas of N2 gas and H2 gas, etches the mask layer 106 through the second opening 105, and then supplies a mixed gas of CF4 gas and H2 gas to etch the silicon oxide film 104a. After that, the silicon nitride film 107 is etched into a tapered shape.

[0152] In the process of etching the silicon nitride film 107 into a tapered shape, the control unit 80 sets the temperature of the wafer to -20°C or lower. Next, the control unit 80 supplies a mixed gas of CF4 gas and H2 gas into the processing container 10. Next, the control unit 80 applies HF power and LF power to the lower electrode 18.

[0153] Next, the control unit 80 etches the silicon nitride film 107 through the plasma generated by the plasma generation unit. In this etching process, through the chemical reaction of SiN (silicon nitride film 107) with the supplied CF4 gas and H2 gas, the reaction product of ammonium fluorosilicate ((NH4)2SiF6) becomes the deposit 110, forming a tapered etching. In this way, the silicon nitride film 107 is formed at the portion where tapered etching is to be performed, and the CD value shrinks.

[0154] Next, as Figure 9 shown in (e), the control unit 80 supplies a mixed gas of CF4 gas and H2 gas, and etches the silicon oxide film 104b through the tapered first opening formed in the silicon nitride film 107 until the silicon nitride film 103 is exposed. At this time, it is preferable to control the wafer temperature to -30°C or lower. Thus, in a state where the wafer is cooled to -30°C or lower, etching is performed through the plasma of CF4 gas and H2 gas, so that vertical etching can be performed on the hole. Thereby, a distance of a specified value or more can be maintained between the gate 102 and the hole. It should be noted that the supplied CF4 gas and H2 gas are an example of the second processing gas. As other examples of the second processing gas, a mixed gas of C4F8 gas, O2 gas, and Ar, a mixed gas of C4F6 gas, O2 gas, and Ar, etc. can also be used. Next, the control unit 80 supplies a mixed gas of CH2F2 gas, O2 gas, and Ar, and etches the silicon nitride film 103 until the impurity layer 101 is exposed.

[0155] Next, as Figure 9 shown in (f), the control unit 80 supplies a mixed gas of O2 gas or N2 gas and H2 gas, and removes the mask layer 106 through ashing. Next, as Figure 9 shown in (g), the control unit 80 buries metal in the etched hole to form the wiring layer 111. It should be noted that the process of removing the mask layer 106 can be the same device as the etching, can also be a different device, can also be performed through a high-temperature plasma ashing device as another device, and can also be peeled off and removed through wet cleaning.

[0156] As Figure 9 shown in (a), for the CD value of the hole formed by performing the etching process of this embodiment, the CD value CD2 at the lower part of the hole becomes smaller than the CD value CD1 at the upper part of the hole, and the hole shrinks during the etching process. Thereby, the distance Q between the gate 102 and the hole can be ensured.

[0157] According to the substrate processing method including the etching process described above, the CD value at the upper end of the etched hole is larger than the CD value of the hole near the gate 102. It should be noted that the CD value at the upper end of the hole is limited by the adjacent wiring.

[0158] For example, by performing etching of the silicon oxide films 104a and 104b under the same process conditions as those in the etching of the silicon nitride film 107, tapered etching is performed. Thus, as shown in Figure 9 (a), the tapered portion of the hole expands, and sometimes the distance between the gate 102 and the hole cannot be ensured.

[0159] Therefore, in the etching process of the present embodiment, at an extremely low temperature of -20°C or lower, using a plasma containing hydrogen and fluorine, only the silicon nitride film 107 as the intermediate layer is tapered-etched. As a result, ammonium fluorosilicate is generated during the etching of the silicon nitride film 107, adheres to the surface of the silicon nitride film 107, and forms a deposit 110. As a result, the silicon nitride film 107 is etched into a tapered shape. The process conditions are changed so that the subsequent etching becomes a vertical shape.

[0160] In this way, using the silicon nitride film 107 as the intermediate layer, ammonium fluorosilicate is deposited on the silicon nitride film 107 to form tapered etching. Thus, as shown in Figure 9 (g), the distance Q between the gate 102 and the hole can be separated by a specified value or more.

[0161] It should be noted that a silicon nitride film is used as the intermediate layer of the stacked structure 2, but it is not limited thereto as long as ammonium fluorosilicate is generated during etching. For example, a silicon oxynitride film such as SiON, etc., as long as it is a silicon film containing nitrogen, the same effect can be expected.

[0162] [Etching a wafer having a stacked structure 3]

[0163] Next, an example in which the substrate processing method including the etching process of the present embodiment is applied to a wafer W having a stacked structure 3 will be described with reference to Figure 10 while being described. Figure 10 FIG. is a diagram showing the etching process of each layer of the stacked structure 3 of an embodiment in sequence.

[0164] As shown in Figure 10 (a) of, the stacked structure 3 is as follows: A gate 120 and a silicon nitride film 121 as a protective film surrounding the gate 120 are formed at the bottom of the Low-k film 122. The Low-k film 122 is the same film, and for the sake of convenience of explanation, it is divided into three layers, namely Low-k films 122a, 122b, and 122c, for description. The Low-k film 122b is an example of the first film to be tapered-etched. The Low-k film 122a is an example of the second film having a second opening 124. The Low-k film 122c is an example of the third film that becomes the base film of the first film. A mask 123 is formed on the upper part of the Low-k film 122a.

[0165] In the stacked structure 3, the control unit 80 supplies a mixed gas of C4F8 gas, Ar gas, and N2 gas to etch the Low-k film 122a. Next, when the control unit 80 only performs the etching process of the Low-k film 122b, it supplies CF4 gas and H2 gas, sets the wafer temperature to an extremely low temperature of -30°C or lower, and applies HF power and LF power for etching. As a result, the Low-k film 122b is etched into a tapered shape, and as shown in (b) of Figure 10 , during etching, the deposit 110 accumulates, and the CD value of the lower end (bottom) of the Low-k film 122b can be reduced relative to the CD value of the upper end of the Low-k film 122b. Next, the control unit 80 supplies the mixed gas of C4F8 gas, Ar gas, and N2 gas again to etch the Low-k film 122c. As a result, the Low-k film 122c is etched vertically, and as shown in (c) of Figure 10 , the distance P between the gate 120 and the hole can be separated by a specified amount or more. It should be noted that the mixed gas of C4F8 gas, Ar gas, and N2 gas supplied during the etching of the Low-k film 122c is an example of the second processing gas.

[0166] As described above, according to the etching processing method of the present embodiment, in the stacked structures 1 to 3, the CD value of the opening can be reduced without blocking the opening of the film formed by etching.

[0167] It should be noted that the first film for performing the tapered etching can be a low dielectric constant film such as the Low-k film 122 of Figure 10 as an example, or it can also be an anti-reflection film such as the silicon-containing anti-reflection film 94 of Figure 2 and Figure 3 . In addition, the first film can contain nitrogen as in the case of the silicon nitride film 107 of Figure 9 as an example. The first film can be a silicon nitride film or a silicon oxynitride film.

[0168] When etching the first film, the wafer temperature when set to an extremely low temperature only needs to be -30°C or lower. The lower limit is not particularly limited. For example, due to device configuration limitations, it can be -60°C or higher.

[0169] After the first film etching process, in the process of etching the third film formed under the first film through the first opening formed in the first film, it is preferable to control the wafer temperature to -30°C or lower, but it is not limited thereto.

[0170] The process of etching the third film can use the plasma of the second processing gas to etch the third film through the first opening.

[0171] The process of etching the third film can be the same as or different from the wafer temperature (the first temperature) set in the process of etching the first film.

[0172] It should be noted that the V DC (self-bias voltage) is, for example, 2000 V from the viewpoint of controllability.

[0173] The substrate processing method and the substrate processing apparatus of an embodiment disclosed herein are examples in all aspects and should be considered not to be limiting. The above-described embodiment can be deformed and improved in various ways without departing from the appended claims and their gist. The matters described in the above-described multiple embodiments can also take other configurations within a non-contradictory range, and can be combined within a non-contradictory range.

[0174] The substrate processing apparatus of the present disclosure can be used in any type of apparatus such as an atomic layer deposition (ALD) apparatus, a capacitively coupled plasma (CCP), an inductively coupled plasma (ICP), a radial line slot antenna (RLSA), an electron cyclotron resonance plasma (ECR), and a helicon wave plasma (HWP).

Claims

1. A substrate processing method, comprising the following steps: A step of preparing a substrate, the substrate having a first film which is a silicon-containing antireflection film, a second film formed on the first film and having a second opening, and a third film formed under the first film, the second film being a photoresist film, and the third film being a spin-on carbon film or an amorphous carbon; A control step of controlling the temperature of the substrate to -30° or lower; A step of etching the first film, etching the first film through the second opening to form a first opening in the first film; and A step of etching the third film after the step of etching the first film, etching the third film through the first opening, In the step of etching the first film, Using a plasma of a first processing gas containing a fluorocarbon gas, and forming the first film into a tapered shape in such a manner that as etching progresses, the shape of the cross-section of the first opening formed in the first film becomes smaller.

2. The substrate processing method according to claim 1, wherein, The first processing gas contains H2 gas.

3. The substrate processing method according to claim 2, wherein, When the temperature of the substrate is set to x (°C) and the partial pressure ratio of the H2 gas to the total flow rate of the first processing gas is set to y (%), The first process gas contains H2 gas with a flow rate satisfying the condition of 0 ≤ y ≤ 0.0078×x 2 - 0.3938×x + 11.

877.

4. The substrate processing method according to any one of claims 1 to 3, wherein, The fluorocarbon gas is a C x F y gas that satisfies y / x > 3.

5. The substrate processing method according to claim 4, wherein, The fluorocarbon gas is CF4 gas.

6. The substrate processing method according to any one of claims 1 to 3, wherein, The fluorocarbon gas is a gas in which the production amount of CF2 as a precursor becomes larger than the production amounts of other precursors when dissociated by plasma.

7. The substrate processing method according to claim 6, wherein, The fluorocarbon gas is any one of C2F4 gas, C3F4 gas, and C2F6 gas.

8. The substrate processing method according to any one of claims 1 to 3, wherein, The first film contains an organic substance.

9. The substrate processing method according to claim 8, wherein, The first film is an organic-containing silicon oxide film.

10. The substrate processing method according to any one of claims 1 to 3, wherein, The first film is a low dielectric constant film.

11. The substrate processing method according to any one of claims 1 to 3, wherein, The first film contains nitrogen.

12. The substrate processing method according to any one of claims 1 to 3, wherein, The first film is a silicon nitride film or a silicon oxynitride film.

13. The substrate processing method according to claim 1, wherein, The step of etching the third film includes: a step of controlling the temperature of the substrate to -30 °C or lower.

14. The substrate processing method according to claim 1 or 13, wherein, In the step of etching the third film, the third film is etched through the first opening using the plasma of the second processing gas.

15. A substrate processing apparatus, comprising: a plasma generation unit that generates plasma in a processing container; and a control unit, The substrate processing apparatus etches a substrate having a first film that is a silicon-containing film and a second film that is formed on the first film and has a second opening, The control unit controls the following processes: A process of preparing a substrate having a first film that is a silicon-containing antireflection film, a second film that is formed on the first film and has a second opening, and a third film that is formed under the first film, wherein the second film is a photoresist film and the third film is a spin-on carbon film or an amorphous carbon; A control process of controlling the temperature of the substrate to -30° or lower; and, A process of etching the first film, etching the first film through the second opening to form a first opening in the first film; and A process of etching the third film after the process of etching the first film, etching the third film through the first opening, In the process of etching the first film, Using plasma of a first processing gas containing a fluorocarbon gas, the first film is formed into a tapered shape in such a manner that as etching progresses, the shape of the cross-section of the first opening formed in the first film becomes smaller.

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