Semiconductor integrated circuit

Abstract

A semiconductor integrated circuit capable of improving ESD resistance while suppressing an increase in chip area in an HVIC in which a part of an HVJT is used as a level shift element. A semiconductor integrated circuit is a semiconductor integrated circuit in which a high-potential side circuit region (101), a high breakdown junction terminal structure (102) surrounding the high-potential side circuit region (101), and a low-potential side circuit region (103) surrounding the high-potential side circuit region (101) across the high breakdown junction terminal structure (102) are integrated in the same semiconductor chip, wherein a first distance (L11) between a ring-shaped well region (5) at a region where a first contact region (11) is formed and a buried layer (13) is shorter than a second distance (L12) between the ring-shaped well region (5) at a region where a carrier receiving region (7a, 7b) is formed and a buried layer (6), the carrier receiving region (7a, 7b) being a carrier receiving region of a level shift element (10a, 10b) included in a level shift circuit that transmits a signal between the low-potential side circuit region (103) and the high-potential side circuit region (101).

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit for power applications. Background Technology

[0002] Primarily used in low-capacitance inverters, high-voltage integrated circuits (HVICs) are employed to drive and control power switching elements that constitute power conversion bridge circuits. The HVIC outputs drive signals from its output terminals to turn the gates of the power switching elements on and off based on input signals from its input terminals. For example, in a power conversion bridge circuit, the power switching elements on the high-potential side and the low-potential side, receiving drive signals from the HVIC, operate separately, thereby performing power conversion.

[0003] In HVIC, a high-voltage junction termination (HVJT) structure electrically separates the high-potential side circuit region (high-side circuit region) from the low-potential side circuit region (low-side circuit region). Additionally, a level shifter is provided to facilitate signal transmission between the high-side and low-side circuit regions.

[0004] Regarding the structure of HVJTs and level shifters, a known configuration uses a portion of the HVJT as the level shifter. This configuration eliminates the need for high-potential wiring across the HVJT, thus offering high reliability. Furthermore, compared to configurations where the HVJT and level shifter are formed independently, the chip size can be reduced by minimizing the area of ​​the level shifter. To implement this configuration, the internal circuitry of the high-side circuitry region needs to be electrically separated from the level shifter.

[0005] In patent document 1 Figure 4 The document describes a structure in which a p-type slit region is used to separate the level shifter from the high-side circuit region, thereby electrically isolating the internal circuitry of the high-side circuit region from the level shifter. Furthermore, in Patent Document 1… Figure 2 The document describes the following structure: the four sides of the high-side circuit area are surrounded by a p-type separation region, thereby electrically separating the internal circuit of the high-side circuit area from the level shifter.

[0006] In patent document 2 Figure 3 The following structure is described: a p-type slit region surrounds three sides of the high-side circuit region, thereby electrically separating the internal circuitry of the high-side circuit region from the level shifter. One side of the high-side circuit region without a p-type slit region is fixed as the highest potential of the high-side circuit region, and the parasitic resistance between this highest potential and the drain of the high-voltage n-type MOSFET constituting the level shifter is used as the level shifting resistor.

[0007] In patent document 3 Figure 4The document describes the following construction: a portion of the HVJT is separated by a trench, thereby electrically separating the internal circuitry of the high-side circuitry region from the level shifter.

[0008] In patent documents 1-3, the lengths of the drift regions (drift lengths) and the break-off voltages are made consistent in both the HVJT and the level shifter. If the break-off voltages are equal, then in the event of an electrostatic discharge (ESD) surge or similar event at the high-potential power terminal, both the HVJT and the level shifter simultaneously enter an avalanche state, resulting in a roughly uniform avalanche current flow in both. Therefore, localized current concentrations are less likely to occur. However, in high-voltage n-type MOSFETs and other level shifters, parasitic npn bipolar transistors are turned on due to the avalanche current, triggering parasitic operation, making them more susceptible to damage compared to HVJTs, which function as pn junction diodes. Furthermore, there are methods to limit the avalanche current flowing to the level shifter by adjusting the level shift resistor, thereby eliminating imbalances in its damage tolerance. However, in this case, the level shift resistor needs to be significantly larger than required, thus imposing design limitations.

[0009] In addition, in patent document 4 Figure 6 The document describes a configuration where the drift length of the level shifter is longer than that of the HVJT, thereby increasing the ESD tolerance of the level shifter. In this configuration, the drift region of the level shifter protrudes towards the high-side circuit region, thus reducing the effective placement area of ​​the high-side circuit. Conversely, in patent document 4, for example... Figure 7 As shown, when the configuration is such that the drift region of the level shifter protrudes to the outer periphery of the ground (GND) region, the chip area increases.

[0010] Existing technical documents

[0011] Patent documents

[0012] Patent Document 1: Japanese Patent Application Publication No. 9-283716

[0013] Patent Document 2: Japanese Patent Application Publication No. 2015-173255

[0014] Patent Document 3: Japanese Patent Application Publication No. 2005-123512

[0015] Patent Document 4: International Publication No. 2017 / 086069 Summary of the Invention

[0016] The problem the invention aims to solve

[0017] In view of the above problems, the object of the present invention is to provide a semiconductor integrated circuit that can improve ESD tolerance while suppressing the increase of chip area in an HVIC in which a portion of the HVJT is used as a level shifter.

[0018] Solution for solving the problem

[0019] One aspect of the present invention is a semiconductor integrated circuit, which integrates a high-potential side circuit region, a high-voltage junction termination structure surrounding the high-potential side circuit region, and a low-potential side circuit region surrounding the high-potential side circuit region via the high-voltage junction termination structure on the same semiconductor chip. The semiconductor integrated circuit aims to include: (a) a central well region of a first conductivity type disposed in the high-potential side circuit region; (b) a buried layer of the first conductivity type buried at the lower end of the central well region; (c) an annular drift region of the first conductivity type disposed around the high-voltage junction termination structure surrounding the central well region; (d) an annular well region of a second conductivity type surrounding the drift region; and (e) a carrier for the first conductivity type. (f) A carrier receiving region of a first conductivity type, disposed in the annular well region, is a carrier supply region for a level shifting element included in a level shifting circuit that transmits signals between a low-potential side circuit region and a high-potential side circuit region; (g) A carrier receiving region of a first conductivity type, disposed in the drift region or the central well region, having a higher impurity concentration than the drift region or the central well region, is a carrier receiving region for a level shifting element; and (g) A first contact region of a first conductivity type, disposed separately from the carrier receiving region in the drift region or the central well region, having a higher impurity concentration than the drift region or the central well region, wherein the minimum of the first distances between the annular well region and the embedded layer at the region forming the first contact region is shorter than the minimum of the second distances between the annular well region and the embedded layer at the region forming the carrier receiving region.

[0020] Another aspect of the present invention is a semiconductor integrated circuit, which is a semiconductor integrated circuit in which a high-potential side circuit region, a high-voltage junction termination structure surrounding the high-potential side circuit region, and a low-potential side circuit region surrounding the high-potential side circuit region through the high-voltage junction termination structure are integrated on the same semiconductor chip. The aim of this semiconductor integrated circuit is to include: (a) a central well region of a first conductivity type disposed in the high-potential side circuit region; (b) a buried layer of a first conductivity type buried at the lower end of the central well region; (c) an annular drift region of a first conductivity type disposed around the high-voltage junction termination structure surrounding the central well region; (d) an annular well region of a second conductivity type surrounding the drift region; and (e) a base region of a second conductivity type disposed in the drift region. f) A carrier supply region of the first conductivity type, disposed in the base region, is a carrier supply region for a level shifting element included in a level shifting circuit that transmits signals between a low-potential side circuit region and a high-potential side circuit region; (g) A carrier receiving region of the first conductivity type, disposed in the drift region or the central well region, having a higher impurity concentration than the drift region or the central well region, is a carrier receiving region for a level shifting element; and (h) A first contact region of the first conductivity type, disposed separately from the carrier receiving region in the drift region or the central well region, having a higher impurity concentration than the drift region or the central well region, wherein the minimum of the first distances between the annular well region at the region forming the first contact region and the embedded layer is shorter than the minimum of the second distances between the annular well region at the region forming the carrier receiving region and the embedded layer.

[0021] The effects of the invention

[0022] According to the present invention, it is possible to provide a semiconductor integrated circuit in which a portion of the HVJT is used as a level shifter, which can improve ESD tolerance while suppressing the increase of chip area. Attached Figure Description

[0023] Figure 1 This is a circuit diagram illustrating an example of a semiconductor integrated circuit involved in an embodiment.

[0024] Figure 2 This is a top view showing an example of a semiconductor integrated circuit involved in the embodiment.

[0025] Figure 3 From Figure 2 A cross-sectional view observed along the AA′ direction.

[0026] Figure 4 From Figure 2 A cross-sectional view observed in the BB′ direction.

[0027] Figure 5This is a graph showing the simulation results of the electric field strength when 850V is applied to the semiconductor integrated circuit involved in the embodiment.

[0028] Figure 6 It is a graph showing the simulation results of the electric field strength when 1000V is applied to the semiconductor integrated circuit involved in the embodiment.

[0029] Figure 7 This is a graph showing the voltage withstand simulation results of the semiconductor integrated circuit involved in the embodiment.

[0030] Figure 8 This is a top view showing the semiconductor integrated circuit involved in the first comparative example.

[0031] Figure 9 This is a top view showing the semiconductor integrated circuit involved in the second comparative example.

[0032] Figure 10 This is a top view showing the semiconductor integrated circuit involved in the third comparative example.

[0033] Figure 11 This is a top view showing an example of a semiconductor integrated circuit involved in the first variation.

[0034] Figure 12 From Figure 11 A cross-sectional view observed along the AA′ direction.

[0035] Figure 13 From Figure 11 A cross-sectional view observed in the BB′ direction.

[0036] Figure 14 The second variation involves semiconductor integrated circuits, and from Figure 11 The cross-sectional view observed in the AA′ direction corresponds to the cross-sectional view.

[0037] Figure 15 The second variation involves semiconductor integrated circuits, and from Figure 11 The cross-sectional view observed in the BB′ direction corresponds to the cross-sectional view.

[0038] Figure 16 The third variation involves semiconductor integrated circuits, and from Figure 11 The cross-sectional view observed in the AA′ direction corresponds to the cross-sectional view.

[0039] Figure 17 The third variation involves semiconductor integrated circuits, and from Figure 11 The cross-sectional view observed in the BB′ direction corresponds to the cross-sectional view.

[0040] Figure 18This is a top view showing an example of a semiconductor integrated circuit involved in the fourth variation.

[0041] Figure 19 This is a top view showing an example of a semiconductor integrated circuit involved in the fifth variation.

[0042] Figure 20 This is a top view showing an example of a semiconductor integrated circuit involved in the sixth variation.

[0043] Figure 21 From Figure 20 A cross-sectional view observed along the AA′ direction.

[0044] Figure 22 From Figure 20 A cross-sectional view observed in the BB′ direction.

[0045] Figure 23 This is a top view showing an example of a semiconductor integrated circuit involved in the seventh variation.

[0046] Figure 24 It is a graph showing the relationship between the radius of curvature of the buried layer of the semiconductor integrated circuit involved in the seventh variation and the withstand voltage.

[0047] Figure 25 This is another top view showing an example of the semiconductor integrated circuit involved in the seventh variation.

[0048] Figure 26 This is a top view showing an example of a semiconductor integrated circuit involved in the eighth variation.

[0049] Figure 27 From Figure 26 A cross-sectional view observed along the AA′ direction.

[0050] Figure 28 From Figure 26 A cross-sectional view observed in the BB′ direction.

[0051] Explanation of reference numerals in the attached figures

[0052] 1, 1a: Substrate; 2: Drift region; 3: Central well region; 4, 4a, 4b, 11, 11a, 11b, 11c, 11d, 11e, 11f, 111: Contact region; 5: Annular well region; 5a, 5b: Base region; 7a, 7b: Carrier receiving region; 8a, 8b: Carrier supply region; 9a, 9b: Gate electrode; 10a, 10b: First level shifting element; 12, 12a, 12b: Slit region; 13, 13a: Buried layer; 14: Semiconductor substrate; 15, 16: Epitaxial growth layer; 17: Diffusion region; 20: Gate insulating film; 21: Field insulating film; 22: Interlayer insulating film; 23: Anode... 24: Cathode electrode; 25: Protective film; 26: Source electrode; 27: Drain electrode; 31, 32, 33, 34, 35, 36: Diode formation region; 41: Low-side circuit; 42: Level shifting circuit; 43: High-side circuit; 45: pMOS transistor; 46: nMOS transistor; 50: Semiconductor integrated circuit; 60: Power conversion unit; 61: Connection point; 65: Bootstrap diode; 66: Bootstrap capacitor; 67: Load; 68: Level shifting resistor; 69: Level shifter; 70: Protection diode; 101: High-side circuit region; 102: HVJT; 103: Low-side circuit region. Detailed Implementation

[0053] Hereinafter, embodiments and variations of the present invention will be described with reference to the accompanying drawings. In the drawings, identical or similar parts are labeled with the same or similar reference numerals, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thicknesses of each layer, etc., may sometimes differ from actual conditions. Furthermore, the drawings may include parts with different dimensional relationships or ratios. Additionally, the embodiments shown below are illustrative of apparatuses and methods for embodying the technical concept of the present invention; the technical concept of the present invention does not specify the material, shape, structure, or arrangement of structural components as described below.

[0054] In this specification, "carrier supply region" refers to the semiconductor region that supplies majority carriers constituting the main current, such as the source region of a field-effect transistor (FET) or a system induction transistor (SIT), or the emitter region of an insulated-gate bipolar transistor (IGBT). In addition, in system induction (SI) thyristors and gate turn-off (GTO) thyristors, the anode region serves as the carrier supply region. Conversely, "carrier receiving region" refers to the semiconductor region that receives majority carriers constituting the main current, such as the drain region of a FET or SIT, or the collector region of an IGBT. In SI thyristors and GTO thyristors, the cathode region functions as the carrier receiving region.

[0055] In addition, "control electrode" refers to the gate electrode of FET, SIT, IGBT, SI thyristor, and GTO thyristor, which has the function of controlling the flow of the main current flowing between the aforementioned carrier supply region and carrier receiving region.

[0056] Furthermore, the definitions of up and down directions in the following description are merely for illustrative purposes and do not limit the technical concept of the present invention. For example, if the object is rotated 90° for observation, up and down is read as left and right; if the object is rotated 180° for observation, up and down are reversed for reading. This is self-evident.

[0057] Furthermore, in the following description, the case where the first conductivity type is n-type and the second conductivity type is p-type is illustrated illustratively. However, the conductivity types can also be chosen in the opposite relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Additionally, the "+" and "-" affixed to "n" and "p" respectively indicate semiconductor regions with relatively high or relatively low impurity concentrations compared to semiconductor regions without "+" and "-" affixes. However, even semiconductor regions labeled with the same "n" and "n" do not necessarily mean that the impurity concentrations of each semiconductor region are strictly the same. Furthermore, in the following description, for components and regions defined by "first conductivity type" and "second conductivity type," unless otherwise explicitly stated, it refers to components and regions formed of semiconductor materials, which is self-evident both technically and logically.

[0058] (Implementation Method)

[0059] like Figure 1 As shown, in the case where the driving object is, for example, a power conversion bridge circuit, the semiconductor integrated circuit 50 according to the embodiment of the present invention is an HVIC that drives the power conversion section 60, which is one phase of the bridge circuit. Regarding the power conversion section 60, the output circuit is constructed by connecting the high-potential side switching element S1 and the low-potential side switching element S2 in series.

[0060] exist Figure 1 The example illustrates a scenario where the high-potential side switching element S1 and the low-potential side switching element S2 are both IGBTs. However, the high-potential side switching element S1 and the low-potential side switching element S2 are not limited to IGBTs; they can also be other power switching elements such as MOSFETs. Figure 1The diagram illustrates an equivalent circuit where the high-potential-side switching element S1 is connected in parallel with a reverse-connected freewheeling diode FWD1, and the low-potential-side switching element S2 is connected in parallel with a reverse-connected freewheeling diode FWD2. For example, it could be a structure where the high-potential-side switching element S1 and the freewheeling diode FWD1 are integrated into a single semiconductor chip (semiconductor substrate), and the low-potential-side switching element S2 and the freewheeling diode FWD2 are integrated into two reverse-conducting IGBTs on other semiconductor chips.

[0061] A high-potential-side switching element S1 and a low-potential-side switching element S2 are connected in series between the high-voltage main power supply VDC (positive side) and the ground potential (GND potential) (negative side of the main power supply VDC) to form a half-bridge circuit. The high-potential-side terminal (collector terminal) of the high-potential-side switching element S1 is connected to the main power supply VDC, and the low-potential-side terminal (emitter terminal) of the low-potential-side switching element S2 is connected to GND potential. The connection point 61 between the low-potential-side terminal (emitter terminal) of the high-potential-side switching element S1 and the high-potential-side terminal (collector terminal) of the low-potential-side switching element S2 is the output point of the power conversion section 60 of one phase of the power conversion bridge circuit. A load 67, such as a motor, is connected at the connection point 61, and the VS potential at the reference potential terminal VS is supplied to the load 67.

[0062] The semiconductor integrated circuit 50 of the embodiment outputs a drive signal from the output terminal OUT to turn the gate of the high-potential-side switching element S1 on and off based on the input signal from the input terminal IN. The semiconductor integrated circuit 50 of the embodiment includes at least a low-potential-side circuit 41, a level shifting circuit 42, and a high-potential-side circuit 43 as part of a circuit. The low-side circuit 41, level shifting circuit 42, and high-side circuit 43 can, for example, be monolithically integrated on a single semiconductor chip. Alternatively, the components constituting the low-side circuit 41, level shifting circuit 42, and high-side circuit 43 can be distributed across two or more semiconductor chips for hybrid integration.

[0063] The low-side circuit 41 operates with the GND potential (first potential) applied to the ground potential terminal GND as the reference potential and the VCC potential applied to the low-potential side power supply terminal VCC as the power supply potential. The low-side circuit 41 generates a low-side level on / off signal based on the input signal from the input terminal IN and outputs it to the level shift circuit 42. Although not shown in the figure, the low-side circuit 41 is, for example, a CMOS circuit comprising nMOS transistors and pMOS transistors.

[0064] The level shifting circuit 42 uses the GND potential (first potential) applied to the ground potential terminal GND as a reference potential to convert the low-side level on / off signal from the low-side circuit 41 into a high-side level on / off signal used on the high-side. The level shifting circuit 42 includes a level shifter (level conversion element) 69, for example, composed of an nMOS transistor. The gate terminal of the level shifter 69 is connected to the low-side circuit 41, the source terminal of the level shifter 69 is connected to the ground potential terminal GND, and the drain terminal of the level shifter 69 is connected to the input terminal of the high-side circuit 43. The drain terminal of the level shifter 69 is connected to one end of a level shifting resistor 68, and the other end of the level shifting resistor 68 is connected to the high-side power supply terminal VB. A protection diode 70 is connected between the gate and source of the level shifter 69.

[0065] The high-side circuit 43 operates with the VS potential applied to the reference potential terminal VS as the reference potential and the VB potential (second potential) applied to the high-side power supply terminal VB as the power supply potential. The high-side circuit 43 outputs a drive signal from the output terminal OUT according to the on / off signal from the level shifting circuit 42, thereby driving the gate of the high-side switching element S1. The high-side circuit 43 includes, for example, a CMOS circuit in its output stage comprising an nMOS transistor 46 as a high-side active element and a pMOS transistor 45 as a reference potential active element. The source terminal of the pMOS transistor 45 is connected to the high-side power supply terminal VB. The source terminal of the nMOS transistor 46 is connected to the reference potential terminal VS. The output terminal OUT is connected between the drain terminal of the pMOS transistor 45 and the drain terminal of the nMOS transistor 46.

[0066] As an example of an implementation method, the semiconductor integrated circuit 50 includes a bootstrap circuit. Figure 1 In the illustrated structure, a bootstrap diode 65, serving as an external component, is connected between the low-potential side power supply terminal VCC and the high-potential side power supply terminal VB. Furthermore, a bootstrap capacitor 66, also serving as an external component, is connected between the high-potential side power supply terminal VB and the reference potential terminal VS. The bootstrap diode 65 and the bootstrap capacitor 66 form part of the circuit for the drive power supply of the high-potential side switching element S1.

[0067] The VB potential is the highest potential applied to the semiconductor integrated circuit 50. Under normal conditions, unaffected by noise, it is maintained by the bootstrap capacitor 66 at approximately 15V higher than the VS potential. By complementary switching of the high-potential side switch element S1 and the low-potential side switch element S2, the VS potential repeatedly rises and falls between the high potential (e.g., around 400V to 600V) and the low potential (GND potential) of the main power supply VDC, thus varying between 0V and several hundredV. Furthermore, the VS potential can sometimes become negative.

[0068] Figure 2 Showing with Figure 1 The illustrated embodiment describes the planar layout of the semiconductor integrated circuit 50 corresponding to the semiconductor integrated circuit. Figure 2 The illustrations of the interlayer insulating film, electrodes, etc., on the upper side of the semiconductor integrated circuit involved in the embodiment are omitted. Figure 2 As shown, the semiconductor integrated circuit according to the embodiment provides a high-potential side circuit region (high-side circuit region) 101 and a low-potential side circuit region (low-side circuit region) 103 disposed around the high-side circuit region 101 on a single chip.

[0069] High-side circuit region 101 includes Figure 1 The high-side circuit 43 shown is an internal circuit, and the low-side circuit region 103 includes... Figure 1 The low-side circuit 41 shown is used as an internal circuit. Figure 2 The illustrations of the components included in the high-side circuit region 101 and the low-side circuit region 103 are omitted. The semiconductor integrated circuit according to the embodiment also includes a high-voltage junction termination structure (HVJT) 102 arranged in a ring around the high-side circuit region 101. The HVJT 102 electrically separates the high-side circuit region 101 from the low-side circuit region 103.

[0070] The high-side circuit region 101 is located in the central well region 3 of the first conductivity type (n-type). For example... Figure 2 As shown, the central well region 3 has a roughly rectangular planar pattern. Around the central well region 3, n... + The first contact area (first diode terminal contact area) 11 is arranged in a straight line along one side of the central well region 3. The first contact area 11 and... Figure 1 The high-potential side power supply terminal VB, to which the VB potential is applied, is electrically connected.

[0071] A p-shaped slit region 12 is provided in the remaining portion surrounding the central well region 3. The slit region 12 is arranged in an upward C-shape along three sides of the central well region 3, different from one side where the first contact region 11 is located. The two ends of the slit region 12 are arranged parallel to the first contact region 11, located on the central side (inner side) of the central well region 3, closer to the center of the central well region 3 than the first contact region 11. An n-shaped slit region is arranged in a ring (frame) shape on the inner side of the slit region 12. + The contact area 111 is of type 1. The contact area 111 is electrically connected to the high-potential side power supply terminal VB.

[0072] In HVJT 102, n are arranged in a ring (frame) shape around the central well region 3. -Type 2 drift region (pressure-resistant region). The impurity concentration in drift region 2 is lower than that in the central well region 3. Furthermore, in Figure 2 In the example shown, the first contact area 11 is located above the central trap area 3, but the first contact area 11 can also be located above the drift area 2.

[0073] On the outer periphery of drift region 2, a second conductivity type (p-type) annular well region (separation region) 5 is arranged in a ring (frame) shape. Above the annular well region 5, a p-type... + The second contact region (second diode terminal contact region) 4 of the type. The impurity concentration of the second contact region 4 is higher than that of the annular well region 5. The second contact region 4 and Figure 1 The grounding potential terminal GND is shown to be electrically connected to the grounding potential terminal where GND potential is applied.

[0074] The low-side circuit region 103 is composed of an n-shaped well region disposed on the outer periphery of the annular well region 5. The n-shaped well regions constituting the low-side circuit region 103 are disposed at the same depth as the central well region 3.

[0075] A first level shifting element 10a and a second level shifting element 10b are provided in a portion of HVJT 102. The first level shifting element 10a and the second level shifting element 10b are connected to... Figure 1 The level shifter 69 shown corresponds to this. The first level shifting element 10a and the second level shifting element 10b can respectively constitute an nMOS transistor that is turned on when the input signal is an ON signal and an nMOS transistor that is turned on when the input signal is an OFF signal. For example... Figure 2 As shown, the first level-shifting element 10a and the second level-shifting element 10b are positioned opposite each other at symmetrical locations. However, the arrangement of the first level-shifting element 10a and the second level-shifting element 10b is not limited to symmetrical positions; they can each be located within a portion of the HVJT 102.

[0076] In the semiconductor integrated circuit according to the embodiment, the slit region 12 surrounds the high-side circuit region 101, thereby increasing the resistance value of the parasitic resistance between the first carrier receiving region 7a and the second carrier receiving region 7b (described later) of the first level shifting element 10a and the second level shifting element 10b and the first contact region 11 of the high-side circuit region 101. This is a method of adjusting the resistance value between the first carrier receiving region 7a and the second carrier receiving region 7b and the first contact region 11 based on the length of the slit region 12 on the planar pattern (parasitic resistance value adjustment method). This parasitic resistance can be used as a level shift resistor 68. Alternatively, the resistance value of the parasitic resistance can be made sufficiently large, and a resistive element with a resistance value smaller than that of the parasitic resistance can be connected in parallel with the parasitic resistance to serve as a level shift resistor 68. The resistive element can be formed of polysilicon, for example, and can be disposed in the high-side circuit region 101.

[0077] Figure 2 The first level-shifting element 10a shown on the right has an annular drift region 2 and a common base region formed by a portion of a p-type annular well region 5. Furthermore, the first level-shifting element 10a has an n + The first source region (first carrier supply region) 8a and the n disposed opposite to the first carrier supply region 8a + The first leak region (first carrier receiving region) 7a is of the type. The impurity concentration of the first carrier supply region 8a and the first carrier receiving region 7a is higher than that of the drift region 2 and the central trap region 3. The annular trap region 5 may also have a shallow region formed in an annular shape on the upper part of the drift region 2 on its inner side. This shallow region becomes a common base region, and the first carrier supply region 8a may also be formed in this shallow region.

[0078] First carrier supply area 8a and Figure 1 The grounding potential terminal GND, to which the applied GND potential is shown, is electrically connected. The first carrier receiving area 7a is connected to the grounding potential terminal GND via the level shift resistor 68. Figure 1 The high-potential side power supply terminal VB, to which the VB potential is applied, is electrically connected.

[0079] Furthermore, the first level-shifting element 10a includes a first gate electrode (control electrode) 9a disposed on a common base region sandwiched between the first carrier supply region 8a and the drift region 2, separated by a gate insulating film (not shown). The gate insulating film can be formed from various insulating films, such as silicon oxide film (SiO2 film), silicon nitride film other than SiO2 film (Si3N4 film), or a stacked film including insulating films such as SiO2 film and Si3N4 film. The first gate electrode 9a controls the potential of the common base region formed by a portion of the annular well region 5. The first gate electrode 9a can be formed, for example, from a polycrystalline silicon film (doped polycrystalline silicon) with impurities introduced, a high-melting-point metal, or a silicide of a high-melting-point metal.

[0080] Figure 2 The second level-shifting element 10b shown on the left is a mirror image of the first level-shifting element 10a and has the same structure. The second level-shifting element 10b is composed of a ring-shaped drift region 2 and a portion of a p-type ring-shaped well region 5, and shares a common base region with the first level-shifting element 10a. Furthermore, the second level-shifting element 10b has an n... + The second source region (second carrier supply region) 8b and the n arranged opposite to the second carrier supply region 8b + The second drain region (second carrier receiving region) 7b is of the type. Furthermore, the second level conversion element 10b has a second gate electrode (control electrode) 9b disposed on a common base region sandwiched between the second carrier supply region 8b and the drift region 2, separated by a gate insulating film (not shown).

[0081] Figure 3 Showing from Figure 2 The cross-sectional view shown on the upper side, including the region (diode forming region) 31 where the second contact region 4 and the first contact region 11 face each other (diode forming region), is viewed along the AA' direction. Figure 3 As shown, the semiconductor integrated circuit according to the embodiment is disposed on the substrate 1. The substrate 1 is constructed of a semiconductor substrate 14 formed of p-type silicon (Si) and an epitaxial growth layer 15 formed of p-type Si disposed on the semiconductor substrate 14. When using the semiconductor integrated circuit 50, the semiconductor substrate 14 is, for example, fixed at the GND potential. In the diode forming region 31, no slit region 12 is formed between the second contact region 4 and the first contact region 11.

[0082] like Figure 2 and Figure 3 As shown, an n-type central well region 3 is selectively formed in the epitaxial growth layer 15. Similarly, an n-type buried layer 13 is buried at the lower end of the central well region 3, i.e., between the semiconductor substrate 14 and the central well region 3. The buried layer 13 is composed of a diffusion layer doped with n-type impurities such as antimony (Sb), phosphorus (P), or arsenic (As). The impurity concentration in the buried layer 13 is higher than that in the central well region 3. Figure 2 In the diagram, the position of the n-shaped embedded layer 13, located below the central well region 3, is schematically shown in the planar pattern using dashed lines. The embedded layer 13 has a generally rectangular planar pattern. Figure 2 On the planar pattern, the internal circuitry of the high-side circuit region 101 is formed inside the buried layer 13. Additionally, while the case where the contact region 111 is disposed inside the buried layer 13 is illustrated, the contact region 111 can also be disposed outside the buried layer 13.

[0083] Figure 2 and Figure 3The buried layer 13 shown has the function of suppressing the operation of parasitic PNP bipolar transistors in the depth direction of the internal circuit formed in the high-side circuit region 101. That is, when the HVIC is operating, it is normally in a state where the VB potential is higher than the VS potential, and the parasitic PNP bipolar transistors in the depth direction of the internal circuit formed in the high-side circuit region 101 do not operate. However, when it becomes a state of negative voltage (a voltage of negative potential) where the VB potential is lower than the VS potential due to noise such as lightning surges, the parasitic PNP bipolar transistors turn on and a large current flows to the semiconductor substrate 14 without the buried layer 13. In contrast, by providing the buried layer 13, the operation of parasitic PNP bipolar transistors can be prevented, thereby preventing damage to the HVIC.

[0084] n are selectively arranged in the upper part of the central trap region 3. + The first contact area (first diode terminal contact area) 11 is of the type. The first contact area 11 is ohmically connected to the cathode electrode (electrode for the first diode) 24 via contact holes in a field insulating film 21 formed by a method such as local silicon oxidation (LOCOS) and an interlayer insulating film 22 on the field insulating film 21. The cathode electrode 24 is covered by a protective film 25. In addition, an n is selectively provided at a position inside the first contact area 11 in the upper part of the central well region 3. + The contact area 111 is of type 111. The contact area 111 is connected to the electrode 28 ohms corresponding to the power supply terminal VB on the same high potential side.

[0085] On the upper part of the epitaxial growth layer 15, n is provided in such a way as to surround the outer periphery of the central well region 3. - A p-type drift region 2 is formed. The drift region 2 can penetrate the epitaxial growth layer 15 in the depth direction to contact the semiconductor substrate 14. A p-type annular well region 5 is selectively provided on the upper part of the epitaxial growth layer 15, surrounding the drift region 2. The annular well region 5 can penetrate the epitaxial growth layer 15 in the depth direction to contact the semiconductor substrate 14. A p-type annular well region 5 is selectively provided on the upper part of the annular well region 5. + The second contact area (second diode terminal contact area) 4 is ohmically connected to the anode electrode (second diode electrode) 23 via contact holes in the field insulating film 21 and the interlayer insulating film 22. The anode electrode 23 is covered by a protective film 25.

[0086] In diode forming region 31, such as Figure 3 As shown schematically, by n -The parasitic diode D1 is formed by the pn junction of the p-type drift region 2 and the p-type annular well region 5, and the HVJT 102 is constructed from this parasitic diode D1. The annular well region 5 functions as the anode region of the parasitic diode D1, and the second contact region 4 functions as the anode contact region of the parasitic diode D1. The drift region 2 and the central well region 3 of the first level shifting element 10a and the second level shifting element 10b function as the cathode regions of the parasitic diode D1, and the first contact region 11 functions as the cathode contact region of the parasitic diode D1.

[0087] Figure 4 Showing from Figure 2 The cross-sectional view shown is taken along the BB' direction, including the first level-shifting element 10a. Figure 2 and Figure 4 As shown, an n-type central well region 3 is selectively provided in a p-type epitaxial growth layer 15 disposed on a p-type semiconductor substrate 14. An n-type buried layer 13 is embedded between the semiconductor substrate 14 and the central well region 3. A p-type slit region 12 is selectively provided so as to penetrate the central well region 3 in the depth direction. The bottom of the slit region 12 is in contact with the semiconductor substrate 14. The slit region 12 can be formed by removing a portion of the epitaxial growth layer 15.

[0088] In the upper part of the central trap region 3, n are selectively arranged. + The first carrier receiving region 7a is connected to the carrier receiving electrode (drain electrode) 27 via contact holes in the field insulating film 21 and the interlayer insulating film 22. The carrier receiving electrode 27 is covered by a protective film 25.

[0089] On the upper part of the epitaxial growth layer 15, n are selectively arranged in a manner that surrounds the central well region 3. - A p-type drift region 2 is selectively provided on the upper part of the epitaxial growth layer 15, functioning as a common base region, surrounding the drift region 2. An n-type annular well region 5 is selectively provided on the upper part of the annular well region 5. + Type 8a is the first carrier supply area.

[0090] In the upper part of the annular trap region 5, p is selectively provided. +The second contact region 4 is in contact with the first carrier supply region 8a and functions as a back gate region. The first carrier supply region 8a and the second contact region 4 are connected to the carrier supply electrode (source electrode) 26 through contact holes in the field insulating film 21 and the interlayer insulating film 22. The carrier supply electrode 26 is covered by a protective film 25. The carrier supply electrode 26 is an electrode shared with the anode electrode (electrode for the second diode) 23 and is electrically connected to the ground potential terminal GND. A first gate electrode (control electrode) 9a is provided on the annular well region 5 sandwiched between the first carrier supply region 8a and the drift region 2, separated by the gate insulating film 20.

[0091] In the semiconductor integrated circuit involved in the implementation method, it is configured in the following manner: with located Figure 2 Compared to the buried layer 13 of the diode forming region 31 facing the first contact region 11, the buried layer 13 of the second contact region 4 shown on the upper side is further away from the annular well region 5 in the forming portions of the first level shifting element 10a and the second level shifting element 10b. That is, Figure 2 and Figure 3 The distance (first distance) L11 between the annular well region 5, which functions as the anode region of the pn junction diode D1 at the diode formation region 31, and the buried layer 13 is greater than that shown. Figure 2 and Figure 4 The annular well region 5, which functions as the common base region of the first level-shifting element 10a and the second level-shifting element 10b, has a short distance (second distance) L12 between it and the buried layer 13. For example, the first distance L11 is about 90 μm to 100 μm, and the second distance L12 is about 100 μm to 110 μm.

[0092] The first distance L11 may not be the same length throughout the entire diode forming region 31. For example, in a portion of the diode forming region 31, the first distance L11 may be the same as L12. Similarly, the second distance L12 may not be the same length throughout the forming regions of the first level-shifting element 10a and the second level-shifting element 10b. However, the minimum value of the first distance L11 is shorter than the minimum value of the second distance L12. That is, the minimum value of the first distance L11 between the annular well region 5 and the buried layer 13 in the diode forming region 31 forming the first contact region 11 is shorter than the minimum value of the second distance L12 between the annular well region 5 and the buried layer 13 in the forming regions of the first level-shifting element 10a and the second level-shifting element 10b.

[0093] The length (width) W0 of the first contact region 11, where the first distance L11 is shorter than the second distance L12, is appropriately determined based on the desired increase in ESD tolerance. Preferably, the width W0 of the diode forming region 31, where the first distance L11 is shorter than the second distance L12, is greater than or equal to the sum of the channel width W1 of the first level-shifting element 10a and the channel width W2 of the second level-shifting element 10b. More preferably, it is greater than or equal to twice the sum of the channel widths W1 and W2.

[0094] In addition, Figure 2 In this configuration, only at the diode forming area 31 on one side of the rectangular planar pattern located in the central well region 3, the first distance L11 is shorter than the second distance L12. However, for any area around the periphery of the central well region 3 where the first level-shifting element 10a and the second level-shifting element 10b are not formed, the distance between the annular well region 5 and the buried layer 13 can be set as the first distance L11, covering positions on two, three, or four sides of the central well region 3. For example, an example is shown in... Figure 2 The distance L13 between the annular trap area 5 and the buried layer 13 is equal to the second distance L12 at one of the edges of the central trap area 3 shown on the lower side. However, the distance L13 between the annular trap area 5 and the buried layer 13 can also be the first distance L11.

[0095] In addition, such as Figure 2 As shown, the drift length L14 of the diode forming region 31 can be approximately the same as, or different from, the drift length L15 of the first level-changing element 10a and the drift length L16 of the second level-changing element 10b. For example, the drift length L14 of the diode forming region 31 can be shorter than the drift length L15 of the first level-changing element 10a and the drift length L16 of the second level-changing element 10b. For example, the drift length L14 of the diode forming region 31 is defined as the distance between the first contact region 11 and the second contact region 4. The drift length L15 of the first level-changing element 10a is defined as the distance between the first carrier supply region 8a and the first carrier receiving region 7a of the first level-changing element 10a. The drift length L16 of the second level-changing element 10b is defined as the distance between the second carrier supply region 8b and the second carrier receiving region 7b of the second level-changing element 10b.

[0096] According to the semiconductor integrated circuit of the embodiment, the first distance L11 between the annular well region 5 at the diode formation region 31 and the buried layer 13 is shorter than the second distance L12 between the annular well region 5 at the formation regions of the first level shifting element 10a and the second level shifting element 10b and the buried layer 13. This mitigates the electric field in the formation regions of the first level shifting element 10a and the second level shifting element 10b, thereby enabling the break-off withstand voltage of the formation regions of the first level shifting element 10a and the second level shifting element 10b to be greater than the break-off withstand voltage of the diode formation region 31. Therefore, even when simultaneously subjected to an input ESD surge and entering an avalanche state, the avalanche current primarily flows through the parasitic diode D1, which does not have a parasitic structure. The avalanche current flowing into the first level shifting element 10a and the second level shifting element 10b, which causes parasitic operation, can be suppressed, thus improving the ESD tolerance of the semiconductor integrated circuit as a whole.

[0097] <Simulation Results>

[0098] Figure 5 and Figure 6 Showing from Figure 2 The observation of the AA′ direction and Figure 3 Simulation results of the electric field intensity at the cross-section of the corresponding diode formation region 31, and from Figure 2 The observations in the BB′ direction and Figure 4 Simulation results of electric field intensity at the cross section of the formation region of the corresponding first level conversion element 10a. Figure 5 The area A1 enclosed by a circle represents the electric field concentration point of the diode forming region 31 when 850V is applied. Figure 6 The area A2 enclosed by a circle represents the electric field concentration point in the formation region of the first level-changing element 10a when 1000V is applied. For example... Figure 5 and Figure 6 As shown, the electric field is concentrated at the end of the buried layer 13.

[0099] Figure 7 The voltage withstand simulation results of the semiconductor integrated circuit involved in the embodiment are shown. Figure 7 The curve “AA′” represents the breakdown voltage of diode formation region 31. Figure 7 The curve “BB′” represents the withstand voltage of the formation region of the first level-shifting element 10a. For example... Figure 7 As shown, it can be seen that the voltage withstand capability of the formation region of the first level-changing element 10a is higher than that of the diode formation region 31.

[0100] <Comparative Example>

[0101] Next, refer to Figures 8-10To illustrate the semiconductor integrated circuits involved in the first to third comparative examples. First, as... Figure 8 As shown, the semiconductor integrated circuit involved in the first comparative example differs from the semiconductor integrated circuit involved in the embodiment in the following aspects: there is no [structure] below the central well region 3. Figure 3 The buried layer 13 is shown. In the semiconductor integrated circuit involved in the first comparative example, there is no... Figure 3 As shown, the buried layer 13 located below the central well region 3 makes it easy for parasitic elements of the internal circuitry of the high-side circuit region 101 to operate. In contrast, in the semiconductor integrated circuits according to the embodiments, such as... Figure 3 As shown, there is a buried layer 13 located below the central well region 3, which can suppress the operation of parasitic elements in the internal circuit of the high-side circuit region 101.

[0102] Furthermore, in the semiconductor integrated circuit involved in the first comparative example, the drift length L21 of the diode formation region 31 is made consistent with the drift length L22 of the first level-shifting element 10a and the second level-shifting element 10b, and the break-off voltage is also equal. When the break-off voltage is equal, under the condition of an input ESD surge, the diode formation region 31, the first level-shifting element 10a, and the second level-shifting element 10b simultaneously enter an avalanche state. Therefore, the avalanche current flows approximately uniformly through the diode formation region 31, the first level-shifting element 10a, and the second level-shifting element 10b. Thus, it is not easy to cause local current concentration. However, in the first level-shifting element 10a and the second level-shifting element 10b, such as a high-voltage n-type MOSFET, the parasitic npn bipolar transistor is turned on due to the avalanche current, thereby inducing parasitic operation, and therefore is more easily damaged than the pn junction diode D1. There is also a method to limit the avalanche current flowing through the first level shifting element 10a and the second level shifting element 10b by adjusting the level shifting resistor, thereby eliminating the imbalance in their damage tolerance. However, in this case, the level shifting resistor needs to be large enough, which is a design limitation.

[0103] In contrast, in the semiconductor integrated circuits involved in the implementation method, such as Figures 2-4As shown, the first distance L11 between the annular well region 5 at the diode formation region 31 and the buried layer 13 is shorter than the second distance L12 between the annular well region 5 at the formation regions of the first level shifting element 10a and the second level shifting element 10b and the buried layer 13. This mitigates the electric field of the first level shifting element 10a and the second level shifting element 10b, thereby improving the overall ESD tolerance of the semiconductor integrated circuit. Furthermore, compared to methods that only use level shifting resistors to limit avalanche current, this method offers greater design flexibility. In addition, by configuring the buried layer 13, the breakdown voltage balance between the diode formation region 31 and the formation regions of the first level shifting element 10a and the second level shifting element 10b can be altered. Therefore, it is not necessary to expand the width (drift length) of the drift region (breakdown region) 2 constituting the HVJT 102 itself, thus suppressing the increase in chip area.

[0104] Next, the semiconductor integrated circuit involved in the second comparative example differs from the semiconductor integrated circuit involved in the embodiment in the following aspects: such as Figure 9 As shown, a portion of the inner peripheral surface of the drift region (voltage withstand region) constituting HVJT 102 protrudes inward in a convex shape, thereby increasing the drift length L22 of the first level-shifting element 10a and the second level-shifting element 10b. In the semiconductor integrated circuit according to the second comparative example, the first level-shifting element 10a and the second level-shifting element 10b protrude inward, thereby reducing the effective area of ​​the internal circuit of the high-side circuit region 101. In contrast, in the semiconductor integrated circuit according to the embodiment, the overall ESD tolerance of the semiconductor integrated circuit can be improved without reducing the effective area of ​​the internal circuit of the high-side circuit region 101.

[0105] Next, the semiconductor integrated circuit involved in the third comparative example differs from the semiconductor integrated circuit involved in the embodiment in the following aspects: such as Figure 10 As shown, a portion of the outer peripheral surface of the drift region 2 protrudes outward in a convex shape, thereby increasing the drift length L22 of the first level-shifting element 10a and the second level-shifting element 10b. In the semiconductor integrated circuit of the third comparative example, the first level-shifting element 10a and the second level-shifting element 10b protrude outward, thereby increasing the chip area. In contrast, in the semiconductor integrated circuit of the embodiment, the overall ESD tolerance of the semiconductor integrated circuit can be improved while minimizing the increase in chip area.

[0106] (First variation)

[0107] Figure 11 Showing with Figure 2 The planar layout of the semiconductor integrated circuit involved in the illustrated embodiment corresponds to the planar layout of the semiconductor integrated circuit involved in the first variation of the embodiment. Figure 12 Showing from Figure 11 The cross-sectional view shown includes the diode forming region 31 and is viewed along the AA′ direction. Figure 13 Showing from Figure 11 The cross-sectional view shown is taken along the BB' direction, including the first level-shifting element 10a. The semiconductor integrated circuit involved in the first modified example is similar to... Figure 2 and Figure 3 The semiconductor integrated circuits involved in the embodiments shown are different: such as Figure 11 and Figure 12 As shown, the first contact area 11 is located at the upper part of the drift area 2. That is, the first contact area 11 can be located at a position that is closer to the inside of the drift area 2.

[0108] Furthermore, the semiconductor integrated circuit involved in the first variation of the implementation method is similar to the following aspects: Figure 2 and Figure 4 The semiconductor integrated circuits involved in the embodiments shown are different: such as Figure 11 and Figure 13 As shown, the n of the first level conversion element 10a + The first drain region (first carrier receiving region) 7a and the second level conversion element 10b of the type n + The second drain region (second carrier receiving region) 7b is respectively disposed on the upper part of the drift region 2. That is, the first carrier receiving region 7a and the second carrier receiving region 7b can be disposed at a position closer to the inside of the drift region 2. Moreover, the slit region 12 is configured to penetrate the drift region 2 in the depth direction. The bottom of the slit region 12 contacts the epitaxial growth layer 15. The slit region 12 can be formed by the epitaxial growth layer 15 generated by removing a portion of the drift region 2. The other structures of the semiconductor integrated circuit involved in the first modification are the same as those of the semiconductor integrated circuit involved in the embodiment, so repeated descriptions are omitted.

[0109] According to the semiconductor integrated circuit of the first modification, similar to the semiconductor integrated circuit of the embodiment, the first distance L11 between the annular well region 5 at the diode formation region 31 and the buried layer 13 is shorter than the second distance L12 between the annular well region 5 at the formation regions of the first level conversion element 10a and the second level conversion element 10b and the buried layer 13. This can mitigate the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the overall ESD tolerance of the semiconductor integrated circuit.

[0110] (Second variation)

[0111] Figure 14 and Figure 15 A cross-sectional view of a semiconductor integrated circuit according to a second variation of the embodiment is shown. Figure 14 and Figure 12 The cross-sectional view of the semiconductor integrated circuit involved in the first modified example shown corresponds to the diode forming region 31. Figure 15 and Figure 13 The cross-sectional view of the semiconductor integrated circuit involved in the first modified example shown corresponds to the first level-shifting element 10a.

[0112] The semiconductor integrated circuit involved in the second variation is similar to the following aspects: Figure 12 and Figure 13 The first variant shown involves a different semiconductor integrated circuit: such as Figure 14 and Figure 15 As shown, the substrate 1a includes a semiconductor substrate 14 formed of p-type Si and an epitaxial growth layer 16 formed of n-type Si on the semiconductor substrate 14. Figure 14 As shown, n + The first contact region 11 of the type is located on the upper part of the epitaxial growth layer 16. For example... Figure 15 As shown, the epitaxial growth layer 16 constitutes the drift region of the first level-shifting element 10a. The epitaxial growth layer 16 has a... Figure 11 The drift region 2 shown has the same annular planar pattern. Furthermore, the slit region 12 is configured to penetrate the epitaxial growth layer 16 in the depth direction. The bottom of the slit region 12 contacts the semiconductor substrate 14. The slit region 12 can also be configured to penetrate the central well region 3 in the depth direction. In this case, it can also be as follows... Figure 3 and Figure 4 Thus, the first contact region 11, the first drain region 7a, and the second drain region 7b are disposed on the upper part of the central well region 3. The other structures of the semiconductor integrated circuit involved in the second modification are the same as those of the semiconductor integrated circuit involved in the embodiment, so repeated descriptions are omitted.

[0113] According to the semiconductor integrated circuit of the second variation, similar to the semiconductor integrated circuit of the embodiment, the first distance L11 between the annular well region 5 at the diode formation region 31 and the buried layer 13 is shorter than the second distance L12 between the annular well region 5 at the formation regions of the first level conversion element 10a and the second level conversion element 10b and the buried layer 13. This can mitigate the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the overall ESD tolerance of the semiconductor integrated circuit.

[0114] (Third variation)

[0115] Figure 16 and Figure 17 A cross-sectional view of a semiconductor integrated circuit according to a third variation of the embodiment is shown. Figure 16 and Figure 14The cross-sectional view of the semiconductor integrated circuit involved in the second modified example shown corresponds to the diode forming region 31. Figure 17 and Figure 15 The cross-sectional view of the semiconductor integrated circuit involved in the second modified example shown corresponds to the first level-shifting element 10a.

[0116] The semiconductor integrated circuit involved in the third variation is similar to the following aspects: Figure 14 and Figure 15 The second variation shown involves the same semiconductor integrated circuit: such as Figure 16 and Figure 17 As shown, the substrate 1a includes a semiconductor substrate 14 formed of p-type Si and an epitaxial growth layer 16 formed of n-type Si on the semiconductor substrate 14. However, it differs from the semiconductor integrated circuit involved in the second variation in the following aspect: an n-type epitaxial growth layer 16 with a higher impurity concentration than the epitaxial growth layer 16 is further provided on the upper part of the n-type epitaxial growth layer 16. - Type 17, impurity addition region (diffusion region). For example... Figure 16 As shown, n + The first contact area 11 of the type is located above the diffusion area 17. For example... Figure 17 As shown, the diffusion region 17 constitutes the drift region of the first level-shifting element 10a. The diffusion region 17 has a similar structure to... Figure 11 The drift zone 2 shown has the same annular planar pattern.

[0117] The diffusion region 17 can contact the central well region 3. In this case, the slit region 12 is configured to penetrate the diffusion region 17 and the epitaxial growth layer 16 in the depth direction. Alternatively, the slit region 12 can also be configured to penetrate the central well region 3 in the depth direction. In this case, it can be as follows: Figure 3 and Figure 4 Thus, the first contact region 11, the first drain region 7a, and the second drain region 7b are disposed on the upper part of the central well region 3. The other structures of the semiconductor integrated circuit involved in the third modification are the same as those of the semiconductor integrated circuit involved in the second modification, so repeated descriptions are omitted.

[0118] According to the semiconductor integrated circuit of the third variation, similar to the semiconductor integrated circuit of the embodiment, the first distance L11 between the annular well region 5 at the diode formation region 31 and the buried layer 13 is shorter than the second distance L12 between the annular well region 5 at the formation regions of the first level conversion element 10a and the second level conversion element 10b and the buried layer 13. This can mitigate the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the overall ESD tolerance of the semiconductor integrated circuit.

[0119] (Fourth variation)

[0120] Figure 18 Showing with Figure 2 The planar layout of the semiconductor integrated circuit according to the illustrated embodiment corresponds to the planar layout of the semiconductor integrated circuit according to the fourth modification of the embodiment. The semiconductor integrated circuit according to the fourth modification differs from the one described below in that it employs the following method... Figure 2 The semiconductor integrated circuits involved in the implementation method shown, which employs parasitic resistance adjustment, are different: such as... Figure 18 As shown, the p-type slit regions 12a and 12b respectively surround the first carrier receiving region 7a of the first level conversion element 10a and the second carrier receiving region 7b of the second level conversion element 10b, thereby electrically separating the first level conversion element 10a and the second level conversion element 10b from the high-side circuit region 101 (segmentation RESURF method).

[0121] like Figure 18 As shown, the high-side circuit region 101 is disposed in the n-type central well region 3. The central well region 3 has a generally rectangular planar pattern composed of straight sections and arc sections. An n-type circuit is disposed around a portion of the central well region 3. + The first contact areas 11a and 11b are of type 3. The first contact area 11a is arranged in a straight line along one side (the upper side) of the central well area 3. The first contact area 11b is arranged in a straight line along one side (the lower side) of the central well area 3 opposite to the upper side.

[0122] P-shaped slit regions 12a and 12b are provided in the remaining portion surrounding the central well region 3. The slit regions 12a and 12b are arranged in a C-shape with opposite orientations on the two opposing sides (left and right) of the central well region 3. The slit regions 12a and 12b are configured to surround the first level-shifting element 10a and the second level-shifting element 10b. The ends of the slit regions 12a and 12b contact the annular well region 5. The structures of the first level-shifting element 10a and the second level-shifting element 10b are similar to... Figure 2 The semiconductor integrated circuits involved in the embodiments shown are the same, so repeated descriptions are omitted.

[0123] In HVJT 102, n are arranged in a ring around the central well region 3. - A p-type drift region (pressure-resistant region) 2. A p-type annular trap region 5 is arranged in a ring around the outer periphery of the drift region 2. A p-type annular trap region 5 is arranged in a ring around the outer periphery of the annular trap region 5. + The second contact area 4 of the type. Figure 18 On the upper side, a diode forming region 31 is provided where a first contact region 11a and a portion of the second contact region 4 face each other. Figure 18 On the lower side, a diode forming region 32 is provided where a first contact region 11b and a portion of the second contact region 4 face each other.

[0124] from Figure 18 The cross-section shown, including the diode forming region 31, observed along the AA′ direction, is similar to... Figure 3 The cross-sectional views of the semiconductor integrated circuits involved in the illustrated embodiments are the same. From Figure 18 The cross section shown, including the first level-shifting element 10a, observed in the BB′ direction, is similar to... Figure 4 The cross-sectional views of the semiconductor integrated circuits involved in the embodiments shown are the same.

[0125] exist Figure 18 In the diagram, the position of the n-type buried layer 13a disposed below the central well region 3 is schematically shown in the planar pattern using dashed lines. The buried layer 13a has a generally rectangular planar pattern. In the semiconductor integrated circuit according to the fourth modification, the first distance L31 between the annular well region 5 at the diode forming regions 31 and 32 and the buried layer 13a is shorter than the second distance L32 between the annular well region 5 at the forming regions of the first level shifting element 10a and the second level shifting element 10b and the buried layer 13a, respectively. The other structures of the semiconductor integrated circuit according to the fourth modification are the same as those of the semiconductor integrated circuit according to the embodiment, and therefore repeated descriptions are omitted.

[0126] According to the semiconductor integrated circuit of the fourth modification, similar to the semiconductor integrated circuit of the embodiment, the first distance L31 between the annular well region 5 at the diode formation regions 31 and 32 and the buried layer 13a is shorter than the second distance L32 between the annular well region 5 at the formation regions of the first level conversion element 10a and the second level conversion element 10b and the buried layer 13a. This can mitigate the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the overall ESD tolerance of the semiconductor integrated circuit.

[0127] (Fifth variation)

[0128] Figure 19 Showing with Figure 18 The planar layout of the semiconductor integrated circuit in the fourth modification shown corresponds to the planar layout of the semiconductor integrated circuit in the fifth modification of the embodiment. The semiconductor integrated circuit in the fifth modification is similar to... Figure 18 The fourth variation shown involves the same semiconductor integrated circuit: such as Figure 19 As shown, the p-type slit regions 12a and 12b respectively surround the first carrier receiving region 7a of the first level conversion element 10a and the second carrier receiving region 7b of the second level conversion element 10b, thereby electrically separating the first level conversion element 10a and the second level conversion element 10b from the high-side circuit region 101 (segmented RESURF method).

[0129] However, the semiconductor integrated circuit involved in the fifth variation is similar to the following aspects: Figure 18 The fourth variation shown involves a different semiconductor integrated circuit: such as Figure 19 As shown, n-shaped traps are also provided at the four corners of the central trap region 3. + The first contact areas 11c, 11d, 11e, and 11f are the same as those of the first level-changing element 10a and are located on the right side of the central well region 3. The first contact areas 11c and 11e are the same as those of the second level-changing element 10b and are located on the left side of the central well region 3. The first contact areas 11c to 11f are respectively connected to the annular p + A portion of the second contact region 4 of the type faces each other and forms diode forming regions 33, 34, 35, and 36 respectively.

[0130] Furthermore, the first contact areas 11c to 11f may have, for example, a generally rectangular or linear planar pattern, but the planar pattern of the first contact areas 11c to 11f is not limited to this. Alternatively, the first contact areas 11c and 11d may be connected to the first contact area 11a to form a single first contact area. Alternatively, the first contact areas 11e and 11f may be connected to the first contact area 11b to form a single first contact area.

[0131] Furthermore, the semiconductor integrated circuit involved in the fifth variation is similar to the following aspects: Figure 18 The fourth variation shown involves a different semiconductor integrated circuit: such as Figure 19 As schematically shown with dashed lines, the planar pattern of the embedded layer 13a is a shape formed by recessing the central portions of the left and right sides of the rectangular pattern inwards. The embedded layer 13a is configured to recess inwards as it approaches the formation areas of the first level-shifting element 10a and the second level-shifting element 10b, away from the p-type annular well region 5, and is furthest from the annular well region 5 at the formation areas of the first level-shifting element 10a and the second level-shifting element 10b.

[0132] In the semiconductor integrated circuit according to the fifth modification, the first distance L31 between the annular well region 5 at the diode forming regions 31-36 and the buried layer 13a is shorter than the second distance L32 between the annular well region 5 at the forming regions of the first level-shifting element 10a and the second level-shifting element 10b and the buried layer 13a. That is, by recessing (receding) a portion of the rectangular pattern of the buried layer 13a inward, diode forming regions 33-36, which are set at the first distance L31, can be provided near the forming regions of the first level-shifting element 10a and the second level-shifting element 10b, which are set at the second distance L32. The other structures of the semiconductor integrated circuit according to the fifth modification are the same as those of the semiconductor integrated circuit according to the fourth modification, so repeated descriptions are omitted.

[0133] According to the semiconductor integrated circuit of the fifth modification, similar to the semiconductor integrated circuit of the embodiment, the first distance L31 between the annular well region 5 at the diode formation region 31 and the buried layer 13 is shorter than the second distance L32 between the annular well region 5 at the formation regions of the first level conversion element 10a and the second level conversion element 10b and the buried layer 13. This can mitigate the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the overall ESD tolerance of the semiconductor integrated circuit.

[0134] Furthermore, by setting the buried layer 13a to gradually move away from the p-type annular well region 5 as it approaches the formation regions of the first level-shifting element 10a and the second level-shifting element 10b, localized concentration of the electric field can be prevented. Additionally, diode formation regions 33 to 36 can be easily formed near the formation regions of the first level-shifting element 10a and the second level-shifting element 10b, such that the distance between the annular well region 5 and the buried layer 13 is a first distance L31.

[0135] (Sixth variation)

[0136] Figure 20 Showing with Figure 18 The planar layout of the semiconductor integrated circuit involved in the fourth variation shown corresponds to the planar layout of the semiconductor integrated circuit involved in the sixth variation of the embodiment. Figure 21 Showing from Figure 20 The cross-sectional view shown on the upper side, including the region (diode forming region) 31 facing the first contact region 11, is viewed in the AA′ direction. Figure 22 Showing from Figure 20 The cross-sectional view shown is taken along the BB' direction, including the first level-shifting element 10a. The semiconductor integrated circuit involved in the sixth variation differs from [the previous example] in that it employs the following method... Figure 18 The fourth variation shown involves the same semiconductor integrated circuit: such as Figure 20 As shown, the first level conversion element 10a and the second level conversion element 10b are electrically separated from the high-side circuit region 101 by the p-type slit regions 12a and 12b (segmentation RESURF method).

[0137] However, the semiconductor integrated circuit involved in the sixth variation is similar to the following aspects. Figure 18 The fourth variation shown involves a different semiconductor integrated circuit: such as Figure 21 As shown, the annular trap region 5 has a shallow region 5c on its inner side. A p is provided on the upper part of the shallow region 5c. + Type 4, second contact area.

[0138] In addition, in the following aspects with Figure 18 The fourth variation shown involves a different semiconductor integrated circuit: such as Figure 20 and Figure 22 As shown, in the formation region of the first level-shifting element 10a, a p-type base region 5a, formed separately from the annular well region 5, is provided at a position closer to the inner side than the annular well region 5. The impurity concentration of the base region 5a can be the same as or higher than that of the annular well region 5. An n-type base region is provided on the upper part of the base region 5a in a manner that allows them to contact each other. + The first carrier supply areas 8a and n of the type + The contact area 4a is of type 2. The impurity concentration of the contact area 4a can be the same as that of the second contact area 4. The anode electrode 23 is separated from the carrier supply electrode 26, which is electrically connected to the ground potential terminal GND via a resistive element.

[0139] Figure 20 The second level-shifting element 10b shown is a mirror image of the first level-shifting element 10a and has the same structure. Regarding the second level-shifting element 10b, a p-type base region 5b, formed separately from the annular well region 5, is provided at a position closer to the annular well region 5. An n-type base region is disposed on the upper part of the base region 5b in contact with each other. + The second carrier supply area 8b and n of the type + Type 4b contact area.

[0140] In this structure, the first distance L41 at the diode formation region 31 is the distance between the shallow region 5c and the buried layer 13, and the second distance L42 at the formation regions of the first level-shifting element 10a and the second level-shifting element 10b is the distance between the base regions 5a and 5b and the buried layer 13. The first distance L41 is shorter than the second distance L42. The other structures of the semiconductor integrated circuit involved in the sixth modification are the same as those involved in the semiconductor integrated circuit involved in the fourth modification, therefore, repeated descriptions are omitted.

[0141] According to the semiconductor integrated circuit of the sixth modification, similar to the semiconductor integrated circuit of the embodiment, the first distance L41 at the diode formation region 31 is made shorter than the second distance L42 at the formation regions of the first level conversion element 10a and the second level conversion element 10b, thereby mitigating the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the overall ESD tolerance of the semiconductor integrated circuit.

[0142] In the semiconductor integrated circuit according to the sixth modification, the annular well region 5 is formed separately from the base regions 5a and 5b. However, the base regions 5a and 5b can also be connected to the annular well region 5 to form an annular well region 5 with a shallow base region. In this case, the anode electrode 23 and the carrier supply electrode 26 become a common electrode and are electrically connected to the ground potential terminal GND.

[0143] Furthermore, in the semiconductor integrated circuit involved in the sixth variation, the segmentation RESURF method was described, but it can also be applied to the parasitic resistance value adjustment method mentioned above.

[0144] (Seventh variation)

[0145] Figure 23 Showing with Figure 2 The planar layout of the semiconductor integrated circuit according to the illustrated embodiment corresponds to the planar layout of the seventh variation of the embodiment. A high-side circuit region 101 is disposed in an n-type central well region 3. The central well region 3 has a generally rectangular planar pattern. In HVJT 102, n-type circuits are disposed in a ring (frame-like) manner surrounding the central well region 3. - A p-shaped annular trap region 5 is provided in a ring shape on the outer periphery of the drift region 2.

[0146] exist Figure 23 In the diagram, the position of the n-type buried layer 13, located below the central well region 3, is schematically shown in the planar pattern using dashed lines. These dashed lines coincide with the outer perimeter of the planar pattern of the high-side circuit region 101. The buried layer 13 has a generally rectangular planar pattern. The first distance L11 between the annular well region 5 at the diode formation region 31 and the buried layer 13 is shorter than the second distance L12 between the annular well regions 5 at the formation regions of the first level-shifting element 10a and the second level-shifting element 10b and the buried layer 13.

[0147] Ideally, in the planar pattern, the radii of curvature R at the four corners of the approximately rectangular buried layer 13 should be larger than the radii of curvature r1 at the corners of the approximately rectangular central well region 3. Furthermore, for example, when the breakdown voltage of the diode formation region is 825V, it is preferable that the radii of curvature R at the four corners of the approximately rectangular buried layer 13 is approximately 80μm or more, and it is desirable that the radii of curvature r1 of the central well region 3 is, for example, approximately 50μm to 60μm. When the radii of curvature R of the buried layer 13 is smaller than the radii of curvature r1 of the central well region 3, the electric field is concentrated at the corners of the buried layer 13, and therefore the avalanche current flows through the corners of the buried layer 13 before flowing through the diode formation region 31. Therefore, by making the radii of curvature R of the buried layer 13 larger than the radii of curvature r1 of the central well region 3, the electric field at the corners of the buried layer 13 can be mitigated, and the breakdown voltage at the corners of the buried layer 13 can be made higher than the breakdown voltage at the diode formation region 31.

[0148] from Figure 23 The cross-section shown, including the diode forming region 31, observed along the AA′ direction, is similar to... Figure 3 The cross-sectional views of the semiconductor integrated circuits involved in the illustrated embodiments are the same. From Figure 23 The cross section shown, including the first level-shifting element 10a, observed in the BB′ direction, is similar to... Figure 4 The cross-sectional views of the semiconductor integrated circuits involved in the illustrated embodiments are the same. The other structures of the semiconductor integrated circuits involved in the seventh variation are the same as those in the embodiments, therefore, repeated descriptions are omitted.

[0149] Figure 24 This is a graph showing the relationship between the radius of curvature R of the embedded layer 13 and its pressure resistance. Figure 24 The image shows a semiconductor integrated circuit with a rated voltage of 600V. Based on... Figure 1 The surge voltage applied to terminal VS in the circuit diagram shown is used to set the withstand voltage of the semiconductor integrated circuit, which is set to 820V. The larger the radius of curvature R of the buried layer 13, the more gentle the electric field at the corners of the buried layer 13, and therefore the higher the withstand voltage. Therefore, it is preferable to increase the radius of curvature R of the buried layer 13 to achieve the required higher withstand voltage. Figure 24 As shown by the dashed line, when the withstand voltage of the diode formation region 31 is 825V, by making the radius of curvature R of the buried layer 13 greater than 80μm, the withstand voltage of the buried layer 13 becomes greater than that of the diode formation region 31.

[0150] Figure 25 Is with Figure 23The seventh variation shown involves a semiconductor integrated circuit with the same planar layout, but schematically illustrates the radius of curvature R of the corners of the roughly rectangular buried layer 13 and the radius of curvature r2 of the outer corners of the drift region 2. In the planar pattern, the radius of curvature R of the buried layer 13 can also be greater than the radius of curvature r2 of the drift region 2. The radius of curvature r2 of the drift region 2 is greater than... Figure 23 The radius of curvature r1 of the central well region 3 shown is, for example, about 100 μm.

[0151] According to the semiconductor integrated circuit of the seventh modification, similar to the semiconductor integrated circuit of the embodiment, the first distance L11 between the annular well region 5 at the diode formation region 31 and the buried layer 13 is shorter than the second distance L12 between the annular well region 5 at the formation regions of the first level conversion element 10a and the second level conversion element 10b and the buried layer 13. This can mitigate the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the overall ESD tolerance of the semiconductor integrated circuit.

[0152] Furthermore, even if the breakdown voltage at the diode formation region 31 is high, the electric field at the corner of the buried layer 13 can be mitigated by making the radius of curvature R of the buried layer 13 larger than the radius of curvature r1 of the central well region 3, and making the radius of curvature R of the buried layer 13 80 μm or more. Therefore, the breakdown voltage at the corner of the buried layer 13 can be higher than that at the diode formation region 31. In addition, as the seventh modified example of the semiconductor integrated circuit, a structure employing a parasitic resistance adjustment method is illustrated, but it can also be applied to a structure employing a segmented RESURF method.

[0153] (Eighth variation)

[0154] Figure 26 Showing with Figure 11 The planar layout of the semiconductor integrated circuit involved in the first variation shown corresponds to the planar layout of the semiconductor integrated circuit involved in the eighth variation of the embodiment. Figure 27 Showing from Figure 26 The cross-section shown is the one observed along the AA′ direction, including the diode forming region 31. Figure 28 Showing from Figure 26 The cross section shown is observed in the BB′ direction, including the first level-shifting element 10a.

[0155] like Figures 26-28 As shown, the semiconductor integrated circuit involved in the eighth variation is similar to the following aspects: Figure 11 The semiconductor integrated circuit involved in the first modified example differs from that in that an n-type central well region 3 is not provided in the high-side circuit region 101. Furthermore, the semiconductor integrated circuit involved in the eighth modified example differs from that in the following aspects... Figure 11The first variation shown differs from the semiconductor integrated circuit in that the drift region 16 is an n-type epitaxial growth layer. The planar layout of the drift region 16 and the surface exposure (outer periphery of HVJT 102) of the pn junction of the annular well region 5 has a generally rectangular planar pattern. This is taken as the planar pattern of the drift region 16. Furthermore, the drift region 16 is not limited to an n-type epitaxial growth layer; for example, it can be an n-type epitaxial growth layer formed on a p-type epitaxial growth layer, similar to the semiconductor integrated circuit described in the embodiment. - Type of diffusion zone.

[0156] Furthermore, the semiconductor integrated circuit involved in the eighth variation is similar to the following aspects: Figure 11 The semiconductor integrated circuit involved in the first modified example shown is different: an n-type buffer layer 18 is provided in a ring (frame) shape above the drift region 16. An n+ type contact region 111 is provided in a ring (frame) shape above the buffer layer 18. The buffer layer 18 can be provided as needed, or it can be omitted.

[0157] The expectation is that, as Figure 26 As shown, in the planar pattern, the radius of curvature R of the embedded layer 13 is greater than the radius of curvature r2 of the corner of the approximately rectangular drift region 16. The radius of curvature r2 of the drift region 16 is, for example, about 100 μm. The other structures of the semiconductor integrated circuit involved in the eighth variation are the same as those involved in the semiconductor integrated circuit involved in the first variation, so repeated descriptions are omitted.

[0158] According to the semiconductor integrated circuit of the eighth modification, similar to the semiconductor integrated circuit of the embodiment, the first distance L11 between the annular well region 5 at the diode formation region 31 and the buried layer 13 is shorter than the second distance L12 between the annular well region 5 at the formation regions of the first level conversion element 10a and the second level conversion element 10b and the buried layer 13. This can mitigate the electric field of the first level conversion element 10a and the second level conversion element 10b, thereby improving the overall ESD tolerance of the semiconductor integrated circuit.

[0159] Furthermore, even if the breakdown voltage at the diode formation region 31 is high, the electric field at the corner of the buried layer 13 can be mitigated by making the radius of curvature R of the buried layer 13 larger than the radius of curvature r2 of the corner of the approximately rectangular drift region 16. Thus, the breakdown voltage at the corner of the buried layer 13 can be higher than that at the diode formation region 31. In addition, while the eighth modified example of the semiconductor integrated circuit illustrates a structure employing parasitic resistance adjustment, it can also be applied to structures employing a segmented RESURF method.

[0160] (Other implementation methods)

[0161] As described above, the present invention has been illustrated by way of embodiments, but it should not be construed that the discussions and drawings, which form part of this disclosure, are intended to limit the invention. Based on this disclosure, those skilled in the art will recognize various alternative embodiments, examples, and application techniques.

[0162] For example, in the implementation, the case with two active elements, namely the first level shifting element 10a and the second level shifting element 10b, is mainly illustrated. However, the number of active elements constituting the level shifter can be at least one, or it can be three or more.

[0163] Furthermore, while the embodiment illustrates a semiconductor integrated circuit using a Si substrate as the substrate 1, the technical concepts described in the embodiment can also be applied to semiconductor integrated circuits using compound semiconductors such as gallium arsenide (GaAs). Moreover, the technical concepts described in the embodiment can also be applied to semiconductor integrated circuits using wide-bandgap semiconductors such as SiC, gallium nitride (GaN), or diamond. Furthermore, they can also be applied to semiconductor integrated circuits using narrow-bandgap semiconductors such as indium antimonide (InSb), half-metals, etc.

[0164] Furthermore, the method for forming the slit region 12 between the first level-shifting element 10a, the second level-shifting element 10b, and the internal circuit of the high-side circuit region 101 can employ either a parasitic resistance adjustment method or a segmented RESURF method. For example, the following configuration can also be used instead of... Figure 18 The p-type slit regions 12a and 12b shown: The first level-changing element 10a and the second level-changing element 10b are separated from the internal circuit of the high-side circuit region 101 by using trenches filled with insulating film or the like.

[0165] Thus, once the spirit of the technical content disclosed in the above embodiments is understood, those skilled in the art will clearly recognize that the present invention can encompass various alternative embodiments, examples, and application techniques. Furthermore, it is self-evident that this includes structures obtained by arbitrarily applying the structures described in the above embodiments and variations, as well as various embodiments not described herein. Therefore, the technical scope of the present invention is determined solely by the inventive features appropriate for the purposes of the above illustrative description, as covered by the claims.

Claims

1. A semiconductor integrated circuit that is a semiconductor integrated circuit in which a high-potential-side circuit region, a high-withstand-voltage junction termination structure surrounding the high-potential-side circuit region, and a low-potential-side circuit region surrounding the high-potential-side circuit region through the high-withstand-voltage junction termination structure are integrated in the same semiconductor chip, the semiconductor integrated circuit characterized by comprising: a central well region of a first conductivity type that is disposed in the high-potential-side circuit region; an embedded layer of the first conductivity type that is embedded in a lower end of the central well region and has a higher impurity concentration than the central well region; a ring-shaped drift region of the first conductivity type that is disposed at a position surrounding the central well region of the high-withstand-voltage junction termination structure; a ring-shaped well region of a second conductivity type that surrounds the drift region; a carrier supply region of the first conductivity type that is disposed in the ring-shaped well region and is a carrier supply region of a level shift element included in a level shift circuit that transfers a signal between the low-potential-side circuit region and the high-potential-side circuit region; a carrier receiving region of the first conductivity type that is disposed in the drift region or the central well region, has a higher impurity concentration than the drift region or the central well region, and is a carrier receiving region of the level shift element; and a first contact region of the first conductivity type that is disposed in the drift region or the central well region separately from the carrier receiving region, has a higher impurity concentration than the drift region or the central well region, a minimum value in a first distance between the ring-shaped well region and the embedded layer at a region where the first contact region is formed is shorter than a minimum value in a second distance between the ring-shaped well region and the embedded layer at a region where the carrier receiving region is formed, and a length of the drift region at the region where the first contact region is formed is the same as a length of the drift region at the region where the carrier receiving region is formed.

2. A semiconductor integrated circuit that is a semiconductor integrated circuit in which a high-potential-side circuit region, a high-withstand-voltage junction termination structure surrounding the high-potential-side circuit region, and a low-potential-side circuit region surrounding the high-potential-side circuit region through the high-withstand-voltage junction termination structure are integrated in the same semiconductor chip, the semiconductor integrated circuit characterized by comprising: a central well region of a first conductivity type that is disposed in the high-potential-side circuit region; an embedded layer of the first conductivity type that is embedded in a lower end of the central well region; a ring-shaped drift region of the first conductivity type that is disposed at a position surrounding the central well region of the high-withstand-voltage junction termination structure; a ring-shaped well region of a second conductivity type that surrounds the drift region; a base region of the second conductivity type that is disposed in the drift region; a carrier supply region of the first conductivity type that is disposed in the base region and is a carrier supply region of a level shift element included in a level shift circuit that transfers a signal between the low-potential-side circuit region and the high-potential-side circuit region; a carrier receiving region of the first conductivity type that is disposed in the drift region or the central well region, has a higher impurity concentration than the drift region or the central well region, and is a carrier receiving region of the level shift element; and ​ ​ ​ ​ ​ ​ wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ a first contact region of a first conductivity type which is disposed in the drift region or the central well region separately from the carrier receiving region, the impurity concentration of which is higher than that of the drift region or the central well region, wherein a minimum value in a first distance between the ring-shaped well region and the buried layer at a region where the first contact region is formed is shorter than a minimum value in a second distance between the ring-shaped well region and the buried layer at a region where the carrier receiving region is formed.

3. The semiconductor integrated circuit according to claim 1, characterized by Further provided are: a control electrode of the level shift element which is disposed on a surface of a portion of the ring-shaped well region which is between the carrier supply region and the drift region, through a gate insulating film; a carrier supply electrode which is in contact with the carrier supply region and a second contact region; a carrier receiving electrode which is in contact with the carrier receiving region; and a diode electrode which is in contact with the first contact region.

4. The semiconductor integrated circuit according to claim 2, wherein the carrier supply region is disposed in a base region of a second conductivity type which is disposed inside the ring-shaped well region, the semiconductor integrated circuit further comprises: a control electrode of the level shift element which is disposed on a surface of a portion of the base region which is between the carrier supply region and the drift region, through a gate insulating film; a carrier supply electrode which is in contact with the carrier supply region; a carrier receiving electrode which is in contact with the carrier receiving region; and a diode electrode which is in contact with the first contact region.

5. The semiconductor integrated circuit according to any one of claims 1 to 4, wherein the central well region is selectively disposed in an epitaxial growth layer of a second conductivity type which is disposed on a semiconductor substrate of a second conductivity type.

6. The semiconductor integrated circuit according to any one of claims 1 to 4, wherein the drift region is composed of an epitaxial growth layer of a first conductivity type which is disposed on a semiconductor substrate of a second conductivity type, the central well region is selectively disposed in the epitaxial growth layer.

7. The semiconductor integrated circuit according to any one of claims 1 to 4, wherein the central well region is selectively disposed in an epitaxial growth layer of a first conductivity type which is disposed on a semiconductor substrate of a second conductivity type, the drift region is selectively disposed in the epitaxial growth layer.

8. The semiconductor integrated circuit according to claim 5, wherein the buried layer is located between the semiconductor substrate and the central well region.

9. The semiconductor integrated circuit according to claim 5, further comprising: a slit region of a second conductivity type which is disposed between the carrier receiving region and the high-potential-side circuit region in a direction linking the carrier supply region and the carrier receiving region, which penetrates the drift region or the central well region in a depth direction, and reaches the epitaxial growth layer or the semiconductor substrate.

10. The semiconductor integrated circuit according to claim 9, wherein the slit region is disposed so as to surround the central well region in a planar pattern. ​ 11. The semiconductor integrated circuit according to claim 9, wherein the slit region is provided so as to extend in the drift region and surround the carrier supply region in a plan view.

12. The semiconductor integrated circuit according to claim 11, wherein the buried layer is provided so as to be farther from the ring-shaped well region as closer to the level shift element in a plan view.

13. The semiconductor integrated circuit according to claim 12, wherein the central well region has a rectangular plan view, a region forming the level shift element and a region forming a pn junction diode are provided on one side of the 1 side of the rectangle of the central well region.

14. The semiconductor integrated circuit according to any one of claims 1 to 4, wherein the buried layer and the central well region each have a rectangular plan view, a radius of curvature of a corner portion of the buried layer is larger than a radius of curvature of a corner portion of the central well region in a plan view.

15. A semiconductor integrated circuit in which a high-potential-side circuit region, a high-withstand- voltage junction terminal structure surrounding the high-potential-side circuit region, and a low-potential-side circuit region surrounding the high-potential-side circuit region through the high-withstand-voltage junction terminal structure are integrated in the same semiconductor chip, the semiconductor integrated circuit comprising: a central well region of a first conductivity type, which is disposed in the high-potential-side circuit region; a buried layer of the first conductivity type, which is buried in a lower end of the central well region and has a higher impurity concentration than the central well region; a ring-shaped drift region of the first conductivity type, which is disposed at a position surrounding the central well region of the high-withstand-voltage junction terminal structure; a ring-shaped well region of a second conductivity type, which surrounds the drift region; a carrier supply region of the first conductivity type, which is disposed in the ring-shaped well region and is a carrier supply region of a level shift element included in a level shift circuit that transfers a signal between the low-potential-side circuit region and the high-potential-side circuit region; a carrier receiving region of the first conductivity type, which is disposed in the drift region or the central well region, has a higher impurity concentration than the drift region or the central well region, and is a carrier receiving region of the level shift element; and a first contact region of the first conductivity type, which is disposed in the drift region or the central well region separately from the carrier receiving region, has a higher impurity concentration than the drift region or the central well region, a minimum value in a first distance between the ring-shaped well region and the buried layer at a region where the first contact region is formed is shorter than a minimum value in a second distance between the ring-shaped well region and the buried layer at a region where the carrier receiving region is formed, wherein the buried layer has a rectangular plan view, the drift region has a frame-shaped plan view, a radius of curvature of a corner portion of the buried layer is larger than a radius of curvature of a corner portion of the drift region in a plan view. wherein ​ ​ ​ ​ 16. A semiconductor integrated circuit that is a semiconductor integrated circuit in which a high-potential-side circuit region, a high-withstand-voltage junction termination structure surrounding the high-potential-side circuit region, and a low-potential-side circuit region surrounding the high-potential-side circuit region via the high-withstand-voltage junction termination structure are integrated in the same semiconductor chip, the semiconductor integrated circuit characterized by comprising: a central well region of a first conductivity type that is disposed in the high-potential-side circuit region; an embedded layer of the first conductivity type that is embedded in a lower end of the central well region and has a higher impurity concentration than the central well region; a ring-shaped drift region of the first conductivity type that is disposed at a position surrounding the central well region of the high-withstand-voltage junction termination structure; a ring-shaped well region of a second conductivity type that surrounds the drift region; a carrier supply region of the first conductivity type that is disposed in the ring-shaped well region and is a carrier supply region of a level shift element included in a level shift circuit that transfers a signal between the low-potential-side circuit region and the high-potential-side circuit region; a carrier receiving region of the first conductivity type that is disposed in the drift region or the central well region, has a higher impurity concentration than the drift region or the central well region, and is a carrier receiving region of the level shift element; and a first contact region of the first conductivity type that is disposed in the drift region or the central well region separately from the carrier receiving region, has a higher impurity concentration than the drift region or the central well region, wherein a minimum value in a first distance between the ring-shaped well region and the embedded layer at a region where the first contact region is formed is shorter than a minimum value in a second distance between the ring-shaped well region and the embedded layer at a region where the carrier receiving region is formed, wherein the embedded layer has a rectangular planar pattern, and wherein a radius of curvature of a corner portion of the embedded layer is 80 μm or more on the planar pattern.

16. A semiconductor integrated circuit that is a semiconductor integrated circuit in which a high-potential-side circuit region, a high-withstand-voltage junction termination structure surrounding the high-potential-side circuit region, and a low-potential-side circuit region surrounding the high-potential-side circuit region via the high-withstand-voltage junction termination structure are integrated in the same semiconductor chip, the semiconductor integrated circuit characterized by comprising: a central well region of a first conductivity type that is disposed in the high-potential-side circuit region; an embedded layer of the first conductivity type that is embedded in a lower end of the central well region and has a higher impurity concentration than the central well region; a ring-shaped drift region of the first conductivity type that is disposed at a position surrounding the central well region of the high-withstand-voltage junction termination structure; a ring-shaped well region of a second conductivity type that surrounds the drift region; a carrier supply region of the first conductivity type that is disposed in the ring-shaped well region and is a carrier supply region of a level shift element included in a level shift circuit that transfers a signal between the low-potential-side circuit region and the high-potential-side circuit region; a carrier receiving region of the first conductivity type that is disposed in the drift region or the central well region, has a higher impurity concentration than the drift region or the central well region, and is a carrier receiving region of the level shift element; and a first contact region of the first conductivity type that is disposed in the drift region or the central well region separately from the carrier receiving region, has a higher impurity concentration than the drift region or the central well region, wherein a minimum value in a first distance between the ring-shaped well region and the embedded layer at a region where the first contact region is formed is shorter than a minimum value in a second distance between the ring-shaped well region and the embedded layer at a region where the carrier receiving region is formed, wherein the embedded layer has a rectangular planar pattern, and wherein a radius of curvature of a corner portion of the embedded layer is 80 μm or more on the planar pattern. ​ ​ ​ ​ ​ ​ wherein, ​ ​ ​

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