Pixel and display device including the same

Abstract

Disclosed are a pixel and a display device including the same. The pixel includes a light emitting element, a first transistor which controls an amount of current flowing from a first power supply to a second power supply through the light emitting element in correspondence with a voltage applied to a first node, a second transistor which is connected between a data line and a second node corresponding to a first electrode of the first transistor, and a gate electrode of the second transistor is connected to a first scan line, a third transistor which is connected between the first node and a third node corresponding to a second electrode of the first transistor, and a gate electrode of the third transistor is connected to the first scan line, and a fourth transistor which is connected between the third transistor and the third node and always maintains an on state.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a pixel and a display device including the same. Background Art

[0002] A display device displays images using pixels that respectively emit light of multiple colors (eg, red, green, and blue light).

[0003] A display device includes pixels connected to data lines and scan lines. These pixels typically include a light-emitting element and a drive transistor for controlling the amount of current flowing into the light-emitting element. The drive transistor controls the amount of current flowing from a first power source to a second power source via the light-emitting element in response to a data signal. The light-emitting element then generates light at a predetermined brightness in response to the current flowing from the drive transistor. Summary of the Invention

[0004] An object of the present disclosure is to provide a pixel for reducing degradation deviation of a transistor for compensating a threshold voltage.

[0005] Another object of the present disclosure is to provide a display device including the pixel.

[0006] However, the purpose of the present disclosure is not limited to the above-mentioned purpose, and various extensions can be made within the scope of the idea and field of the present disclosure.

[0007] In order to achieve one purpose of the present disclosure, a pixel according to an embodiment of the present disclosure may include: a light-emitting element; a first transistor, which controls the amount of current flowing from a first power source to a second power source via the light-emitting element in response to a voltage applied to a first node; a second transistor, which is connected between a data line and a second node corresponding to a first electrode of the first transistor, and a gate electrode of the second transistor is connected to a first scan line; a third transistor, which is connected between the first node and a third node corresponding to the second electrode of the first transistor, and a gate electrode of the third transistor is connected to the first scan line; and a fourth transistor, which is connected between the third transistor and the third node and is always kept in an on state.

[0008] According to an embodiment, the third transistor and the fourth transistor may be connected in series between the first node and the third node.

[0009] According to an embodiment, the fourth transistor may include a gate electrode connected to a DC power source that turns on the fourth transistor.

[0010] According to an embodiment, the gate electrode of the fourth transistor may be connected to the second power supply.

[0011] According to an embodiment, the third transistor may include a plurality of third transistors connected in series between the first node and the fourth transistor, and gate electrodes of the plurality of third transistors may be commonly connected to the first scan line.

[0012] According to one embodiment, the pixel may further include: a fifth transistor connected between the first power supply and the second node, and the gate electrode of the fifth transistor is connected to the light-emitting control line; a sixth transistor connected between the third node and the light-emitting element, and the gate electrode of the sixth transistor is connected to the light-emitting control line; and a storage capacitor connected between the first power supply and the first node.

[0013] According to one embodiment, the pixel may further include: a seventh transistor connected between the first node and the initialization power supply, and the gate electrode of the seventh transistor is connected to the second scan line; and an eighth transistor connected between the light-emitting element and the initialization power supply, and the gate electrode of the eighth transistor is connected to the third scan line.

[0014] According to an embodiment, the fourth transistor may include a gate electrode connected to the initialization power source.

[0015] According to an embodiment, the second scan line and the third scan line may be the same scan line.

[0016] To achieve one object of the present disclosure, a display device according to an embodiment of the present disclosure may include: a pixel positioned so as to be connectable to a scan line, a light emission control line, and a data line; a scan driver for supplying a scan signal to the pixel via the scan line; a light emission driver for supplying a light emission control signal to the pixel via the light emission control line; and a data driver for supplying a data signal to the pixel via the data line. The pixel in the i-th row and j-th column may include: a light emitting element; a first transistor for controlling an amount of current flowing from a first power source to a second power source via the light emitting element in response to a voltage applied to a first node; a second transistor connected between the j-th data line and a second node corresponding to a first electrode of the first transistor, with a gate electrode of the second transistor connected to the first scan line of the i-th pixel row; a third transistor connected between the first node and a third node corresponding to the second electrode of the first transistor, with a gate electrode of the third transistor connected to the first scan line of the i-th pixel row; and a fourth transistor connected between the third transistor and the third node and always maintained in an on state, wherein i and j are natural numbers.

[0017] According to an embodiment, the third transistor and the fourth transistor may be connected in series between the first node and the third node.

[0018] According to an embodiment, the fourth transistor may include a gate electrode connected to a DC power source that turns on the fourth transistor.

[0019] According to an embodiment, the gate electrode of the fourth transistor may be connected to the second power supply.

[0020] According to an embodiment, the third transistor may include a plurality of third transistors connected in series between the first node and the fourth transistor, and gate electrodes of the plurality of third transistors may be commonly connected to the first scan line.

[0021] According to one embodiment, the pixel in the i-th row and the j-th column may further include: a fifth transistor connected between the first power supply and the second node, and a gate electrode connected to a light-emitting control line; a sixth transistor connected between the third node and the light-emitting element, and a gate electrode connected to the light-emitting control line; and a storage capacitor connected between the first power supply and the first node.

[0022] According to one embodiment, the pixel in the i-th row and the j-th column may further include: a seventh transistor, connected between the first node and the initialization power supply, and a gate electrode connected to the second scan line of the i-th pixel row; and an eighth transistor, connected between the light-emitting element and the initialization power supply, and a gate electrode connected to the third scan line of the i-th pixel row.

[0023] According to an embodiment, the fourth transistor may include a gate electrode connected to the initialization power source.

[0024] According to one embodiment, the display device may further include a power supply unit that generates the first power supply and the second power supply and supplies them to the pixels, and generates a low power supply and a high power supply for generating the scan signal and supplies them to the scan driving unit.

[0025] According to an embodiment, the fourth transistor may include a gate electrode connected to the low power source.

[0026] (Effect of disclosure)

[0027] According to an embodiment of the present disclosure, a pixel and a display device including the same include a fourth transistor connected in series with a third transistor, thereby making the degradation level of the third transistor of each pixel similar according to the data voltage difference, thereby improving image sticking.

[0028] Furthermore, the fourth transistor functioning as a resistor reduces the source-drain voltage of the third transistor, thereby preventing current leakage from the third transistor to the storage capacitor and bright spots and / or dark spots in the image caused by the current leakage.

[0029] However, the effects of the present disclosure are not limited to the above-mentioned effects, and various extensions can be made within the scope of the idea and field of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0031] Figure 2 is a circuit diagram illustrating a pixel according to an embodiment of the present disclosure.

[0032] Figure 3a and Figure 3b It shows Figure 2 A timing diagram showing an example of pixel operation.

[0033] Figure 4 It is shown that it is included in Figure 1 A circuit diagram of an example of a pixel of a display device.

[0034] Figure 5 and Figure 6 It is shown that it is included in Figure 1 A circuit diagram of an example of a pixel of a display device. DETAILED DESCRIPTION

[0035] The following describes in detail embodiments of the present disclosure, as well as matters necessary for those skilled in the art to facilitate understanding of the present disclosure, with reference to the accompanying drawings. However, the present disclosure can be implemented in a variety of different forms within the scope of the present disclosure, and therefore the embodiments described below, whether expressed or not, are merely illustrative.

[0036] That is, the present disclosure is not limited to the embodiments disclosed below and can be implemented in a variety of different forms. When a part is described as being connected to another part in the following description, it includes not only direct connection but also connection with another element interposed therebetween. In addition, it should be noted that for the same components in the drawings, even if they are shown in different drawings, the same reference numerals and symbols are used as much as possible.

[0037] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0038] Reference Figure 1The display device 1000 may include a pixel portion 100 , a scan driving portion 200 , a light emitting driving portion 300 , a data driving portion 400 , and a timing control portion 500 .

[0039] In one embodiment, the display device 1000 may further include a power supply unit 600 that supplies a first power supply VDD, a second power supply VSS, and an initialization power supply VINT to the pixel unit 100. The power supply unit 600 may supply a low power supply VGL and a high power supply VGH, which determine the voltage levels of scan signals and / or light-emitting control signals, to the scan driver 200 and / or the light-emitting driver 300. The low power supply VGL may have a lower voltage level than the high power supply VGH. However, this is merely exemplary, and at least one of the first power supply VDD, the second power supply VSS, the initialization power supply VINT, the low power supply VGL, and the high power supply VGH may be supplied from the timing control unit 500 or the data driver 400. Furthermore, the first power supply VDD, the second power supply VSS, the initialization power supply VINT, the low power supply VGL, and the high power supply VGH may each be a DC power supply.

[0040] According to an embodiment, the first power supply VDD and the second power supply VSS can generate a voltage for driving the light-emitting element LED. In one embodiment, the voltage of the second power supply VSS can be lower than the voltage of the first power supply VDD. For example, the voltage of the first power supply VDD can be a positive voltage, and the voltage of the second power supply VSS can be a negative voltage.

[0041] The voltage of the initialization power supply VINT can be set to a voltage lower than the lowest voltage of the data signal. The low power supply VGL corresponds to a voltage that turns on the transistors included in the scan driver 200 and the light driver 300, and the high power supply VGH corresponds to a voltage that turns off the transistors included in the scan driver 200 and the light driver 300.

[0042] The pixel unit 100 may include a plurality of scan lines (S1 to Sn), a plurality of emission control lines (E1 to En), and a plurality of data lines (D1 to Dm), and may include a plurality of pixels P (where m and n are integers greater than 1) connected to the scan lines (S1 to Sn), the emission control lines (E1 to En), and the data lines (D1 to Dm), respectively. Each pixel P may include a driving transistor and a plurality of switching transistors.

[0043] The timing control unit 500 generates a first control signal SCS, a second control signal ECS, and a third control signal DCS in response to an externally supplied synchronization signal. The timing control unit 500 may supply the first control signal SCS to the scan driver 200, the second control signal ECS to the light driver 300, and the third control signal DCS to the data driver 400. Furthermore, the timing control unit 500 may rearrange externally supplied image data IDATA and supply it to the data driver 400.

[0044] The first control signal SCS may include a scan start pulse and a clock signal. The scan start pulse can control the first timing of the scan signal. The clock signal can be used to shift the scan start pulse.

[0045] The second control signal ECS may include a light emission control start pulse and a clock signal. The light emission control start pulse can control the first timing of the scan signal. The clock signal can be used to shift the light emission control start pulse.

[0046] The third control signal DCS may include a source start pulse and a clock signal. The source start pulse controls the data sampling starting point. The clock signal is used to control the sampling operation.

[0047] According to an embodiment, the timing control unit 500 can generate a fourth control signal PCS for driving the power supply unit 600. The fourth control signal PCS can control the supply timing of at least one of the first power VDD, the second power VSS, the initialization power VINT, the low power VGL, and the high power VGH.

[0048] The scan driver 200 receives a first control signal SCS from the timing controller 500 and can supply scan signals to the scan lines (S1 to Sn) based on the first control signal SCS. For example, the scan driver 200 can sequentially supply scan signals to the scan lines (S1 to Sn). When the scan signals are sequentially supplied, the pixels P can be selected as horizontal line units (or pixel row units).

[0049] The scan signal may be set to a gate-on voltage (eg, a low voltage). A transistor included in the pixel P and receiving the scan signal may be set to a conductive state when supplied with the scan signal.

[0050] The light driving unit 300 receives the second control signal ECS from the timing control unit 500 and can supply scanning signals to the light control lines (E1 to En) based on the second control signal ECS. For example, the light driving unit 300 can sequentially supply light control signals to the light control lines (E1 to En).

[0051] The light emission control signal may be set to a gate-on voltage (eg, a low voltage). A transistor included in the pixel P and receiving the light emission control signal may be turned on when the light emission control signal is supplied, and may be turned off otherwise.

[0052] The light-emission control signal is used to control the light-emission duration of the pixel P. To this end, the light-emission control signal can be set to a width wider than the scan signal. For example, the scan driver 200 can supply a scan signal to the i-1th scan line Si-1 and the i-th scan line Si so that the gate-off interval of the light-emission control signal supplied to the i-th light-emission control line Ei overlaps (where i is an integer greater than 2 and less than n).

[0053] The scanning driver 200 and the light-emitting driver 300 can be mounted on the substrate using thin film technology. Alternatively, the scanning driver 200 can be positioned with the pixel unit 100 in the middle and positioned on either side. Alternatively, the light-emitting driver 300 can be positioned with the pixel unit 100 in the middle and positioned on either side.

[0054] In addition, Figure 1 2 and 3. In the figure, the scanning driving unit 200 and the light emitting driving unit 300 respectively supply the scanning signal and the light emitting control signal, but the present disclosure is not limited thereto. As an example, the scanning signal and the light emitting control signal may be supplied by one driving unit.

[0055] The data driver 400 can receive a third control signal DCS and image data signals RGB from the timing control unit 500. The data driver 400 can supply data signals to the data lines (D1 to Dm) in response to the third control signal DCS. The data signals supplied to the data lines (D1 to Dm) can be supplied to selected pixels P via scan signals. To this end, the data driver 400 can supply data signals to the data lines (D1 to Dm) in synchronization with the scan signals.

[0056] On the other hand, Figure 1 , n scan lines (S1 to Sn) and n emission control lines (E1 to En) are shown, but the present disclosure is not limited thereto. As an example, corresponding to the circuit structure of pixel P, the pixel P located in the current horizontal line (or current pixel row) can be additionally connected to the scan line located in the previous horizontal line (or previous pixel row) and / or the scan line located in the next horizontal line (or next pixel row). To this end, virtual scan lines and / or virtual emission control lines (not shown) can be additionally formed in the pixel unit 100.

[0057] Figure 2 is a circuit diagram illustrating a pixel according to an embodiment of the present disclosure.

[0058] exist Figure 2For the sake of convenience, the pixel 10 (or P(j, i)) located on the i-th horizontal line (or i-th pixel row) and connected to the j-th data line Dj is shown (wherein i and j are natural numbers).

[0059] Reference Figure 2 , the pixel 10 may include a light emitting element LED, first to eighth transistors T1 to T8 , and a storage capacitor Cst.

[0060] The first electrode of the light-emitting element LED may be connected to one electrode of the eighth transistor T8, and the second electrode may be connected to the second power supply VSS. The light-emitting element LED can generate light of a predetermined brightness corresponding to the amount of current (driving current) supplied from the first transistor T1. In one embodiment, the light-emitting element LED may be an organic light-emitting diode including an organic light-emitting layer. In this case, the first electrode of the light-emitting element LED may be an anode electrode, and the second electrode may be a cathode electrode. Conversely, the first electrode of the light-emitting element LED may be a cathode electrode, and the second electrode may be an anode electrode.

[0061] In other embodiments, the light emitting element LED may be an inorganic light emitting element formed of an inorganic substance. Alternatively, the light emitting element LED may include a plurality of inorganic light emitting elements connected in parallel and / or in series between the second power supply VSS and one electrode of the seventh transistor T7.

[0062] The first transistor T1 may be coupled between a second node N2 electrically connected to a first power source VDD and a third node N3 electrically connected to a first electrode of the light-emitting element LED. The first transistor T1 can generate a drive current and provide it to the light-emitting element LED. The gate electrode of the first transistor T1 may be coupled to the first node N1. The first transistor T1 functions as a drive transistor for the pixel 10.

[0063] The second transistor T2 may be coupled between the data line Dj (the jth data line) and the second node N2. The second transistor T2 may include a gate electrode that receives a scan signal. For example, the gate electrode of the second transistor T2 may be connected to the first scan line S1i of the i-th pixel row. The second transistor T2 is turned on when the scan signal is supplied to the first scan line S1i, and can electrically connect the data line Dj to the second node N2. Therefore, the data voltage DATA (or data signal) can be transmitted to the second node N2.

[0064] The storage capacitor Cst is connected between the first power source VDD and the first node N1 and can store the data voltage DATA (and a voltage corresponding to the threshold voltage of the first transistor T1).

[0065] The fifth transistor T5 may be coupled between the first power source VDD and the second node N2. The fifth transistor T5 may include a gate electrode receiving a light emission control signal. The gate electrode of the fifth transistor T5 may be connected to the light emission control line Ei.

[0066] The sixth transistor T6 may be coupled between the third node N3 and the first electrode of the light emitting element LED. The sixth transistor T6 may include a gate electrode receiving a light emitting control signal. The gate electrode of the sixth transistor T6 may be connected to the light emitting control line Ei.

[0067] The fifth transistor T5 and the sixth transistor T6 may be turned on during a gate-on period (eg, a logic low level period) of the light emitting control signal, and may be turned off during a gate-off period (eg, a logic high level period).

[0068] The seventh transistor T7 may be coupled between the first node N1 and the initialization power source VINT. The seventh transistor T7 may include a gate electrode connected to the second scan line S2i of the i-th pixel row.

[0069] The seventh transistor T7 can be turned on when a scan signal is supplied to the second scan line S2i, supplying the voltage of the initialization power supply VINT to the first node N1. Thus, the voltage of the first node N1, i.e., the gate voltage of the first transistor T1, can be initialized to the voltage of the initialization power supply VINT. In one embodiment, the initialization power supply VINT can be set to a voltage lower than the lowest voltage of the data voltage DATA.

[0070] The eighth transistor T8 may be coupled between the initialization power source VINT and the first electrode of the light emitting element LED. The eighth transistor T8 may include a gate electrode connected to the third scan line S3i of the i-th pixel row.

[0071] The eighth transistor T8 is turned on when a scan signal is supplied to the third scan line S3i, supplying a voltage of the initialization power supply VINT to the first electrode of the light-emitting element LED. Supplying the voltage of the initialization power supply VINT to the first electrode of the light-emitting element LED discharges the parasitic capacitance of the light-emitting element LED. Discharging the parasitic capacitance improves the black rendering of the pixel 10.

[0072] The third transistor T3 may be electrically coupled between the first node N1 and the third node N3. The third transistor T3 may include a gate electrode connected to the first scan line S1i. Specifically, the third transistor T3 may be directly coupled between the first node N1 and the fourth node N4.

[0073] The third transistor T3 can be turned on when a scan signal is supplied to the first scan line S1i, electrically connecting the gate electrode of the first transistor T1 and the third node N3. Therefore, when the third transistor T3 is turned on, the first transistor T1 can be connected in a diode-like manner. In other words, the third transistor T3 can perform the functions of writing the data voltage DATA and threshold voltage compensation for the first transistor T1.

[0074] On the other hand, in the case of a pixel 10 composed of a PMOS (P-channel metal oxide semiconductor) transistor, the black data voltage is set to be greater than the white data voltage. As an example, the black data voltage can be set to approximately 6.6V and the white data voltage can be set to approximately 3V. The black data voltage is the data voltage DATA corresponding to a black image, and the white data voltage is the data voltage DATA corresponding to a white image.

[0075] Therefore, a degradation rate may be different between pixels supplied with a black data voltage and pixels supplied with a white data voltage, thereby possibly causing image sticking.

[0076] This degradation deviation and image sticking are significantly affected by the deviation between the gate-source voltage (e.g., Vgs) of the third transistor T3 when a black data voltage is applied and the gate-source voltage of the third transistor T3 when a white data voltage is applied. For example, when a black data voltage is applied, the difference between the gate-source voltage (e.g., Vgs) of the third transistor T3 in an on-bias state (or a conductive state) and the gate-source voltage of the third transistor T3 in an off-bias state (or a disconnected state) can be calculated using a first delta. When a white data voltage is applied, the deviation between the gate-source voltage of the third transistor T3 in an on-bias state and the gate-source voltage of the third transistor T3 in an off-bias state can be calculated using a second delta.

[0077] Due to fluctuations in the gate-source voltage of the third transistor T3, the third transistor T3 degrades. Furthermore, due to variations in the first delta and the second delta, the level of degradation may vary from pixel to pixel. Therefore, the greater the variation between the first delta and the second delta, the more susceptible the pixel is to image sticking.

[0078] The first delta and the second delta can be adjusted by reducing the difference between the gate-source voltage of the third transistor T3 corresponding to the white data voltage and the black data voltage, respectively. For example, in the on-bias state, if the difference between the gate-source voltage of the third transistor T3 caused by the application of the black data voltage and the gate-source voltage of the third transistor T3 caused by the application of the white data voltage is reduced, the degradation deviation can be improved.

[0079] To improve such degradation deviation and image sticking, the fourth transistor T4 may be connected between the third transistor T3 (or the fourth node N4) and the third node N3. That is, the fourth transistor T4 may be connected in series with the third transistor T3 between the first node N1 and the third node N3.

[0080] The fourth transistor T4 can remain in an on state at all times. The gate electrode of the fourth transistor T4 can be connected to a DC power supply having a voltage level that turns on the fourth transistor T4. In one embodiment, the gate electrode of the fourth transistor T4 can be connected to a second power supply VSS. The second power supply VSS can have a negative voltage level that can turn on the fourth transistor T4. For example, the second power supply VSS can be approximately -4.5V.

[0081] The fourth transistor T4 can remain in the on state at all times, acting as a predetermined resistor. Therefore, the voltage of the first electrode of the third transistor T3, i.e., the voltage of the fourth node N4, can decrease. As a result, the source voltage of the third transistor T3 decreases, and the absolute value of the gate-source voltage of the third transistor T3 in the on-bias state can be reduced. In particular, in the on-bias state, the absolute value of the gate-source voltage of the third transistor T3 caused by the black data voltage (e.g., |Vgs|) can be relatively significantly reduced by the fourth transistor T4 acting as a resistor. At this point, even if the fourth transistor T4 is added to the pixel 10, the gate-source voltage of the third transistor T3 in the off-bias state does not change.

[0082] As a result, in the on-bias state, the deviation between the gate-source voltage of the third transistor T3 caused by the black data voltage and the gate-source voltage of the third transistor T3 caused by the white data voltage can be reduced. Furthermore, the fluctuation range of the gate-source voltage of the third transistor T3 due to repeated on / off switching is reduced, thereby reducing the stress (degradation) applied to the third transistor T3. As a result, the degradation level of the third transistor T3 caused by the black data voltage and the degradation level of the third transistor T3 caused by the white data voltage can be made similar. Therefore, image sticking can be improved.

[0083] Furthermore, the absolute value of the source-drain voltage (eg, |Vsd|) of the third transistor T3 is reduced by the fourth transistor T4 functioning as a resistor, thereby preventing current leakage through the third transistor T3 (particularly, Figure 5 and / or dark spots of an image according to the current leakage.

[0084] On the other hand, Figure 2 1 and 2. The transistors (T1 to T8) included in the pixel 10 are shown as P-type transistors, but the type of the transistors is not limited thereto. For example, at least some of the transistors (T1 to T8) may be N-type transistors.

[0085] Figure 3a and Figure 3b It shows Figure 2 A timing diagram showing an example of pixel operation.

[0086] Reference Figures 2 to 3b , a scan signal (low voltage) can be supplied to the first scan line S1i, the second scan line S2i, and the third scan line S3i during a period in which the light emitting control signal supplied to the light emitting control line Ei has a gate-off voltage (high voltage).

[0087] If the fifth transistor T5 and the sixth transistor T6 are turned off by the light emission control signal, the electrical connection between the first power supply VDD and the second node N2 is cut off. Therefore, during the period when the light emission control signal has the gate-off voltage, the pixel 10 can be set to a non-light emitting state.

[0088] Afterwards, a scan signal may be supplied to the second scan line S2i. For example, the second scan line S2i may be the same as the first scan line (e.g., S1i-1) of the previous pixel row (e.g., the i-1th pixel row). Alternatively, a scan signal may be supplied to both the second scan line S2i and the first scan line (e.g., S1i-1) of the previous pixel row. When the scan signal is supplied to the second scan line S2i, the seventh transistor T7 is turned on, enabling the voltage of the initialization power supply VINT to be supplied to the first node N1.

[0089] In one embodiment, if Figure 3a As shown, the scan signal can be supplied to the third scan line S3i and the second scan line S2i simultaneously. For example, the third scan line S3i and the second scan line S2i can be the same scan line. When the scan signal is supplied to the third scan line S3i, the eighth transistor T8 can be turned on. When the eighth transistor T8 is turned on, the voltage of the initialization power supply VINT can be supplied to the first electrode of the light-emitting element LED.

[0090] Afterwards, a scan signal is supplied to the first scan line S1i, turning on the second transistor T2 and the third transistor T3. If the second transistor T2 is turned on, the data voltage DATA can be supplied to the second node N2. If the third transistor T3 is turned on, the first transistor T1 can be connected in a diode-like manner. At this time, the fourth transistor T4 remains in the on state, and the voltage of the fourth node N4 can be different from the voltage of the third node N3. For example, the voltage of the fourth node N4 can be lower than the voltage of the third node N3.

[0091] If the first transistor T1 is turned on, the data voltage DATA supplied to the second node N2 is supplied to the first node N1 via the diode-connected first transistor T1. The storage capacitor Cst may store the voltage applied to the first node N1.

[0092] After the voltage of the first node N1 is stored in the storage capacitor Cst, a light emission control signal may be supplied to the light emission control line Ei. If the light emission control signal is supplied to the light emission control line Ei, the fifth transistor T5 and the sixth transistor T6 may be turned on.

[0093] At this time, the first transistor T1 can control the amount of driving current flowing from the first power source VDD to the second power source VSS via the light emitting element LED according to the voltage of the first node N1.

[0094] On the other hand, in one embodiment, Figure 3b As shown, after the scan signal is supplied to the first scan line S1i, the scan signal can be supplied to the third scan line S3i. In this case, the third scan line S3i can be the same as the first scan line (e.g., S1i+1) of the next pixel row (e.g., the i+1th pixel row). However, this is merely illustrative, and the third scan line S3i can also be replaced by the first scan line S1i of the i-th pixel row.

[0095] Figure 4 It is shown that Figure 1 A circuit diagram of an example of a pixel of a display device.

[0096] exist Figure 4 In the reference Figure 2 The same reference numerals are used for the components described, and repeated descriptions of these components are omitted. Figure 4 If the third transistor is removed from the pixel, the pixel can have Figure 2 The pixels have substantially the same or similar structure.

[0097] Reference Figure 4 The third transistor T3 included in the pixel 10 may include a plurality of third transistors T3_1 and T3_2 connected in series with each other.

[0098] The third transistors T3_1 and T3_2 may be connected in series between the first node and the fourth transistor T4 (or the fourth node N4 ), and gate electrodes of the third transistors T3_1 and T3_2 may be commonly connected to the first scan line S1i.

[0099] The series connection of the third transistors T3_1 and T3_2 prevents leakage current from flowing through the off-state third transistors T3_1 and T3_2. However, due to process limitations, the third transistors T3_1 and T3_2 do not have identical device characteristics. Therefore, when a scan signal is supplied to the first scan line S1i, the third transistors T3_1 and T3_2 may turn on at different times. This can cause undesirable current leakage because the source-drain voltage of the third transistor T3 is asymmetrically split between the third transistors T3_1 and T3_2.

[0100] Thus, a fourth transistor T4, which is always on, can be connected between the fourth node N4 and the third node N4. The fourth transistor T4 acts as a resistor, thereby making the degradation level of the third transistor T3 uniform across all pixels 10 depending on the magnitude of the data voltage. This improves image sticking.

[0101] Figure 5 and Figure 6 It is shown that Figure 1 A circuit diagram of an example of a pixel of a display device.

[0102] exist Figure 5 and Figure 6 In the reference Figure 2 The same reference numerals are used for the components described, and repeated descriptions of these components are omitted. Figure 5 and Figure 6 If the fourth transistor is removed from the pixel, the pixel can have Figure 2 The pixels have substantially the same or similar structure.

[0103] Reference Figure 5 and Figure 6 , the fourth transistor T4 included in the pixel 10 may be connected between the third node N3 and the fourth node N4.

[0104] The fourth transistor T4 can always remain in the on state. Figure 5 As shown, the gate electrode of the fourth transistor T4 can be connected to the initialization power supply VINT. Figure 6 As shown, the gate electrode of the fourth transistor T4 can be connected to the low power source VGL. The low power source VGL can be supplied to the scan driving unit (eg, Figure 1 200) of DC power supply.

[0105] According to an embodiment, the initialization power supply VINT and the low power supply VGL may have a voltage level lower than the second power supply VSS. For example, the initialization power supply VINT may be about -5V to about -10V, and the low power supply VGL may be about -8V to about -13V. Therefore, the fourth transistor T4 can maintain a more stable on state.

[0106] As described above, the pixel 10 and the display device including the same according to the embodiment of the present disclosure (eg, Figure 1 The fourth transistor T4 is connected in series with the third transistor T3, so that the degradation level of the third transistor T3 in each pixel 10 can be made similar according to the difference in data voltage. Therefore, image sticking can be improved.

[0107] In addition, the source-drain voltage of the third transistor T3 is reduced by the fourth transistor T4, thereby preventing the current from leaking through the third transistor T3 (especially, Figure 5 a current leakage according to the series connection structure of the third transistor) and a bright spot and / or a dark spot of an image according to the current leakage.

[0108] The above description is made with reference to the embodiments of the present disclosure, but it should be understood that those skilled in the art can make various modifications and changes to the present disclosure without departing from the scope of the ideas and fields of the present disclosure described in the present disclosure.

Claims

1. A pixel, wherein include: Light-emitting element; a first transistor for controlling an amount of current flowing from the first power source to the second power source via the light emitting element in response to a voltage applied to the first node; a second transistor connected between the data line and a second node corresponding to the first electrode of the first transistor, and a gate electrode of the second transistor connected to the first scan line; a third transistor connected between the first node and a third node corresponding to the second electrode of the first transistor, and a gate electrode of the third transistor connected to the first scan line; as well as The fourth transistor is connected between the third transistor and the third node and is always in an on state.

2. The pixel according to claim 1, wherein The third transistor and the fourth transistor are connected in series between the first node and the third node.

3. The pixel according to claim 1, wherein The fourth transistor includes a gate electrode connected to a DC power source that turns on the fourth transistor.

4. The pixel according to claim 3, wherein: The gate electrode of the fourth transistor is connected to the second power source.

5. The pixel according to claim 1, wherein The third transistor includes a plurality of third transistors connected in series with each other between the first node and the fourth transistor, Gate electrodes of the plurality of third transistors are commonly connected to the first scan line.

6. The pixel according to claim 1, wherein The pixel further comprises: a fifth transistor connected between the first power source and the second node, wherein a gate electrode of the fifth transistor is connected to a light emitting control line; a sixth transistor connected between the third node and the light emitting element, wherein a gate electrode of the sixth transistor is connected to the light emitting control line; and A storage capacitor is connected between the first power source and the first node.

7. The pixel according to claim 6, wherein: The pixel further comprises: a seventh transistor connected between the first node and an initialization power source, wherein a gate electrode of the seventh transistor is connected to a second scan line; and An eighth transistor is connected between the light emitting element and the initialization power source, and a gate electrode of the eighth transistor is connected to a third scan line.

8. The pixel according to claim 7, wherein: The fourth transistor includes a gate electrode connected to the initialization power source.

9. The pixel according to claim 7, wherein: The second scan line and the third scan line are the same scan line as each other.

10. A display device, wherein: include: Pixels are positioned so as to be connected to scan lines, light-emitting control lines, and data lines; a scan driving unit for supplying a scan signal to the pixel through the scan line; a light-emitting driving unit, supplying a light-emitting control signal to the pixel through the light-emitting control line; as well as a data driving unit that supplies data signals to the pixels through the data lines; The pixels in the i-th row and j-th column of the pixels include: Light-emitting element; a first transistor for controlling an amount of current flowing from the first power source to the second power source via the light emitting element in response to a voltage applied to the first node; a second transistor connected between the jth data line and a second node corresponding to the first electrode of the first transistor, and a gate electrode of the second transistor connected to the first scan line of the i-th pixel row; a third transistor connected between the first node and a third node corresponding to the second electrode of the first transistor, and a gate electrode of the third transistor connected to the first scan line of the i-th pixel row; and a fourth transistor connected between the third transistor and the third node and always kept in an on state; Among them, i and j are natural numbers.

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