Current Sensor Test System

Abstract

The present invention provides a current sensor test system, which includes: a capacitor C with its positive terminal connected to the first node A; a signal generator that outputs a pulse signal; a current setting circuit connected to the second node B, which sets the current value flowing through itself based on the amplitude of the pulse signal; a current-carrying conductor connected between the third node E and the fourth node F, wherein a reference current sensor and a to-be-tested current sensor are connected in series on the current-carrying conductor; a switching network connected between the first node A, the second node B, the third node E, and the fourth node F, which is configured to control the direction of the current flowing through the current-carrying conductor; a first detection unit for collecting the output of the reference current sensor; and a second detection unit for collecting the output of the to-be-tested current sensor. In this way, the present invention uses a pulsed current as the measured current, greatly suppressing the generation of Joule heat, thereby ensuring the stability of the test system and improving the test accuracy.

Description

Technical Field

[0001] The present invention relates to the field of current sensor testing, and particularly to a current sensor testing system based on pulse current generated by capacitor discharge.

Background Art

[0002] Traditional current sensor testing systems generate a constant current through a DC power supply, which has two disadvantages: on the one hand, it has high requirements for the driving ability of the DC power supply; on the other hand, in the case of large currents, a large amount of Joule heat will be generated, thus affecting the stability of the system.

[0003] Therefore, it is necessary to propose a technical solution to overcome the above problems.

Summary of the Invention

[0004] One of the objectives of the present invention is to provide a current sensor testing system, which uses a pulse current as the measured current, greatly suppressing the generation of Joule heat, thus ensuring the stability of the testing system and improving the testing accuracy.

[0005] According to one aspect of the present invention, a current sensor testing system is provided, which includes: a capacitor C with its positive terminal connected to the first node A; a signal generator that outputs a pulse signal; a current setting circuit connected to the second node B, which sets the current value flowing through itself based on the amplitude of the pulse signal; a current-carrying conductor connected between the third node E and the fourth node F, where a reference current sensor and a to-be-tested current sensor are connected in series on the current-carrying conductor; a switching network connected between the first node A, the second node B, the third node E, and the fourth node F, which is configured to control the direction of the current flowing through the current-carrying conductor; a first detection unit for collecting the output of the reference current sensor; and a second detection unit for collecting the output of the to-be-tested current sensor.

[0006] Compared with the prior art, in the current sensor testing system of the present invention, a signal generator is used to control the capacitor to discharge and generate a pulse current, and this pulse current serves as the measured current flowing through the reference current sensor and the to-be-tested current sensor, greatly suppressing the generation of Joule heat, thus ensuring the stability of the testing system and improving the testing accuracy.

Description of the Drawings

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. Among them:

[0008] Figure 1Schematic diagram of the current sensor test system based on capacitor discharge in one embodiment of the present invention;

[0009] Figure 2 is Figure 1 The timing of signals at each port of the current sensor test system shown in the case of generating a positive current in one embodiment;

[0010] Figure 3 It is a curve showing the dependence of the output of the current sensor under test measured by the typical current sensor test system in the present invention on the current obtained by the reference current sensor.

Specific Embodiments

[0011] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0012] As used herein, "one embodiment" or "embodiment" refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that excludes other embodiments. Unless otherwise specified, the terms "connected", "coupled", and "joined" indicating electrical connection herein all mean direct or indirect electrical connection.

[0013] Please refer to Figure 1 shown, which is a schematic diagram 100 of the current sensor test system based on capacitor discharge in one embodiment of the present invention. Figure 1 The current sensor test system 100 shown includes a signal generator 101, a current setting circuit 108, a first detection unit 102, a second detection unit 103, a capacitor C, a switch network 107 for controlling the current direction, a reference current sensor 104, a current sensor under test 105, and a current-carrying conductor 106.

[0014] Among them, the positive terminal of the capacitor C is connected to the first node A, and the negative terminal of the capacitor C is connected to the ground terminal. The first detection unit 102 is used to collect the output of the reference current sensor 104; the second detection unit 103 is used to collect the output of the current sensor to be measured 105; the current-carrying conductor 106 is connected between the third node E and the fourth node F, and the reference current sensor 104 and the current sensor to be measured 105 are connected in series on the current-carrying conductor 106. The switching network 107 is connected between the first node A, the second node B, the third node E and the fourth node F, and is used to control the direction of the current flowing through the current-carrying conductor 106. For example, flowing from the third node E to the fourth node F, or flowing from the fourth node F to the third node E. The signal generator 101 outputs a pulse signal. The current setting circuit 108 is connected to the second node B, and sets the current value flowing through itself based on the amplitude of the pulse signal. Based on the output of the first detection unit 102, the reference current (or true current) measured by the reference current sensor 104 is obtained. Based on the output of the second detection unit 103, the measured current measured by the current sensor to be measured 105 is obtained, and then the dependence relationship between the measured current and the reference current is obtained, such as Figure 3 As shown, that is, the dependence relationship curve of the output of the current sensor to be measured on the current obtained by the reference current sensor.

[0015] The current setting circuit 108 includes an operational amplifier OPAMP, a feedback MOS transistor NMOS3, and a load resistor R. The first connection end of the feedback MOS transistor NMOS3 is connected to the second node B, and its second connection end is grounded through the load resistor R; the first input end of the operational amplifier OPAMP is used to receive the pulse signal, its second input end is connected to the connection node between the second connection end of the feedback MOS transistor NMOS3 and the load resistor R, and its output end is connected to the control end of the feedback MOS transistor NMOS3.

[0016] In Figure 1 In the specific embodiment shown, the feedback MOS transistor NMOS3 is an NMOS transistor, and the first connection end, the second connection end, and the control end of the feedback MOS transistor NMOS3 are the drain, source, and gate of the NMOS transistor respectively; the first input end and the second input end of the operational amplifier OPAMP are the non-inverting input end and the inverting input end respectively; the first detection unit 102 is a first multimeter, and the second detection unit 103 is a second multimeter.

[0017] In one embodiment, the switch network 107 operates in a first switch combination state or a second switch combination state. In the first switch combination state, the first node A is connected to the third node E, the first node A is disconnected from the fourth node F, the second node B is connected to the fourth node F, and the second node B is disconnected from the third node E. At this time, the current sensor test system 100 performs a positive current test, and the measured current flows from the third node E to the fourth node F. In the second switch combination state, the first node A is disconnected from the third node E, the first node A is connected to the fourth node F, the second node B is disconnected from the fourth node F, and the second node B is connected to the third node E. At this time, the current sensor test system 100 performs a negative current test, and the measured current flows from the fourth node F to the third node E.

[0018] Specifically, the switch network 107 includes a first switch connected between the first node A and the third node E, a second switch connected between the first node A and the fourth node F, a third switch connected between the second node B and the third node E, and a fourth switch connected between the second node B and the fourth node F. In the first switch combination state, the first switch is turned on, the second switch is turned off, the fourth switch is turned on, and the third switch is turned off. In the second switch combination state, the first switch is turned off, the second switch is turned on, the fourth switch is turned off, and the third switch is turned on. The switch network 107 is controlled by a first control signal V C1 and a second control signal V C2 to operate in the first switch combination state or the second switch combination state.

[0019] More specifically, the first switch is a first PMOS transistor PMOS1, the second switch is a second PMOS transistor PMOS2, the third switch is a second NMOS transistor NMOS2, and the fourth switch is a first NMOS transistor NMOS1. The drain of the first PMOS transistor PMOS1, the drain of the second NMOS transistor NMOS2, and the third node E are interconnected; the drain of the second PMOS transistor PMOS2, the drain of the first NMOS transistor NMOS1, and the fourth node F are interconnected; the sources of the first PMOS transistor PMOS1 and the second PMOS transistor PMOS2 are connected to the first node A; the sources of the first NMOS transistor NMOS1 and the second NMOS transistor NMOS2 are connected to the second node B. The switch network 107 further includes a first inverter INV1 and a second inverter INV2. The first control signal V C1 is respectively interconnected with the input terminal of the first inverter INV1 and the gate of the first NMOS transistor NMOS1, and the output terminal of the first inverter INV1 is interconnected with the gate of the first PMOS transistor PMOS1; the second control signal V C2They are respectively interconnected with the input end of the second inverter INV2 and the gate of the second NMOS transistor NMOS2, and the output end of the second inverter INV2 is interconnected with the gate of the second PMOS transistor PMOS2.

[0020] As Figure 2 (a), 2(b) shows that when the first control signal V C1 is a pulse signal and the second control signal V C2 is at a low level, the switching network 107 operates in the first switching combination state. When the first control signal V C1 is at a low level and the second control signal V C2 is a pulse signal, the switching network 107 operates in the second switching combination state. Referring to Figure 2 (c), the pulse signal output by the signal generator 101 is synchronized with the pulse signal of the control signal VC1 or VC2.

[0021] In one embodiment, the synchronization terminal Sync of the signal generator 101 is interconnected with the external trigger terminal Ext Trig of the first detection unit 102 and the external trigger terminal Ext Trig of the second detection unit 103. The output terminal Output of the reference current sensor 104 is interconnected with the positive input terminal Input HI of the first detection unit 102, and its ground terminal GND is interconnected with the negative input terminal Input LO of the first detection unit 102. The output terminal Output of the current sensor under test 105 is interconnected with the positive input terminal Input HI of the second detection unit 103, and its ground terminal GND is interconnected with the negative input terminal Input LO of the second detection unit 103. When the current sensor test system performs a positive current test or a negative current test, the signal generator 101 outputs a pulse signal to the operational amplifier OPAMP of the current setting circuit 108, and its synchronization terminal Sync outputs a synchronization signal to the external trigger terminal Ext Trig of the first detection unit 102 and the external trigger terminal Ext Trig of the second detection unit 103 to trigger the first detection unit 102 to synchronously collect the output of the reference current sensor 104 and trigger the second detection unit 103 to synchronously collect the output of the current sensor under test 105.

[0022] When the current sensor test system 100 performs a positive current test, the waveforms of the pulse signals of the control signals V C1 and V C2 are as shown in Figure 2 (a) and 2(b), V C1 is a high-level pulse, V C2is at a low level. At this time, the first node A is connected to the third node E, the fourth node F is connected to the second node B, and the non-inverting input terminal of the operational amplifier OPAMP receives a pulse signal (waveform as shown in Figure 2 (c)) output by the signal generator 101; the capacitor C discharges to generate a pulse current, and the pulse current flows from the positive terminal of the capacitor C through the third node E, the fourth node F, the feedback transistor NMOS3, and the load resistor R to the ground terminal GND in sequence; at the same time, the signal generator 101 outputs a synchronization signal (as shown in Figure 2 (d)), and the first detection unit 102 synchronously collects the output of the reference current sensor 104, as shown in Figure 2 (f); the second detection unit 103 synchronously collects the output of the current sensor to be measured 105, as shown in Figure 2 (g). Please refer to Figure 2 shown, which is the timing diagram 200 of each port signal of the current sensor test system 100 shown in Figure 1 in one embodiment when generating a positive current.

[0023] Specifically, when the first control signal V C1 is a high-level pulse and the second control signal V C2 is at a low level, the Output terminal (output terminal) of the signal generator 101 generates a pulse signal v I [as shown in Figure 2 (c)], as the input signal of the non-inverting terminal of the operational amplifier OPAMP. The existence of the feedback transistor NMOS3 makes the input signal v - of the inverting terminal of the operational amplifier OPAMP equal to v I [as shown in Figure 2 (e)]. The pulse current flowing into the current-carrying conductor 106 is I = v - / R = v I / R. The pulse current is generated by the discharge of the capacitor C and flows through the first PMOS transistor PMOS1, the third node E, the fourth node F, the first NMOS transistor NMOS1, the feedback transistor NMOS3, the load resistor R in sequence, and finally flows into the ground terminal GND; the Sync terminal (synchronization terminal) of the signal generator 101 generates a synchronization signal [as shown in Figure 2 (d)], as the Ext Trig (external trigger) of the first multimeter 102 and the second multimeter 103. After a trigger delay, the first multimeter 102 collects the output of the reference current sensor 104 [as shown in Figure 2 (f)], and the second multimeter 103 collects the output of the current sensor to be measured 105. The signal generator 101 can form pulse currents with different current values on the current setting circuit 108 by controlling the amplitude of the output pulse signal v I .

[0024] When the current sensor test system 100 performs a negative current test, V C1 is at a low level, and V C2 is a high-level pulse. The switching network 107 connects the first node A and the fourth node F, and the third node E and the second node B. The non-inverting input terminal of the operational amplifier OPAMP receives a pulse signal output by the signal generator 101. The capacitor C discharges to generate a pulse current, and the pulse current flows from the positive terminal of the capacitor C through the fourth node F, the third node E, the feedback transistor NMOS3, and the load resistor R to the ground terminal GND in sequence. The first detection unit 102 collects the output of the reference current sensor 104. The second detection unit 103 collects the output of the current sensor 105 to be measured.

[0025] More specifically, the process of the current sensor test system 100 generating a negative current is as follows: The first control signal V C1 is at a low level, causing the first PMOS transistor PMOS1 and the first NMOS transistor NMOS1 to be in a cut-off state. The second control signal VC2 is a high-level pulse, causing the second PMOS transistor PMOS2 and the second NMOS transistor NMOS2 to be in a conducting state. When the first control signal V C1 is at a low level and the second control signal V C2 is a high-level pulse, the Output terminal of the signal generator 101 generates a pulse signal v I , which is used as the input signal of the non-inverting terminal of the operational amplifier OPAMP. The existence of the feedback transistor NMOS3 makes the input signal v - of the inverting terminal of the operational amplifier OPAMP equal to v I . The pulse current flowing into the current-carrying conductor 106 is I = v- / R = v I / R. The pulse current is generated by the discharge of the capacitor C and flows into the second PMOS transistor PMOS2 in sequence, flows in from the other end F of the current-carrying conductor 106, flows out from one end E of the current-carrying conductor 107, flows into the second NMOS transistor NMOS2, the feedback transistor NMOS3, and the load resistor R, and then flows into the ground terminal GND. The Sync terminal of the signal generator 101 generates a synchronization signal, which is used as the Ext Trig (external trigger) of the first multimeter 102 and the second multimeter 103. After a trigger delay, the first multimeter 102 collects the output of the reference current sensor 104, and the second multimeter 103 collects the output of the current sensor 105 to be measured.

[0026] The electrical connections between the first detection unit 102, the second detection unit 103, the signal generator 101, and the current setting circuit 108 can be realized through coaxial cables.

[0027] The true current (or measured current) can be obtained by referring to the output of the reference current sensor 104, so as to obtain the dependence of the output of the current sensor 105 to be measured on the true current. Please refer to Figure 3 As shown, it is the dependence curve 300 of the output of the current sensor 105 to be measured on the current obtained by the reference current sensor 104 measured by a typical current sensor test system in the present invention, which includes a part where the measured current is negative and a part where the measured current is positive.

[0028] Compared with the prior art, in the current sensor test system of the present invention, the signal generator 101 controls the capacitor C to discharge to generate a pulsed current. The positive and negative (or flow direction) of the pulsed current can be regulated by the switch network 107 that controls the current direction. The magnitude of the pulsed current can be controlled by the amplitude of the pulsed signal generated by the signal generator 101, which greatly suppresses the generation of Joule heat, thus ensuring the stability of the test system and improving the test accuracy.

[0029] In the present invention, words indicating electrical connection such as "connected", "linked", "joined", "connected", etc., without special explanation, mean direct or indirect electrical connection.

[0030] The above is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment. Any equivalent modification or change made by those of ordinary skill in the art according to the disclosure of the present invention should be included in the protection scope recorded in the claims.

Claims

1. A current sensor testing system, characterized in that, It includes: A capacitor C with its positive terminal connected to the first node A; A signal generator that outputs a pulse signal; A current setting circuit connected to the second node B, which sets the current value flowing through itself based on the amplitude of the pulse signal; A current-carrying conductor connected between the third node E and the fourth node F, where a reference current sensor and a current sensor to be measured are connected in series on the current-carrying conductor; A switching network connected between the first node A, the second node B, the third node E, and the fourth node F, which is configured to control the direction of the current flowing through the current-carrying conductor; A first detection unit for collecting the output of the reference current sensor; A second detection unit for collecting the output of the current sensor to be measured.

2. The current sensor test system according to claim 1, wherein, Based on the output of the first detection unit, obtain the reference current measured by the reference current sensor, and based on the output of the second detection unit, obtain the measured current measured by the current sensor to be measured, thereby obtaining the dependence relationship between the measured current and the reference current.

3. The current sensor test system according to claim 1, wherein The current setting circuit includes an operational amplifier OPAMP, a feedback MOS transistor NMOS3, and a load resistor R. The first connection end of the feedback MOS transistor NMOS3 is connected to the second node B, and its second connection end is grounded through the load resistor R. The first input terminal of the operational amplifier OPAMP is used to receive the pulse signal, its second input terminal is connected to the connection node between the second connection end of the feedback MOS transistor NMOS3 and the load resistor R, and its output terminal is connected to the control end of the feedback MOS transistor NMOS3.

4. The current sensor test system according to claim 3, characterized in that, The feedback MOS transistor NMOS3 is an NMOS transistor, and the first connection end, the second connection end, and the control end of the feedback MOS transistor NMOS3 are respectively the drain, source, and gate of the NMOS transistor; The first input terminal and the second input terminal of the operational amplifier OPAMP are respectively the non-inverting input terminal and the inverting input terminal; The first detection unit is a first multimeter, and the second detection unit is a second multimeter.

5. The current sensor test system according to claim 1, characterized in that, The switching network operates in a first switch combination state or a second switch combination state. In the first switch combination state, the first node A and the third node E are connected, the first node A is disconnected from the fourth node F, the second node B and the fourth node F are connected, and the second node B is disconnected from the third node E. In the second switch combination state, the first node A and the third node E are disconnected, the first node A is connected to the fourth node F, the second node B and the fourth node F are disconnected, and the second node B is connected to the third node E.

6. The current sensor testing system according to claim 5, characterized in that, The switching network includes a first switch connected between a first node A and a third node E, a second switch connected between the first node A and a fourth node F, a third switch connected between a second node B and the third node E, and a fourth switch connected between the second node B and the fourth node F. In the first switch combination state, the first switch is turned on, the second switch is turned off, the fourth switch is turned on, and the third switch is turned off. In the second switch combination state, the first switch is turned off, the second switch is turned on, the fourth switch is turned off, and the third switch is turned on. The switch network is controlled by a first control signal V C1 and a second control signal V C2 to operate in a first switch combination state or a second switch combination state.

7. The current sensor testing system according to claim 6, wherein The first switch is a first PMOS transistor PMOS1, the second switch is a second PMOS transistor PMOS2, the third switch is a second NMOS transistor NMOS2, and the fourth switch is a first NMOS transistor NMOS1. The drain of the first PMOS transistor PMOS1, the drain of the second NMOS transistor NMOS2, and the third node E are interconnected; the drain of the second PMOS transistor PMOS2, the drain of the first NMOS transistor NMOS1, and the fourth node F are interconnected; the sources of the first PMOS transistor PMOS1 and the second PMOS transistor PMOS2 are connected to the first node A; the sources of the first NMOS transistor NMOS1 and the second NMOS transistor NMOS2 are connected to the second node B.

8. The current sensor testing system according to claim 7, wherein The switching network further includes a first inverter INV1 and a second inverter INV2. The first control signal V C1 are respectively interconnected with the input terminal of the first inverter INV1 and the gate of the first NMOS transistor NMOS1, and the output terminal of the first inverter INV1 is interconnected with the gate of the first PMOS transistor PMOS1; the second control signal V C2 are respectively interconnected with the input terminal of the second inverter INV2 and the gate of the second NMOS transistor NMOS2, and the output terminal of the second inverter INV2 is interconnected with the gate of the second PMOS transistor PMOS2.

9. The current sensor testing system according to claim 8, wherein The first control signal V C1 is a pulse signal. When the second control signal V C2 is at a low level, the switching network operates in the first switching combination state. When the first control signal V C1 is at a low level and the second control signal V C2 is a pulse signal, the switching network operates in the second switching combination state, and the pulse signal output by the signal generator is synchronized with the pulse signal of the control signal.

10. The current sensor testing system according to claim 1, characterized in that, The synchronization terminal of the signal generator is interconnected with the external trigger terminals of the first detection unit and the second detection unit. The output terminal of the reference current sensor is interconnected with the positive input terminal of the first detection unit, and its ground terminal GND is interconnected with the negative input terminal of the first detection unit; the output terminal of the current sensor to be tested is interconnected with the positive input terminal of the second detection unit, and its ground terminal GND is interconnected with the negative input terminal of the second detection unit.

11. The current sensor testing system according to claim 10, wherein When the current sensor testing system performs a positive current test or a negative current test, the signal generator outputs a pulse signal to the current setting circuit, and its synchronization terminal outputs a synchronization signal to the external trigger terminals of the first detection unit and the second detection unit to trigger the first detection unit to collect the output of the reference current sensor and trigger the second detection unit to collect the output of the current sensor to be tested.

12. The current sensor testing system according to claim 1, wherein The magnitude of the pulse signal generated by the signal generator controls the magnitude of the current flowing through the current setting circuit. The negative terminal of the capacitor C is connected to the ground.

Images