Method and device for scheduling microinstruction sequence

Abstract

The present application discloses a method and device for scheduling a microinstruction sequence, the method comprising: when a first command is received, executing a first microinstruction sequence corresponding to the first command; when a second command is received, if the first microinstruction sequence is being executed, pausing the first microinstruction sequence; and executing a second microinstruction sequence corresponding to the second command.

Description

Technical Field

[0001] The present invention relates to a solid state storage device (SSD), and more specifically, to a method and device for scheduling a microinstruction sequence. Background Art

[0002] Similar to mechanical hard disks, solid-state storage devices (SSDs) are also large-capacity, non-volatile storage devices used in computer systems. Solid-state storage devices generally use flash memory as the storage medium. Figure 1 As shown, it is a block diagram of a storage system of the prior art. It mainly includes a host system 110 and a solid-state storage device 120. Among them, the solid-state storage device 120 includes an interface module 130, a storage controller 140, and a Flash array 160 composed of a plurality of flash memory particles 150. Among them, the interface module 130 is mainly used to implement an interface protocol for communicating with the host system, such as SATA (Serial Advanced Technology Attachment), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express), NVMe (NVM Express), SCSI (Small Computer System Interface), IDE (Integrated Drive Electronics), etc. Through the interface module 130, the solid-state storage device presents to the host system a standard storage device with a certain logical address space or physical address space. The storage controller 140 is the control core of the entire storage device, and is mainly responsible for the transmission of control signals and data between the interface module 130 and the flash array 160, flash memory management, conversion or mapping of host logical addresses to flash memory physical addresses, wear leveling, and / or bad block management, etc. The storage controller 140 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof.

[0003] The storage controller 140 accesses the flash memory particles 150 by sending commands to the flash memory particles 150 in the flash memory array 160. The commands for accessing the flash memory particles 150 include, for example, reading, programming and / or erasing, etc. The commands for accessing the flash memory particles 150 also include a suspend command for temporarily suspending the execution of the commands sent to the flash memory particles 150.

[0004] Since the execution time of commands such as programming and erasing is relatively long compared to the read command, if the read command is issued to the flash memory particle 150 after the programming or erasing command, the read command needs to wait for the execution of the programming or erasing command to be completed before it can be executed, which in turn leads to a longer response time for the read operation and increases the read delay of the storage device 120. Similarly, if the programming command is issued to the flash memory particle 150 after the erasing command, the programming command needs to wait for the execution of the erasing command to be completed before it can be executed, which in turn leads to a longer response time for the programming command.

[0005] By issuing a suspend command to the flash memory particles 150, the execution of the program or erase command on the flash memory particles 150 can be temporarily suspended, and then the flash memory particles 150 can respond to the read command, and after the read command is executed, the execution of the suspended program or erase command can be resumed by issuing a resume command to the flash memory particles 150. During the execution of the program or erase command by the flash memory particles 150, the suspend command and the resume command can be received multiple times, and the same program or erase command can be suspended and resumed multiple times.

[0006] In the U.S. patent application with publication number US2013 / 0198451A1, conditional execution of the pause command is provided. When a read / write command is received, a pause threshold is calculated based on the pause policy, and it is determined whether the previous erase operation meets the pause threshold. If the pause threshold is met, the previous erase operation is paused, and if the pause threshold is not met, the previous erase operation is completed.

[0007] In the Chinese patent application with publication number CN1414468A, a scheme for processing CPU (Central Processing Unit) instructions by executing a microinstruction sequence is provided. When the CPU is to process a specific instruction, the conversion logic circuit converts the specific instruction into a microinstruction sequence corresponding thereto, and implements the function of the specific instruction by executing the microinstruction sequence. The microinstruction sequence or the template of the microinstruction sequence is stored in a ROM (Read Only Memory). In the process of converting the specific instruction into the microinstruction sequence, the microinstruction sequence template can be filled to correspond to the specific instruction. Summary of the invention

[0008] Although the prior art provides a solution for determining whether to issue a pause command by checking a pause threshold, it is still desirable to provide more flexibility to control the timing of issuing a pause command. It is also expected that a user of a storage device can participate in the flexible control of the timing of issuing a flash memory pause command, rather than relying on a storage controller to schedule multiple commands for accessing flash memory particles.

[0009] To achieve the above object, the present invention responds to commands from a host or a user by executing a microinstruction sequence. Through the execution of the microinstruction sequence by the microinstruction processor, an operation command is issued to the flash memory particle and / or data or other information read from the flash memory particle is received. The user of the storage device can participate in the flexible control of the timing of issuing the flash memory pause command by programming, updating and / or modifying the microinstruction sequence.

[0010] According to a first aspect of the present invention, a first method for scheduling a microinstruction sequence is provided, comprising: when a first command is received, executing a first microinstruction sequence corresponding to the first command; when a second command is received, if the first microinstruction sequence is being executed, suspending the first microinstruction sequence; and executing a second microinstruction sequence corresponding to the second command.

[0011] According to the first aspect of the present invention, a second method for scheduling microinstruction sequences is also provided, comprising: when a first command is received, executing a first microinstruction sequence corresponding to the first command; the first microinstruction sequence causes the controller to perform the following operations: the first microinstruction sequence yields; when a second command is received, executing a second microinstruction sequence corresponding to the second command; the second microinstruction sequence causes the controller to perform the following operations: the second microinstruction sequence yields; checking the execution status of the microinstruction sequence; and restoring the second microinstruction sequence.

[0012] According to the first method or the second method of the first aspect of the present invention, a third method of the first aspect of the present invention is provided, wherein: the execution of the first microinstruction sequence corresponding to the first command also includes: starting a timer.

[0013] According to the third method of the first aspect of the present invention, a fourth method of the first aspect of the present invention is provided, wherein if the first microinstruction sequence is being executed and if the time recorded by the timer is less than a threshold, the first microinstruction sequence is suspended; and the second microinstruction sequence is executed.

[0014] According to the first method of the first aspect of the present invention, a fifth method of the first aspect of the present invention is provided, wherein: if the first microinstruction sequence is being executed, and if the priority of the second command is higher than the first command, the first microinstruction sequence is suspended; and the second microinstruction sequence is executed.

[0015] According to one of the above methods of the first aspect of the present invention, a sixth method of the first aspect of the present invention is provided, wherein: the first command indicates a memory erase operation and / or a memory programming operation; and the second command indicates a memory read operation.

[0016] According to one of the above methods of the first aspect of the present invention, a seventh method of the first aspect of the present invention is provided, wherein the suspending of the first microinstruction sequence includes: sending a command to the memory to suspend the memory erase operation and / or memory programming operation.

[0017] According to the seventh method of the first aspect of the present invention, an eighth method of the first aspect of the present invention is provided, and the eighth method further includes: in response to the completion of execution of the second microinstruction sequence, restoring the first microinstruction sequence.

[0018] According to the eighth method of the first aspect of the present invention, a ninth method of the first aspect of the present invention is provided, wherein restoring the first microinstruction sequence includes: sending a command to the memory to restore the memory erase operation and / or memory programming operation.

[0019] According to the fifth method of the first aspect of the present invention, a tenth method of the first aspect of the present invention is provided, and the tenth method further includes: adjusting the priority of the first command and / or the second command.

[0020] According to a second aspect of the present invention, there is provided a first method for scheduling memory operations, comprising: when a first command is received, if the first command indicates an erase operation, executing an erase operation microinstruction sequence;

[0021] The erase operation microinstruction sequence causes the memory controller to perform the following operations:

[0022] issuing an erase command to the storage device; and

[0023] The erase operation microinstruction sequence yields;

[0024] When the second command is received, if the second command indicates a read operation, a read operation microinstruction sequence is executed; the read operation microinstruction sequence causes the memory controller to perform the following operations:

[0025] The read operation microinstruction sequence yields; and

[0026] issuing a read command to the storage device;

[0027] The first method also includes checking the execution status of the microinstruction sequence; and restoring the read operation microinstruction sequence.

[0028] According to the first method of the second aspect of the present invention, a second method of the second aspect of the present invention is provided, wherein the erase operation microinstruction sequence causes the memory controller to perform the following operations:

[0029] issuing an erase command to the storage device;

[0030] Starting a timer; and

[0031] The erase operation microinstruction sequence yields;

[0032] And in the second method of the second aspect of the present invention: check the execution status of the microinstruction sequence, if the time recorded by the timer is less than the threshold, send a command to the memory to suspend the memory erase operation, and resume the read operation microinstruction sequence.

[0033] According to the first method of the second aspect of the present invention, a third method of the second aspect of the present invention is provided, wherein the erase operation microinstruction sequence causes the memory controller to perform the following operations:

[0034] Start the timer;

[0035] issuing an erase command to the storage device; and

[0036] The erase operation microinstruction sequence yields;

[0037] And in the third method of the second aspect of the present invention: checking the execution status of the microinstruction sequence, if the time recorded by the timer is less than the threshold, sending a command to suspend the memory erase operation to the memory, and resuming the read operation microinstruction sequence.

[0038] According to the second method or the third method of the second aspect of the present invention, a fourth method of the second aspect of the present invention is provided, wherein the execution status of the microinstruction sequence is checked, and if the time recorded by the timer is less than a threshold, the timer is also paused.

[0039] According to the fourth method of the second aspect of the present invention, a fifth method of the second aspect of the present invention is provided, wherein the read operation microinstruction sequence causes the memory controller to perform the following operations:

[0040] The read operation microinstruction sequence yields;

[0041] issuing a read command to the memory device; and

[0042] Get the data returned by the storage;

[0043] And in the fifth method of the second aspect of the present invention: in response to the completion of the execution of the read operation microinstruction sequence, the erase operation microinstruction sequence is restored.

[0044] According to the fifth method of the second aspect of the present invention, a sixth method of the second aspect of the present invention is provided, wherein restoring the erase operation microinstruction sequence includes restoring the timer.

[0045] According to the first method of the second aspect of the present invention, a seventh method of the second aspect of the present invention is provided, wherein the execution status of the microinstruction sequence is checked, and if the priority of the second command is higher than the priority of the first command, a command to suspend the memory erase operation is sent to the memory to resume the read operation microinstruction sequence.

[0046] According to one of the above methods of the second aspect of the present invention, an eighth method of the second aspect of the present invention is provided, wherein the restoring the read operation microinstruction sequence includes: sending a command to the memory to restore the memory erase operation and / or memory programming operation.

[0047] According to the seventh method of the second aspect of the present invention, a ninth method of the second aspect of the present invention is provided, and the ninth method further includes: adjusting the priority of the first command and / or the second command.

[0048] According to a third aspect of the present invention, a first execution method of a microinstruction sequence is provided, comprising: processing a first command, and if the first command indicates an erase operation, issuing an erase command to a storage device; during the execution of the erase operation, if a second command indicating a read operation is received, issuing a command to suspend the erase operation to the storage device, and issuing a read command to the storage device.

[0049] According to the first method of the third aspect of the present invention, a second method of the third aspect of the present invention is provided, wherein after a read command is issued to the storage device, the execution status is checked, and if the execution of the read command is not completed, the microinstruction sequence yields.

[0050] According to the first method or the second method of the third aspect of the present invention, a third method of the third aspect of the present invention is provided, wherein after a read command is issued to the storage device, the execution status is checked, and if the execution of the read command is completed, the data returned by the storage device is obtained; and a command to resume the erase operation is issued.

[0051] According to the third method of the third aspect of the present invention, a fourth method of the third aspect of the present invention is provided, wherein after a read command is issued to the storage device, the execution status is checked, and if the execution of the read command is completed, after a command to resume the erase operation is issued, the microinstruction sequence yields.

[0052] According to one of the above methods of the third aspect of the present invention, a fifth method of the third aspect of the present invention is provided, wherein after a read command is issued to the storage device, the execution status is checked, and if the execution of the read command is completed, if the first command indicates an erase operation, a timer is also started; and if a second command indicating a read operation is received and the time recorded by the timer is less than a threshold value, a command to suspend the erase operation is issued to the storage device, and a read command is issued to the storage device.

[0053] According to the fifth method of the third aspect of the present invention, a sixth method of the third aspect of the present invention is provided, wherein after a read command is issued to the storage device, the execution status is checked, and if the execution of the read command is completed, after the execution of the read command is completed and the data returned by the storage device is obtained, the timer is restored.

[0054] According to one of the above methods of the third aspect of the present invention, a seventh method of the third aspect of the present invention is provided, wherein if a second command indicating a read operation is received and the priority of the second command is higher than the first command, a command to suspend the erase operation is issued to the storage device, and a read command is issued to the storage device.

[0055] According to the seventh method of the third aspect of the present invention, an eighth method of the third aspect of the present invention is provided, and the eighth method further includes: adjusting the priority of the first command and / or the second command.

[0056] According to a fourth aspect of the present invention, a first execution method of a microinstruction sequence is still provided, comprising: processing a first command, and if the first command indicates an erase operation, issuing an erase command to a storage device; checking a second command, and if the second command indicates a read operation, issuing a command to suspend the erase operation to the storage device, and issuing a read command to the storage device.

[0057] According to the first method of the fourth aspect of the present invention, a second method of the fourth aspect of the present invention is provided, wherein after a read command is issued to the storage device, the execution status is checked, and if the execution of the read command is not completed, the microinstruction sequence yields.

[0058] According to the first method or the second method of the fourth aspect of the present invention, a third method of the fourth aspect of the present invention is provided, wherein after a read command is issued to the storage device, the execution status is checked, and if the execution of the read command is completed, the data returned by the storage device is obtained; and a command to resume the erase operation is issued.

[0059] According to the third method of the fourth aspect of the present invention, a fourth method of the fourth aspect of the present invention is provided, wherein after issuing a command to resume the erase operation, the microinstruction sequence yields.

[0060] According to one of the above methods of the fourth aspect of the present invention, a fifth method of the fourth aspect of the present invention is provided, wherein if the first command indicates an erase operation, a timer is also started; and if the second command indicates a read operation and the time recorded by the timer is less than a threshold, a command to suspend the erase operation is issued to the storage device, and a read command is issued to the storage device.

[0061] According to the fifth method of the fourth aspect of the present invention, a sixth method of the fourth aspect of the present invention is provided, wherein after the execution of the read command is completed and the data returned by the memory is obtained, the timer is restored.

[0062] According to one of the above methods of the fourth aspect of the present invention, a seventh method of the fourth aspect of the present invention is provided, wherein if the second command indicates a read operation and the priority of the second command is higher than the first command, a command to suspend the erase operation is issued to the storage device, and a read command is issued to the storage device.

[0063] According to the seventh method of the fourth aspect of the present invention, an eighth method of the fourth aspect of the present invention is provided, and the eighth method further includes: adjusting the priority of the first command and / or the second command.

[0064] According to a fifth aspect of the present invention, a first storage controller is provided, comprising a microinstruction memory, a microinstruction processor and a scheduler; a first microinstruction sequence and a second microinstruction sequence are stored in the microinstruction memory; in response to receiving a first command, the microinstruction processor executes the first microinstruction sequence; in response to receiving a second command, the scheduler checks the execution status of the first microinstruction sequence, and if the first microinstruction sequence is being executed, suspends the first microinstruction sequence; and causes the microinstruction processor to execute the second microinstruction sequence.

[0065] According to a fifth aspect of the present invention, a second storage controller is provided, comprising a microinstruction memory, a microinstruction processor and a scheduler; a first microinstruction sequence and a second microinstruction sequence are stored in the microinstruction memory; in response to receiving a first command, the microinstruction processor executes the first microinstruction sequence; the first microinstruction sequence causes the controller to perform the following operations: the first microinstruction sequence yields; in response to receiving a second command, the microinstruction processor executes the second microinstruction sequence; the second microinstruction sequence causes the controller to perform the following operations: the second microinstruction sequence yields; the scheduler checks the execution status of the microinstruction sequence and resumes the execution of the second microinstruction sequence on the microinstruction processor.

[0066] According to the first storage controller or the second storage controller of the fifth aspect of the present invention, a third storage controller of the fifth aspect of the present invention is provided, wherein: the storage controller also includes a timer; and the execution of the first microinstruction sequence also includes: starting the timer.

[0067] According to the third storage controller of the fifth aspect of the present invention, a fourth storage controller according to the fifth aspect of the present invention is provided, wherein if the scheduler finds that the first microinstruction sequence is being executed and if the time recorded by the timer is less than a threshold, the first microinstruction sequence is suspended and the microinstruction processor is caused to execute the second microinstruction sequence.

[0068] According to the first storage controller of the fifth aspect of the present invention, a fifth storage controller according to the fifth aspect of the present invention is provided, wherein: if the scheduler finds that the first microinstruction sequence is being executed, and if the priority of the second command is higher than the first command, the first microinstruction sequence is suspended and the microinstruction processor is caused to execute the second microinstruction sequence.

[0069] According to one of the above-mentioned storage controllers according to the fifth aspect of the present invention, a sixth storage controller according to the fifth aspect of the present invention is provided, wherein: the first command indicates a memory erase operation and / or a memory programming operation; and the second command indicates a memory read operation.

[0070] According to one of the above-mentioned storage controllers according to the fifth aspect of the present invention, a seventh storage controller according to the fifth aspect of the present invention is provided, wherein the suspending of the first microinstruction sequence includes: sending a command to suspend the memory erase operation and / or memory programming operation to the memory through the interface controller.

[0071] According to the seventh storage controller of the fifth aspect of the present invention, there is provided an eighth storage controller according to the fifth aspect of the present invention, further comprising: the scheduler causes the microinstruction processor to restore the first microinstruction sequence in response to completion of execution of the second microinstruction sequence.

[0072] According to the eighth storage controller of the fifth aspect of the present invention, there is provided a ninth storage controller according to the fifth aspect of the present invention, wherein restoring the first microinstruction sequence comprises: sending a command to restore the memory erase operation and / or memory programming operation to the memory through the interface controller.

[0073] According to the fifth storage controller of the fifth aspect of the present invention, there is provided a tenth storage controller according to the fifth aspect of the present invention, further comprising: the scheduler adjusting the priority of the first command and / or the second command.

[0074] According to a sixth aspect of the present invention, a first storage controller is provided, comprising a microinstruction memory, a microinstruction processor and a scheduler; the microinstruction memory stores an erase operation microinstruction sequence and a read operation microinstruction sequence; in response to receiving a first command, if the scheduler determines that the first command indicates an erase operation, the microinstruction processor is caused to execute the erase operation microinstruction sequence; the erase operation microinstruction sequence causes the microinstruction processor to perform the following operations: issue an erase command to a storage device; and the erase operation microinstruction sequence yields; in response to receiving a second command, if the scheduler determines that the second command indicates a read operation, the microinstruction processor is caused to execute the read operation microinstruction sequence; the read operation microinstruction sequence causes the microinstruction processor to perform the following operations: the read operation microinstruction sequence yields; and issue a read command to the storage device; the scheduler checks the execution status of the microinstruction sequence and causes the microinstruction controller to resume the execution of the read operation microinstruction sequence.

[0075] According to the first storage controller according to the sixth aspect of the present invention, there is provided a second storage controller according to the sixth aspect of the present invention, wherein the second storage controller also includes a timer, wherein the erase operation microinstruction sequence causes the microinstruction processor to perform the following operations: issue an erase command to the storage device; start the timer; and the erase operation microinstruction sequence yields; and wherein: the scheduler checks the execution status of the microinstruction sequence, and if the time recorded by the timer is less than a threshold, causes the interface controller to send a command to the memory to pause the memory erase operation, and causes the microinstruction processor to resume the execution of the read operation microinstruction sequence.

[0076] According to the first storage controller of the sixth aspect of the present invention, there is provided a third storage controller of the sixth aspect of the present invention, the third storage controller also includes a timer, wherein the erase operation microinstruction sequence causes the microinstruction processor to perform the following operations: start the timer; issue an erase command to the storage device; and the erase operation microinstruction sequence yields; and wherein: the scheduler checks the execution status of the microinstruction sequence, and if the time recorded by the timer is less than a threshold value, causes the interface controller to send a command to the memory to suspend the memory erase operation, and causes the microinstruction processor to resume the execution of the read operation microinstruction sequence.

[0077] According to the second storage controller or the third storage controller of the sixth aspect of the present invention, a fourth storage controller according to the sixth aspect of the present invention is provided, wherein the scheduler checks the execution status of the microinstruction sequence, and if the time recorded by the timer is less than a threshold, the timer is also paused.

[0078] According to the fourth storage controller according to the sixth aspect of the present invention, there is provided a fifth storage controller according to the sixth aspect of the present invention, wherein the read operation microinstruction sequence causes the microinstruction processor to perform the following operations: the read operation microinstruction sequence yields; issues a read command to the storage device; and obtains data returned by the storage device; and wherein: in response to the completion of the execution of the read operation microinstruction sequence, the scheduler causes the microinstruction processor to resume the execution of the erase operation microinstruction sequence.

[0079] According to the fifth storage controller of the sixth aspect of the present invention, there is provided a sixth storage controller according to the sixth aspect of the present invention, wherein said restoring said erase operation microinstruction sequence comprises restoring said timer.

[0080] According to the first storage controller according to the sixth aspect of the present invention, a seventh storage controller according to the sixth aspect of the present invention is provided, wherein the scheduler checks the execution status of the microinstruction sequence, and if the priority of the second command is higher than the priority of the first command, the interface controller sends a command to the memory to suspend the memory erase operation, and the microinstruction processor resumes the execution of the read operation microinstruction sequence.

[0081] According to one of the above-mentioned storage controllers according to the sixth aspect of the present invention, a fifth storage controller according to the eighth aspect of the present invention is provided, wherein the scheduler enables the microinstruction controller to resume the execution of the read operation microinstruction sequence: enables the interface controller to send a command to the memory to resume the memory erase operation and / or memory programming operation.

[0082] According to the seventh storage controller according to the sixth aspect of the present invention, there is provided a ninth storage controller according to the sixth aspect of the present invention, wherein the scheduler adjusts the priority of the first command and / or the second command.

[0083] According to a seventh aspect of the present invention, there is provided a storage device comprising one of the storage controllers according to the fifth aspect or the sixth aspect of the present invention.

[0084] According to an eighth aspect of the present invention, there is provided an electronic system comprising a computer and a storage device coupled to the computer, wherein the storage device can respond to an access request from the computer; the storage device is the storage device according to the seventh aspect of the present invention.

[0085] According to the ninth aspect of the present invention, a non-transitory computing device readable medium is provided, on which a program is stored, the program comprising a sequence of microinstructions; when executed by a computing device, the program causes the computing device to be configured to perform one of the methods according to the third aspect or the fourth aspect of the present invention.

[0086] According to a tenth aspect of the present invention, there is provided a program comprising a sequence of microinstructions, which, when executed by a computing device, causes the computing device to be configured to perform one of the methods according to the third aspect or the fourth aspect of the present invention.

[0087] According to the eleventh aspect of the present invention, there is provided a first execution device of a microinstruction sequence, comprising: a first device for processing a first command, and if the first command indicates an erase operation, issuing an erase command to a storage device; and a second device for, during the execution of the erase operation, if a second command indicating a read operation is received, issuing a command to suspend the erase operation to the storage device, and issuing a read command to the storage device.

[0088] According to the first device of the eleventh aspect of the present invention, there is provided a second device of the eleventh aspect of the present invention, wherein after a read command is issued to the storage device, the execution status is checked, and if the execution of the read command is not completed, the microinstruction sequence yields.

[0089] According to the first device or the second device of the eleventh aspect of the present invention, a third device of the eleventh aspect of the present invention is provided, wherein after a read command is issued to the storage device, the execution status is checked, and if the execution of the read command is completed, the data returned by the storage device is obtained; and a command to resume the erase operation is issued.

[0090] According to the third device of the eleventh aspect of the present invention, a fourth device of the eleventh aspect of the present invention is provided, wherein after a read command is issued to the storage device, the execution status is checked, and if the execution of the read command is completed, after a command to resume the erase operation is issued, the microinstruction sequence yields.

[0091] According to one of the above-mentioned devices of the eleventh aspect of the present invention, a fifth device of the eleventh aspect of the present invention is provided, wherein after a read command is issued to the storage device, the execution status is checked, and if the execution of the read command is completed, if the first command indicates an erase operation, a timer is also started; and if a second command indicating a read operation is received and the time recorded by the timer is less than a threshold value, a command to suspend the erase operation is issued to the storage device, and a read command is issued to the storage device.

[0092] According to the fifth device of the eleventh aspect of the present invention, a sixth device of the eleventh aspect of the present invention is provided, wherein after a read command is issued to the storage device, the execution status is checked, and if the execution of the read command is completed, wherein after the execution of the read command is completed and the data returned by the storage device is obtained, the timer is restored.

[0093] According to one of the above-mentioned devices of the eleventh aspect of the present invention, a seventh device of the eleventh aspect of the present invention is provided, wherein if a second command indicating a read operation is received and the priority of the second command is higher than the first command, a command to suspend the erase operation is issued to the storage device, and a read command is issued to the storage device.

[0094] According to the seventh device of the eleventh aspect of the present invention, there is provided the eighth device of the eleventh aspect of the present invention, the eighth device further comprising: a third device for adjusting the priority of the first command and / or the second command.

[0095] According to the twelfth aspect of the present invention, there is still provided a first execution device of a microinstruction sequence, comprising: a first device for processing a first command, and if the first command indicates an erase operation, issuing an erase command to a storage device; and a second device for checking a second command, and if the second command indicates a read operation, issuing a command to suspend the erase operation to the storage device, and issuing a read command to the storage device.

[0096] According to the first device of the twelfth aspect of the present invention, a second device of the twelfth aspect of the present invention is provided, wherein after a read command is issued to the storage device, the execution status is checked, and if the execution of the read command is not completed, the microinstruction sequence yields.

[0097] According to the first device or the second device of the twelfth aspect of the present invention, a third device of the twelfth aspect of the present invention is provided, wherein after a read command is issued to the storage device, the execution status is checked, and if the execution of the read command is completed, the data returned by the storage device is obtained; and a command to resume the erase operation is issued.

[0098] According to the third device of the twelfth aspect of the present invention, there is provided a fourth device of the twelfth aspect of the present invention, wherein after issuing a command to resume the erase operation, the microinstruction sequence yields.

[0099] According to one of the above-mentioned devices of the twelfth aspect of the present invention, a fifth device of the twelfth aspect of the present invention is provided, wherein if the first command indicates an erase operation, a timer is also started; and if the second command indicates a read operation and the time recorded by the timer is less than a threshold, a command to suspend the erase operation is issued to the storage device, and a read command is issued to the storage device.

[0100] According to the fifth device of the twelfth aspect of the present invention, there is provided a fifth device of the twelfth aspect of the present invention, wherein after the execution of the read command is completed and the data returned by the memory is obtained, the timer is restored.

[0101] According to one of the above-mentioned devices of the twelfth aspect of the present invention, a seventh device of the twelfth aspect of the present invention is provided, wherein if the second command indicates a read operation and the priority of the second command is higher than the first command, a command to suspend the erase operation is issued to the storage device, and a read command is issued to the storage device.

[0102] According to the seventh device of the twelfth aspect of the present invention, an eighth device of the twelfth aspect of the present invention is provided, and the eighth device also includes: a third device for adjusting the priority of the first command and / or the second command. BRIEF DESCRIPTION OF THE DRAWINGS

[0103] The invention, together with the preferred mode of use and further objects and advantages thereof, will be best understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, in which:

[0104] Figure 1 is a block diagram of a storage system of the prior art;

[0105] Figure 2 is a structural block diagram of a component for processing microinstructions of a memory controller according to an embodiment of the present invention;

[0106] Figure 3 is a flow chart of a method for scheduling a microinstruction sequence according to an embodiment of the present invention;

[0107] Figure 4 is a structural block diagram of a component for processing microinstructions of a memory controller according to another embodiment of the present invention;

[0108] Figure 5 A timing diagram showing processing by a scheduler and a microinstruction processor according to another embodiment of the present invention is shown;

[0109] Figure 6 is a structural block diagram of a component for processing microinstructions of a memory controller according to another embodiment of the present invention;

[0110] Figure 7 is a flow chart of a method for executing a microinstruction sequence according to an embodiment of the present invention;

[0111] Figure 8 is a flow chart of a method for executing a microinstruction sequence according to another embodiment of the present invention; and

[0112] Fig. 9 is a flow chart of a method for executing a microinstruction sequence according to yet another embodiment of the present invention. DETAILED DESCRIPTION

[0113] See also Figure 2 , Figure 2 2 is a block diagram of a component of a memory controller for processing microinstructions according to an embodiment of the present invention. To process microinstructions, the memory controller of the storage device may include a microinstruction processor 210, a command queue 220, an interface controller 230 and / or a microinstruction memory 240.

[0114] The microinstruction memory 240 is used to store microinstructions. The microinstruction processor 210 reads and executes microinstructions from the microinstruction memory 240. The microinstructions enable the microinstruction processor to issue commands to access the flash memory particles through the interface controller 230, including, for example, commands such as read, program, erase, pause, read flash memory particle features and / or read and set flash memory particle features. The microinstructions also enable the microinstruction processor to obtain data read from the flash memory particles through the interface controller 230. One microinstruction or multiple microinstructions may correspond to one of the commands to access the flash memory particles such as read, program, erase and / or pause. The microinstructions may also include branch and jump microinstructions, which enable the microinstruction processor to change the order of executing the microinstructions.

[0115] One or more microinstruction sequences may be stored in the microinstruction memory 240. For example, Figure 2 The microinstruction memory 240 stores n segments of microinstruction sequences, including microinstruction sequence 1, microinstruction sequence 2, ..., and microinstruction sequence n. Each segment of microinstruction sequence 1, microinstruction sequence 2, ..., and microinstruction sequence n includes a plurality of microinstructions.

[0116] Multiple microinstructions in a microinstruction sequence can be executed by the microinstruction processor 210. Each microinstruction sequence has its own execution state, so that the execution of each microinstruction can be suspended and resumed. The microinstruction processor can suspend the microinstruction sequence being executed and choose to execute other microinstruction sequences. A yield microinstruction can also be provided in the microinstruction sequence. When the yield microinstruction is executed, the microinstruction processor can schedule and execute other microinstruction sequences. When the microinstruction processor 210 suspends the microinstruction sequence being executed, or executes the yield microinstruction, the execution state of the microinstruction sequence being executed is saved; when the microinstruction processor resumes the execution of the microinstruction sequence, the saved execution state is read out, thereby continuing the execution of the resumed microinstruction sequence.

[0117] The interface controller 230 is coupled to the flash memory particles and is used to issue commands to the flash memory particles to access the flash memory particles, including, for example, reading, programming, erasing, suspending and / or resuming, etc.; and is also used to obtain data read from the flash memory particles.

[0118] The command queue 220 is used to cache commands from users or upper systems. The commands from users or upper systems may include commands such as read, write, delete, mark as invalid, etc., and may also include commands such as read storage device status, read / set flash memory particle features, etc., and may also include user-defined commands. The command queue 220 may be implemented by a memory, a first-in-first-out memory register file, etc.

[0119] When processing the command in the command queue 220, a microinstruction sequence corresponding to the command is obtained, and the microinstruction sequence is executed by the microinstruction processor 210 to complete the processing of the command in the command queue 220. The conversion from processing the command in the command queue 220 to the microinstruction sequence can be achieved by a conversion circuit (not shown). The conversion from processing the command in the command queue 220 to the microinstruction sequence can also be achieved by the microinstruction processor 210. In the process of obtaining the microinstruction sequence, the microinstruction sequence can be filled or adapted based on the command in the command queue 220 so that the microinstruction sequence is compatible with the command in the command queue 220.

[0120] For example, when microinstruction processor 210 executes microinstruction sequence 1, new commands from user or upper system are written in command queue 220. Scheduling logic (not shown) can be provided to assist microinstruction processor 210 in scheduling of microinstruction sequence. In response to this new command, scheduling logic can suspend the execution of microinstruction sequence 1, and schedule the microinstruction sequence (for example, microinstruction sequence 2) corresponding to the new command to be executed by microinstruction processor. The execution state of suspended microinstruction sequence 1 is preserved so that when the execution of microinstruction sequence 1 is restored, the execution state when suspended can be obtained. In one embodiment, this new command is a read command. The read command can have a higher priority, and the scheduling logic has a higher priority based on the read command and suspends the execution of microinstruction sequence 1 in response to this new command.

[0121] In one embodiment, microinstruction sequence 1 is used to perform an erase operation on a flash memory particle. When the scheduling logic suspends the execution of microinstruction sequence 1, the scheduling logic also issues a command to the flash memory particle to suspend the erase operation of the flash memory particle. When microinstruction sequence 2 is executed, the scheduling logic also issues a command to the flash memory particle to resume the erase operation of the flash memory particle. Then, the execution state of microinstruction sequence 1 when it is suspended is obtained, and the execution of microinstruction sequence 1 is resumed.

[0122] In another embodiment, microinstruction sequence 1 is used to perform programming operations on flash memory particles. When the scheduling logic suspends the execution of microinstruction sequence 1, the scheduling logic also issues a command to suspend the programming operation of the flash memory particles to the flash memory particles. When microinstruction sequence 2 is executed, the scheduling logic also issues a command to resume the programming operation of the flash memory particles to the flash memory particles. Then, the execution state of microinstruction sequence 1 when it is suspended is obtained, and the execution of microinstruction sequence 1 is resumed.

[0123] The scheduling logic may be implemented as software, hardware circuit and / or firmware, and may be independent of the microinstruction processor 210 or may be integrated into the microinstruction processor 210 .

[0124] In one embodiment, microinstruction sequence 1 includes a yield microinstruction. When the microinstruction processor 210 executes the yield microinstruction, the execution state of the microinstruction sequence 1 is saved, and one of the microinstruction sequences is selected to be executed or restored. At this time, if there is a new command from a user or an upper system in the command queue 220, the new command corresponds to the microinstruction sequence 2, and the scheduling logic can execute the microinstruction sequence 2 in response to the new command. The scheduling logic can also restore the microinstruction sequence 3 based on the existence of the yielded or suspended microinstruction sequence 3. In a further embodiment, after the microinstruction processor 210 executes the yield microinstruction of the microinstruction sequence 1, the priority of the microinstruction sequence 1, the microinstruction sequence 2 and / or the microinstruction sequence 3 is compared, and which microinstruction is executed next. In a further embodiment, the priority of the microinstruction sequence corresponding to the read operation is higher than the priority of the microinstruction sequence corresponding to the erase operation. The priority of the microinstruction sequence corresponding to the read operation is higher than the priority of the microinstruction sequence corresponding to the programming operation.

[0125] In one embodiment, both microinstruction sequence 1 and microinstruction sequence 2 include a yield microinstruction. For example, the starting positions of microinstruction sequence 1 and microinstruction sequence 2 include a yield microinstruction. When microinstruction sequence 1 is executed in response to a command in command queue 220, microinstruction sequence 1 yields as the yield microinstruction is executed. At this time, the scheduling logic determines which microinstruction sequence to execute next. If there is a new command corresponding to microinstruction sequence 2 in command queue 220, the scheduling logic can schedule the execution of microinstruction sequence 2. Since the starting position of microinstruction sequence 2 includes a yield microinstruction, microinstruction sequence 2 also yields. At this time, both microinstruction sequence 1 and microinstruction sequence 2 have yielded. The scheduling logic can select one of microinstruction sequence 1 or microinstruction sequence 2 to resume execution; if new commands corresponding to other microinstruction sequences (e.g., microinstruction sequence n) are stored in command queue 220, the scheduling logic can also select to execute microinstruction sequence n. In a further embodiment, the scheduling logic determines which microinstruction sequence to execute based on the priority of microinstruction sequence 1, microinstruction sequence 2 and / or microinstruction sequence n.

[0126] In another embodiment, both microinstruction sequence 1 and microinstruction sequence 2 include a yield microinstruction. For example, the starting positions of microinstruction sequence 1 and microinstruction sequence 2 include a yield microinstruction. When microinstruction sequence 1 is executed in response to a command in command queue 220, microinstruction sequence 1 yields as the yield microinstruction is executed. At this time, the scheduling logic determines which microinstruction sequence to execute next. If there is a new command corresponding to microinstruction sequence 2 in command queue 220, the scheduling logic can schedule the execution of microinstruction sequence 2. Since the starting position of microinstruction sequence 2 includes a yield microinstruction, microinstruction sequence 2 also yields. At this time, the scheduling logic determines which microinstruction sequence to execute next. The scheduling logic finds that both microinstruction sequence 1 and microinstruction sequence 2 have yielded. The scheduling logic can resume the execution of microinstruction sequence 1 based on the principle of first come first served. Next, during the execution of microinstruction sequence 1, the interface controller 230 is caused to issue an erase operation to the flash memory particles. Further yield instructions may be included in microinstruction sequence 1. As the yield instruction is executed, microinstruction sequence 1 yields again. The scheduling logic again determines which microinstruction sequence to execute next. Since microinstruction sequence 1 corresponds to an erase operation, and microinstruction sequence 2 corresponds to a read operation, and the priority of the read operation is higher than the erase operation, the scheduling logic decides to resume the execution of microinstruction sequence 2. At this time, the scheduling logic also causes the interface controller 230 to issue an erase pause command to the flash memory particles to pause the erase command issued by microinstruction sequence 1, so that the flash memory particles can respond to subsequent read commands. Next, during the execution of microinstruction sequence 2, the instruction processor 210 causes the interface controller to issue a read command to the flash memory particles. In a further embodiment, when the data returned by the flash memory particles is received, the execution of microinstruction sequence 2 is completed. The scheduling logic again determines which microinstruction sequence to execute next. Noting that microinstruction sequence 1 has yielded, the scheduling logic decides to resume the execution of microinstruction sequence 1. To resume microinstruction sequence 1, the scheduling logic also causes the interface controller 230 to issue a command to resume the erase operation to the flash memory particles, and then resume the execution of microinstruction sequence 1. In a manner similar to executing microinstruction sequence 1 corresponding to the erase operation, the scheduling logic can schedule the microinstruction sequence corresponding to the programming operation. In one embodiment, the commands from the user or the upper system in the command queue 220 provide command priority information.

[0127] In another embodiment, during the execution of microinstruction sequence 1, the interface controller 230 issues an erase operation to the flash memory particle. Microinstruction sequence 1 may include further yielding instructions. With the execution of the yielding instructions, microinstruction sequence 1 yields again. The scheduling logic starts a timer for the erase operation of microinstruction sequence 1 to record the time after the erase operation is issued to the flash memory particle. Next, when responding to the command in the command queue 220 and wishing to execute microinstruction sequence 2, the scheduling logic again determines which microinstruction sequence to execute next. In this embodiment, microinstruction sequence 1 corresponds to an erase operation, while microinstruction sequence 2 corresponds to a read operation, and the read operation has a higher priority than the erase operation. The scheduling logic further checks the timer. If the value of the timer is greater than the threshold, it means that a long time has passed since the issuance of the erase command of the previous flash memory particle, and it can be expected that the erase operation will be completed soon. At this time, if an erase pause command is issued to the flash memory particle to pause the previous erase operation, and a read command is issued, the improvement effect on the delay of the read operation is not obvious, and the execution delay of the previous erase operation is increased. In this case, the scheduling logic will not schedule the execution of microinstruction sequence 2, nor will the interface controller 230 issue an erase pause command to the flash memory particles. If the value of the timer is not greater than or less than the threshold, it means that the previous erase command still needs to be executed for a long time. In this case, if the read command is executed after waiting for the erase command to be completed, the execution delay of the read operation experienced by the user will be significantly increased. Therefore, the scheduling logic chooses to schedule the execution of microinstruction sequence 2. And the interface controller 230 issues an erase pause command to the flash memory particles, and pauses the timer. The scheduling logic can also adjust the priority of microinstruction sequence 1 and / or microinstruction sequence 2. Then during the execution of microinstruction sequence 2, microinstruction sequence 2 will cause the interface controller 230 to issue a read command to the flash memory particles. After the execution of microinstruction sequence 2 is completed, or after the data specified by the read command is read from the flash memory particles, the scheduling logic causes the interface controller 230 to issue a command to resume the erase operation to the flash memory particles, and resume the timer, so that the timer continues to count. In a further embodiment, in response to the desire to execute other microinstruction sequences, the scheduling logic again causes the interface controller 230 to issue an erase pause command to the flash memory particles, and stops the timer again. In yet another embodiment, microinstruction sequence 1 corresponds to a program operation and microinstruction sequence 2 corresponds to a read operation.

[0128] See also Figure 3 , Figure 3 A flow chart of a method for scheduling a microinstruction sequence according to an embodiment of the present invention is shown. Figure 3 The processing flow can be implemented by the scheduling logic. The scheduling logic can be implemented as software, hardware circuits and / or firmware, and can be independent of the microinstruction processor 210 (see Figure 2 ) and can also be integrated into the microinstruction processor 210.

[0129] When a first command (310) is received from a user or an upper system through, for example, the command queue 220, the scheduling logic schedules the execution of a first microinstruction sequence (320) corresponding to the first command. In one embodiment, the conversion circuit converts the first command into a first microinstruction sequence according to the content of the first command. Figure 2 The microinstruction sequence may be stored in the microinstruction memory 240, and selected by the conversion circuit according to the content of the first command. The microinstruction memory may also store a template of the microinstruction sequence, and the conversion circuit fills the microinstruction sequence template according to the content of the first command to obtain a microinstruction sequence that can be executed by the microinstruction processor 210.

[0130] During the execution of the first microinstruction sequence, a second command (330) is received from a user or an upper system through, for example, the command queue 220. The scheduling logic checks the execution status of the first microinstruction sequence and / or other microinstruction sequences (340). In one embodiment, the first microinstruction sequence is being executed and can be suspended. In another embodiment, the first microinstruction sequence is being executed and can be suspended, and the priority corresponding to the second command is higher than the priority of the first command. In another embodiment, the first microinstruction sequence has yielded, for example, by executing a yield microinstruction. The scheduling logic pauses the first microinstruction sequence (350). To pause and resume the first microinstruction sequence, the scheduling logic also saves the execution status of the first microinstruction sequence. In one embodiment, the first microinstruction sequence issues a flash memory particle erase command. The scheduling logic also issues an erase pause command to the flash memory particle. Next, the scheduling logic schedules the execution of the second microinstruction sequence (360).

[0131] Figure 4 is a structural block diagram of a component for processing microinstructions of a memory controller according to another embodiment of the present invention. Figure 4 The components for processing microinstructions provided in Figure 2 The components for processing microinstructions provided in the embodiment are similar, including a microinstruction processor 410, a command queue 420, an interface controller 430 and / or a microinstruction memory 440. The microinstruction memory 440 stores microinstruction sequence 1, microinstruction sequence 2, ..., microinstruction sequence n. Figure 4 In the embodiment of FIG. 4 , a status register 450 , a register pool 460 , and a scheduler 470 are also shown.

[0132] The status register 450 is coupled to the microinstruction processor 410 and is used to store and provide the execution status of the microinstruction sequence. The execution status of the microinstruction sequence includes a program counter (PC), a general register (GR), a physical address register and / or a timer, etc. The program counter is used to indicate the address of the microinstruction currently executed in the microinstruction sequence. The physical address register is used to indicate the address of the flash memory particle accessed by the microinstruction sequence.

[0133] The register pool 460 is used to save the execution status of the microinstruction sequence. The execution status of the microinstruction sequence saved by the register pool 460 may include the content of the status register 450. In the register pool 460, the execution status of one or more microinstruction sequences 460 may be saved. The microinstruction sequence 460 with the status information saved in the register pool 460 may be resumed by the scheduler 470. By restoring the status information corresponding to a microinstruction sequence saved in the register pool 460 to the status register 450, the microinstruction processor 410 may resume the execution of the microinstruction sequence.

[0134] Scheduler 470 is coupled to microinstruction processor 410 and command queue 420. Scheduler 470 can instruct microinstruction processor 410 to suspend the microinstruction sequence being executed. Scheduler 470 can instruct microinstruction processor 410 to resume the execution of the microinstruction sequence. Scheduler 470 can also instruct microinstruction processor 410 to start a new execution of the microinstruction sequence. Scheduler 470 implements the scheduling of the microinstruction sequence by storing the state information corresponding to the microinstruction sequence (e.g., program counter value, general counter value, physical address register value and / or timer value, etc.) in status register 450.

[0135] The scheduler 470 may also be implemented as a microinstruction sequence. In one embodiment, the microinstruction sequence is scheduled to be executed on the microinstruction processor 410 by periodically calling the microinstruction sequence corresponding to the scheduler 470 to check the execution status of the microinstruction sequence.

[0136] Figure 5 A timing diagram showing the processing of a scheduler and a microinstruction processor according to another embodiment of the present invention is shown. Figure 5 In FIG. 5 , the arrow direction of the time axis shows the direction of time flow. The processing executed by the scheduler 570 is listed below the scheduler 570 , and the processing executed by the microinstruction processor 510 is listed below the microinstruction processor 510 .

[0137] exist Figure 5In the embodiment of, first, the scheduler 570 discovers or responds to the reception of the first command (520). The scheduler schedules the first microinstruction sequence (522). As a result of scheduling the first microinstruction sequence, the microprocessor 510 starts to execute the first microinstruction sequence (532). During the execution of the first microinstruction sequence (532), the scheduler discovers or responds to the reception of the second command (524). After judging the execution condition and / or the scheduling condition, the scheduler 570 pauses the microinstruction processor 510 to instruct the first microinstruction sequence (526). In response, the microinstruction processor 510 stops executing the first microinstruction sequence. The state information of the paused first microinstruction sequence is saved. The scheduler schedules the second microinstruction sequence (528). As a result of scheduling the second microinstruction sequence, the microprocessor 510 starts to execute the second microinstruction sequence (534). As the processing proceeds, the execution of the second microinstruction sequence is completed. After further judging the execution condition and / or the scheduling condition, the scheduler 570 decides to schedule the first microinstruction sequence (530). Microinstruction processor 510 resumes execution of the first microinstruction sequence by restoring the state information previously saved for the first microinstruction sequence (536).

[0138] Figure 6 is a structural block diagram of a component for processing microinstructions of a memory controller according to another embodiment of the present invention. Figure 6 The components for processing microinstructions provided in Figure 6 The components for processing microinstructions provided in the embodiment are similar to those provided in the embodiment, including a microinstruction processor 610, a command queue 620, an interface controller 630 and / or a microinstruction memory 640. A microinstruction sequence is stored in the microinstruction memory 640. Figure 6 In an embodiment, the microinstruction sequence stored in the microinstruction memory 640 includes microinstructions for instructing the interface controller 630 to issue one or more commands to the flash memory particles. For example, the microinstruction sequence stored in the microinstruction memory 640 includes an erase microinstruction, an erase pause microinstruction, a read microinstruction, and an erase resume microinstruction. The erase microinstruction is used to instruct the interface controller 630 to issue an erase command to the flash memory particles. The erase pause microinstruction is used to instruct the interface controller 630 to issue an erase pause command to the flash memory particles. The read microinstruction is used to instruct the interface controller 630 to issue a read command to the flash memory particles. The erase resume microinstruction is used to instruct the interface controller 630 to issue an erase resume command to the flash memory particles. In another embodiment, the microinstruction sequence stored in the microinstruction memory 640 also includes a program pause microinstruction, and / or a program resume microinstruction. The program pause microinstruction is used to instruct the interface controller 630 to issue a program pause command to the flash memory particles, and the program resume microinstruction is used to instruct the interface controller 630 to issue a program resume command to the flash memory particles.

[0139] Figure 77 is a flow chart of an execution method of a microinstruction sequence 710 according to an embodiment of the present invention. Figure 7 In FIG. 7 , the direction of the time axis arrow shows the direction of time flow. In one embodiment, the first command indicates a flash memory particle erase operation. By executing the microinstruction sequence 710, the first command 720 is processed. The command queue 620 (see FIG. 7 ) can be used to execute the first command. Figure 6 ) to obtain the first command. Those skilled in the art will appreciate that there are other ways to obtain the first command. By executing the microinstructions in the microinstruction sequence 710, an erase command 730 is issued to the flash memory particle. By executing the microinstructions in the microinstruction sequence 710, a second command 740 is obtained and processed. For example, by executing the microinstructions in the microinstruction sequence 710, the microinstruction sequence 710 checks the command queue 620 (see Figure 6 ) whether the second command is received, and after receiving the second command, the second command is processed. Next, by executing the microinstructions in the microinstruction sequence 710, the microinstruction sequence 710 determines to suspend the erase command issued previously, and then issues an erase suspend command 750 to the flash memory particles. For example, by executing the microinstructions in the microinstruction sequence 710, the microinstruction sequence 710 determines whether to suspend the erase command issued previously by comparing the priority of the first command and the second command. In another example, based on the fact that the first command corresponds to an erase, program or write operation, and the second command corresponds to a read operation, it is determined to suspend the erase command or write command issued previously to the flash memory particles. Next, by executing the microinstructions in the microinstruction sequence 710, a read command 760 is issued to the flash memory particles.

[0140] Figure 8 FIG. 8 is a flowchart of a method for executing the first microinstruction sequence 810 according to another embodiment of the present invention. Figure 8 In the diagram, the direction of the timeline arrow shows the direction of time flow.

[0141] In one embodiment, the first command indicates a flash memory particle erase operation. The first command 820 is processed by executing the first microinstruction sequence 810. The command queue 620 (see Figure 6 ) to obtain the first command. Those skilled in the art will appreciate that there are other ways to obtain the first command. By executing the microinstructions in the first microinstruction sequence 810, an erase command 830 is issued to the flash memory particle. Subsequently, the yield microinstruction in the first microinstruction sequence 810 is executed to make the first microinstruction sequence 810 yield 835. After the first microinstruction sequence 810 yields, the microinstruction processor 610 (see Figure 6) can execute the microinstructions 837 in other microinstruction sequences 815. In one example, the microinstruction sequence that the microinstruction processor 610 executes next is selected by the scheduler or scheduling logic. In another example, since there are no other microinstruction sequences waiting to be executed or the priority of the first microinstruction sequence 810 is higher, the scheduler or scheduling logic chooses to resume the execution of the first microinstruction sequence 810. The other microinstruction sequences 815 also include yield microinstructions. By executing the yield microinstructions in the other microinstruction sequences 815, the other microinstruction sequences 815 yield 839. Because the other microinstruction sequences 815 yield, the microprocessor 610 can execute another microinstruction sequence. In one example, the scheduler or scheduling logic chooses to resume the execution of the first microinstruction sequence 810. By restoring the execution state (e.g., program counter value, general counter value, physical address register value and / or timer value, etc.) when the first microinstruction sequence 810 yields, the microinstruction processor 610 continues to execute the first microinstruction sequence 810.

[0142] Next, the second command 840 is obtained and processed by executing the microinstructions in the first microinstruction sequence 810. For example, by executing the microinstructions in the first microinstruction sequence 810, the microinstruction sequence 810 checks the command queue 620 (see Figure 6 ) whether the second command is received, and after receiving the second command, the second command is processed. Next, by executing the microinstructions in the microinstruction sequence 810, the first microinstruction sequence 810 determines to suspend the erase command issued previously, and then issues an erase suspend command 850 to the flash memory particles. For example, by executing the microinstructions in the first microinstruction sequence 810, the microinstruction sequence 810 determines whether to suspend the erase command issued previously by comparing the priority of the first command and the second command. In another example, based on the fact that the first command corresponds to an erase, program, or write operation, and the second command corresponds to a read operation, it is determined to suspend the erase command or program command issued previously to the flash memory particles. Next, by executing the microinstructions in the first microinstruction sequence 810, a read command 860 is issued to the flash memory particles.

[0143] Fig. 9 1 is a flow chart of a method for executing a microinstruction sequence according to yet another embodiment of the present invention. Figure 8 In the diagram, the direction of the timeline arrow shows the direction of time flow.

[0144] In one embodiment, the first command indicates a flash memory particle erase operation. By executing the first microinstruction sequence 910, the first command 920 is processed. The command queue 620 (see Figure 6) to obtain the first command. Those skilled in the art will appreciate that there are other ways to obtain the first command. By executing the microinstructions in the first microinstruction sequence 910, an erase command 930 is issued to the flash memory particles. Subsequently, the yield microinstruction in the first microinstruction sequence 910 is executed to make the first microinstruction sequence 910 yield 935. In a further embodiment, when the first microinstruction sequence 910 yields, its execution state (for example, a program counter value, a general counter value, a physical address register value and / or a timer value, etc.) is saved. After the first microinstruction sequence 910 yields, the microinstruction processor 610 (see Figure 6 ) can execute microinstructions 937 in other microinstruction sequences 915. In one example, the microinstruction sequence that the microinstruction processor 610 executes next is selected by the scheduler or scheduling logic. In another example, because there are no other microinstruction sequences waiting to be executed or the priority of the first microinstruction sequence 910 is higher, the scheduler or scheduling logic selects to resume the execution of the first microinstruction sequence 910.

[0145] The other microinstruction sequence 915 also includes a yield microinstruction. By executing the yield microinstruction in the other microinstruction sequence 915, the other microinstruction sequence 915 yields 939. Since the other microinstruction sequence 915 yields, the microprocessor 610 can execute another microinstruction sequence. In one example, the scheduler or scheduling logic selects to resume the execution of the first microinstruction sequence 910. The microinstruction processor 610 continues to execute the first microinstruction sequence 910 by restoring the execution state (e.g., program counter value, general counter value, physical address register value and / or timer value, etc.) when the first microinstruction sequence 910 yielded.

[0146] Next, the second command 940 is obtained and processed by executing the microinstructions in the first microinstruction sequence 910. For example, by executing the microinstructions in the first microinstruction sequence 910, the microinstruction sequence 910 checks the command queue 620 (see Figure 6) whether the second command is received, and after receiving the second command, the second command is processed. Next, by executing the microinstructions in the microinstruction sequence 910, the first microinstruction sequence 910 determines to suspend the erase command issued previously, and then issues an erase suspension command 950 to the flash memory particles. For example, by executing the microinstructions in the first microinstruction sequence 910, the microinstruction sequence 910 determines whether to suspend the erase command issued previously by comparing the priority of the first command and the second command. In another example, based on the first command corresponding to the erase, program or write operation, and the second command corresponding to the read operation, it is determined to suspend the erase command or program command issued previously to the flash memory particles. In still another example, by the first microinstruction sequence 910, before or after executing the step 930 of issuing the erase command, a timer is started. When the first microinstruction sequence 910 determines whether to suspend the erase command issued previously, the value of the timer is also referred to. If the value of the timer is greater than the threshold value, it means that a long time has passed since the issuance of the erase command of the previous flash memory particle, and it can be expected that the erase operation will be completed soon. At this time, if an erase pause command is issued to the flash memory particles to suspend the previous erase operation, and a read command is issued, the improvement effect on the delay of the read operation is not obvious, and the execution delay of the previous erase operation is increased. In this case, the microinstruction sequence 910 will not issue an erase pause command to the flash memory particles. And if the value of the timer is not greater than or less than the threshold value, it means that the previous erase command still needs to be executed for a long time. In this case, if the read command is executed again after waiting for the erase command to complete, the execution delay of the read operation experienced by the user will be significantly increased. Therefore, through the microinstruction in the microinstruction sequence 910, an erase pause command 950 is issued to the flash memory particles. Afterwards, the first microinstruction sequence 910 also suspends the timer.

[0147] Next, by executing the microinstructions in the first microinstruction sequence 910, a read command is issued to the flash memory particle 960. By executing the microinstructions in the first microinstruction sequence 910, it is checked whether the read command is completed 970. For example, in response to obtaining data corresponding to the read command from the flash memory particle, it is determined that the read command is executed. If the read command is executed, an erase recovery command is issued to the flash memory particle 980. In a further embodiment, the timer is restored to continue timing. If the read command has not been executed, the first microinstruction sequence 910 yields 972. In a further embodiment, when the first microinstruction sequence 910 yields, its execution state (for example, the program counter value, the general counter value, the physical address register value and / or the timer value, etc.) is saved. After the first microinstruction sequence 910 yields, the microinstruction processor 610 (see Figure 6) can execute microinstructions 974 in other microinstruction sequences 915. In one example, the microinstruction sequence (e.g., other microinstruction sequences 915) to be executed next by the microinstruction processor 610 is selected by the scheduler or scheduling logic. In another example, because there are no other microinstruction sequences waiting to be executed or the priority of the first microinstruction sequence 910 is higher, the scheduler or scheduling logic chooses to resume the execution of the first microinstruction sequence 910.

[0148] The other microinstruction sequence 915 may also include a yield microinstruction. By executing the yield microinstruction in the other microinstruction sequence 915, the other microinstruction sequence 915 yields 976. When the other microinstruction sequence 915 yields, its execution state (e.g., program counter value, general counter value, physical address register value, and / or timer value, etc.) is saved. After the other microinstruction sequence 915 yields, the microinstruction processor 610 (see Figure 6 ) can select to execute the microinstructions in the first microinstruction sequence 910 or other microinstruction sequences 915. In one example, the scheduler or scheduling logic selects the microinstruction sequence to be executed next by the microinstruction processor 610. In another example, because the first microinstruction sequence 910 is waiting to be executed and / or the priority of the first microinstruction sequence 910 is higher, the scheduler or scheduling logic selects to resume the execution of the first microinstruction sequence 910.

[0149] Next, by executing the microinstructions in the first microinstruction sequence 910, it is checked whether the erase command is completed 990. The erase command is the erase command issued to the flash memory particle in step 930. If the erase command is executed, the execution of the first microinstruction sequence 910 is completed 998. If the erase command is not executed, the first microinstruction sequence 910 yields 992. After the first microinstruction sequence 910 yields, the microinstruction processor 610 (see Figure 6 ) can execute microinstructions 994 in other microinstruction sequences 915. Other microinstruction sequences may also include yield microinstructions. By executing the yield microinstruction in other microinstruction sequences 915, other microinstruction sequences 915 yield 996. After other microinstruction sequences 915 yield, microinstruction processor 610 (see Figure 6 ) can choose to execute microinstructions in the first microinstruction sequence 910 or other microinstruction sequences 915.

[0150] Next, when the first microinstruction sequence 910 is resumed for execution again, it is checked whether the command queue 620 receives a new command. After receiving the new command, by executing the microinstructions in the microinstruction sequence 910, the first microinstruction sequence 910 determines again whether to suspend the erase command issued previously. In a further embodiment, the microinstruction sequence 910 checks the timer again, and if the timer is not greater than or less than the threshold value, and the second command corresponds to the flash memory particle read operation, it is determined to suspend the erase command issued previously again. In another embodiment, the microinstruction sequence 910 compares the priority of the first command with the new command. If the priority of the new command is higher than the priority of the first command, it is determined to suspend the erase command issued previously again. In still another example, as time passes or according to the value of the timer, the priority of the first command, the second command and / or the new command is adjusted. In still another example, when the user or the upper system issues the first command, the second command and / or the new command, the priority of the command is provided. In still another example, the user or the upper system can adjust the priority of the command.

[0151] The new command may be processed by using step 940 of processing the second command and subsequent steps. Also, an erase suspend and / or erase resume command may be issued to the flash memory particles again.

[0152] By providing a microinstruction sequence execution mechanism, as well as microinstructions such as yield, erase pause, and erase resume, the user of the storage device is provided with the ability to control the timing of issuing the pause command. This allows the user of the storage device to participate in the flexible control of the timing of issuing the flash memory pause command, rather than relying on the storage controller to schedule multiple commands to access the flash memory particles. The user of the storage device can participate in the flexible control of the timing of issuing the flash memory pause command by programming, updating, and / or modifying the microinstruction sequence.

[0153] The above discloses various embodiments of the present invention by taking flash memory particles as an example. Those skilled in the art will appreciate that the embodiments of the present invention can also be applied to other types of storage media supporting erase suspend and / or erase resume commands, such as phase change memory, resistive memory, ferroelectric memory, etc.

[0154] The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those skilled in the art.

Claims

1. A method for scheduling a microinstruction sequence, characterized in that: include: When a first command is received, a first microinstruction sequence corresponding to the first command is executed, wherein the first microinstruction sequence causes the controller to perform the following operations: the first microinstruction sequence yields; When receiving the second command, if the first microinstruction sequence is being executed, pausing the first microinstruction sequence; executing a second microinstruction sequence corresponding to the second command, wherein the second microinstruction sequence causes the controller to perform the following operations: the second microinstruction sequence yields; wherein the start position of the second microinstruction sequence includes a yield microinstruction; The method further includes: in response to both the first microinstruction sequence and the second microinstruction sequence having yielded, selecting one of the first microinstruction sequence and the second microinstruction sequence to resume execution.

2. The method according to claim 1, characterized in that The executing the first microinstruction sequence corresponding to the first command also includes: starting a timer.

3. The method according to claim 2, characterized in that When receiving the second command, if the first microinstruction sequence is being executed and if the time recorded by the timer is less than a threshold, pausing the first microinstruction sequence; The second microinstruction sequence is executed.

4. The method according to claim 1, characterized in that: The method further comprises: If the first microinstruction sequence is being executed, and if the second command has a higher priority than the first command, pausing the first microinstruction sequence; The second microinstruction sequence is executed.

5. The method according to any one of claims 1 to 4, characterized in that When the first command indicates a memory erase operation and / or a memory programming operation, and the second command indicates a memory read operation, suspending the first microinstruction sequence includes: sending a command to suspend the memory erase operation and / or the memory programming operation to the memory.

6. A method for scheduling a microinstruction sequence, characterized in that: include: executing a microinstruction sequence to process a first command, and if the first command indicates an erase operation, issuing an erase command to the storage device; executing the microinstruction sequence, checking a second command, and if the second command indicates a read operation, issuing a command to suspend the erase operation to the storage device, and issuing a read command to the storage device; The method further comprises: executing the microinstruction sequence, after issuing a read command to the storage device, checking the execution status of the read command; If the execution of the read command is not completed, the microinstruction sequence yields; another microinstruction sequence is selected for execution, and the other microinstruction sequence yields; wherein the starting position of the other microinstruction sequence includes a yield microinstruction; in response to both the microinstruction sequence and the other microinstruction sequence yielding, one of the microinstruction sequence and the other microinstruction sequence is selected to resume; If the execution of the read command is completed, the data returned by the storage device is obtained, and a command to resume the erase operation is issued.

7. The method according to claim 6, characterized in that The method further includes: after the command to resume the erase operation is issued, the microinstruction sequence yields.

8. A computing device readable medium, characterized in that: A program is stored on the computing device readable storage medium, the program comprising a microinstruction sequence; when executed by the computing device, the program enables the computing device to be configured to perform the method according to any one of claims 1-7.

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