A circuit for power-off reset of a magnetic latching relay

Abstract

The present invention discloses a circuit for power-off reset of a magnetic latching relay, which includes a field-effect transistor Q1, a field-effect transistor Q2, a triode Q3, a field-effect transistor Q4, a field-effect transistor Q5 and a relay K. The models of the field-effect transistor Q2 and the field-effect transistor Q5 are AO3401. The G pole of the field-effect transistor Q1 is connected to the output end of a diode D2, and is also connected to the input end of a capacitor C1 and the input end of a resistor R2. The S pole of the field-effect transistor Q1 is connected to the output end of the capacitor C1 and the output end of the resistor R2 and then grounded. The circuit for power-off reset of this magnetic latching relay has a fast response speed, is economical, simple and low in cost, is easy to debug, does not require manual intervention, and has high flexibility in use and can be transplanted to different application scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of magnetic latching relays, and specifically to a circuit for power-off reset of a magnetic latching relay. Background Art

[0002] Once a magnetic latching relay is closed and powered off without reset, it will cause the relay to malfunction when powered on next time, affecting the loads and devices connected to the relay. Currently, for the power-off reset of magnetic latching relays, an MCU is generally used, or manual reset is performed, which increases costs and complexity and has poor flexibility in use.

[0003] Magnetic latching relays are widely used in high-current applications, and the drive is relatively simple. Just applying corresponding pulses can open or close them. Since the magnetic latching relay remains in the closed state under the action of residual magnetism after power-off, if it is not reset, the relay will still remain in the closed state when powered on next time, causing misoperation for loads and devices that require time for initialization and potentially causing permanent damage to the devices. In a harsh environment, the MCU in the MCU reset circuit may not work properly, and the program may run away and crash.

[0004] Currently, additional costs are required for an MCU to detect power-off reset. The program debugging is complex, the anti-interference ability is poor, the software code is too complex and not conducive to debugging and maintenance, and the redundancy of the code affects the program execution efficiency. Manual reset is not flexible, the operation is not simple and troublesome, it requires manual intervention, and the cost is high. The circuit is complex and the debugging is also complex, and the transplantation and modification are not flexible.

[0005] Based on the above defects, a circuit for power-off reset of a magnetic latching relay is proposed. Summary of the Invention

[0006] The purpose of the present invention is to provide a circuit for power-off reset of a magnetic latching relay, which has a fast response speed, is economical, simple, and low-cost, is easy to debug, does not require manual intervention, has high flexibility in use and can be transplanted to different application scenarios, and solves the problems in the prior art that manual reset is not flexible, the operation is not simple and troublesome, it requires manual intervention, and the cost is high, the circuit is complex and the debugging is also complex, and the transplantation and modification are not flexible.

[0007] To achieve the above object, the present invention provides the following technical solution: A circuit for power-off reset of a magnetic latching relay, including a field effect transistor Q1, a field effect transistor Q2, a triode Q3, a field effect transistor Q4, a field effect transistor Q5 and a relay K. The G pole of the field effect transistor Q1 is connected to the output end of the diode D2, and is connected to the input end of the capacitor C1 and the input end of the resistor R2. The S pole of the field effect transistor Q1 is connected to the output end of the capacitor C1 and the output end of the resistor R2 and then grounded; the input end of the diode D2 is connected to the output end of the diode D1, the input end of the diode D1 is connected to the output end of the resistor R1, and the input end of the resistor R1 is connected to the Vin power supply terminal; the Vin power supply terminal is connected to the input end of the diode D3, the input end of the diode D4, the input end of the resistor R9 and the input end of the capacitor CE1. The output end of the capacitor CE1 is grounded. The output end of the diode D3 is connected to the S pole of the field effect transistor Q2, and is connected to the input end of the resistor R3 and the input end of the resistor R4. The G pole of the field effect transistor Q2 is connected to the output end of the resistor R3 and then connected to the collector of the triode Q3, and is connected to the input end of the resistor R6. The D pole of the field effect transistor Q2 is connected to the input end of the capacitor CE2, and is connected to the S pole of the field effect transistor Q5 and the pin 2 of the relay K; the output end of the diode D4 is connected to the input end of the resistor R5, the output end of the resistor R5 is connected to the base of the triode Q3, and is connected to the input end of the resistor R7. The emitter of the triode Q3 is connected to the output end of the resistor R7, the output end of the resistor R6 and the output end of the capacitor CE2 and then grounded; the input end of the resistor R9 is connected to the output end of the diode D8, the input end of the diode D8 is connected to the G pole of the field effect transistor Q5, and is connected to the input end of R10. The output end of the resistor R10 is grounded; the D pole of the field effect transistor Q5 is connected to the input end of the diode D7, the output end of the diode D7 is connected to the G pole of the field effect transistor Q4, and is connected to the input end of the capacitor C2 and the input end of the resistor R8. The S pole of the field effect transistor Q4 is connected to the output end of the capacitor C2 and the output end of the resistor R8 and then grounded; the D pole of the field effect transistor Q1 is connected to the input end of the diode D5, and is connected to the pin 1 of the relay K1. The output end of the diode D5 is connected to the output end of the diode D6, and is connected to the pin 2 of the relay K. The input end of the diode D6 is connected to the D pole of the field effect transistor Q4, and is connected to the pin 3 of the relay K. The pin 4 of the relay K is connected to the output of the K1 terminal, and the pin 5 of the relay K is connected to the output of the K2 terminal.

[0008] Preferably, the model of the diode D7 is IN4148.

[0009] Preferably, the models of the field effect transistor Q2 and the field effect transistor Q5 are AO3401.

[0010] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0011] The circuit for power-off reset of this magnetic latching relay has a fast response speed, is economical, simple and low-cost, is easy to debug, does not require manual intervention, and has high flexibility in use and can be transplanted to different application scenarios. Brief Description of the Drawings

[0012] Figure 1 It is the circuit schematic diagram of the present invention. Detailed Embodiments

[0013] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0014] Please refer to Figure 1, A circuit for power-off reset of a magnetic latching relay, including field-effect transistor Q1, field-effect transistor Q2, triode Q3, field-effect transistor Q4, field-effect transistor Q5 and relay K. The models of field-effect transistor Q2 and field-effect transistor Q5 are AO3401. The G pole of field-effect transistor Q1 is connected to the output end of diode D2, and is also connected to the input end of capacitor C1 and the input end of resistor R2. The S pole of field-effect transistor Q1 is connected to the output end of capacitor C1 and the output end of resistor R2 and then grounded; the input end of diode D2 is connected to the output end of diode D1, the input end of diode D1 is connected to the output end of resistor R1, and the input end of resistor R1 is connected to the Vin power supply terminal; the Vin power supply terminal is connected to the input end of diode D3, the input end of diode D4, the input end of resistor R9 and the input end of capacitor CE1. The output end of capacitor CE1 is grounded. The output end of diode D3 is connected to the S pole of field-effect transistor Q2, and is also connected to the input end of resistor R3 and the input end of resistor R4. The G pole of field-effect transistor Q2 is connected to the output end of resistor R3 and then connected to the collector of triode Q3, and is also connected to the input end of resistor R6. The D pole of field-effect transistor Q2 is connected to the input end of capacitor CE2, and is also connected to the S pole of field-effect transistor Q5 and pin 2 of relay K; the output end of diode D4 is connected to the input end of resistor R5, the output end of resistor R5 is connected to the base of triode Q3, and is also connected to the input end of resistor R7. The emitter of triode Q3 is connected to the output end of resistor R7, the output end of resistor R6 and the output end of capacitor CE2 and then grounded; the input end of resistor R9 is connected to the output end of diode D8, the input end of diode D8 is connected to the G pole of field-effect transistor Q5, and is also connected to the input end of R10. The output end of resistor R10 is grounded; the D pole of field-effect transistor Q5 is connected to the input end of diode D7, the output end of diode D7 is connected to the G pole of field-effect transistor Q4, and is also connected to the input end of capacitor C2 and the input end of resistor R8. The model of diode D7 is IN4148. The S pole of field-effect transistor Q4 is connected to the output end of capacitor C2 and the output end of resistor R8 and then grounded; the D pole of field-effect transistor Q1 is connected to the input end of diode D5, and is also connected to pin 1 of relay K1. The output end of diode D5 is connected to the output end of diode D6, and is also connected to pin 2 of relay K. The input end of diode D6 is connected to the D pole of field-effect transistor Q4, and is also connected to pin 3 of relay K. Pin 4 of relay K is connected to the output of K1 terminal, and pin 5 of relay K is connected to the output of K2 terminal.

[0015] The principle of the circuit for power-off reset of the magnetic latching relay is as follows:

[0016] When the external Vin input voltage is normal, the field effect transistors Q1 and Q2 are forward-biased and conducting, and there is current flowing through the K_ON terminal of the relay K. The K1 terminal and the K2 terminal of the relay K are closed. When the external Vin input voltage drops, there is no voltage to maintain the conduction of the field effect transistors Q1 and Q2, and the field effect transistors Q1 and Q2 are turned off. There is no current flowing through the K_ON terminal of the relay K. Due to the residual magnetism of the relay K, the K1 terminal and the K2 terminal of the relay K remain closed. The gate of the field effect transistor Q5 is reverse-biased and conducting, the field effect transistor Q4 is forward-biased and conducting, and there is current flowing through the K_OFF terminal of the relay K. The K1 terminal and the K2 terminal of the relay K are disconnected. At this time, the call is hung up, and the load device on the relay K is disconnected.

[0017] The working process is as follows:

[0018] When Vin has a normal operating voltage, the diode D1 conducts, the field effect transistor Q1 conducts, the triode Q3 and the field effect transistor Q2 conduct, the diode D8 conducts, and the field effect transistor Q5 is turned off, and the relay K is closed. When Vin loses power and has no voltage, the diode D1 is not sufficient to break down and conduct, the field effect transistor Q1 is turned off, the triode Q3 has no forward-biased voltage and is turned off, the field effect transistor Q2 has no forward-biased voltage and is turned off, the diode D8 is turned off, and the field effect transistor Q5 is reverse-biased and conducting. When Vin loses power, the reset power supply is provided by the capacitor CE2. According to different occasions, the capacitor CE2 can be composed of multiple capacitors in parallel. Through the discharge circuit formed by the field effect transistor Q4 and the relay K_OFF, the reset current of the relay K is provided, and the relay K is reset and disconnected; the capacitor C2 is adjusted according to the reset delay requirement to avoid conflicts between the K_ON terminal and the K_OFF terminal of the relay K.

[0019] In summary, the circuit for power-off reset of this magnetic latching relay has a fast response speed, is economical, simple, and low-cost, is easy to debug, does not require manual intervention, has high flexibility in use, and can be transplanted to different application scenarios.

[0020] Although the embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A circuit for power-off reset of a magnetic latching relay, comprising a field effect transistor Q1, a field effect transistor Q2, a triode Q3, a field effect transistor Q4, a field effect transistor Q5 and a relay K. The G pole of the field effect transistor Q1 is connected to the output end of the diode D2, and is connected to the input end of the capacitor C1 and the input end of the resistor R2. The S pole of the field effect transistor Q1 is connected to the output end of the capacitor C1 and the output end of the resistor R2 and then grounded; the input end of the diode D2 is connected to the output end of the diode D1, the input end of the diode D1 is connected to the output end of the resistor R1, and the input end of the resistor R1 is connected to the Vin power supply terminal ； The Vin power supply terminal is connected to the input end of the diode D3, the input end of the diode D4, the input end of the resistor R9 and the input end of the capacitor CE1. The output end of the capacitor CE1 is grounded. The output end of the diode D3 is connected to the S pole of the field effect transistor Q2, and is connected to the input end of the resistor R3 and the input end of the resistor R4. The G pole of the field effect transistor Q2 is connected to the output end of the resistor R3 and then connected to the collector of the triode Q3, and is connected to the input end of the resistor R6. The D pole of the field effect transistor Q2 is connected to the input end of the capacitor CE2, and is connected to the S pole of the field effect transistor Q5 and the pin 2 of the relay K; the output end of the diode D4 is connected to the input end of the resistor R5, the output end of the resistor R5 is connected to the base of the triode Q3, and is connected to the input end of the resistor R7. The emitter of the triode Q3 is connected to the output end of the resistor R7, the output end of the resistor R6 and the output end of the capacitor CE2 and then grounded; the input end of the resistor R9 is connected to the output end of the diode D8, the input end of the diode D8 is connected to the G pole of the field effect transistor Q5, and is connected to the input end of R10, and the output end of the resistor R10 is grounded; The models of the field effect transistor Q2 and the field effect transistor Q5 are AO3401; The D pole of the field effect transistor Q5 is connected to the input end of the diode D7, the output end of the diode D7 is connected to the G pole of the field effect transistor Q4, and is connected to the input end of the capacitor C2 and the input end of the resistor R8. The S pole of the field effect transistor Q4 is connected to the output end of the capacitor C2 and the output end of the resistor R8 and then grounded; the model of the diode D7 is IN4148; The D pole of the field effect transistor Q1 is connected to the input end of the diode D5, and is connected to the pin 1 of the relay K1. The output end of the diode D5 is connected to the output end of the diode D6, and is connected to the pin 2 of the relay K; The input end of the diode D6 is connected to the D pole of the field effect transistor Q4, and is connected to the pin 3 of the relay K. The pin 4 of the relay K is connected to the output of the K1 terminal, and the pin 5 of the relay K is connected to the output of the K2 terminal.

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