Lead stabilization in semiconductor packages

Abstract

This disclosure relates to lead stabilization in semiconductor packages. One or more embodiments generally described pertain to a semiconductor package including a plurality of leads and a method of forming the same. The plurality of leads includes active leads electrically coupled to bonding pads of a semiconductor die and thereby coupled to active components of the semiconductor die, and passive leads not electrically coupled to bonding pads of the semiconductor die. The active leads have surfaces exposed at the lower surface of the semiconductor package and form solder joints, while the passive leads are not exposed at the lower surface of the package.

Description

Technical Field

[0001] The embodiments disclosed herein relate to semiconductor packages and methods for assembling them. Background Technology

[0002] Leadless (or leadless) packages are typically used in applications requiring small package sizes. Typically, a flat leadless package provides near-chip-level encapsulation formed by a planar lead frame. A solder pad located on the lower surface of the package provides electrical connection to another device, such as a printed circuit board (PCB). Leadless packages (e.g., quad flat leadless (QFN) packages) comprise a semiconductor die or chip mounted to a lead frame support surface (e.g., die pads or lead ends). The semiconductor die is typically electrically coupled to the leads via conductive wires.

[0003] The bonding process for conductive wires may involve thermal and ultrasonic energy. Due to lead instability, a bouncing effect may occur when the conductive wire is bonded to the lead. The ultrasonic energy introduced during the bonding process may exacerbate the bouncing effect, and the bouncing effect may result in a weaker bond between the lead and the conductive wire. Therefore, improvements are needed. Summary of the Invention

[0004] The general description of one or more embodiments relates to a semiconductor package including multiple leads and a method of forming the same. The multiple leads include active leads electrically coupled to bonding pads on a semiconductor die and thereby coupled to active components on the semiconductor die, and passive leads not electrically coupled to bonding pads on the semiconductor die. The active leads have surfaces exposed at the lower surface of the semiconductor package and form solder joints, while the passive leads are not exposed at the lower surface of the package. In one or more embodiments, the passive leads provide additional stability during assembly, e.g., during die attachment and conductive wiring bonding processes.

[0005] The passive leads have a reduced thickness relative to at least a portion of the active leads. In one embodiment, the passive leads are half-etched, and only a portion of the active leads are half-etched. The total thickness of each passive lead is less than at least a portion of the thickness of the active leads. Both passive and active leads may be exposed at a side surface of the semiconductor package. In at least one embodiment, the leads are formed by a lead frame and are arranged symmetrically about at least one axis of the lead frame (e.g., a central axis). Attached Figure Description

[0006] In the accompanying drawings, the same reference numerals identify the same elements. The dimensions and relative positions of the elements in the drawings need not be drawn to scale.

[0007] Figure 1AA top perspective view of a semiconductor package according to one embodiment is shown.

[0008] Figure 1B yes Figure 1A A bottom view of a semiconductor package.

[0009] Figure 1C yes Figure 1A A side view of a semiconductor package.

[0010] Figure 2A It is according to one embodiment for forming Figure 1A A top view of the lead frame array of a semiconductor package.

[0011] Figure 2B yes Figure 2A A bottom view of the lead frame array.

[0012] Figure 3A yes Figure 2A A top view of the individual lead frames of the lead frame array.

[0013] Figure 3B yes Figure 2B A bottom view of the individual lead frames of the lead frame array.

[0014] Figures 4A-4F yes Figure 1A Cross-sectional views of semiconductor packages at various stages of assembly. Detailed Implementation

[0015] One or more embodiments described herein relate to a semiconductor package comprising a plurality of leads and a method of forming the same. The plurality of leads includes active leads electrically coupled to bonding pads of a semiconductor die and thereby coupled to active components of the semiconductor die, and passive leads not electrically coupled to bonding pads of the semiconductor die. The active leads have surfaces exposed at the lower surface of the semiconductor package and form solder joints, while the passive leads are not exposed at the lower surface of the package. In one or more embodiments, the passive leads provide additional stability during assembly, e.g., during die attachment and conductive wiring bonding processes.

[0016] Figure 1A A perspective view of a semiconductor package 10 according to one embodiment is shown. The semiconductor package 10 is an on-line chip (COL) semiconductor package. Figure 1B This is a bottom view of the semiconductor package 10, and Figure 1C This is a side view of the semiconductor package 10.

[0017] The semiconductor package 10 includes an upper surface 12a, a lower surface 12b, and a side surface 12c. The semiconductor package 10 includes a plurality of leads 14, each lead 14 having an internal portion 16a supporting a semiconductor die or chip 18. Figure 4C ) and the outer portion 16b extending to the side surface 12c of the semiconductor package 10.

[0018] Semiconductor die 18 is made of a semiconductor material such as silicon and includes an active surface on which one or more electronic components (e.g., integrated circuits) are integrated. The active surface of semiconductor die 18 includes conductive bonding pads electrically connected to one or more electronic components.

[0019] The semiconductor die 18 is coupled to an internal portion 16a of a plurality of leads 14 by means of a material configured to hold the semiconductor die 18 in place during assembly. In one embodiment, the semiconductor die 18 is coupled to the internal portion 16a of the plurality of leads 14 by an adhesive material such as glue, paste, tape, etc. In other embodiments, the semiconductor die 18 is coupled to die pads (not shown) supporting the semiconductor die, and as is known in the art, the plurality of leads are located around and spaced apart from the die pads.

[0020] Multiple leads 14 may be arranged symmetrically around one or more axes, and may also be arranged symmetrically around the axis of the semiconductor die 18. The multiple leads 14 include active leads 14a and passive leads 14b.

[0021] Although the semiconductor die 18 is coupled to both active lead 14a and passive lead 14b for support, the active surface of the semiconductor die 18 is electrically coupled only to the active lead 14a. Specifically, the bonding pads of the semiconductor die 18 are electrically coupled to the surface of the active lead 14a via conductive wiring 20. For example, a first end 22 of the conductive wiring 20 is coupled to the bonding pad of the semiconductor die 18, and a second end 24 of the conductive wiring 20 is coupled to the first surface of the active lead 14a.

[0022] As previously described, the passive lead 14b of the plurality of leads 14 is not electrically coupled to the active surface of the semiconductor die 18. Therefore, the active lead 14a is electrically coupled to the integrated circuit on the active surface of the semiconductor die 18, while the passive lead 14b is electrically decoupled from the integrated circuit on the active surface of the semiconductor die 18.

[0023] In other embodiments, the active surface of the semiconductor die 18 may be electrically coupled to the active lead 14a via other techniques (e.g., flip-chip technology known in the art). In such embodiments, the semiconductor die is flip-chip-faced and the conductive bumps are located between the active lead and the bonding pads of the semiconductor die.

[0024] Encapsulation 30 covers a portion of the semiconductor die 18, conductive wiring 20, and leads 14. Encapsulation 30 is an insulating material, such as an encapsulating material, that protects the electronic components and conductive wiring of the semiconductor die from damage (e.g., corrosion, physical damage, moisture damage, or other causes of damage to electrical components and materials). In some embodiments, encapsulation 30 is at least one of a polymer, silicone, resin, polyimide, and epoxy resin. Encapsulation 30 in... Figure 1A The portion is shown as transparent, allowing easy viewing of the internal details of the semiconductor package 10. However, the package is typically made of an opaque material.

[0025] refer to Figure 1B The active lead 14a has a second surface that is exposed from the package body 30 at the lower surface 12b of the semiconductor package 10 to form a solder area. The remaining portion of the active lead 14a is covered by the package body 30. Figure 1B As shown, the passive lead 14b is not exposed from the package body 30 at the lower surface 12b of the semiconductor package 10. Instead, the package body 30 covers the passive lead 14b at the lower surface.

[0026] refer to Figure 1C Both passive lead 14b and active lead 14a have surfaces exposed at the side surface 12c of the semiconductor package 10. The surfaces of passive lead 14b and active lead 14a may be flush with the surface of the package 30. The surface of active lead 14a extends along the corresponding side surface 12c of the semiconductor package 10 to the lower surface 12b of the semiconductor package 10, while the surface of passive lead 14b does not extend to the lower surface 12b of the semiconductor package 10. That is, the package 30 lies between the exposed surface of passive lead 14b and the lower surface 12b of the semiconductor package 10. As previously described, the package 30 covers the surface of passive lead 14b at the lower surface 12b of the semiconductor package 10 such that the surface of passive lead 14b is not exposed at the lower surface 12b of the semiconductor package 10.

[0027] like Figure 1C As best shown, the active lead 14a and the passive lead 14b have different thicknesses. In at least one embodiment, the thickness of the passive lead 14b is approximately half the thickness of the outer portion of the active lead 14a, for example, between 40% and 60%. As will be explained in more detail below, the passive lead 14b provides stability during the assembly of the semiconductor package 10. In at least one embodiment, the passive lead 14b and the active lead 14a provide suitable support for the semiconductor die 18 during conductive wiring bonding.

[0028] The number and combination of active leads 14a may differ from those shown. Any number or combination of active leads 14a can be selected, including active leads placed along both sides (e.g., opposite sides) of the semiconductor package or only along one side of the semiconductor package. Generally, which leads 14a will be active leads 14a is typically determined based on customer requirements and the application of the semiconductor package.

[0029] The active lead 14a has a first thickness and a second thickness. The first thickness is located in the inner portion 16a of the active lead 14a, and the second thickness is located in the outer portion 16b of the active lead 14a. Figure 4F The first thickness is less than the second thickness. In some embodiments, the first thickness is between 40% and 60% of the second thickness, and in one embodiment, the first thickness is about 50% of the second thickness. As previously described, the lower surface of the outer portion 16b of the active lead 14a forms a solder area for coupling a semiconductor package to another device.

[0030] The passive lead 14b has a constant thickness, which can be the same as the first thickness of the active lead. The outer portion 16b of the passive lead 14b has the first thickness, while the outer portion 16b of the active lead 14a has a second thickness, which is greater than the first thickness. The package 30 covers the lower surface of the passive lead 14b and the portion of the active lead 14a with the first thickness.

[0031] Figure 2A An example of forming a semiconductor package (e.g., according to one embodiment) is shown. Figures 1A to 1C The upper surface of the lead frame array 34 of the semiconductor package 10. Figure 2B It shows Figure 2A The lower surface of the lead frame array 34. The lead frame array 34 is made of a conductive material such as metal. In at least one embodiment, the lead frame array 34 is made of copper or a copper alloy. The lead frame 34 is shown in a stippling manner to clearly show which portions form the lead frame and which portions do not, and to indicate depth. In particular, the bottom view of the lead frame 34 includes coarser stippling to indicate the thicker portions of the lead frame 34.

[0032] The lead frame array 34 includes a plurality of individual lead frames 34a arranged in columns and rows, each lead frame for forming a corresponding semiconductor package. The leads 14 of adjacent individual lead frames 34a are coupled together by connecting rods 36. In at least one embodiment, the leads 14 are arranged symmetrically around one or more axes (e.g., a central axis) of the individual lead frame 34a.

[0033] During assembly, the leads 14 of adjacent individual lead frames 34a provide appropriate stability for any active leads during the conductive wire bonding process. The active leads of adjacent individual lead frames can be opposite each other at the connecting rod 36, or passive leads can be opposite active leads. Furthermore, the assembly of the package is improved by providing more leads than are used as active leads in the final semiconductor package. In particular, passive leads provide stability during the conductive wire bonding process.

[0034] Figure 3A and Figure 3B Close-up views of the upper and lower surfaces of the individual lead frame 34a are shown, respectively. (Reference) Figure 3A The upper surfaces of the leads 14 (including active and passive leads) of the individual lead frame 34 lie in the same plane as indicated by the same dot volume. (Reference) Figure 3B The lower surface of the passive lead 14b and the first portion of the active lead 14a of the individual lead frame 34 lie in the same plane as indicated by the same dot volume. The outer portion of the active lead 14a lies in a different plane as indicated by the increased dot volume. In particular, the outer portion of the active lead 14a is thicker than the inner portion and has a surface in a plane extending outside the page.

[0035] Figure 4A and Figure 4B The diagram illustrates the manufacturing process. Figure 2A and Figure 2B The various stages of the lead frame array 34. Figure 4A The lead frame array 34 already has leads, but passive leads have not yet been formed.

[0036] like Figure 4A As shown, the outer portion of the solder area 31 forming the active lead 14a is covered with material, allowing the remaining leads to be etched. In one embodiment, the active lead 14a is plated with one or more metallic materials, such as Au, Ag, Ni / Pd / Ag, Ni / Pd / Au-Ag alloy, or Ni / Pd / Au / Ag, thereby forming the solder area of ​​the active lead 14a. In another embodiment, as is known in the art, the outer portion of the active lead 14a is patterned using a photosensitive material.

[0037] refer to Figure 4BThe lower surfaces of leads 14 (active leads 14a and passive leads 14b) are etched using standard semiconductor etching techniques. Specifically, the internal portions of the active leads 14 that do not include plated metal or photosensitive materials are etched, and the entire surface of the passive leads 14b is etched. The etching occurs at a depth of approximately half the original thickness of the lead frame (also known as half-etching). In one embodiment, the etching occurs at approximately 50% of the original thickness of the leads. In some other embodiments, the etching occurs between 40% and 60% of the original thickness of the leads. After etching, as... Figure 1B As shown, each individual lead frame 34a of the lead frame array 34 includes an active lead 14a and a passive lead 14b.

[0038] Figures 4C-4F The illustration shows an assembly according to one embodiment. Figure 1A The various stages of semiconductor packaging. In particular, such as Figure 4C As shown, the semiconductor die 18 is coupled to the internal portion 16a of the lead 14. Specifically, the semiconductor die 18 is coupled to the internal portion 16a of both the active lead 14a and the passive lead 14b. By providing both the active lead 14a and the passive lead 14b for supporting each semiconductor die 18, the support structure for the semiconductor die is improved. Furthermore, the symmetrical arrangement of the multiple leads provides improved support for the semiconductor die 18 during die attachment. Additionally, the leads of adjacent individual lead frames 34a are coupled together by connecting rods 36 and are able to provide improved support to each other during die attachment.

[0039] refer to Figure 4D During the bonding process, the semiconductor die 18 is electrically coupled to the active lead 14a. Specifically, the first end 22 of the conductive connection 20 is coupled to the bonding pad of the semiconductor die 18, and the second end 24 of the conductive connection 20 is coupled to the outer portion 16b of the active lead 14a. The bonding process for coupling the conductive connection 20 may involve thermal and ultrasonic energy. Although only one conductive connection is shown for each individual lead frame, it should be understood that the conductive connection is coupled to... Figure 4D Other active leads and bonding pads of the semiconductor die not shown.

[0040] During the bonding process that couples the conductive wire 20 to the active lead 14a, all leads 14 (both active and passive leads 14b) provide stability. For example, when ultrasonic energy is applied during the bonding process, the stability of the lead frame, partially generated by the passive leads, eliminates or reduces any bouncing effects that the ultrasonic energy might introduce. In this respect, a stronger bond can be provided between the active lead 14a and the conductive wire 20.

[0041] As mentioned earlier, the number and location of active leads can be determined, for example, by the customer, based on the specific application of the semiconductor package. However, the number of passive leads can be selected based on the desired level of stability during manufacturing.

[0042] like Figure 4E As shown, a package 30 is formed on portions of the semiconductor die 18, conductive wiring 20, and a plurality of leads 14 to form a semiconductor package. In at least one embodiment, the package 30 is formed in a mold. Specifically, as is known in the art, a lead frame array 34 is placed in the mold, and a molding material such as resin is introduced into the mold. In at least one embodiment, the molding material is hardened in a curing step to form the package 30.

[0043] like Figure 4E As shown, package 30 is formed on the upper and lower surfaces of passive lead 14b. The outer portion 16b of active lead 14a remains exposed from package 30 to form a solder area, while the inner portion 16a of active lead 14a at the lower surface is covered by package 30.

[0044] The assembly process also includes separating the semiconductor package into individual packages 10. Specifically, this involves cutting at... Figure 4E The cutting occurs at the location indicated by the arrow, and the cut separates the connected semiconductor package into pieces as shown. Figure 4F The individual semiconductor package 10 is shown. The semiconductor package 10 is separated by cutting through the connecting rod 36, package body 30, and leads. The cutting method can be any method suitable for separating the semiconductor package (including sawing and laser cutting). Although not shown, as is known in the art, the attached semiconductor package can be secured to a support structure such as tape during the cutting step.

[0045] During cutting, such as Figure 1C As shown, the side surfaces of both the active lead 14a and the passive lead 14b are exposed at the side surface of the individual semiconductor package.

[0046] The manufacturing and assembly stages can also be performed in different sequences. For example, the leads can be partially etched after the semiconductor die has been coupled to the lead frame. Furthermore, although the embodiment shown in the figures illustrates leads supporting the semiconductor, in other embodiments, the lead frame package includes die pads supporting the semiconductor die.

[0047] The various embodiments described above can be combined to provide other embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned and / or listed in the application data sheets are incorporated herein by reference in their entirety. If it is necessary to employ the concepts of various patents, applications, and publications to provide other embodiments, aspects of the embodiments may be modified.

[0048] These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but rather as encompassing all possible embodiments and the full scope of equivalents claimed by such claims. Therefore, the claims are not limited by the disclosure.

Claims

1. A semiconductor package, comprising: A plurality of leads, the plurality of leads having a first end spaced apart from the second end, the plurality of leads comprising: Multiple active leads, each active lead including a first outer surface located at the second end; and Multiple passive leads, each passive lead including a second outer surface located at the second end; A semiconductor die having an active surface opposite a back surface coupled to a first end of the plurality of leads, the semiconductor die including a plurality of bonding pads on the active surface; A conductive wire having a first end coupled to a first bonding pad among a plurality of bonding pads on the active surface, and a second end coupled to a second end of a first active lead among the plurality of active leads; and A package covers the semiconductor die, the conductive wiring, and the first ends of the plurality of leads. The first outer surfaces of the plurality of active leads are exposed from the package and form solder pads. The second outer surfaces of the plurality of passive leads are covered by the package. The active surface of the semiconductor die is electrolytically coupled to the plurality of passive leads, and the plurality of passive leads are electrolytically coupled to the active surface of any other semiconductor die in the semiconductor package. The plurality of passive leads are exposed at corresponding side surfaces of the semiconductor package, and The plurality of passive leads are coplanar with the package body at the respective side surfaces of the semiconductor package.

2. The semiconductor package of claim 1, wherein the thickness of the plurality of passive leads is less than half the thickness of the second end of the plurality of active leads.

3. The semiconductor package of claim 1, wherein the plurality of leads are arranged symmetrically around a first axis of the semiconductor die.

4. The semiconductor package of claim 3, wherein the plurality of leads are arranged symmetrically about a second axis, wherein the second axis is orthogonal to the first axis.

5. The semiconductor package of claim 1, wherein the plurality of active leads extend along respective side surfaces of the semiconductor package to the first outer surface of the semiconductor package.

6. A semiconductor package, comprising: A plurality of active leads, the plurality of active leads having first ends spaced apart from second ends, each second end having a first surface; A passive lead, wherein the passive lead has a first end and a second end; A semiconductor die having a back surface opposite an active surface, first ends of a plurality of active leads coupled to the back surface, and first ends of a passive lead coupled to the back surface, the semiconductor die including a plurality of bonding pads on the active surface; A conductive wire having a first end coupled to the plurality of bonding pads on the active surface, and a second end opposite the first end and coupled to the second end of the plurality of active leads; and The package is located on portions of the conductive wiring, the semiconductor die, the passive leads, and the plurality of active leads. The active surface of the semiconductor die is electrolytically coupled to the passive lead, and the passive lead is electrolytically coupled to the active surface of any other semiconductor die in the semiconductor package. The passive leads are exposed at the corresponding side surfaces of the semiconductor package, and The passive leads are coplanar with the package body at the respective side surface of the semiconductor package.

7. The semiconductor package of claim 6, wherein a second surface opposite to the first surface of the second end of the plurality of active leads is exposed from the package body and forms a solder area.

8. The semiconductor package of claim 7, wherein the inner and outer portions of the passive leads are covered by the package body.

9. The semiconductor package of claim 6, wherein the thickness of the first end of the passive lead is less than the thickness of the first end of the plurality of active leads.

10. The semiconductor package of claim 9, wherein the thickness of the first end of the passive lead is less than half the thickness of the first end of the plurality of active leads.

11. The semiconductor package of claim 6, comprising a plurality of passive leads, wherein the plurality of passive leads and the plurality of active leads are arranged symmetrically about at least one axis.

12. A method of forming a semiconductor package, comprising: Couple a semiconductor die to multiple leads; The bonding pads of the semiconductor die are electrically coupled to a first set of multiple leads to form multiple active leads, the multiple active leads having first ends spaced apart from second ends, each second end having a first surface, wherein a second set of the multiple leads is decoupled from the bonding pads of the semiconductor die and forms passive leads, the passive leads having first ends and second ends, wherein the semiconductor die has a back surface opposite the active surface, the first ends of the multiple active leads are coupled to the back surface, and the first ends of the passive leads are coupled to the back surface, the semiconductor die including the bonding pads on the active surface; as well as A package is formed on some portions of the semiconductor die, the passive leads, and the plurality of active leads. The active surface of the semiconductor die is electrolytically coupled to the passive lead, and the passive lead is electrolytically coupled to the active surface of any other semiconductor die in the semiconductor package. The passive leads are exposed at the corresponding side surfaces of the semiconductor package, and The passive leads are coplanar with the package body at the respective side surface of the semiconductor package.

13. The method of claim 12, wherein the electrical coupling includes coupling a first end of the conductive wire to the bonding pad of the semiconductor die, and coupling a second end of the conductive wire to the first set of a plurality of leads.

14. The method of claim 12, wherein the surface of the passive leads is covered by the package at the back surface of the package, and wherein the solder pads of the plurality of active leads are exposed from the package at the back surface.

15. The method of claim 12, wherein the second set of the plurality of leads is half-etched before coupling the semiconductor die to the plurality of leads.

16. The method of claim 15, wherein the inner portion of the first set of the plurality of leads is half-etched before coupling the semiconductor die to the plurality of leads.

17. The method of claim 12, wherein forming the package comprises using a mold to introduce molding material to form the package.

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