Display device

Abstract

A display device is disclosed. The display device can include a substrate, a plurality of pixels, a first driver, a scan line, a first fan-out line, and a first electrostatic discharge portion, wherein the substrate includes a display area and a non-display area, the plurality of pixels are disposed in the display area, each pixel includes a pixel transistor and a light emitting element connected to the pixel transistor, the first driver is disposed in the non-display area and configured to provide a scan signal to the pixels, the scan line is configured to transmit the scan signal to the pixels, the first fan-out line is disposed in the non-display area and connected to the scan line, and the first electrostatic discharge portion is disposed in the non-display area and located between the first fan-out line and the scan line. The first electrostatic discharge portion can include a bottom metal layer arranged on the substrate and a transistor arranged on the bottom metal layer and electrically connected to the bottom metal layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from and all benefits derived from Korean Patent Application No. 10-2019-0047872, filed on April 24, 2019, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] Generally, a display device may include a display area for displaying an image and a non-display area surrounding a side of the display area.

[0005] In recent years, as interest in information display and demand for the use of portable information media have increased, demand and commercialization of display devices have increased and developed. In addition, in order to meet the demand for increased display area, there is a desire to reduce the non-display area of ​​the display device. Summary of the Invention

[0006] In various embodiments, a display device is provided. The display device can be manufactured by disposing a bottom metal layer on an electrostatic discharge portion to increase the capacitance of a capacitor included in the electrostatic discharge portion, thereby better preventing static electricity from being generated from outside the display device. Dead zones in the display device can be reduced by reducing or minimizing the area of ​​the electrostatic discharge portion.

[0007] In an embodiment, a display device may include a substrate, at least one pixel, a first driver, a scan line, a first fan-out line, and a first electrostatic discharge portion, wherein the substrate includes a display area and a non-display area, at least one pixel is provided in the display area, each of the at least one pixel includes at least one pixel transistor and a light-emitting element connected to the at least one pixel transistor, the first driver is provided in the non-display area and configured to provide a scan signal to the at least one pixel, the scan line is configured to transmit the scan signal to the at least one pixel, the first fan-out line is provided in the non-display area and connected to the scan line, and the first electrostatic discharge portion is provided in the non-display area and located in an area between the first fan-out line and the scan line. Here, the first electrostatic discharge portion may include a bottom metal layer provided on the substrate and a transistor provided on the bottom metal layer and electrically connected to the bottom metal layer.

[0008] In an embodiment, the transistor of the first electrostatic discharge portion may include an active pattern, a gate electrode, a source electrode, and a drain electrode, wherein the active pattern is arranged on a buffer layer on a substrate, the gate electrode is arranged on the active pattern, and the source electrode and the drain electrode are respectively connected to sides of a central region overlapping with the gate electrode in the active pattern.

[0009] In an embodiment, the bottom metal layer may include a first bottom metal layer and a second bottom metal layer located between the substrate and the buffer layer. The first bottom metal layer and the second bottom metal layer may be spaced apart from each other.

[0010] In an embodiment, the first static electricity discharging portion may include a first lower electrode disposed on the first bottom metal layer, a first upper electrode disposed on the first lower electrode, a second lower electrode disposed on the second bottom metal layer, and a second upper electrode disposed on the second lower electrode.

[0011] In an embodiment, the first lower electrode and the first upper electrode may form a first capacitor, at least one interlayer insulating layer is arranged between the first lower electrode and the first upper electrode, and the second lower electrode and the second upper electrode may form a second capacitor, at least one interlayer insulating layer is arranged between the second lower electrode and the second upper electrode.

[0012] In an embodiment, the first bottom metal layer and the first lower electrode may form a first additional capacitor, at least one insulating layer is located below the at least one interlayer insulating layer and is arranged between the first bottom metal layer and the first lower electrode, and the second bottom metal layer and the second lower electrode may form a second additional capacitor, at least one insulating layer is arranged between the second bottom metal layer and the second lower electrode.

[0013] In an embodiment, the first lower electrode and the second lower electrode may be integrated with the gate electrode.

[0014] In an embodiment, the gate electrode, the first lower electrode, and the second lower electrode may be located in the same layer as the scan line.

[0015] In an embodiment, in a plan view, the first upper electrode may overlap the first bottom metal layer, and the second upper electrode may overlap the second bottom metal layer.

[0016] In an embodiment, each of the first upper electrode and the second upper electrode may overlap a portion of the gate electrode in a plan view.

[0017] In an embodiment, each of the first bottom metal layer and the second bottom metal layer may overlap a portion of the gate electrode in a plan view.

[0018] In an embodiment, the display device may further include a power supply line located in the non-display area and configured to provide driving power to at least one pixel. The first static electricity discharge portion may be electrically connected to the first fan-out line and the power supply line.

[0019] In an embodiment, the first fan-out line may be integrated with the first upper electrode and may be electrically connected to the first bottom metal layer, and the power supply line may be integrated with the second upper electrode and may be electrically connected to the second bottom metal layer.

[0020] In an embodiment, the first electrostatic discharge portion may include a first connection wiring electrically connecting the first bottom metal layer and the first fan-out line.

[0021] In an embodiment, the first connection wiring may be located in the same layer as the first lower electrode and the second lower electrode.

[0022] In an embodiment, the display device may include a second driver, a data line, a second fan-out line, and a second electrostatic release portion, wherein the second driver is located in a non-display area and is configured to provide a data signal to at least one pixel, the data line is configured to transmit the data signal to at least one pixel, the second fan-out line is located in the non-display area and is connected to the data line, and the second electrostatic release portion is provided in the non-display area and is located in an area between the second fan-out line and the data line.

[0023] In an embodiment, the first upper electrode and the second upper electrode may be located in the same layer as the data line.

[0024] In an embodiment, the second electrostatic discharge unit may include the same structure as the first electrostatic discharge unit.

[0025] In an embodiment, the first static electricity discharging portion may include a lower electrode disposed on the bottom metal layer and an upper electrode disposed on the lower electrode.

[0026] In an embodiment, the lower electrode and the upper electrode may form a capacitor, with at least one interlayer insulating layer disposed therebetween.

[0027] In an embodiment, the bottom metal layer and the lower electrode may form an additional capacitor, and at least one insulating layer is located below the at least one interlayer insulating layer and is arranged between the bottom metal layer and the lower electrode.

[0028] In an embodiment, the gate electrode may be integrated with the first fan-out line, and the lower electrode may be positioned to be spaced apart from the gate electrode.

[0029] In an embodiment, the first static electricity discharging portion may include a first connection wiring electrically connecting one of the source electrode and the drain electrode with the lower electrode and a second connection wiring electrically connecting the other of the source electrode and the drain electrode with the lower electrode.

[0030] In an embodiment, at least one pixel transistor may include a pixel active pattern disposed on the buffer layer, a pixel gate electrode disposed on the pixel active pattern, and a first terminal and a second terminal respectively connected to sides of a central region overlapping the pixel gate electrode in the pixel active pattern.

[0031] In an embodiment, at least one pixel may include a lower electrode integral with a pixel gate electrode and an upper electrode disposed on the lower electrode. The lower electrode and the upper electrode may form a storage capacitor, with at least one interlayer insulating layer disposed therebetween.

[0032] In an embodiment, at least one pixel may include a conductive pattern overlapping the pixel gate electrode, and the conductive pattern may be located in the same layer as the bottom metal layer.

[0033] In an embodiment, at least one pixel may include a second connection wiring disposed on and electrically connected to the upper electrode and a bridge pattern disposed on and electrically connected to the second connection wiring.

[0034] In an embodiment, the light emitting element may include an anode disposed on and electrically connected to the bridge pattern, a light emitting layer disposed on the anode, and a cathode disposed on the light emitting layer.

[0035] In another embodiment, a display device may include a substrate, at least one pixel, a first driver, a second driver, a scan line, a data line, a first fan-out line, a second fan-out line, a first electrostatic discharge unit, and a second electrostatic discharge unit, wherein the substrate includes a display area and a non-display area, at least one pixel is provided in the display area, and each of the at least one pixel includes at least one pixel transistor and a light-emitting element connected to the at least one pixel transistor. The first driver is provided in the non-display area and configured to provide a scan signal to the at least one pixel. The second driver is provided in the non-display area and configured to provide a data signal to the at least one pixel. The scan line is configured to transmit the scan signal to the at least one pixel. The data line is configured to transmit the data signal to the at least one pixel. The first fan-out line is provided in the non-display area and connected to the scan line. The second fan-out line is provided in the non-display area and connected to the data line. The first electrostatic discharge unit is provided in the non-display area and located in a region between the first fan-out line and the scan line. The second electrostatic discharge unit is provided in the non-display area and located in a region between the second fan-out line and the data line. Each of the first and second electrostatic discharge units may include a bottom metal layer provided on the substrate and a transistor provided on the bottom metal layer and electrically connected to the bottom metal layer.

[0036] In various embodiments, the non-display area of ​​the display device can be reduced by reducing or minimizing the area of ​​the electrostatic discharge circuit. The display device can block static electricity from flowing into the display area.

[0037] Effects and advantages of various examples of the present disclosure are not limited to the contents of the above examples, and more various effects and advantages will be apparent to those of ordinary skill in the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and other features of the present invention will become more apparent by further describing examples of the present invention in detail with reference to the accompanying drawings, in which:

[0039] Figure 1 is a plan view schematically showing a display device having pixels according to an embodiment;

[0040] Figure 2 It shows Figure 1 An equivalent circuit diagram of one pixel among the plurality of pixels shown in ;

[0041] Figure 3 It is shown in detail Figure 1 A plan view of one pixel among the plurality of pixels shown in ;

[0042] Figure 4 It is along Figure 3 A cross-sectional view taken along line II';

[0043] Figure 5A It shows Figure 1 An equivalent circuit diagram of the first electrostatic discharge unit and the second electrostatic discharge unit shown in FIG;

[0044] Figure 5B It shows Figure 5A An equivalent circuit diagram of a first electrostatic discharge unit;

[0045] Figure 6 It shows Figure 5A A plan view of the first electrostatic discharge portion and the second electrostatic discharge portion shown in FIG.

[0046] Figure 7 It is along Figure 6 A cross-sectional view taken along line II-II';

[0047] Figure 8 According to another embodiment Figure 6 A plan view of a first electrostatic discharge portion and a second electrostatic discharge portion;

[0048] Figure 9 It is along Figure 8 A cross-sectional view taken along line III-III';

[0049] Figure 10 According to another embodiment Figure 8 A plan view of a first electrostatic discharge portion and a second electrostatic discharge portion;

[0050] Figure 11 It is along Figure 10 A cross-sectional view taken along line IV-IV';

[0051] Figure 12 According to another embodiment Figure 6 A plan view of a first electrostatic discharge portion and a second electrostatic discharge portion;

[0052] Figure 13 It is along Figure 12 A cross-sectional view taken along line V-V';

[0053] Figure 14 It is shown in detail Figure 5B A plan view of the first electrostatic discharge portion shown in FIG;

[0054] Figure 15 It is along Figure 14 A cross-sectional view taken along line VI-VI' of ; and

[0055] Figure 16 According to another embodiment Figure 14 A plan view of the first electrostatic release portion. DETAILED DESCRIPTION

[0056] Specific examples are shown in the drawings and described in detail in the specification. However, the disclosed systems and devices may be modified in various ways and take various forms that differ from the detailed drawings but are consistent with the present disclosure. Therefore, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed. Furthermore, it should be understood that the present disclosure is intended to cover all modifications, equivalents, and alternative forms within the spirit and technical scope of the present disclosure.

[0057] When describing each accompanying drawing, similar reference numerals are used for similar elements. In the accompanying drawings, for the sake of clarity of this disclosure, the size of the structure is shown as amplified from the actual size. The words first, second, etc. can be used to describe various elements, but the elements should not be limited by the words. These words are only used to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be referred to as the second element, and similarly, the second element may also be referred to as the first element. Unless otherwise clearly indicated in the context, singular expressions include plural expressions.

[0058] It should be understood that the words "include," "have," or the like in the description are used to indicate the presence of a feature, number, step, operation, element, part, or combination thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, parts, or combinations thereof. In addition, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, this includes not only the case where the portion is "directly" "on" the other portion, but also the case where another portion exists between the portion and the other portion. In addition, in the description, when a portion of a layer, film, region, plate, or the like is formed on another portion, the formation direction is not limited to the upward direction, but includes forming the portion on the side surface or in the downward direction. Conversely, when a portion of a layer, film, region, plate, or the like is formed "below" another portion, this includes not only the case where the portion is "below" the other portion, but also the case where another portion exists between the portion and the other portion.

[0059] Furthermore, in the description, the phrase “in a plan view” means when an object portion is viewed from above, and the phrase “in a cross-sectional view” means when a cross-sectional view obtained by vertically cutting the object portion is viewed from the side.

[0060] When a layer, film, district, substrate or region is referred to as being "on" another layer, film, district, substrate or region, it may be directly located on another film, district, substrate or region, or there may be an intermediate film, district, substrate or region between them. On the contrary, when a layer, film, district, substrate or region is referred to as being "directly" on another layer, film, district, substrate or region, there may not be an intermediate layer, film, district, substrate or region between them. In addition, when a layer, film, district, substrate or region is referred to as being "under" another layer, film, district, substrate or region, it may be directly located under another layer, film, district, substrate or region, or there may be an intermediate layer, film, district, substrate or region between them. On the contrary, when a layer, film, district, substrate or region is referred to as being "directly" on another layer, film, district, substrate or region, there may not be an intermediate layer, film, district, substrate or region between them. In addition, "above" or "on" may include being positioned on or under an object, and does not necessarily imply a direction based on gravity.

[0061] In addition, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component, as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device shown in the figures is turned over, a device located "below" or "beneath" another device can be placed "above" the other device. Accordingly, the illustrative term "below" can include both lower and upper positions. The device can also be oriented in other directions, and thus, the spatially relative terms can be interpreted differently depending on the orientation.

[0062] Throughout the description, when an element is referred to as being “connected” to another element, the element can be “directly connected” to the other element or “electrically connected” to the other element with one or more intervening elements interposed therebetween.

[0063] Additionally, to take into account the errors associated with the measurements and the measurement of a particular quantity (i.e., the limitations of the measurement system), the terms "about" or "approximately" as used herein include the stated values ​​and means that are within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 80%, or 5% of the stated value.

[0064] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that, unless expressly defined in the description, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and will not be interpreted in an idealized or overly formal sense.

[0065] Hereinafter, various examples of the present disclosure and other examples necessary for those skilled in the art to understand the present disclosure will be described with reference to the accompanying drawings.

[0066] Figure 1 is a plan view schematically showing a display device according to an embodiment.

[0067] The display device may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB, a driver disposed on the substrate SUB to drive the plurality of pixels PXL, and a wiring portion connecting the plurality of pixels PXL and the driver to each other.

[0068] The substrate SUB may include a display area DA and a non-display area NDA.

[0069] The display area DA may be arranged in the central area of ​​the display device, and the non-display area NDA may be arranged in the edge area of ​​the display device to surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed.

[0070] The display area DA may be an area where a plurality of pixels PXL for displaying one or more images are provided, and the non-display area NDA may be an area where a driver for driving the plurality of pixels PXL and a portion of a wiring portion for connecting the plurality of pixels PXL and the driver are provided.

[0071] The display area DA may have various shapes. For example, the display area DA may be configured in various shapes, such as a closed polygon including sides formed by straight lines, a circle and an ellipse including sides formed by curved lines, and a semicircle and a semiellipse including sides formed by straight lines and curved lines.

[0072] The non-display area NDA may be disposed on at least one side of the display area DA. The non-display area NDA may surround a periphery of the display area DA.

[0073] The substrate SUB may be formed of a transparent insulating material and may transmit light.

[0074] The substrate SUB may be a rigid substrate. For example, the substrate SUB may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0075] The substrate SUB may be a flexible substrate. Here, the substrate SUB may be one of a film substrate and a plastic substrate including a polymer organic substance. For example, the substrate SUB may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the material constituting the substrate SUB may be variously changed and may include fiber reinforced plastic (FRP) or any other known or later developed material suitable for the purpose of the present disclosure.

[0076] An area on the substrate SUB may be provided as a display area DA where a plurality of pixels PXL are arranged. The remaining area may be provided as a non-display area NDA. The display area DA may include a plurality of pixel areas where a plurality of pixels PXL are arranged. The non-display area NDA may be provided in the periphery of the display area DA.

[0077] Each of the plurality of pixels PXL may be disposed in a display area DA on a substrate SUB. In an embodiment, the plurality of pixels PXL may be arranged in a matrix along pixel rows extending in a first direction DR1 and pixel columns extending in a second direction DR2. However, the arrangement of the plurality of pixels PXL is not limited thereto. For example, the plurality of pixels PXL may be arranged in the display area DA in various configurations.

[0078] Each of the plurality of pixels PXL may include a light emitting element for emitting white light and / or colored light (refer to Figure 2 ) and a pixel circuit for driving a light emitting element (refer to Figure 2 ). The pixel circuit may include at least one pixel transistor connected to the light emitting element.

[0079] As a non-limiting example, each pixel PXL may emit any one of red, green, and blue light. For example, a pixel PXL may emit one of cyan, magenta, yellow, and white light, or a set of multiple pixels PXL may emit cyan, magenta, yellow, and white light together.

[0080] The driver may include a scan driver SDV, a data driver DDV, and a timing controller (not shown).

[0081] The scan driver SDV may generate a plurality of scan signals and sequentially output the plurality of scan signals to the plurality of scan lines SL. The scan driver SDV may include at least one transistor formed by the same process as that used to form the pixel circuits of the plurality of pixels PXL. Such a process may include, for example, a low-temperature polysilicon (LTPS) process or a low-temperature polysilicon oxide (LTPO) process. The scan driver SDV may be provided as a separate chip in a chip-on-glass type in the non-display area NDA of the substrate SUB, or may be mounted on a printed circuit board and connected to the substrate SUB via a connection member.

[0082] The scan driver SDV may also output another control signal and a clock signal, etc. to the pixel circuits of the plurality of pixels PXL. For example, the scan driver SDV may generate a plurality of control signals and sequentially output the plurality of control signals to the plurality of control lines CL.

[0083] The data driver DDV may be disposed in the non-display area NDA and may output a plurality of data signals to a plurality of data lines DL. The plurality of data signals supplied to the plurality of data lines DL may be supplied to a plurality of pixels PXL selected by a scan signal.

[0084] The scan driver SDV and the data driver DDV may be disposed in the non-display area NDA of the substrate SUB. The positions of the scan driver SDV and / or the data driver DDV may not be limited thereto but may be changed as required in various locations.

[0085] The driver may further include drivers other than the above-described scan driver SDV and data driver DDV.

[0086] The wiring portion may include a plurality of scan lines SL, a plurality of data lines DL, a plurality of control lines CL, a plurality of control signal lines CSL, a power line PL, and a fan-out line FOL.

[0087] Each of the plurality of scan lines SL may be connected to a corresponding pixel PXL among the plurality of pixels PXL. Each of the plurality of data lines DL may be connected to a corresponding pixel PXL among the plurality of pixels PXL. Each of the plurality of control lines CL may be arranged in parallel with a corresponding scan line SL among the plurality of scan lines SL. The plurality of control signal lines CSL may transmit a plurality of scan control signals to the scan driver SDV.

[0088] The power lines PL may include a plurality of first power lines PL1 and a second power line PL2. Each of the plurality of first power lines PL1 may be connected to a corresponding pixel PXL among the plurality of pixels PXL. The second power line PL2 may be disposed in the non-display area NDA and may be connected to the first electrostatic discharge portion ESDP1. A common level of driving power may be applied to each of the plurality of first power lines PL1 and the second power lines PL2.

[0089] The fan-out lines FOL may be disposed in the non-display area NDA, and may include a plurality of first fan-out lines FOL1 and a plurality of second fan-out lines FOL2.

[0090] The plurality of first fan-out lines FOL1 may be connected between the scan driver SDV and the plurality of scan lines SL, and may transmit a plurality of scan signals generated in the scan driver SDV to the plurality of scan lines SL. The plurality of second fan-out lines FOL2 may be connected between the data driver DDV and the plurality of data lines DL, and may transmit a plurality of data signals generated in the data driver DDV to the plurality of data lines DL.

[0091] In many recent models of display devices that display high-quality images, the gaps between the circuits and wiring arranged in the display devices can become narrow, which may increase the likelihood of static electricity. When static electricity is generated, the pixel circuits may malfunction or problems may arise in the pixel circuit configuration. To address this issue, a circuit for preventing static electricity may be provided on or each of the scan lines SL and / or the data lines DL.

[0092] In an embodiment, the display device may include an electrostatic discharge part ESDP for preventing static electricity.

[0093] The electrostatic discharge portion ESDP may be disposed in the non-display area NDA and may include one or more first electrostatic discharge portions ESDP1 and one or more second electrostatic discharge portions ESDP2 .

[0094] Each of the plurality of first electrostatic discharge portions ESDP1 may be located in a region between each of the plurality of first fan-out lines FOL1 and a corresponding scan line SL. Each of the plurality of first electrostatic discharge portions ESDP1 may be electrically connected to the second power line PL2. Each of the plurality of first electrostatic discharge portions ESDP1 may electrically connect the second power line PL2 to one of the scan lines SL to prevent static electricity generated in the one scan line SL.

[0095] Each of the plurality of second electrostatic discharging portions ESDP2 may be located in a region between each of the plurality of second fan-out lines FOL2 and a data line DL corresponding to each second fan-out line FOL2. Each of the plurality of second electrostatic discharging portions ESDP2 may be electrically connected to the first power line PL1. Each of the plurality of second electrostatic discharging portions ESDP2 may electrically connect the first power line PL1 to one of the data lines DL to prevent static electricity generated in the one data line DL.

[0096] Will refer to Figure 5A 、 Figure 5B and Figure 6 The configurations of the first electrostatic discharging portion ESDP1 and the second electrostatic discharging portion ESDP2 are further described.

[0097] Figure 2 It shows Figure 1 8 is an equivalent circuit diagram of one pixel PXL among a plurality of pixels PXL shown in FIG.

[0098] exist Figure 2 , as an example, a pixel PXL connected to the j-th data line DLj, the i-th scan line SLi, and the i-th control line CLi is shown. Figure 1 and Figure 2 The pixel PXL may include a light emitting element OLED, a jth data line DLj, an ith scan line SLi, a first power line PL1, and an ith control line CLi. The pixel PXL may include a pixel circuit connected to the jth data line DLj, the ith scan line SLi, the ith control line CLi, and the first power line PL1.

[0099] The anode of the light-emitting element OLED can be connected to the pixel circuit, and the cathode of the light-emitting element OLED can be connected to the second driving power source ELVSS. The light-emitting element OLED can generate light with a predetermined brightness corresponding to the amount of current supplied from the pixel circuit. The first driving power source ELVDD applied to the first power line PL1 can be set to a voltage higher than the second driving power source ELVSS to allow current to flow to the light-emitting element OLED. During the light-emitting period of the pixel PXL, the potential difference between the first driving power source ELVDD and the second driving power source ELVSS can be set to be equal to or greater than the threshold voltage of the light-emitting element OLED.

[0100] The pixel circuit can control the amount of current flowing from the first driving power source ELVDD to the second driving power source ELVSS through the light-emitting element OLED in response to the data signal during the driving period. The pixel circuit can provide current information of the light-emitting element OLED to a compensator (not shown) during the sensing period. To this end, the pixel circuit may include first to third pixel transistors T1 to T3, a storage capacitor Cst, and an auxiliary capacitor Coled.

[0101] The first pixel transistor (or driving transistor) T1 may be connected between a first driving power source ELVDD and a second driving power source ELVSS together with the light-emitting element OLED, and may supply a current for driving the light-emitting element OLED to the light-emitting element OLED. One electrode of the first pixel transistor T1 (e.g., the source electrode of the first pixel transistor T1) may be connected to the anode of the light-emitting element OLED, and the other electrode (e.g., the drain electrode) may be connected to a first power line PL1 to which the first driving power source ELVDD is applied. The gate electrode of the first pixel transistor T1 may be connected to a first node N1. The first pixel transistor T1 may control the amount of current flowing from the first driving power source ELVDD through the light-emitting element OLED to the second driving power source ELVSS in response to the voltage of the first node N1.

[0102] A second pixel transistor (or switching transistor) T2 may be connected between the jth data line DLj and the first node N1. A gate electrode of the second pixel transistor T2 may be connected to the i-th scan line SLi connected to the pixel PXL. When a scan signal having a gate-on voltage (e.g., a high voltage) is supplied to the i-th scan line SLi, the second pixel transistor T2 may be turned on to electrically connect the j-th data line DLj and the first node N1 to each other. Therefore, when the second pixel transistor T2 is turned on, the data signal supplied to the j-th data line DLj may be transmitted to the first node N1.

[0103] The third pixel transistor T3 may be connected between an initialization power line IPL to which an initialization power source Vint is applied and a second node N2. When a control signal is supplied to the i-th control line CLi during the initialization period, the third pixel transistor T3 may be turned on to electrically connect the initialization power line IPL and the second node N2 to each other. The control signal may have a voltage (e.g., a high voltage) capable of turning on the third pixel transistor T3. Therefore, when the third pixel transistor T3 is turned on, the initialization power source Vint applied to the initialization power line IPL may be transmitted to the second node N2. The initialization power source Vint may have a voltage, for example, lower than the lowest voltage of the data signal.

[0104] When a control signal is supplied to the i-th control line CLi during a sensing period, the third pixel transistor T3 may be turned on. When the third pixel transistor T3 is turned on during the sensing period, a reference voltage from a compensator (not shown) may be supplied to the anode of the light-emitting element OLED. A predetermined current corresponding to the reference voltage may flow through the light-emitting element OLED, and the predetermined current may be supplied to the compensator as degradation information.

[0105] The first to third pixel transistors T1 to T3 included in the pixel circuit are all implemented as N-type thin film transistors, but the embodiment is not limited thereto. In other examples, the first to third pixel transistors T1 to T3 included in the pixel circuit may be implemented as P-type thin film transistors.

[0106] The storage capacitor Cst may be connected between the first node N1 and the second node N2 and may store the data signal supplied to the first node N1 and a voltage corresponding to the threshold voltage of the first pixel transistor T1 .

[0107] Considering the capacitance of a parasitic capacitor generated by the anode and cathode of the light emitting element OLED, the auxiliary capacitor Coled may be connected to utilize a coupling effect with the storage capacitor Cst.

[0108] Figure 3 It is shown in detail Figure 1 A plan view of one pixel PXL among the plurality of pixels PXL shown in FIG. 1 , and Figure 4 It is along Figure 3 A cross-sectional view taken along line II'.

[0109] like Figure 3 As shown in FIG, the pixel PXL may be arranged in the i-th row and the j-th column in the display area DA. The scan line SLi of the i-th row, the control line CLi of the i-th row, the data line DLj of the j-th column, the first power line PL1 of the j-th column, and the initialization power line IPL of the i-th row may be arranged relative to the pixel PXL.

[0110] exist Figure 3 and Figure 4 In the figure, for the convenience of description, the scan line of the i-th row is called the "scan line SLi", the control line of the i-th row is called the "control line CLi", the data line of the j-th column is called the "data line DLj", the first power line of the j-th column is called the "first power line PL1", and the initialization power line IPL of the i-th row is called the "initialization power line IPL".

[0111] Figure 3 and Figure 4 The structure of one pixel PXL is shown by simplifying the structure of one pixel PXL, such as showing each electrode as a single electrode layer and each insulating layer as a single insulating layer. However, Figure 3 and Figure 4 represents one non-limiting example, and the present disclosure is not limited thereto.

[0112] Reference Figures 1 to 4 As described above, the display device may include a substrate SUB, pixels PXL disposed on the substrate SUB, and a wiring portion connected to the pixels PXL. The wiring portion may provide signals to the pixels PXL and includes a scan line SLi, a control line CLi, a data line DLj, a first power line PL1, and an initialization power line IPL.

[0113] The scan line SLi may extend in a first direction DR1 on the substrate SUB and may be connected to the pixel PXL. The scan line SLi may be disposed and / or formed on the gate insulating layer GI. The gate insulating layer GI may be an inorganic insulating film including an inorganic material. The i-th scan signal generated by the scan driver SDV may be provided to the scan line SLi via the corresponding first fan-out line FOL1.

[0114] In a plan view, the control line CLi may extend in a first direction DR1 and may be spaced apart from the scan line SLi. A control signal may be applied to the control line CLi. The control line CLi may be arranged in the same layer as the scan line SLi and may include the same material as the scan line SLi. In the description, "arranged and / or formed in the same layer" may mean formed using the same process.

[0115] In a plan view, the initialization power line IPL may extend in a first direction DR1 and may be spaced apart from the control line CLi. An initialization power source Vint may be applied to the initialization power line IPL. The initialization power line IPL may be arranged in the same layer as the scan line SLi and the control line CLi and may include the same material as the scan line SLi and the control line CLi. The initialization power line IPL may be disposed and / or formed on the gate insulating layer GI. However, the present disclosure is not limited thereto. The initialization power line IPL may be disposed on the first interlayer insulating layer ILD1 between the data line DLj and the scan line SLi. Here, the first interlayer insulating layer ILD1 may be an inorganic insulating film including an inorganic material or an organic insulating film including an organic material.

[0116] The data lines DLj may extend in the second direction DR2. Data signals generated in the data driver DDV may be provided to the data lines DLj via corresponding second fan-out lines FOL2. The data lines DLj may be disposed and / or formed on the second interlayer insulating layer ILD2. The second interlayer insulating layer ILD2 may be an inorganic insulating film including an inorganic material or an organic insulating film including an organic material.

[0117] The first power line PL1 may extend in the second direction DR2 and may be spaced apart from the data line DLj. A first driving power source ELVDD may be applied to the first power line PL1. The first power line PL1 may be arranged in the same layer as the data line DLj and may include the same material as the data line DLj. The first power line PL1 may be disposed and / or formed on the second interlayer insulating layer ILD2.

[0118] The pixel PXL may include first to third pixel transistors T1 to T3 , a storage capacitor Cst, a light emitting element OLED, first to fifth connection wirings CNL1 to CNL5 , and a bridge pattern BRP.

[0119] The first pixel transistor T1 may include a first gate electrode GE1 , a first active pattern ACT1 , a first source electrode SE1 , and a first drain electrode DE1 .

[0120] The first gate electrode GE1 may be connected to the second source electrode SE2 of the second pixel transistor T2. The second connection wiring CNL2 connects the second source electrode SE2 and the first gate electrode GE1 to each other. In a plan view, the first gate electrode GE1 may extend along the second direction DR2 and may be integrally provided with the lower electrode LE of the storage capacitor Cst described later. When the lower electrode LE is integrally provided with the first gate electrode GE1, the lower electrode LE may be a region of the first gate electrode GE1.

[0121] One end of the second connection wiring CNL2 can be connected to the second source electrode SE2 through a third contact hole CH3 passing through the first interlayer insulating layer ILD1 and the gate insulating layer GI, and the other end of the second connection wiring CNL2 can be connected to the first gate electrode GE1 through a fourth contact hole CH4 passing through the first interlayer insulating layer ILD1.

[0122] In an embodiment, the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be formed of a semiconductor layer not doped with impurities or doped with impurities. The first source electrode SE1 and the first drain electrode DE1 may be formed of a semiconductor layer doped with impurities, and the first active pattern ACT1 may be formed of a semiconductor layer not doped with impurities.

[0123] In a plan view, the first active pattern ACT1 may overlap the first gate electrode GE1.

[0124] One end of the first source electrode SE1 may be connected to the first active pattern ACT1 , and the other end of the first source electrode SE1 may be electrically connected to the upper electrode UE of the storage capacitor Cst through an eighth contact hole CH8 sequentially passing through the gate insulating layer GI and the first interlayer insulating layer ILD1 .

[0125] One end of the first drain electrode DE1 may be connected to the first active pattern ACT1 , and the other end of the first drain electrode DE1 may be connected to the first power line PL1 through a sixth contact hole CH6 sequentially passing through the gate insulating layer GI, the first interlayer insulating layer ILD1 , and the second interlayer insulating layer ILD2 .

[0126] As shown in the figure, the first pixel transistor T1 may be provided as a plurality of transistors to prevent leakage current, but is not limited thereto. The first pixel transistor T1 may be provided as one transistor.

[0127] The second pixel transistor T2 may include a second gate electrode GE2 , a second active pattern ACT2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0128] The second gate electrode GE2 may be electrically connected to the scan line SLi. A first connection wiring CNL1 may connect the second gate electrode GE2 and the scan line SLi. The second gate electrode GE2 may be provided separately from the scan line SLi and independently of the scan line SLi, but the present disclosure is not limited thereto. The second gate electrode GE2 may be provided as part of the scan line SLi or may be provided in a shape protruding in one direction from the scan line SLi.

[0129] One end of the first connection wiring CNL1 can be connected to the scan line SLi through a first contact hole CH1 that sequentially passes through the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, and the other end of the first connection wiring CNL1 can be connected to the second gate electrode GE2 through a second contact hole CH2 that sequentially passes through the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2.

[0130] In an embodiment, the second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be formed of a semiconductor layer that is not doped with impurities or is doped with impurities. The second source electrode SE2 and the second drain electrode DE2 may be formed of a semiconductor layer doped with impurities, and the second active pattern ACT2 may be formed of a semiconductor layer that is not doped with impurities. In a plan view, the second active pattern ACT2 may overlap with the second gate electrode GE2.

[0131] One end of the second source electrode SE2 may be connected to the second active pattern ACT2, and the other end of the second source electrode SE2 may be electrically connected to the second connection wiring CNL2 through the third contact hole CH3. As described above, since the second connection wiring CNL2 may be electrically connected to the first gate electrode GE1 through the fourth contact hole CH4, the second source electrode SE2 may ultimately be connected to the first gate electrode GE1.

[0132] One end of the second drain electrode DE2 may be connected to the second active pattern ACT2 , and the other end of the second drain electrode DE2 may be connected to the data line DLj through a fifth contact hole CH5 sequentially passing through the gate insulating layer GI, the first interlayer insulating layer ILD1 , and the second interlayer insulating layer ILD2 .

[0133] The third pixel transistor T3 may include a third gate electrode GE3 , a third active pattern ACT3 , a third source electrode SE3 , and a third drain electrode DE3 .

[0134] The third gate electrode GE3 may be electrically connected to the control line CLi. A third connection wiring CNL3 may connect the third gate electrode GE3 and the control line CLi to each other. The third gate electrode GE3 may be provided separately from the control line CLi and independently of the control line CLi, but the present disclosure is not limited thereto. The third gate electrode GE3 may be provided as part of the control line CLi or may be provided in a shape protruding from the control line CLi.

[0135] One end of the third connection wiring CNL3 may be electrically connected to the third gate electrode GE3 through a ninth contact hole CH9 sequentially passing through the first and second interlayer insulating layers ILD1 and ILD2. The other end of the third connection wiring CNL3 may be electrically connected to the control line CLi through a tenth contact hole CH10 sequentially passing through the first and second interlayer insulating layers ILD1 and ILD2.

[0136] In an embodiment, the third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 may be formed of a semiconductor layer that is not doped with impurities or is doped with impurities. The third source electrode SE3 and the third drain electrode DE3 may be formed of a semiconductor layer doped with impurities, and the third active pattern ACT3 may be formed of a semiconductor layer that is not doped with impurities.

[0137] In a plan view, the third active pattern ACT3 may overlap the third gate electrode GE3.

[0138] One end of the third source electrode SE3 may be connected to the third active pattern ACT3 , and the other end of the third source electrode SE3 may be electrically connected to the first source electrode SE1 , and may be electrically connected to the upper electrode UE through the eighth contact hole CH8 .

[0139] One end of the third drain electrode DE3 may be connected to the third active pattern ACT3 , and the other end of the third drain electrode DE3 may be electrically connected to the fourth connection wiring CNL4 through an eleventh contact hole CH11 sequentially passing through the gate insulating layer GI, the first interlayer insulating layer ILD1 , and the second interlayer insulating layer ILD2 .

[0140] One end of the fourth connection wiring CNL4 may be connected to the third drain electrode DE3 through the eleventh contact hole CH11, and the other end of the fourth connection wiring CNL4 may be connected to the initialization power line IPL through the twelfth contact hole CH12 sequentially passing through the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. As described above, since the fourth connection wiring CNL4 can be electrically connected to the initialization power line IPL through the twelfth contact hole CH12, the third drain electrode DE3 may ultimately be electrically connected to the initialization power line IPL.

[0141] The third pixel transistor T3 may be provided as a plurality of transistors to prevent leakage current, but the embodiment is not limited thereto. In other various examples, the third pixel transistor T3 may be provided as one transistor similar to the second pixel transistor T2.

[0142] The storage capacitor Cst may include a lower electrode LE and an upper electrode UE. The lower electrode LE may be integrally provided with the first gate electrode GE1 of the first pixel transistor T1. When the lower electrode LE may be integrally provided with the first gate electrode GE1, the lower electrode LE may be a region of the first gate electrode GE1.

[0143] In a plan view, the upper electrode UE may overlap with the lower electrode LE and may cover the lower electrode LE. The capacitance of the storage capacitor Cst may be increased by increasing the overlapping area of ​​the upper electrode UE and the lower electrode LE.

[0144] The upper electrode UE may be electrically connected to the third source electrode SE3 of the third pixel transistor T3 and the first source electrode SE1 of the first pixel transistor T1 through the eighth contact hole CH8 and to the fifth connection wiring CNL5 through the thirteenth contact hole CH13 passing through the second interlayer insulating layer ILD2.

[0145] One end of the fifth connection wiring CNL5 may be electrically connected to the upper electrode UE through the thirteenth contact hole CH13 , and the other end of the fifth connection wiring CNL5 may be electrically connected to the bridge pattern BRP through the fourteenth contact hole CH14 passing through the third interlayer insulating layer ILD3 .

[0146] One end of the bridge pattern BRP may be electrically connected to the fifth connection wiring CNL5 through the fourteenth contact hole CH14 , and the other end of the bridge pattern BRP may be electrically connected to the anode AD of the light emitting element OLED through the fifteenth contact hole CH15 passing through the protective layer PSV.

[0147] The bridge pattern BRP may be an intermediate medium for electrically connecting the fifth connection wiring CNL5 and the anode AD. However, in various examples, the bridge pattern BRP may be omitted depending on the material and process conditions of the fifth connection wiring CNL5. For example, when the fifth connection wiring CNL5 is formed of copper and a portion of the fifth connection wiring CNL5 is exposed to the outside, the bridge pattern BRP may be electrically connected to the anode AD while covering the fifth connection wiring CNL5 to prevent corrosion. The bridge pattern BRP may be formed of a corrosion-resistant conductive material.

[0148] The anode AD may be formed and / or disposed on the protective layer PSV. The anode AD may be electrically connected to the bridge pattern BRP through the fifteenth contact hole CH15. As described above, since the bridge pattern BRP is electrically connected to the fifth connection wiring CNL5, the fifth connection wiring CNL5 is electrically connected to the upper electrode UE, and the upper electrode UE is connected to each of the first source electrode SE1 of the first pixel transistor T1 and the third source electrode SE3 of the third pixel transistor T3, the anode AD may ultimately be connected to the first source electrode SE1 of the first pixel transistor T1 and the third source electrode SE3 of the third pixel transistor T3.

[0149] A pixel-defining layer (PDL) may be provided on the portion of the substrate SUB where the anode AD is disposed, for partitioning (or defining) the light-emitting area of ​​the pixel PXL. The pixel-defining layer (PDL) may include an opening that exposes a portion of the upper surface of the anode AD and may protrude from the substrate SUB along the periphery of the pixel PXL. The pixel-defining layer (PDL) may be an organic insulating film including an organic material.

[0150] An emitting layer EML may be provided and / or formed on the upper surface of the anode AD exposed through the opening of the pixel defining layer PDL. A cathode CD may be provided and / or formed on the emitting layer EML. The emitting layer EML may be arranged on the exposed anode AD. The emitting layer EML may have a multilayer thin film structure including at least a photogenerating layer. For example, the emitting layer EML may have a multilayer thin film structure including a hole injection layer, a hole transport layer, a photogenerating layer, a hole blocking layer, an electron transport layer, and an electron injection layer, wherein the hole injection layer injects holes, the hole transport layer increases the chance of hole recombination by suppressing the movement of unbound electrons in the photogenerating layer, the photogenerating layer emits light through the recombination of injected electrons and holes, the hole blocking layer suppresses the movement of unbound holes in the emitting layer, the electron transport layer smoothly transports electrons to the photogenerating layer, and the electron injection layer injects electrons. The hole injection layer, hole transport layer, hole blocking layer, electron transport layer, and electron injection layer may be common films connected to each other in adjacent pixels.

[0151] The color of light generated in the light generating layer may be one of red, green, blue, and white, but is not limited thereto. For example, the color of light generated in a given light generating layer of the light emitting layer EML may be one of magenta, cyan, and yellow.

[0152] A thin film encapsulation film TFE covering the cathode CD may be disposed and / or formed on the cathode CD.

[0153] The thin film encapsulation film (TFE) may be formed of a single layer, but may also be formed of multiple layers. The thin film encapsulation film (TFE) may include an insulating film that covers the light-emitting element (OLED). Specifically, the thin film encapsulation film (TFE) may include at least one inorganic film and at least one organic film. For example, the thin film encapsulation film (TFE) may have a structure in which at least one inorganic film and at least one organic film are alternately stacked. The thin film encapsulation film (TFE) may be an encapsulation substrate that is arranged on the light-emitting element (OLED) and bonded to the substrate (SUB) via a sealant.

[0154] The display device may include a touch sensor (not shown) disposed on the thin film encapsulation film (TFE). The touch sensor may be arranged on a surface of the display device that displays an image and may receive a user's touch input. The touch sensor may recognize a touch event on the display device by the user's hand or a separate input device.

[0155] The pixel PXL may include a conductive pattern CP disposed and / or formed on a substrate SUB.

[0156] The conductive pattern CP may be formed of a conductive material (e.g., metal). The conductive pattern CP may be formed of a single metal, but may also be formed of two or more metals or an alloy of two or more metals. The conductive pattern CP may be formed as a single layer or multiple layers. The conductive pattern CP may block light from entering the rear surface of the substrate SUB. In a plan view, the conductive pattern CP may partially overlap with the first pixel transistor T1.

[0157] The conductive pattern CP can be electrically connected to the upper electrode UE through the seventh contact hole CH7 that sequentially passes through the buffer layer BFL, the gate insulating layer GI, and the first interlayer insulating layer ILD1. As described above, since the upper electrode UE can be electrically connected to the first source electrode SE1 of the first pixel transistor T1, the conductive pattern CP can be electrically connected to the first source electrode SE1 through the upper electrode UE. Therefore, a voltage of the same level as the voltage applied to the first source electrode SE1 can be transmitted to the conductive pattern CP.

[0158] The conductive pattern CP may be an element arranged on the substrate SUB with first priority. In an embodiment, the conductive pattern CP may be disposed between the first pixel transistor T1 and the substrate SUB and may partially overlap the first pixel transistor T1. The conductive pattern CP may overlap the first active pattern ACT1 of the first pixel transistor T1. When light enters from the back side of the substrate SUB, the conductive pattern CP may cover the first active pattern ACT1 to block the light from propagating to the first active pattern ACT1.

[0159] When the conductive pattern CP is electrically connected to the first source electrode SE1, a swing margin of the second driving power source ELVSS can be ensured. In this example and other examples, a driving range of a gate voltage applied to the first gate electrode GE1 of the first pixel transistor T1 can be advantageously expanded.

[0160] Figure 5A It shows Figure 1 The equivalent circuit diagram of the first electrostatic discharge portion ESDP1 and the second electrostatic discharge portion ESDP2 shown in FIG. Figure 5B According to another example Figure 5A FIG. 4 is an equivalent circuit diagram of the first electrostatic dissipation unit ESDP1.

[0161] Reference Figure 1 、 Figure 2 、 Figure 5A and Figure 5B , the display device may include a first electrostatic discharge portion ESDP1 and a second electrostatic discharge portion ESDP2 arranged in the non-display area NDA.

[0162] Each of the first and second electrostatic discharge portions ESDP1 and ESDP2 may be connected to a corresponding power line and a corresponding fan-out line, and may include at least one transistor ET interconnected with the corresponding power line and the corresponding fan-out line. Each of the first and second electrostatic discharge portions ESDP1 and ESDP2 may be designed to have low impedance within a predetermined high voltage range to discharge excess current, be designed to self-destruct to block static electricity inflow, and have high impedance in a normal driving environment to avoid affecting signals provided via the corresponding fan-out line.

[0163] Each of the first and second electrostatic discharge units ESDP1 and ESDP2 may include a transistor ET, a first capacitor C1, and a second capacitor C2. The transistor ET of the first electrostatic discharge unit ESDP1 may be connected to a first fan-out line FOL1 supplied with a scan signal of a scan driver SDV and a second power line PL2 supplied with a second driving power source ELVSS. The transistor ET of the second electrostatic discharge unit ESDP2 may be connected to a second fan-out line FOL2 supplied with a data signal of a data driver DDV and a first power line PL1 supplied with a first driving power source ELVDD.

[0164] For the purpose of description, the transistor ET included in the first electrostatic discharge portion ESDP1 is referred to as a “first transistor ET”, and the transistor ET included in the second electrostatic discharge portion ESDP2 is referred to as a “second transistor ET”.

[0165] In the first electrostatic discharging portion ESDP1 , the first capacitor C1 may be connected between the gate electrode of the first transistor ET and the first terminal of the first transistor ET, and the second capacitor C2 may be connected between the gate electrode of the first transistor ET and the second terminal of the first transistor ET.

[0166] In the second electrostatic discharging portion ESDP2 , the first capacitor C1 may be connected between the gate electrode of the second transistor ET and the first terminal of the second transistor ET, and the second capacitor C2 may be connected between the gate electrode of the second transistor ET and the second terminal of the second transistor ET.

[0167] According to the form (or application form) of the scan driver SDV provided to the display device, such as Figure 5B As shown in FIG, the first electrostatic discharge portion ESDP1 may be configured to include a transistor ET and a capacitor C. Figure 5BAs shown in , when the scan driver SDV is configured to include at least one transistor formed by the same process as the pixel circuit of the pixel PXL, the first electrostatic discharge portion ESDP1 may be configured to include one transistor ET and one capacitor C. In this example and other examples, the gate electrode of the transistor ET of the first electrostatic discharge portion ESDP1 may be connected to the clock signal line CL provided to the scan driver SDV, the first terminal and the second terminal of the transistor ET may be electrically connected to one side of the capacitor C, and the other side of the capacitor C may be connected to the second power line PL2.

[0168] like Figure 5A As shown in , when the scan driver SDV is provided as a chip-on-glass type in the non-display area NDA of the substrate SUB, the first electrostatic discharge part ESDP1 may be provided in a form including one transistor ET and two capacitors C1 and C2.

[0169] Figure 6 It shows Figure 5A , and Figure 7 It is along Figure 6 A cross-sectional view taken along line II-II'.

[0170] In various examples of the present disclosure, “disposed and / or formed in the same layer” may mean formed in the same process.

[0171] Reference Figures 1 to 5A 、 Figure 6 and Figure 7 The display device may include a first electrostatic releasing portion ESDP1 and a second electrostatic releasing portion ESDP2, wherein the first electrostatic releasing portion ESDP1 is connected between the first fan-out line FOL1 and the second power line PL2 in the non-display area NDA of the substrate SUB, and the second electrostatic releasing portion ESDP2 is connected between the second fan-out line FOL2 and the first power line PL1.

[0172] Each of the first fan-out line FOL1 and the second fan-out line FOL2 may extend along a second direction DR2 on the substrate SUB. A scan signal generated in the scan driver SDV may be applied to the first fan-out line FOL1, and a data signal generated in the data driver DDV may be applied to the second fan-out line FOL2. The first fan-out line FOL1 may be a sensing line that applies a control signal to the i-th control line CLi to sense degradation information of the light-emitting element OLED by turning on the third pixel transistor T3 of each pixel PXL during a sensing period.

[0173] Each of the first power line PL1 and the second power line PL2 may extend along the second direction DR2 on the substrate SUB in a plan view and may be arranged to be spaced apart from the corresponding fan-out line. For example, the first power line PL1 may be spaced apart from the second fan-out line FOL2 in a plan view, and the second power line PL2 may be spaced apart from the first fan-out line FOL1 in a plan view.

[0174] Each of the first and second electrostatic discharge portions ESDP1 and ESDP2 may include first and second bottom metal layers BML1 and BML2, a transistor ET, and first and second capacitors C1 and C2. The first and second electrostatic discharge portions ESDP1 and ESDP2 may have substantially the same or similar structures. In the following description, for convenience, the first electrostatic discharge portion ESDP1 will be representatively described.

[0175] The first electrostatic discharging part ESDP1 may include a transistor ET, first and second capacitors C1 and C2 , and first and second bottom metal layers BML1 and BML2 .

[0176] The transistor ET may include a gate electrode GE, an active pattern ACT, a source electrode SE, and a drain electrode DE.

[0177] The gate electrode GE may be disposed in the same layer as the scan line SL connected to each of the plurality of pixels PXL of the display area DA, and may include the same material as the scan line SL.

[0178] The active pattern ACT, the source electrode SE, and the drain electrode DE may be formed of a semiconductor layer that is not doped (or injected) with impurities or that is doped (or injected) with impurities. For example, the source electrode SE and the drain electrode DE may be formed of a semiconductor layer doped (or injected) with impurities, and the active pattern ACT may be formed of a semiconductor layer that is not doped (or injected) with impurities.

[0179] The active pattern ACT may extend in a predetermined direction and may have a shape that bends multiple times along the longitudinal direction of the extension. The active pattern ACT may overlap with the gate electrode GE in a plan view. Since the active pattern ACT is formed into a long structure, the channel region of the transistor ET may be formed into a long shape.

[0180] One end of the source electrode SE may be connected to one end of the active pattern ACT, and the other end of the source electrode SE may be connected to the first upper electrode UE1 of the first capacitor C1 through a twenty-first contact hole CH21 sequentially passing through the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2.

[0181] One end of the drain electrode DE may be connected to the other end of the active pattern ACT. The other end of the drain electrode DE may be electrically connected to the second upper electrode UE2 of the second capacitor C2 through a twenty-second contact hole CH22 sequentially passing through the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2.

[0182] The first capacitor C1 may include a first lower electrode LE1 and a first upper electrode UE1.

[0183] The first lower electrode LE1 may be integral with the gate electrode GE of the transistor ET. When the first lower electrode LE1 is integrally provided with the gate electrode GE, the first lower electrode LE1 may be a region of the gate electrode GE. The first lower electrode LE1 may not be integrally provided with the gate electrode GE of the transistor ET, but in other examples may be provided in a layer different from the gate electrode GE of the transistor ET.

[0184] The first upper electrode UE1 may be provided in a form extending along the second direction DR2 and may overlap the first lower electrode LE1. In a plan view, the first upper electrode UE1 may cover the first lower electrode LE1. The capacitance of the first capacitor C1 may be increased by increasing the overlapping area of ​​the first upper electrode UE1 and the first lower electrode LE1. The first upper electrode UE1 may be electrically connected to the first bottom metal layer BML1 through a twenty-sixth contact hole CH26 that sequentially passes through the buffer layer BFL, the gate insulating layer GI, and the first and second interlayer insulating layers ILD1 and ILD2. In a plan view, the first upper electrode UE1 may completely cover the source electrode SE and may not cover the active pattern ACT. The first upper electrode UE1 may not cover the gate electrode GE that overlaps with the active pattern ACT.

[0185] Similar to the first capacitor C1 , the second capacitor C2 may include a second lower electrode LE2 and a second upper electrode UE2 .

[0186] The second lower electrode LE2 of the second capacitor C2 may be integral with the gate electrode GE of the transistor ET. When the second lower electrode LE2 is integrally provided with the gate electrode GE, the second lower electrode LE2 may be a region of the gate electrode GE. In an example of the present disclosure, each of the first lower electrode LE1 and the second lower electrode LE2 may be a region of the gate electrode GE. According to one example, the second lower electrode LE2 may not be integrally provided with the gate electrode GE of the transistor ET, but in other examples, it may be provided in a layer different from the gate electrode GE of the transistor ET.

[0187] The second upper electrode UE2 may be provided in a form extending along the second direction DR2 and may overlap the second lower electrode LE2. In a plan view, the second upper electrode UE2 may cover the second lower electrode LE2. The capacitance of the second capacitor C2 may be increased by increasing the overlapping area between the second upper electrode UE2 and the second lower electrode LE2. The second upper electrode UE2 may be electrically connected to the second bottom metal layer BML2 via a twenty-fifth contact hole CH25 sequentially passing through the buffer layer BFL, the gate insulating layer GI, and the first and second interlayer insulating layers ILD1 and ILD2. In a plan view, the second upper electrode UE2 may completely cover the drain electrode DE and may not cover the active pattern ACT. The second upper electrode UE2 may not cover the gate electrode GE that overlaps with the active pattern ACT.

[0188] The second upper electrode UE2 may be integral with the second power line PL2. When the second upper electrode UE2 is integrally provided with the second power line PL2, the second upper electrode UE2 may be a region of the second power line PL2. The second upper electrode UE2 may not be integrally provided with the second power line PL2, but may be provided in a different layer from the second power line PL2. For example, the second upper electrode UE2 may be provided in the same layer as the bridge pattern BRP of each pixel PXL, or may be provided in the same layer as the anode AD of each pixel PXL.

[0189] The first bottom metal layer BML1 may be disposed on the substrate SUB and may overlap the first lower electrode LE1 and the first upper electrode UE1. The first bottom metal layer BML1 may be electrically connected to the first upper electrode UE1 through the twenty-sixth contact hole CH26. The first bottom metal layer BML1 may be electrically connected to the first fan-out line FOL1 through the connection wiring CNL.

[0190] The connection wiring CNL is provided in a form extending along the first direction DR1 and may be a medium for electrically connecting the first bottom metal layer BML1 and the first fan-out line FOL1 to each other. In a plan view, one end of the connection wiring CNL may overlap with the first bottom metal layer BML1, and the other end of the connection wiring CNL may overlap with the first fan-out line FOL1.

[0191] One end of the connection wiring CNL may be electrically connected to the first bottom metal layer BML1 via a twenty-fourth contact hole CH24 sequentially passing through the buffer layer BFL and the gate insulating layer GI. The other end of the connection wiring CNL may be electrically connected to the first fan-out line FOL1 via a twenty-third contact hole CH23 sequentially passing through the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. The connection wiring CNL may be disposed in the same layer as the gate electrode GE and may include the same material as the gate electrode GE. The connection wiring CNL may be disposed on the gate insulating layer GI, but the present disclosure is not limited thereto. The connection wiring CNL may be disposed and / or formed on the first interlayer insulating layer ILD1 between the first fan-out line FOL1 and the first bottom metal layer BML1.

[0192] The first bottom metal layer BML1 may be formed of a conductive material (e.g., a metal). The first bottom metal layer BML1 may be formed of a single metal, but in other examples, may be formed of two or more metals or an alloy of two or more metals. The first bottom metal layer BML1 may be formed as a single layer or multiple layers. The first bottom metal layer BML1 may be disposed and / or formed in the same layer as the conductive pattern CP of each of the plurality of pixels PXL of the display area DA, and may include the same material as the conductive pattern CP.

[0193] The second bottom metal layer BML2 may be disposed on the substrate SUB and spaced apart from the first bottom metal layer BML1. The second bottom metal layer BML2 may be disposed and / or formed in the same layer as the first bottom metal layer BML1 and may include the same material as the first bottom metal layer BML1. The second bottom metal layer BML2 may overlap with the second lower electrode LE2 and the second upper electrode UE2. The second bottom metal layer BML2 may be electrically connected to the second upper electrode UE2 through the twenty-fifth contact hole CH25. As described above, since the second upper electrode UE2 is a region of the second power line PL2, the second bottom metal layer BML2 may be electrically connected to the second power line PL2.

[0194] Now refer to Figure 6 and Figure 7 , the structure of the first electrostatic discharging portion ESDP1 will be described in a stacking order.

[0195] The first and second bottom metal layers BML1 and BML2 of the first static electricity discharging part ESDP1 may be disposed and / or formed in the non-display area NDA of the substrate SUB.

[0196] Furthermore, a buffer layer (BFL) may be provided and / or formed on the first bottom metal layer (BML1) and the second bottom metal layer (BML2). The buffer layer (BFL) may be an inorganic insulating film including an inorganic material. The buffer layer (BFL) may prevent impurities from diffusing into the transistor (ET). The buffer layer (BFL) may be provided as a single layer, but in other embodiments, it may be provided as a multilayer layer of at least two layers. When the buffer layer (BFL) is provided as a multilayer layer, each layer may be formed of the same material or different materials. Depending on the material of the substrate (SUB) and process conditions, the buffer layer (BFL) may be omitted.

[0197] The active pattern ACT may be formed and / or disposed on the buffer layer BFL.

[0198] The source electrode SE and the drain electrode DE contacting both ends of the active pattern ACT may be formed by forming the gate electrode GE on the substrate SUB and then implanting (or doping) impurities.

[0199] A gate insulating layer GI may be formed and / or disposed on the active pattern ACT. The gate insulating layer GI may be an inorganic insulating film including an inorganic material.

[0200] The gate electrode GE and the connection wiring CNL may be disposed on the gate insulating layer GI. The gate electrode GE may include a first lower electrode LE1 of the first capacitor C1 and a second lower electrode LE2 of the second capacitor C2.

[0201] The connection wiring CNL may be electrically connected to the first bottom metal layer BML1 through a twenty-fourth contact hole CH24 sequentially passing through the buffer layer BFL and the gate insulating layer GI.

[0202] First and second interlayer insulating layers ILD1 and ILD2 may be sequentially formed and / or disposed on the gate insulating layer GI including the gate electrode GE and the like. Each of the first and second interlayer insulating layers ILD1 and ILD2 may be an inorganic insulating film including an inorganic material, but the present disclosure is not limited thereto.

[0203] The second power line PL2, the first fan-out line FOL1, the first upper electrode UE1, and the second upper electrode UE2 may be disposed and / or formed on the second interlayer insulating layer ILD2. The second power line PL2 may be integrally disposed with the second upper electrode UE2.

[0204] The first fan-out line FOL1 may be electrically connected to the connection wiring CNL through a twenty-third contact hole CH23 sequentially passing through the first and second interlayer insulating layers ILD1 and ILD2 .

[0205] The first upper electrode UE1 may be connected to the first bottom metal layer BML1 through a twenty-sixth contact hole CH26 sequentially passing through the buffer layer BFL, the gate insulating layer GI, and the first and second interlayer insulating layers ILD1 and ILD2 .

[0206] The first upper electrode UE1 overlaps the first lower electrode LE1 with the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 interposed therebetween to form a first capacitor C1 .

[0207] The first lower electrode LE1 may overlap the first bottom metal layer BML1 with the buffer layer BFL and the gate insulating layer GI interposed therebetween to form an additional capacitor. The additional capacitor may increase the capacitance of the first capacitor C1.

[0208] The second upper electrode UE2 may be electrically connected to the second bottom metal layer BML2 through a twenty-fifth contact hole CH25 sequentially passing through the buffer layer BFL, the gate insulating layer GI, and the first and second interlayer insulating layers ILD1 and ILD2 .

[0209] The second upper electrode UE2 may overlap the second lower electrode LE2 with the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 interposed therebetween to form a second capacitor C2. The second lower electrode LE2 may overlap the second bottom metal layer BML2 with the buffer layer BFL and the gate insulating layer GI interposed therebetween to form an additional capacitor. The additional capacitor may further increase the capacitance of the second capacitor C2.

[0210] A protection layer PSV, a pixel defining layer PDL, and a thin film encapsulation film TFE may be sequentially disposed and / or formed on the first upper electrode UE1 and the second upper electrode UE2 .

[0211] As described above, in an example of the present disclosure, the first bottom metal layer BML1 may be disposed between the substrate SUB and the buffer layer BFL to increase the capacitance of the first capacitor C1 without increasing the overlap area between the first upper electrode UE1 and the first lower electrode LE1. The second bottom metal layer BML2 may be disposed between the substrate SUB and the buffer layer BFL to increase the capacitance of the second capacitor C2 without increasing the overlap area between the second upper electrode UE2 and the second lower electrode LE2.

[0212] As the capacitance of each of the first capacitor C1 and the second capacitor C2 increases, the first static electricity discharging portion ESDP1 may more stably block static electricity generated from the outside.

[0213] When the areas of the first upper electrode UE1 and the first lower electrode LE1 are designed to increase the overlapping area between the first upper electrode UE1 and the first lower electrode LE1 to enhance the anti-static effect of the first electrostatic discharge portion ESDP1, the increased areas of the first upper electrode UE1 and the first lower electrode LE1 can increase the area occupied by the first electrostatic discharge portion ESDP1 in the non-display area NDA. Similarly, the areas of the second upper electrode UE2 and the second lower electrode LE2 are designed to increase the overlapping area between the second upper electrode UE2 and the second lower electrode LE2. As the areas of the second upper electrode UE2 and the second lower electrode LE2 increase, the area occupied by the first electrostatic discharge portion ESDP1 in the non-display area NDA can similarly increase. As a result, the dead zone of the non-display area NDA can be increased.

[0214] Therefore, in the embodiment of the present disclosure, the capacitance of the first capacitor C1 and the second capacitor C2 can be increased by disposing the first bottom metal layer BML1 and the second bottom metal layer BML2 between the substrate SUB and the buffer layer BFL without increasing the area of ​​the first upper electrode UE1 and the second upper electrode UE2. Accordingly, by reducing the area occupied by the first electrostatic discharge portion ESDP1 in the non-display area NDA, the dead zone of the non-display area NDA can be reduced or minimized.

[0215] As described above, the first lower electrode LE1 and the second lower electrode LE2 may be integrated with the gate electrode GE, but the structure is not limited thereto. In other examples, the first lower electrode LE1 and the second lower electrode LE2 may be disposed and / or formed in a configuration separate from the gate electrode GE. For example, the first lower electrode LE1 and the second lower electrode LE2 may be disposed and / or formed on the first interlayer insulating layer ILD1, and the first lower electrode LE1 and the second lower electrode LE2 may be electrically connected to the gate electrode GE via separate connection means.

[0216] When the first lower electrode LE1 is disposed and / or formed on the first interlayer insulating layer ILD1, the first upper electrode UE1 may form a first capacitor C1 with the first lower electrode LE1 via the second interlayer insulating layer ILD2 interposed therebetween. The first lower electrode LE1 may form an additional capacitor with the first bottom metal layer BML1 via the first interlayer insulating layer ILD1, the gate insulating layer GI, and the buffer layer BFL interposed therebetween.

[0217] When the second lower electrode LE2 is disposed and / or formed on the first interlayer insulating layer ILD1, the second upper electrode UE2 may form a second capacitor C2 with the second lower electrode LE2 via the second interlayer insulating layer ILD2 interposed therebetween. The second lower electrode LE2 may form an additional capacitor with the second bottom metal layer BML2 via the first interlayer insulating layer ILD1, the gate insulating layer GI, and the buffer layer BFL interposed therebetween.

[0218] The first and second bottom metal layers BML1 and BML2 may be disposed between the substrate SUB and the buffer layer BFL, but their arrangement is not limited thereto.

[0219] In other examples, the first bottom metal layer BML1 and the second bottom metal layer BML2 may be provided in the same layer as the active pattern ACT. The first bottom metal layer BML1 and the second bottom metal layer BML2 may be doped (or implanted) with impurities that can be used to provide conductivity. When the first bottom metal layer BML1 and the second bottom metal layer BML2 are provided in the same layer as the active pattern ACT, the first bottom metal layer BML1 may overlap with the first lower electrode LE1 with the gate insulating layer GI interposed therebetween to form an additional capacitor, and the second bottom metal layer BML2 may overlap with the second lower electrode LE2 with the gate insulating layer GI interposed therebetween to form an additional capacitor. The first lower electrode LE1 and the second lower electrode LE2 may be provided in the same layer as the upper electrode UE of the storage capacitor Cst of each pixel PXL. With the gate insulating layer GI and the first interlayer insulating layer ILD1 interposed therebetween, the first bottom metal layer BML1 may overlap with the first lower electrode LE1 to form an additional capacitor, and with the gate insulating layer GI and the first interlayer insulating layer ILD1 interposed therebetween, the second bottom metal layer BML2 may overlap with the second lower electrode LE2 to form an additional capacitor.

[0220] According to another example, the first bottom metal layer BML1 and the second bottom metal layer BML2 may be disposed in the same layer as the scan line SLi of each pixel PXL on the gate insulating layer GI. When the first bottom metal layer BML1 and the second bottom metal layer BML2 are disposed in the same layer as the scan line SLi of each pixel PXL, the first lower electrode LE1 and the second lower electrode LE2 may be disposed in the same layer as the first power line PL1 of each pixel PXL, and the first upper electrode UE1 and the second upper electrode UE2 may be disposed in the same layer as the bridge pattern BRP of each pixel PXL. With the third interlayer insulating layer ILD3 interposed therebetween, the first upper electrode UE1 may overlap with the first lower electrode LE1 to form a first capacitor C1, and the first lower electrode LE1 may form an additional capacitor with the first bottom metal layer BML1 via the first and second interlayer insulating layers ILD1 and ILD2 interposed therebetween. With the third interlayer insulating layer ILD3 interposed therebetween, the second upper electrode UE2 may overlap with the second lower electrode LE2 to form a second capacitor C2, and the second lower electrode LE2 may form an additional capacitor with the second bottom metal layer BML2 via the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 interposed therebetween. The first upper electrode UE1 and the second upper electrode UE2 are disposed on the third interlayer insulating layer ILD3, but their configuration is not limited thereto. In other examples, the first upper electrode UE1 and the second upper electrode UE2 may be disposed in the same layer as the anode AD of each pixel PXL.

[0221] As described above, the first capacitor C1 and the second capacitor C2 of each of the first and second electrostatic discharging portions ESDP1 and ESDP2 may have capacitance configured as a combination of three conductive layers arranged in different layers with at least one layer interposed therebetween, among the plurality of conductive layers included in each pixel PXL.

[0222] Figure 8 According to another embodiment Figure 6 A plan view of the first electrostatic discharging portion ESDP1 and the second electrostatic discharging portion ESDP2, and Figure 9 It is along Figure 8 A cross-sectional view taken along line III-III'.

[0223] Figure 8 and Figure 9 The first electrostatic discharging portion ESDP1 and the second electrostatic discharging portion ESDP2 shown in FIG. Figure 6 and Figure 7 The first and second electrostatic discharge portions ESDP1 and ESDP2 are substantially the same or similar configurations, except that each of the first and second bottom metal layers BML1 and BML2 overlaps the gate electrode GE of the corresponding transistor ET.

[0224] Therefore, in order to avoid repeated description, the following description will be mainly based on the aspects that are different from the above-mentioned embodiment. Figure 8 and Figure 9 The first electrostatic discharge portion ESDP1 and the second electrostatic discharge portion ESDP2 are provided. In the parts not specifically described in this embodiment, the same reference numerals denote the same elements according to the above embodiment, and similar reference numerals denote similar elements.

[0225] Figure 8 and Figure 9 The structures of the first and second electrostatic discharge parts ESDP1 and ESDP2 are shown by simplifying them, such as illustrating each electrode as a single electrode layer and each insulating layer as a single insulating layer. However, their structures are not limited thereto.

[0226] Reference Figure 1 、 Figure 5A 、 Figure 8 and Figure 9 , the first electrostatic discharging portion ESDP1 may be connected between the second power line PL2 and the first fan-out line FOL1 , and the second electrostatic discharging portion ESDP2 may be connected between the first power line PL1 and the second fan-out line FOL2 .

[0227] The first driving power supply of the same level (refer to Figure 2 The ELVDD) may be applied to the first power line PL1 and the second power line PL2. The scan signal generated in the scan driver SDV may be applied to the first fan-out line FOL1, and the data signal generated in the data driver DDV may be applied to the second fan-out line FOL2. The first fan-out line FOL1 may be a sensing line that applies a control signal to the i-th control line CLi to sense degradation information of the light emitting element OLED by turning on the third pixel transistor T3 of each pixel PXL during a sensing period.

[0228] Each of the first and second electrostatic discharging parts ESDP1 and ESDP2 may include first and second bottom metal layers BML1 and BML2 , a transistor ET, a connection wiring CNL, and first and second capacitors C1 and C2 .

[0229] The transistor ET of each of the first and second static electricity discharging parts ESDP1 and ESDP2 may include a gate electrode GE, an active pattern ACT, a source electrode SE, and a drain electrode DE.

[0230] The first capacitor C1 of each of the first and second electrostatic discharge parts ESDP1 and ESDP2 may include a first lower electrode LE1 and a first upper electrode UE1 , and the second capacitor C2 of each of the first and second electrostatic discharge parts ESDP1 and ESDP2 may include a second lower electrode LE2 and a second upper electrode UE2 .

[0231] The first bottom metal layer BML1 of each of the first and second electrostatic discharge portions ESDP1 and ESDP2 may overlap with the first lower electrode LE1 of the corresponding first capacitor C1. Therefore, the first bottom metal layer BML1 of each of the first and second electrostatic discharge portions ESDP1 and ESDP2 may form an additional capacitor with the first lower electrode LE1 of the corresponding first capacitor C1 via the buffer layer BFL and the gate insulating layer GI interposed therebetween. The additional capacitor may increase the capacitance of the first capacitor C1.

[0232] The first bottom metal layer BML1 of each of the first and second electrostatic discharge portions ESDP1 and ESDP2 may be configured to extend in the second direction DR2 and may overlap the gate electrode GE of the corresponding transistor ET. Therefore, the first bottom metal layer BML1 of each of the first and second electrostatic discharge portions ESDP1 and ESDP2 may form an additional capacitor with the gate electrode GE of the corresponding transistor ET via the buffer layer BFL and the gate insulating layer GI interposed therebetween. The additional capacitor may further increase the capacitance of the first capacitor C1 of each of the first and second electrostatic discharge portions ESDP1 and ESDP2.

[0233] The second bottom metal layer BML2 of each of the first and second electrostatic discharge parts ESDP1 and ESDP2 may overlap with the second lower electrode LE2 of the corresponding second capacitor C2. Therefore, the second bottom metal layer BML2 of each of the first and second electrostatic discharge parts ESDP1 and ESDP2 may form an additional capacitor with the second lower electrode LE2 of the second capacitor C2 via the buffer layer BFL and the gate insulating layer GI interposed therebetween. The additional capacitor may increase the capacitance of the second capacitor C2.

[0234] The second bottom metal layer BML2 of each of the first and second electrostatic discharge portions ESDP1 and ESDP2 may be configured to extend in the second direction DR2 and may overlap the gate electrode GE of the corresponding transistor ET. Therefore, the second bottom metal layer BML2 of each of the first and second electrostatic discharge portions ESDP1 and ESDP2 may form an additional capacitor with the gate electrode GE of the corresponding transistor ET via the buffer layer BFL and the gate insulating layer GI interposed therebetween. The additional capacitor may further increase the capacitance of the second capacitor C2.

[0235] As described above, as the capacitance of each of the first and second capacitors C1 and C2 increases, the first and second static electricity discharging portions ESDP1 and ESDP2 may more stably block static electricity generated from the outside.

[0236] Figure 10 According to another embodiment Figure 8 A plan view of the first electrostatic discharging portion ESDP1 and the second electrostatic discharging portion ESDP2, and Figure 11 It is along Figure 10 A cross-sectional view taken along line IV-IV'.

[0237] Figure 10 and Figure 11 The first electrostatic discharging portion ESDP1 and the second electrostatic discharging portion ESDP2 shown in FIG. Figure 8 and Figure 9 The first and second electrostatic discharge portions ESDP1 and ESDP2 are substantially the same or similar configurations, except that each of the first and second upper electrodes UE1 and UE2 overlaps with the gate electrode GE of the corresponding transistor ET.

[0238] In order to avoid repeated description, the following description will be mainly based on the aspects different from the above embodiment. Figure 10 and Figure 11 The first electrostatic discharge portion ESDP1 and the second electrostatic discharge portion ESDP2 are provided. In the parts not specifically described in this embodiment, the same reference numerals denote the same elements according to the above embodiment, and similar reference numerals denote similar elements.

[0239] Figure 10 and Figure 11 The structures of the first and second electrostatic discharge parts ESDP1 and ESDP2 are shown by simplifying them, such as illustrating each electrode as a single electrode layer and each insulating layer as a single insulating layer. However, their structures are not limited thereto.

[0240] Reference Figure 1 、 Figure 5A 、 Figure 9 and Figure 10 The first electrostatic discharge portion ESDP1 may be connected between the second power line PL2 and the first fan-out line FOL1, and the second electrostatic discharge portion ESDP2 may be connected between the first power line PL1 and the second fan-out line FOL2. The first fan-out line FOL1 may be a sensing line that applies a control signal to the i-th control line CLi to sense degradation information of the light-emitting element OLED by turning on the third pixel transistor T3 of each pixel PXL during a sensing period.

[0241] Each of the first and second electrostatic discharging parts ESDP1 and ESDP2 may include first and second bottom metal layers BML1 and BML2 , a transistor ET, a connection wiring CNL, and first and second capacitors C1 and C2 .

[0242] The transistor ET of each of the first and second static electricity discharging parts ESDP1 and ESDP2 may include a gate electrode GE, an active pattern ACT, a source electrode SE, and a drain electrode DE.

[0243] The first capacitor C1 of each of the first and second electrostatic discharge parts ESDP1 and ESDP2 may include a first lower electrode LE1 and a first upper electrode UE1 , and the second capacitor C2 of each of the first and second electrostatic discharge parts ESDP1 and ESDP2 may include a second lower electrode LE2 and a second upper electrode UE2 .

[0244] The first bottom metal layer BML1 of each of the first and second electrostatic discharge portions ESDP1 and ESDP2 may be configured to extend in the second direction DR2 and may overlap the gate electrode GE of the corresponding transistor ET. Therefore, the first bottom metal layer BML1 of each of the first and second electrostatic discharge portions ESDP1 and ESDP2 may form an additional capacitor with the gate electrode GE of the corresponding transistor ET via the buffer layer BFL and the gate insulating layer GI interposed therebetween. The additional capacitor may increase the capacitance of the first capacitor C1 of each of the first and second electrostatic discharge portions ESDP1 and ESDP2.

[0245] In a plan view, the first upper electrode UE1 of each of the first and second electrostatic discharging portions ESDP1 and ESDP2 may be arranged to extend in the second direction DR2 and may overlap the gate electrode GE of the corresponding transistor ET. Since the gate electrode GE is integrated with the first lower electrode LE1 of the first capacitor C1, the overlapping area between the first upper electrode UE1 and the first lower electrode LE1 of each of the first and second electrostatic discharging portions ESDP1 and ESDP2 may increase. This increase in the overlapping area between the first upper electrode UE1 and the first lower electrode LE1 may further increase the capacitance of the first capacitor C1 of each of the first and second electrostatic discharging portions ESDP1 and ESDP2.

[0246] The second bottom metal layer BML2 of each of the first and second electrostatic discharge parts ESDP1 and ESDP2 may be arranged to extend along the second direction DR2 and may overlap the gate electrode GE of the corresponding transistor ET. Therefore, the second bottom metal layer BML2 of each of the first and second electrostatic discharge parts ESDP1 and ESDP2 may form an additional capacitor with the gate electrode GE of the corresponding transistor ET via the buffer layer BFL and the gate insulating layer GI interposed therebetween. The additional capacitor may increase the capacitance of the second capacitor C2 of each of the first and second electrostatic discharge parts ESDP1 and ESDP2.

[0247] In a plan view, the second upper electrode UE2 of each of the first and second electrostatic discharging portions ESDP1 and ESDP2 may be arranged to extend in the second direction DR2 and may overlap with the gate electrode GE of the corresponding transistor ET. Since the gate electrode GE is integrated with the second lower electrode LE2 of the second capacitor C2, the overlapping area between the second upper electrode UE2 and the second lower electrode LE2 of each of the first and second electrostatic discharging portions ESDP1 and ESDP2 may increase. The increase in the overlapping area between the second upper electrode UE2 and the second lower electrode LE2 may further increase the capacitance of the second capacitor C2 of each of the first and second electrostatic discharging portions ESDP1 and ESDP2.

[0248] As described above, as the capacitances of the first and second capacitors C1 and C2 increase, the first and second static electricity discharging portions ESDP1 and ESDP2 may more stably block static electricity generated from the outside.

[0249] Figure 12 According to another embodiment Figure 6 A plan view of the first electrostatic discharging portion ESDP1 and the second electrostatic discharging portion ESDP2, and Figure 13 It is along Figure 12 A cross-sectional view taken along line V-V'.

[0250] Figure 12 and Figure 13 The first electrostatic discharging portion ESDP1 and the second electrostatic discharging portion ESDP2 shown in FIG. Figure 6 and Figure 7 The first and second electrostatic discharge portions ESDP1 and ESDP2 are substantially the same or similar configurations, except that each of the first and second upper electrodes UE1 and UE2 overlaps with the gate electrode GE of the corresponding transistor ET.

[0251] In order to avoid repeated description, the following description will be mainly based on the aspects different from the above embodiment. Figure 12 and Figure 13The first electrostatic discharge portion ESDP1 and the second electrostatic discharge portion ESDP2 are provided. In the parts not specifically described in this embodiment, the same reference numerals denote the same elements according to the above embodiment, and similar reference numerals denote similar elements. Figure 12 and Figure 13 The structures of the first and second electrostatic discharge parts ESDP1 and ESDP2 are shown by simplifying them, such as illustrating each electrode as a single electrode layer and each insulating layer as a single insulating layer. However, their structures are not limited thereto.

[0252] Reference Figure 1 、 Figure 5A 、 Figure 12 and Figure 13 The first electrostatic discharge portion ESDP1 may be connected between the second power line PL2 and the first fan-out line FOL1, and the second electrostatic discharge portion ESDP2 may be connected between the first power line PL1 and the second fan-out line FOL2. The first fan-out line FOL1 may be a sensing line that applies a control signal to the i-th control line CLi to sense degradation information of the light-emitting element OLED by turning on the third pixel transistor T3 of each pixel PXL during a sensing period.

[0253] Each of the first and second electrostatic discharging parts ESDP1 and ESDP2 may include first and second bottom metal layers BML1 and BML2 , a transistor ET, a connection wiring CNL, and first and second capacitors C1 and C2 .

[0254] The transistor ET of each of the first and second static electricity discharging parts ESDP1 and ESDP2 may include a gate electrode GE, an active pattern ACT, a source electrode SE, and a drain electrode DE.

[0255] The first capacitor C1 of each of the first and second electrostatic discharge parts ESDP1 and ESDP2 may include a first lower electrode LE1 and a first upper electrode UE1 , and the second capacitor C2 of each of the first and second electrostatic discharge parts ESDP1 and ESDP2 may include a second lower electrode LE2 and a second upper electrode UE2 .

[0256] The first and second upper electrodes UE1 and UE2 of each of the first and second static electricity discharging parts ESDP1 and ESDP2 may be provided in a bar shape extending along the second direction DR2 and may be arranged on the same plane to be spaced apart from each other at regular intervals.

[0257] The first upper electrode UE1 of each of the first and second electrostatic discharging portions ESDP1 and ESDP2 may overlap with the first lower electrode LE1 of the corresponding first capacitor C1 and the gate electrode GE of the corresponding transistor ET. Since the gate electrode GE and the first lower electrode LE1 are integrally provided with each other, the overlapping area between the first upper electrode UE1 and the first lower electrode LE1 of each of the first and second electrostatic discharging portions ESDP1 and ESDP2 may increase. The increase in the overlapping area between the first upper electrode UE1 and the first lower electrode LE1 may further increase the capacitance of the first capacitor C1 of each of the first and second electrostatic discharging portions ESDP1 and ESDP2.

[0258] The second upper electrode UE2 of each of the first and second electrostatic discharging portions ESDP1 and ESDP2 may overlap with the second lower electrode LE2 of the corresponding second capacitor C2 and the gate electrode GE of the corresponding transistor ET. Since the gate electrode GE and the second lower electrode LE2 are integrally provided, the overlapping area between the second upper electrode UE2 and the second lower electrode LE2 of each of the first and second electrostatic discharging portions ESDP1 and ESDP2 may increase. The increase in the overlapping area between the second upper electrode UE2 and the second lower electrode LE2 may further increase the capacitance of the second capacitor C2 of each of the first and second electrostatic discharging portions ESDP1 and ESDP2.

[0259] As described above, as the capacitances of the first and second capacitors C1 and C2 increase, the first and second static electricity discharging portions ESDP1 and ESDP2 may more stably block static electricity generated from the outside.

[0260] In various examples of the present disclosure as described above, the first bottom metal layer BML1 and the second bottom metal layer BML2 may be arranged in the first electrostatic discharge portion ESDP1 and the second electrostatic discharge portion ESDP2 to increase the capacitance of each of the first capacitor C1 and the second capacitor C2, and thus the reliability of the first electrostatic discharge portion ESDP1 and the second electrostatic discharge portion ESDP2 may be further improved.

[0261] The display device can increase the capacitance of the first capacitor C1 and the second capacitor C2 without increasing the area of ​​the first capacitor C1 and the second capacitor C2, and thus can reduce the area occupied by the first and second electrostatic discharge portions ESDP1 and ESDP2 in the non-display area NDA. Therefore, the display device can reduce or minimize the dead zone of the non-display area NDA.

[0262] Figure 14 It is shown in detail Figure 5B , and Figure 15 It is along Figure 14 In the description, “disposed and / or formed in the same layer” may mean formed in the same process.

[0263] Reference Figure 1 、 Figure 5B 、 Figure 14 and Figure 15 , the first electrostatic discharging portion ESDP1 may be connected between the clock signal line CL and the second power line PL2 .

[0264] Each of the clock signal line CL and the second power line PL2 may extend along a second direction DR2. A clock signal provided to the scan driver SDV may be applied to the clock signal line CL, and a first driving power source may be applied to the second power line PL2. The clock signal line CL and the second power line PL2 may be arranged to be spaced apart from each other in a plan view.

[0265] The first static electricity discharging part ESDP1 may include a bottom metal layer BML, a transistor ET, and a capacitor C. The transistor ET may include a gate electrode GE, an active pattern ACT, a source electrode SE, and a drain electrode DE.

[0266] The gate electrode GE may be provided in a form protruding from the clock signal line CL along the first direction DR1. In an example of the present disclosure, the gate electrode GE may be provided and / or formed integrally with the clock signal line CL. When the gate electrode GE is provided integrally with the clock signal line CL, the gate electrode GE may be a region of the clock signal line CL.

[0267] The active pattern ACT, the source electrode SE, and the drain electrode DE may be formed of a semiconductor layer that is not doped (or injected) with impurities or that is doped (or injected) with impurities. For example, the source electrode SE and the drain electrode DE may be formed of a semiconductor layer doped (or injected) with impurities, and the active pattern ACT may be formed of a semiconductor layer that is not doped (or injected) with impurities.

[0268] The active pattern ACT may extend along the second direction DR2 in a plan view and overlap the gate electrode GE.

[0269] One end of the source electrode SE may be connected to one end of the active pattern ACT, and the other end of the source electrode SE may be electrically connected to the first connection wiring CNL1 through a twenty-third contact hole CH23 sequentially passing through the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2.

[0270] One end of the drain electrode DE may be connected to the other end of the active pattern ACT and the other end of the drain electrode DE may be electrically connected to the second connection wiring CNL2 through a twenty-fourth contact hole CH24 sequentially passing through the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2.

[0271] One end of the first connection wiring CNL1 may be connected to the source electrode SE through a 23rd contact hole CH23 , and the other end may be electrically connected to the lower electrode LE through a 21st contact hole CH21 sequentially passing through the first and second interlayer insulating layers ILD1 and ILD2 .

[0272] One end of the second connection wiring CNL2 may be connected to the drain electrode DE through a 24th contact hole CH24 , and the other end may be electrically connected to the lower electrode LE through a 22nd contact hole CH22 sequentially passing through the first and second interlayer insulating layers ILD1 and ILD2 .

[0273] The first and second connection wirings CNL1 and CNL2 may be commonly connected to the lower electrodes LE.

[0274] The capacitor C may include a lower electrode LE and an upper electrode UE.

[0275] The lower electrode LE may have a stripe shape extending along the first direction DR1 and may be disposed and / or formed in the same layer as the gate electrode GE. The lower electrode LE and the gate electrode GE may be disposed and / or formed on the gate insulating layer GI. The lower electrode LE and the gate electrode GE may be arranged to be spaced apart from each other by a predetermined distance in a plan view.

[0276] The upper electrode UE may be provided in a form extending along the first direction DR1 and may be provided integrally with the second power line PL2. When the upper electrode UE is provided integrally with the second power line PL2, the upper electrode UE may be a region of the second power line PL2.

[0277] The upper electrode UE may overlap with and cover the lower electrode LE in a plan view. With the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 interposed therebetween, the upper electrode UE may overlap with the lower electrode LE to form a capacitor C. The capacitance of the capacitor C may be increased by widening the overlapping area of ​​the upper electrode UE and the lower electrode LE.

[0278] The upper electrode UE may be electrically connected to the bottom metal layer BML through a twenty-fifth contact hole CH25 sequentially passing through the buffer layer BFL, the gate insulating layer GI, and the first and second interlayer insulating layers ILD1 and ILD2 .

[0279] The bottom metal layer BML may have a bar shape extending along the first direction DR1 with a configuration arranged with a first priority on the substrate SUB. The bottom metal layer BML may overlap each of the lower electrode LE and the upper electrode UE in a plan view.

[0280] The bottom metal layer BML may be formed of a conductive material (e.g., metal). The bottom metal layer BML may be formed of a single metal, but may also be formed of two or more metals or an alloy of two or more metals. The bottom metal layer BML may be formed as a single layer or multiple layers. The bottom metal layer BML may be provided and / or formed in a conductive pattern (refer to FIG. 1 ) in contact with each of the plurality of pixels PXL of the display area DA. Figure 3 The CP) is in the same layer as the conductive pattern and may include the same material as the conductive pattern.

[0281] The lower electrode LE may overlap the bottom metal layer BML with the buffer layer BFL and the gate insulating layer GI interposed therebetween to form an additional capacitor. The additional capacitor may increase the capacitance of the capacitor C. As described above, as the capacitance of the capacitor C increases, the first static electricity discharging portion ESDP1 may more stably block static electricity generated from the outside.

[0282] Figure 16 According to another embodiment Figure 14 FIG. 1 is a plan view of a first electrostatic dissipation portion ESDP1.

[0283] Figure 16 The first electrostatic discharge portion ESDP1 shown in FIG. Figure 14 and Figure 15 The first electrostatic discharge portion ESDP1 has substantially the same or similar configuration, except Figure 16 The first electrostatic discharge portion ESDP1 shown in FIG includes a transistor with a dual-gate structure.

[0284] In order to avoid repeated description, the following description will be mainly based on the aspects different from the above embodiment. Figure 16 The first electrostatic discharge portion ESDP1 is shown. In parts not specifically described in this embodiment, the same reference numerals denote the same elements, and similar reference numerals denote similar elements according to the above-mentioned embodiment.

[0285] Reference Figure 1 、 Figure 5B and Figure 16 , the first electrostatic discharging portion ESDP1 may be connected between the clock signal line CL and the second power line PL2 .

[0286] Each of the clock signal line CL and the second power line PL2 may extend along the second direction DR2 .

[0287] The first electrostatic discharging part ESDP1 may include a bottom metal layer BML, a transistor ET, and a capacitor C.

[0288] The transistor ET may be configured as a dual-gate structure to prevent leakage current. For example, the transistor ET may include a first transistor ETa and a second transistor ETb. The first transistor ETa may include a first gate electrode GEa, a first active pattern ACTa, a first source electrode SEa, and a first drain electrode DEa. The second transistor ETb may include a second gate electrode GEb, a second active pattern ACTb, a second source electrode SEb, and a second drain electrode DEb.

[0289] Each of the first gate electrode GEa and the second gate electrode GEb may be provided in a form protruding from the clock signal line CL along the first direction DR1. Each of the first gate electrode GEa and the second gate electrode GEb may be provided and / or formed integrally with the clock signal line CL so as to be electrically and / or physically connected to the clock signal line CL. When each of the first gate electrode GEa and the second gate electrode GEb is integrally formed with the clock signal line CL, each of the first gate electrode GEa and the second gate electrode GEb may be a region of the clock signal line CL.

[0290] Each of the first and second active patterns ACTa and ACTb, the first and second source electrodes SEa and SEb, and the first and second drain electrodes DEa and DEb may be formed from a semiconductor layer doped (or implanted) with impurities or a semiconductor layer not doped with impurities. For example, each of the first and second source electrodes SEa and SEb and the first and second drain electrodes DEa and DEb may be formed from a semiconductor layer doped with impurities, and each of the first and second active patterns ACTa and ACTb may be formed from a semiconductor layer not doped with impurities. The first active pattern ACTa corresponds to a portion overlapping with the first gate electrode GEa, and the second active pattern ACTb corresponds to a portion overlapping with the second gate electrode GEb.

[0291] One end of the first source electrode SEa may be connected to the first active pattern ACTa, and the other end of the first source electrode SEa may be electrically connected to the first connection wiring CNL1 through the twenty-third contact hole CH23. One end of the first drain electrode DEa may be connected to the first active pattern ACTa, and the other end of the first drain electrode DEa may be electrically connected to the second source electrode SEb of the second transistor ETb.

[0292] One end of the second source electrode SEb may be connected to the second active pattern ACTb, and the other end of the second source electrode SEb may be electrically connected to the first drain electrode DEa of the first transistor ETa. One end of the second drain electrode DEb may be connected to the second active pattern ACTb, and the other end of the second drain electrode DEb may be electrically connected to the second connection wiring CNL2 through the twenty-fourth contact hole CH24.

[0293] One end of the first connection wiring CNL1 may be connected to the first source electrode SEa through the twenty-third contact hole CH23, and the other end of the first connection wiring CNL1 may be electrically connected to the lower electrode LE through the twenty-first contact hole CH21. One end of the second connection wiring CNL2 may be connected to the second drain electrode DEb through the twenty-fourth contact hole CH24, and the other end of the second connection wiring CNL2 may be electrically connected to the lower electrode LE through the twenty-second contact hole CH22. For example, the first connection wiring CNL1 and the second connection wiring CNL2 may be commonly connected to the lower electrode LE.

[0294] The capacitor C may include a lower electrode LE and an upper electrode UE.

[0295] The lower electrode LE may have a strip shape extending along the first direction DR1. The upper electrode UE may have a strip shape extending along the first direction DR1 and overlapping the lower electrode LE. The upper electrode UE may be integrally provided with the second power line PL2. The upper electrode UE may be electrically connected to the bottom metal layer BML through the twenty-fifth contact hole CH25.

[0296] The bottom metal layer BML may have a configuration of being arranged with first priority on the substrate SUB, but its configuration is not limited thereto. The bottom metal layer BML may have a stripe shape extending along the first direction DR1. The bottom metal layer BML may overlap each of the lower electrode LE and the upper electrode UE in a plan view.

[0297] In the buffer layer (refer to Figure 15 BFL) and gate insulation layer (refer to Figure 15 In the case where the lower electrode LE is interposed with the bottom metal layer BML, the lower electrode LE may overlap with the bottom metal layer BML to form an additional capacitor. The additional capacitor may increase the capacitance of the capacitor C. As described above, as the capacitance of the capacitor C increases, the first static electricity discharging portion ESDP1 may more stably block static electricity generated from the outside.

[0298] The above description is provided to illustrate and describe the present disclosure. The above description only illustrates and describes examples of the present disclosure and is applicable to various other combinations, modifications, and environments as described above, and may be changed or modified within the scope of the concepts of the present disclosure disclosed in the specification, the scope equivalent to the disclosure herein, and / or within the skill or knowledge of those skilled in the art. Accordingly, the above detailed description of the present disclosure is not intended to limit the present disclosure to the disclosed examples. The appended claims should be interpreted to include other examples.

Claims

1. A display device comprising: A substrate, the substrate comprising a display area and a non-display area; at least one pixel, the at least one pixel being disposed in the display area, each of the at least one pixel comprising at least one pixel transistor and a light emitting element connected to the at least one pixel transistor; a first driver disposed in the non-display area and configured to provide a scan signal to the at least one pixel; a scan line configured to transmit the scan signal to the at least one pixel; a first fan-out line, the first fan-out line being disposed in the non-display area and connected to the scan line; a power supply line configured to supply driving power to the at least one pixel, and the power supply line includes a second power supply line located in the non-display area; as well as a first electrostatic discharge portion, the first electrostatic discharge portion being provided in the non-display area and located in an area between the first fan-out line and the scan line; Wherein, the first electrostatic release unit includes: a bottom metal layer disposed on the substrate; and a transistor disposed on and electrically connected to the bottom metal layer, and The first electrostatic discharge unit is electrically connected to the first fan-out line and the second power line.

2. The display device according to claim 1, wherein The transistor of the first electrostatic discharge unit includes: an active pattern, wherein the active pattern is arranged on the buffer layer on the substrate; a gate electrode disposed on the active pattern; and A source electrode and a drain electrode are respectively connected to sides of a central region of the active pattern overlapping the gate electrode.

3. The display device according to claim 2, wherein: The bottom metal layer includes a first bottom metal layer and a second bottom metal layer located between the substrate and the buffer layer, and The first bottom metal layer and the second bottom metal layer are spaced apart from each other.

4. The display device according to claim 3, wherein The first electrostatic release unit includes: a first lower electrode, the first lower electrode being arranged on the first bottom metal layer; a first upper electrode, the first upper electrode being arranged on the first lower electrode; a second lower electrode disposed on the second bottom metal layer; and A second upper electrode is disposed on the second lower electrode.

5. The display device according to claim 4, wherein The first lower electrode and the first upper electrode form a first capacitor, at least one interlayer insulating layer is arranged between the first lower electrode and the first upper electrode, and The second lower electrode and the second upper electrode form a second capacitor, and the at least one interlayer insulating layer is disposed between the second lower electrode and the second upper electrode. The display device according to claim 5 , wherein: The first bottom metal layer and the first lower electrode form a first additional capacitor, at least one insulating layer is located below the at least one interlayer insulating layer, the at least one insulating layer is arranged between the first bottom metal layer and the first lower electrode, and The second bottom metal layer and the second lower electrode form a second additional capacitor, and the at least one insulating layer is arranged between the second bottom metal layer and the second lower electrode.

7. The display device according to claim 4, wherein The first lower electrode and the second lower electrode are integrated with the gate electrode.

8. The display device according to claim 7, wherein: The gate electrode, the first lower electrode, and the second lower electrode are located in the same layer as the scan line.

9. The display device according to claim 7, wherein: In a plan view, the first upper electrode overlaps the first bottom metal layer, and the second upper electrode overlaps the second bottom metal layer.

10. The display device according to claim 9, wherein In the plan view, each of the first upper electrode and the second upper electrode overlaps a portion of the gate electrode.

11. The display device according to claim 9, wherein In the plan view, each of the first bottom metal layer and the second bottom metal layer overlaps a portion of the gate electrode.

12. The display device according to claim 4, wherein The first fan-out line is integrated with the first upper electrode and electrically connected to the first bottom metal layer, and The power supply line is integrated with the second upper electrode and is electrically connected to the second bottom metal layer.

13. The display device according to claim 12, wherein: The first electrostatic discharge unit further includes a first connection wiring electrically connecting the first bottom metal layer and the first fan-out line.

14. The display device according to claim 13, wherein: The first connection wiring is located in the same layer as the first lower electrode and the second lower electrode.

15. The display device according to claim 4, further comprising: a second driver located in the non-display area and configured to provide a data signal to the at least one pixel; a data line configured to transmit the data signal to the at least one pixel; a second fan-out line located in the non-display area and connected to the data line; as well as A second electrostatic discharge portion is provided in the non-display area and is located in an area between the second fan-out line and the data line.

16. The display device according to claim 15, wherein The first upper electrode and the second upper electrode are located in the same layer as the data line.

17. The display device according to claim 16, wherein: The power line further includes a first power line, the second electrostatic discharge portion includes the same structure as the first electrostatic discharge portion, and the second electrostatic discharge portion is electrically connected to the second fan-out line and the first power line.

18. The display device according to claim 2, wherein: The first electrostatic release unit includes: a lower electrode disposed on the bottom metal layer; and An upper electrode is arranged on the lower electrode.

19. The display device according to claim 18, wherein The lower electrode and the upper electrode form a capacitor, and at least one interlayer insulating layer is disposed between the lower electrode and the upper electrode.

20. The display device according to claim 19, wherein The bottom metal layer and the lower electrode form an additional capacitor, and at least one insulating layer is located below the at least one interlayer insulating layer, the at least one insulating layer being arranged between the bottom metal layer and the lower electrode.

21. The display device according to claim 20, wherein The gate electrode is integrated with the first fan-out line, and The lower electrode is positioned to be spaced apart from the gate electrode.

22. The display device according to claim 21, wherein The first electrostatic discharge unit further includes: a first connection wiring electrically connecting one of the source electrode and the drain electrode to the lower electrode; and a second connecting wiring electrically connecting the other of the source electrode and the drain electrode to the lower electrode.

23. The display device according to claim 13, wherein: The at least one pixel transistor comprises: a pixel active pattern, the pixel active pattern being arranged on the buffer layer; a pixel gate electrode, the pixel gate electrode being arranged on the pixel active pattern; and A first terminal and a second terminal, the first terminal and the second terminal being respectively connected to sides of a central region overlapping the pixel gate electrode in the pixel active pattern.

24. The display device according to claim 23, wherein The at least one pixel further comprises: a lower electrode, the lower electrode being integrated with the pixel gate electrode; and an upper electrode, the upper electrode being arranged on the lower electrode, The lower electrode and the upper electrode form a storage capacitor, and at least one interlayer insulating layer is arranged between the lower electrode and the upper electrode.

25. The display device according to claim 24, wherein The at least one pixel further includes a conductive pattern overlapping the pixel gate electrode, and The conductive pattern is located in the same layer as the bottom metal layer.

26. The display device according to claim 25, wherein The at least one pixel further comprises: a second connection wiring arranged on the upper electrode and electrically connected to the upper electrode; and A bridge pattern is provided on the second connection wiring and is electrically connected to the second connection wiring.

27. The display device according to claim 26, wherein: The light emitting element comprises: an anode disposed on the bridge pattern and electrically connected to the bridge pattern; a light-emitting layer disposed on the anode; and A cathode is disposed on the light-emitting layer.

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