Transconductance enhancement cascode compensation for amplifiers

Abstract

Embodiments of the present disclosure relate to transconductance enhancement cascode compensation for an amplifier. A differential pair of transistors receives an input voltage. A current mirror transistor and a cascode transistor are coupled to the differential pair of transistors. The differential pair of transistors is coupled between the cascode transistor and a tail transistor that draws a first bias current from a tail node, the first bias current having a magnitude equal to a product of a total bias current and a constant less than one. A first current source transistor draws a second bias current from a node between the differential pair and the cascode transistor, such that the second bias current bypasses one of the differential pair of transistors. The second bias current has a magnitude equal to a product of the total bias current and a value equal to one minus the constant. An output stage is biased by an output at the node between the cascode transistor and the current mirror transistor.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 838,011, filed April 24, 2019, the contents of which are incorporated by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the field of operational amplifiers, and in particular, to operational amplifier designs with boosted cascode compensation. BACKGROUND

[0004] In the design of operational amplifiers, such as for use as error amplifiers, cascode (stacked) transistors are used to increase gain and provide enhanced high frequency power supply rejection ratio. However, this can cause the frequency response of the amplifier to peak, which can lead to instability at higher frequencies. Therefore, it is known to increase the transconductance of the cascode to obtain stability at higher frequencies.

[0005] In Figure 1A This design of amplifier 20 is shown in FIG. 1. Amplifier 20 is comprised of a differential input stage 21 and an output (or gain) stage 22. Differential input stage 21 includes a pair of differential input transistors Tdi1 and Tdi2, whose control terminals receive a reference voltage Vref and a feedback voltage Vfb indicative of an output current Iout produced by output stage 22, respectively. Cascode transistors Tc1 and Tc2 are stacked between the pair of differential input transistors Tdi1 and Tdi2 and load transistors Tm1 and Tm2. Note that transistors Tdi1 and Tdi2 are of the same size as each other, transistors Tc1 and Tc2 are of the same size as each other, and transistors Tm1 and Tm2 are of the same size as each other.

[0006] A tail current source transistor Tt, controlled by a bias voltage Vb, provides a bias current I for differential input stage 21; thus, note that when Vref is equal to Vfb, the current through Tdi1 and Tdi2 will be I / 2. Output stage 22 produces an output current Iout for the load in accordance with the drain voltage of load transistor Tm2.

[0007] In Figure 1BThe frequency response of the amplifier 20 with respect to gain is shown in Fig. 1. A gain peaking can be observed. With an increase of the output current Iout, the gain peaking will worsen, possibly leading to high frequency instability. To reduce the gain peaking, it is known to increase the transconductance of the cascode transistors Tc1 and Tc2 by increasing the bias current I. However, this has the effect of increasing the transconductance of the pair of differential input transistors Tdi1 and Tdi2 and thereby the unity gain bandwidth, actually reducing the stability. Therefore, this design is not effective in some cases, as it would be preferable to increase the transconductance of the cascode transistors Tc1 and Tc2 independent of the pair of differential input transistors Tdi1 and Tdi2.

[0008] In Figure 1C An amplifier design 20' that realizes an increase of the transconductance of the cascode transistors Tc1 and Tc2 independent of the pair of differential input transistors Tdi1 and Tdi2 is shown in Fig. 1 (note that all details of this design can be found in the publication B. K. Ahuja, "An improved frequency compensation technique for CMOS operational amplifiers", IEEE Journal of Solid State Circuits, vol. 18, no. 6, pp. 629-633, Dec. 1983, which is incorporated herein by reference). Here, a common gate stage 23 is inserted between the differential input stage 21 and the output stage 22. The common gate stage 23 consists of a cascode transistor Tcg2 stacked between a transistor Tcg1 and a transistor Tcgt. The transistors Tcg1 and Tcg2 are biased by bias voltages Vbcg1 and Vbcg2, respectively, while the transistor Tcgt is biased by the same bias voltage Vb as the tail transistor Tt. Note that, therefore, a current Icg flows through the cascode transistor Tcg2. As a result of the current Icg added in the common gate stage 23, the transconductance of the amplifier 20 is increased at the cost of additional power consumption.

[0009] This additional power consumption is not desirable in some applications. Therefore, further developments are needed. SUMMARY

[0010] An amplifier is disclosed herein that includes a differential amplifier stage and an output stage. The amplifier stage includes a differential pair of transistors that receives a first voltage and a second voltage, a current mirror pair of transistors, and a cascode pair of transistors coupled between the differential pair at first and second nodes and the current mirror pair at third and fourth nodes. The differential pair is coupled between the cascode pair and a tail node. A tail transistor draws a first bias current from the tail node, the first bias current having an amplitude equal to a product of a total bias current and a constant k, where k is less than 1. A first current source transistor draws a second bias current from the second node such that the second bias current bypasses a second one of the differential pair, the second bias current having an amplitude identical to a product of the total bias current and a value equal to 1 minus k. The output stage is biased by the fourth node.

[0011] The differential pair includes a first differential input transistor coupled between the first node and the tail node, the first differential input transistor receiving the first voltage. The differential pair also includes a second differential input transistor coupled between the second node and the tail node and receiving the second voltage. The current mirror pair includes a first current mirror transistor coupled between a supply voltage and the third node, and a second current mirror transistor coupled between the supply voltage and the fourth node. The cascode pair includes a first cascode transistor coupled between the first and third nodes, and a second cascode transistor coupled between the second and fourth nodes.

[0012] For a given size of the first cascode transistor equal to k*given_size, the size of the second cascode transistor is equal to (2-k)*given_size. Further, for a given size of the first current mirror transistor equal to k*given_size, the size of the second current mirror transistor is equal to (2-k)*given_size, k being less than 1. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1A is a schematic diagram of a prior art amplifier with cascode compensation.

[0014] Figure 1B is a plot of the frequency response of the amplifier of Figure 1A relative to gain.

[0015] Figure 1C is a schematic diagram of another prior art amplifier with cascode compensation.

[0016] Figure 2 is a schematic diagram of an amplifier with cascode compensation according to the present disclosure.

[0017] Figure 3 is a plot of the gain versus frequency of the design of Figure 2 relative to prior art designs.

[0018] Figure 4 is a plot of power supply rejection ratio (PSRR) versus frequency for a design of Figure 2

[0019] Figure 5 is another plot of power supply rejection ratio (PSRR) versus frequency for a design of Figure 2

[0020] Figure 6 is a schematic of another amplifier with cascode compensation according to the present disclosure.

[0021] Figure 7 is a schematic of a differential amplifier of Figure 2 showing small signal analysis. DETAILED DESCRIPTION

[0022] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of the present disclosure. The present disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

[0023] Reference is now made to Figure 2 Described is an amplifier 100 (e.g., operational amplifier) with cascode compensation, the transconductance of the cascode transistors is enhanced in a manner that provides enhanced stability and reduced power consumption compared to prior art designs.

[0024] The amplifier 100 includes a differential amplifier stage 110 (e.g., error amplifier stage) and an output stage 120, and a load 125 is connected to the output stage 120.

[0025] The differential amplifier stage 110 includes a pair of differential input transistors MN1 and MN2 coupled to a tail current source transistor MN5, cascode transistors MN3 and MN4, and current mirror (or load) transistors MP1 and MP2.

[0026] In more detail, the differential input transistor pair is comprised of NMOS transistors MN1 and MN2. The source of NMOS transistor MN1 is connected to a tail node Ntail, its drain is connected to a first node N1, and its gate is connected to receive a feedback voltage Vfb. The source of NMOS transistor MN2 is connected to the tail node Ntail, its drain is connected to a second node N2, and its gate is connected to receive a reference voltage Vref. Note that the tail transistor MN5 is an NMOS transistor, its drain is connected to the tail node Ntail, its source is connected to ground, and its gate is connected to receive a first bias voltage Vb1.​​

[0027] Cascode transistor MN3 is an NMOS transistor whose drain is connected to the first node N1, whose source is connected to the third node N3, and whose gate is connected to the second bias voltage Vb2. Cascode transistor MN4 is an NMOS transistor whose drain is connected to the second node N2, whose source is connected to the fourth node N4, and whose gate is connected to the gate of NMOS transistor MN3 and thereby to the second bias voltage Vb2. Cascode transistors MN3 and MN4 have the same size.

[0028] Current mirror transistor MP1 is a PMOS transistor whose source is connected to the supply voltage Vsup, whose drain is connected to the third node N3, and whose gate is connected to its drain at the third node N3. Current mirror transistor MP2 is a PMOS transistor whose source is connected to the supply voltage Vsup, whose drain is connected to the fourth node N4, and whose gate is connected to the gate of PMOS transistor MP1 and thereby to the third node N3. PMOS transistors MP1 and MP2 have the same size.

[0029] Compensation output transistor MP3 is a PMOS transistor whose source is connected to the supply voltage Vsup and thereby to the source of transistor MP2, whose drain is connected to the fourth node N4 and thereby to the drain of transistor MP2, and whose gate is connected to the gates of PMOS transistors MP1 and MP2. Cascode transistor MN6 is an NMOS transistor whose drain is connected to node N4 and thereby to the drain of NMOS transistor MN4, whose source is connected to the second node N2 and thereby to the source of transistor MN4, and whose gate is connected to the gates of NMOS transistors MN3 and MN4 and thereby to the second bias voltage Vb2. Current source transistor MN7 is an NMOS transistor whose drain is connected to the second node N2 and thereby to the sources of NMOS transistors MN6 and MN4, whose source is connected to ground, and whose gate is connected to the gate of NMOS transistor MN5 and thereby to the first bias voltage Vb1.

[0030] Note that the sizes of the transistors in Figure 2 are scaled relative to the sizes of the transistors in Figure 1A in the same proportion as the currents flowing through them.

[0031] Thus, note that MN5 has a size of k*(size of Tt), MN1 has a size of k*(size of Tdil), MN2 has a size of k*(size of Tdi2), MN3 has a size of k*(size of Tc1), MN4 has a size of k*(size of Tc2), MP1 has a size of k*(size of Tml), and MP2 has a size of k*(size of Tm2). Thus, also note that MP3 has a size of 2(l-k)*(size of Tml or Tm2), MN6 has a size of 2(l-k)*(size of Tc1 or Tc2), and MN7 has a size of (l-k)*(size of MN5).

[0032] The output stage 120 includes a PMOS transistor MP4 having its source connected to the supply voltage Vsup, its drain connected to the output node Nout, and its gate connected to the fourth node N4 and thereby to the drains of PMOS transistors MP2 and MP3. The capacitor Cl represents the gate capacitance due to PMOS transistor MP4 as well as the parasitic capacitance at node N4. The compensation capacitor Cc is connected between the second node N2 and the output node Nout.

[0033] In operation, the differential pair MN1 and MN2 takes the difference between Vfb and Vref and multiplies the difference by the gain. The cascode transistors MN4 and MN6 provide compensation through the capacitor Cc, while the current mirror formed by transistors MP1, MP2, and MP3 forms the active load of the differential amplifier 110 and provides the output of the differential amplifier 110 at node N4. The output transistor MP4 is biased by node N4 and generates the output current Iout. The feedback voltage Vfb is generated at the center tap of the sense resistors R2 and Rl and represents the output current Iout.

[0034] The total bias current I of the differential amplifier stage 110 is split into two parts - a current II through the tail transistor MN5 and a current I3 through the tail transistor MN7. Note that the current II drawn by the tail transistor MN5 is equal to k*I, while the current I2 drawn through each branch is I2 = k*I / 2 when Vref is equal to Vfb. The current I3 emitted by transistor MP3 and absorbed by transistor MN7 is I3 = (1-k)*I; thus, note that I = II + I3 = k*I + (1-k)*I. This splitting of the total bias current I means that, in contrast to prior art designs with a bias current I, such as Figure 1A ) no extra power is consumed by adding the cascode compensation transistor MN6 to the differential amplifier stage, which, as will be explained, provides an increased cascode transconductance. Note that the value of k used in this example is less than 1 and is the same as the k value of the transistor sizes listed above.

[0035] The addition of the cascode compensation transistor MN6 enables an effective enhancement of the cascode transistor MN4 transconductance (labeled kgm3) by the transconductance of MN6 (labeled 2(1-k)gm3) to help compensate, while leaving the overall transconductance of the differential amplifier 110 unchanged. Thus, note that instead of the cascode MN4 transconductance (such as Figure 1A the prior art design of

[0036] kgm3+2(1-k)gm3=kgm3+2gm3-2kgm3=2gm3-kgm3

[0037] The enhancement of the cascode transistor MN6 transconductance is achieved by feeding current I3 to the drain of the cascode transistor MN6 using transistor MP3 and taking current I3 out of the source of the cascode transistor MN6 using the tail transistor MN7, and using the same biasing for transistors MP2 and MP3 so that the overall transconductance of the differential amplifier 110 is unchanged.

[0038] Note that the overall transconductance of the cascode transistors MN4 and MN6 is increased by a factor of (2-k), while keeping the overall transconductance of the differential amplifier 110 the same.

[0039] For example, from the curves of Figure 3 one can see the improved performance of the amplifier 100 design over the prior art design, Figure 3 showing a 4.86dB reduction in DC gain (e.g., a 1 / (2-k) factor reduction for k=0.25), unchanged high frequency performance, and a reduced peak. Note also that due to the transconductance increase provided by the cascode compensation transistor MN6, Figure 4 the curves of

[0040] If one were to try to achieve the same increase in the amplifier 100 transconductance using the design of Figure 1A then, for example, the current Icg would need to be equal to I*(1-0.5k). Thus, the design of the amplifier 100 has a reduced current consumption of I*(1-0.5k) over this prior art design. This also means that, given the equivalent current consumption is acceptable, the transconductance can be improved by a factor of (2-0.5k), which in turn will further improve the high frequency PSRR, remembering that the value of Cap2 needs to be increased by a factor of to maintain the same phase margin. Thus, note in the curves of Figure 5 for k=0.25, the low frequency PSRR remains unchanged, while the high frequency PSRR is improved by 5.4dB, remembering that for Figure 5For example, the overall bias current I increases the amount of current saved compared to existing technologies.

[0041] Those skilled in the art will understand that, Figure 2 In the design, instead of using transistor MP3 coupled in parallel with transistor MP2 and instead of using transistor MN6 coupled in parallel with transistor MN4, the size of transistors MP2 and MP4 can be increased (while keeping the addition of transistor MN7, which draws current I3 from node N2).

[0042] Such implementation, for example Figure 6 As shown. In this embodiment, amplifier 100' consists of a differential amplifier stage 110' and an output stage 120. Output stage 120 maintains the configuration described above. Figure 2 As stated above.

[0043] In this application, the differential amplifier stage 110' includes: a differential input transistor pair MN1 and MN2 coupled to the tail current source transistor MN5, cascode transistors MN3 and MN4', and current mirror (or load) transistors MP1 and MP2'.

[0044] More specifically, the differential input transistor pair consists of NMOS transistors MN1 and MN2. The source of NMOS transistor MN1 is connected to the tail node Ntail, its drain is connected to the first node N1, and its gate is connected to receive the feedback voltage Vfb. The source of NMOS transistor MN2 is connected to the tail node Ntail, its drain is connected to the second node N2, and its gate is connected to receive the reference voltage Vref. Note that the tail transistor MN5 is an NMOS transistor with its drain connected to the tail node Ntail, its source connected to ground, and its gate connected to receive the first bias voltage Vb1.

[0045] The cascode transistor MN3 is an NMOS transistor with its drain connected to the first node N1, its source connected to the third node N3, and its gate connected to the second bias voltage Vb2. The cascode transistor MN4' is an NMOS transistor with its drain connected to the second node N2, its source connected to the fourth node N4, and its gate connected to the gate of the NMOS transistor MN3 and thus connected to the second bias voltage Vb2.

[0046] The current mirror transistor MP1 is a PMOS transistor, with its source connected to the power supply voltage Vsup, its drain connected to the third node N3, and its gate connected to its drain at the third node N3. The current mirror transistor MP2' is a PMOS transistor, with its source connected to the power supply voltage Vsup, its drain connected to the fourth node N4, and its gate connected to the gate of the PMOS transistor MP1 and thus connected to the third node N3.

[0047] The drain of NMOS transistor MN7 is coupled to node N2 and capacitor Cc, its source is coupled to ground, and its gate is coupled to bias voltage Vbl.

[0048] The dimensions of transistors MP1, MN1, MN2, MN3, and MN5 are k times the dimensions of transistors Tml, Tidl, Tid2, Tcl, and Tt, respectively. Figure 1A The dimensions of transistors MP2' and MN4' are (2-k) times the dimensions of transistors Tm2 and Tc2, respectively. Figure 1A The dimensions of transistors MP2' and MN4' are (2-k) times the dimensions of transistors Tm2 and Tc2, respectively.

[0049] In operation of differential amplifier 100, differential pair MN1 and MN2 take the difference between Vfb and Vref and multiply the difference by the gain. Cascode transistors MN3 and MN4' provide compensation, while current mirror formed by transistors MP1 and MP2' form the active load of differential amplifier stage 110 and provide the output of differential amplifier 110 at node N4. Output transistor MP4 is biased by node N4 and generates output current Iout. Feedback voltage Vfb is generated at the center tap of sense resistors R2 and Rl and represents output current Iout.

[0050] Here, note that bias current Ii absorbed by transistor MN5 is equal to kI; current I2 emitted by transistor MP1 is equal to kI / 2 when Vref is equal to Vfb; and current I3 absorbed by transistor MN7 is equal to (1-k)I, while the current emitted by transistor MP2' is I2+I3=kI / 2+(1-k)I when Vref is equal to Vfb. The result is that the increase in current I2+I3 emitted by current mirror transistor MP2' to cascode transistor MN4' causes an increase in the transconductance of MN4' without increasing the transconductance of transistor MN2 (because MN2 absorbs current I2, as current I3 bypasses MN2). Thus, the transconductance of transistor MN2 remains kgml, while the transconductance of cascode transistor MN4' increases to:

[0051] kgm3+2(1-k)gm3=2gm3-kgm3

[0052] The overall transconductance of differential amplifier 110' remains gm1.

[0053] Referring to Figure 7The small signal diagram of the differential amplifier 110' is shown, which can be the easiest to see. From this, it can be readily observed that the overall transconductance of the differential amplifier 110' is gmin = gml, and thus remains unchanged. As noted above, the transconductance of the cascode transistor MN4' is gmcas = (2-k)gm3, and thus is increased by a factor of 2-k over the prior art. Thus, it will be appreciated that through the design of the differential amplifier 110' (and the differential amplifier 110), the overall cascode device transconductance is increased by a factor of 2-k, but the input transconductance remains the same for the same total bias current I. Thus, power is saved.

[0054] Figure 6 The performance of the amplifier 100' is compared to Figure 2 the amplifier 100, and thus the curves presented previously are applicable.

[0055] While the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having the benefit of the present disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the present disclosure as disclosed herein. Accordingly, the scope of the present disclosure is limited only by the appended claims.

Claims

1. An amplifier, comprising: Amplifier stages, including: A differential transistor pair receives a first voltage and a second voltage; Current mirror transistor pair; A common-source, common-gate transistor pair is coupled between the differential transistor pair at the first and second nodes and the current mirror transistor pair at the third and fourth nodes; The differential transistor pair is coupled between the cascode transistor pair and the tail node; and The tail transistor draws a first bias current from the tail node, the magnitude of which is equal to the product of the total bias current and a constant k, where the constant k is less than 1. A first current source transistor draws a second bias current from either the first or second node, such that the second bias current bypasses one of the differential transistor pairs. The magnitude of the second bias current is equal to the product of the total bias current and a value equal to 1 minus k. The output stage is biased by the third node or the fourth node.

2. The amplifier according to claim 1, further comprising: The second current source transistor is coupled in parallel with one of the transistors in the current mirror transistor pair; as well as A compensating cascode transistor is coupled in parallel with one of the transistors in the cascode transistor pair. The second current source transistor sends the second bias current to the compensation cascode transistor, and the first current source transistor absorbs the second bias current from the compensation cascode transistor.

3. The amplifier of claim 1, wherein the differential transistor pair comprises: A first differential input transistor is coupled between the first node and the tail node and receives the first voltage; and a second differential input transistor, coupled between the second node and the tail node, and receiving the second voltage; wherein the current mirror transistor pair includes a first current mirror transistor coupled between the power supply voltage and the third node, and a second current mirror transistor coupled between the power supply voltage and the fourth node, the first current mirror transistor and the second current mirror transistor being in a current mirror relationship; wherein the cascode transistor pair includes a first cascode transistor coupled between the first node and the third node, and a second cascode transistor coupled between the second node and the fourth node.

4. The amplifier according to claim 3, further comprising: The second current source transistor is coupled in parallel with the second current mirror transistor; as well as A compensation cascode transistor is coupled in parallel with the second cascode transistor. The second current source transistor sends the second bias current to the compensation cascode transistor, and the first current source transistor absorbs the second bias current from the compensation cascode transistor.

5. The amplifier of claim 4, wherein for a given size of the second current mirror transistor equal to k×given_size, the size of the second current source transistor is (1-k)×given_size; and wherein for a given size of the second cascode transistor equal to k×given_size, the size of the compensation cascode transistor is 2(1-k)×given_size.

6. The amplifier of claim 3, wherein the second current mirror transistor is larger than the first current mirror transistor; and wherein the second cascode transistor is larger than the first cascode transistor.

7. The amplifier of claim 6, wherein for a given size of the first cascode transistor equal to k × given_size, the size of the second cascode transistor is equal to (2-k) × given_size; and wherein for a given size of the first current mirror transistor equal to k × given_size, the size of the second current mirror transistor is equal to (2-k) × given_size.

8. The amplifier of claim 1, wherein the amplifier stage is an error amplifier stage, wherein the first voltage is a feedback voltage representing the current delivered from the output stage to the load, and wherein the second voltage is a reference voltage.

9. An amplifier, comprising: Amplifier stages, including: A differential transistor pair receives a first voltage and a second voltage; Current mirror transistor pair; and A common-source, common-gate transistor pair is coupled between the differential transistor pair and the current mirror transistor pair; The common-source, common-gate compensation stage includes: The output transistor is biased by the current mirror transistor pair and is directly connected between the power supply voltage and the first node. A compensating cascode transistor, biased by the cascode transistor pair, is directly connected between the first node and the second node; and The current source transistor is directly connected between the second node and ground; and The output stage includes a transistor having a gate that is directly coupled to the cascode compensation stage, and the transistor is directly connected between the power supply voltage and the output voltage.

10. The amplifier according to claim 9, wherein: The differential transistor pair includes a first differential input transistor and a second differential input transistor; The current mirror transistor pair includes a first current mirror transistor and a second current mirror transistor; and The common-source cascode transistor pair includes a first common-source cascode transistor and a second common-source cascode transistor, wherein the first common-source cascode transistor and the second common-source cascode transistor are respectively coupled between the first differential input transistor and the second differential input transistor and the first current mirror transistor and the second current mirror transistor; and in: The output transistor has the same bias as the second current mirror transistor; and The compensated cascode transistor has the same bias as the second cascode transistor.

11. The amplifier of claim 9, wherein the differential transistor pair comprises a first transistor and a second transistor, the gate of the first transistor being coupled to the second voltage, and the gate of the second transistor being coupled to the first voltage; and wherein the transconductance of the first transistor of the differential transistor pair is decoupled from the transconductance of the compensation cascode transistor of the cascode compensation stage.

12. The amplifier of claim 9, wherein the current mirror transistor pair comprises transistors having the same aspect ratio as each other; wherein the cascode transistor pair comprises transistors having the same aspect ratio as each other; and wherein: The differential transistor pair includes a first differential input transistor and a second differential input transistor; The current mirror transistor pair includes a first current mirror transistor and a second current mirror transistor, wherein the second current mirror transistor is coupled in parallel with the output transistor of the cascode compensation stage; and The cascode transistor pair includes a first cascode transistor and a second cascode transistor. The first cascode transistor and the second cascode transistor are respectively coupled between the first differential input transistor and the second differential input transistor and the first current mirror transistor and the second current mirror transistor. The second cascode transistor is coupled in parallel with the compensation cascode transistor.

13. The amplifier of claim 12, wherein the amplifier stage further comprises a tail current source configured to draw a first current from a tail node; wherein the first differential input transistor is configured to send a second current to the tail node; wherein the second differential input transistor is also configured to send the second current to the tail node; wherein the first current mirror transistor is configured to send the second current to the first cascode transistor; wherein the second current mirror transistor is configured to send the second current to the second cascode transistor; wherein the second current is equal to half of the first current; wherein the output transistor is configured to send a third current to the cascode compensation transistor; and wherein the cascode compensation stage further comprises a current sink transistor configured to draw the third current from the cascode compensation transistor to bypass the second differential input transistor.

14. The amplifier of claim 9, wherein the amplifier stage further comprises a tail current source configured to absorb a first current from the tail node; wherein each of the current mirror transistor pairs is configured to send a second current to one of the transistors in the cascode transistor pair, the second current being equal to half of the first current; wherein each of the differential transistor pairs is configured to send the second current to the tail node; wherein the output transistor is configured to send a third current to the cascode compensation transistor; and wherein the cascode compensation stage further comprises a current sink transistor configured to absorb the third current from the cascode compensation transistor to bypass the differential transistor pair.

15. An amplifier, comprising: An amplifier stage, wherein the amplifier stage includes an error amplifier stage, the error amplifier stage comprising: A differential transistor pair receives a first voltage and a second voltage, the differential transistor pair including a first differential input transistor and a second differential input transistor, wherein the first voltage includes a feedback voltage and the second voltage includes a reference voltage; A current mirror transistor pair, the current mirror transistor pair comprising a first current mirror transistor and a second current mirror transistor; and A common-source cascode transistor pair is coupled between the differential transistor pair and the current mirror transistor pair. The common-source cascode transistor pair includes a first common-source cascode transistor coupled between the first differential input transistor and the second differential input transistor, and a second common-source cascode transistor coupled between the first current mirror transistor and the second current mirror transistor. The common-source, common-gate compensation stage includes: An output transistor is biased by the current mirror transistor pair, wherein the output transistor has the same bias as the second current mirror transistor; A compensating cascode transistor, biased by the second cascode transistor, wherein the compensating cascode transistor has the same bias as the second cascode transistor; and An output stage is coupled to the cascode compensation stage, wherein the output stage includes: The output transistor is biased by the output of the output transistor of the cascode compensation stage and generates a load current; and The sensing resistor is configured to generate the second voltage based on the load current.

16. An amplifier, comprising: Amplifier stage; A differential transistor pair, receiving a first voltage and a second voltage, wherein the differential transistor pair comprises: The first NMOS transistor has a drain, a source coupled to the tail node, and a gate coupled to receive the second voltage; and The second NMOS transistor has a drain, a source coupled to the tail node, and a gate coupled to receive the first voltage. Current mirror transistor pair, wherein the current mirror transistor pair comprises: A first PMOS transistor has a source coupled to a power supply node, a drain coupled to a first intermediate node, and a gate coupled to the drain of the first PMOS transistor; and The second PMOS transistor has a source coupled to the power node, a drain coupled to the second intermediate node, and a gate coupled to the gate of the first PMOS transistor. A common-source cascode transistor pair is coupled between the differential transistor pair and the current mirror transistor pair, wherein the common-source cascode transistor pair includes: A third NMOS transistor has a drain coupled to the first intermediate node, a source coupled to the drain of the first NMOS transistor, and a gate; and The fourth NMOS transistor has a drain coupled to the second intermediate node, a source coupled to the drain of the second NMOS transistor, and a gate coupled to the gate of the third NMOS transistor; and The common-source, common-gate compensation stage includes: The output transistor is biased by the current mirror transistor; and Compensating the cascode transistor, biased by the cascode transistor pair; and The output stage is coupled to the cascode compensation stage. The tail current source includes a fifth NMOS transistor having a drain coupled to the tail node, a source coupled to ground, and a gate. The output transistor of the common-source common-gate compensation stage includes a third PMOS transistor, the third PMOS transistor having a source coupled to the power node, a drain coupled to the drain of the second PMOS transistor, and a gate coupled to the gate of the first PMOS transistor and the gate of the second PMOS transistor; The compensation cascode compensation stage includes a sixth NMOS transistor having a drain coupled to the drain of the third PMOS transistor and a gate coupled to the gate of the third NMOS transistor and the gate of the fourth NMOS transistor; and The common-source, common-gate compensation stage includes a seventh NMOS transistor having a drain coupled to the source of the sixth NMOS transistor, a source coupled to ground, and a gate coupled to the gate of the fifth NMOS transistor.

17. The amplifier of claim 16, wherein the output stage comprises: The fourth PMOS transistor has a source coupled to the power node, a drain coupled to the output node, and a gate coupled to the drain of the second PMOS transistor and the drain of the third PMOS transistor. A capacitor is coupled between the gate of the fourth PMOS transistor and the power supply node; A compensation capacitor is coupled between the source and the output node of the sixth NMOS transistor; as well as A voltage divider is coupled between the output node and ground, wherein the second voltage is generated at the center tap of the voltage divider, and wherein the center tap of the voltage divider is coupled to the gate of the first NMOS transistor.

18. The amplifier of claim 16, wherein the gate of the fifth NMOS transistor and the gate of the seventh NMOS transistor are coupled to receive a first bias voltage.

19. An amplifier, comprising: Amplifier stages, including: The first differential input transistor and the second differential input transistor receive the first voltage and the second voltage, respectively; First current mirror transistor and second current mirror transistor; A first cascode transistor and a second cascode transistor are coupled between the first differential input transistor and the second differential input transistor and the first current mirror transistor and the second current mirror transistor; and A tail current source is coupled to absorb a first current from the first differential input transistor and the second differential input transistor, such that both the first differential input transistor and the second differential input transistor send a second current to the tail current source, the second current being equal to half of the first current. A current source is configured to draw a third current from the second cascode transistor, such that the third current bypasses the second differential input transistor; and The output stage is biased by the second current mirror transistor and the second cascode transistor. The first current mirror transistor is configured to send the second current to the first cascode transistor, but the size of the second current mirror transistor is different from that of the first current mirror transistor, so as to send a current equal to the sum of the second current and the third current to the second cascode transistor. The first cascode transistor is configured to send the second current to the first differential input transistor, but the second cascode transistor has a different size than the first cascode transistor, so as to draw a current from the second current mirror transistor equal to the sum of the second current and the third current, such that the transconductance of the second cascode transistor is greater than that of the first cascode transistor, and the second differential input transistor has the same transconductance as the first differential input transistor.

20. The amplifier of claim 19, wherein the second current mirror transistor is larger than the first current mirror transistor; wherein the second cascode transistor is larger than the first cascode transistor; and wherein the first differential input transistor and the second differential input transistor have the same size.

21. The amplifier of claim 20, wherein the tail current source comprises a transistor; and wherein the transistor comprising the current source has the same size as the transistor of the tail current source.

22. The amplifier of claim 19, wherein the amplifier stage includes an error amplifier stage; wherein the first voltage includes a feedback voltage, and the second voltage includes a reference voltage; and wherein the output stage includes: The output transistor is biased by the second current mirror transistor and the second common-source cascode transistor, and generates the load current; as well as The sensing resistor is configured to generate the second voltage based on the load current.

23. The amplifier according to claim 19, The first differential input transistor includes a first NMOS transistor, which has a drain, a source coupled to the tail node, and a gate coupled to receive the second voltage. The second differential input transistor includes a second NMOS transistor having a drain, a source coupled to the tail node, and a gate coupled to receive the first voltage. The first current mirror transistor includes a first PMOS transistor, which has a source coupled to a power node, a drain coupled to a first intermediate node, and a gate coupled to the drain of the first PMOS transistor. The second current mirror transistor includes a second PMOS transistor, which has a source coupled to the power node, a drain coupled to the second intermediate node, and a gate coupled to the gate of the first PMOS transistor. The first common-source common-gate transistor includes a third NMOS transistor, the third NMOS transistor having a drain coupled to the first intermediate node, a source coupled to the drain of the first NMOS transistor, and a gate; The second common-source common-gate transistor includes a fourth NMOS transistor, the fourth NMOS transistor having a drain coupled to the second intermediate node, a source coupled to the drain of the second NMOS transistor, and a gate coupled to the gate of the third NMOS transistor; and The tail current source includes a fifth NMOS transistor having a drain coupled to the tail node, a source coupled to ground, and a gate coupled to receive a bias voltage. as well as The current source includes a sixth NMOS transistor having a drain coupled to the source of the fourth NMOS transistor, a source coupled to ground, and a gate also coupled to receive the bias voltage.

24. The amplifier of claim 23, wherein the output stage comprises: The third PMOS transistor has a source coupled to the power node, a drain coupled to the output node, and a gate coupled to the drain of the second PMOS transistor. A capacitor is coupled between the drain of the third PMOS transistor and the power supply node; A compensation capacitor is coupled between the source and the output node of the fourth NMOS transistor; as well as A voltage divider is coupled between the output node and ground, wherein the second voltage is generated at the center tap of the voltage divider, and the center tap of the voltage divider is coupled to the gate of the first NMOS transistor.

25. An amplifier, comprising: Amplifier stages, including: The first differential input transistor and the second differential input transistor receive the first voltage and the second voltage, respectively; The first current mirror transistor and the second current mirror transistor have different sizes from each other; The first cascode transistor and the second cascode transistor have different sizes from each other and are coupled between the first differential input transistor and the second differential input transistor and the first current mirror transistor and the second current mirror transistor. The first current mirror transistor and the second current mirror transistor are coupled between the power node and the first cascode transistor and the second cascode transistor, wherein the power node receives a positive power supply voltage; The first differential input transistor and the second differential input transistor are coupled between the first cascode transistor and the second cascode transistor and the tail node; and A tail transistor is coupled to draw a first current from the tail node; A current source transistor is coupled in parallel with the second current mirror transistor; A compensation cascode transistor is coupled in parallel with the second cascode transistor. The second tail transistor draws a second current from the second cascode transistor, such that the second current bypasses the second differential input transistor; and An output transistor is coupled between the power supply node and the output node, and the output transistor has a control terminal coupled to the drain of the current source transistor and the drain of the compensation cascode transistor.

26. The amplifier of claim 25, wherein for a given size of the second current mirror transistor equal to k × given_size, the size of the compensated cascode transistor is (1-k) × given_size.

27. The amplifier of claim 25, wherein for a given size of the second cascode transistor equal to k × given_size, the size of the compensated cascode transistor is 2(1-k) × given_size.

28. The amplifier of claim 25, wherein the amplifier stage is an error amplifier stage, wherein the first voltage is a feedback voltage representing the current delivered by the output transistor to the load, and the second voltage is a reference voltage.

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