Method and Circuit for Generating Pulse Width Modulation Signal

Abstract

This application relates to a method and a circuit for generating a pulse width modulation signal. In the described example, the method for generating a pulse width modulation (PWM) signal (218) includes: repetitively performing a master control count by a master control counter generator, the master control count including incrementing the master control counter from a minimum value and / or decrementing the master control counter from a maximum value; and repetitively performing a slave control count (214) having a phase delay Φd relative to the master control count, and during a transition period (220), the slave control count (214) to a new maximum value or a new phase delay Φd. The maximum count of the transition period (220) is selected such that the transition period (220) reaches the minimum value at the new phase delay count Φd. The PWM signal (218) is generated by generating a rising edge when the slave control counter (214) reaches a rising edge threshold (222) and generating a falling edge when the slave control counter (214) reaches a falling edge threshold (224).

Description

Technical Field

[0001] This application generally relates to electronic circuits, and more particularly to pulse width modulation methods and circuits. Background Art

[0002] Figure 1A An example of a count plot 100 showing an amplitude proportional to the count and representing the count of a pulse width modulation (PWM) control counter 102 over time, and an example of a timing diagram 104 of a PWM waveform 106 generated using the control counter 102 are shown. (Here, "control count" refers to both the count generator and the resulting count. When suitable for illustration, reference is made to the count of the control counter). The count plot 100 and the timing diagram 104 use the same time axis. Thus, the count value in the control counter 102 represented at a particular point on the x-axis (time axis) in the count plot 100 and the PWM value (high or low) in the PWM waveform 106 represented at the same point on the x-axis (time axis) in the timing diagram 104 are both represented simultaneously. This time axis alignment applies to each of the figures in this document, which include plots of PWM control counters and timing diagrams of PWM waveforms generated using such control counters.

[0003] Figure 1A The exemplary PWM control counter 102 and PWM waveform 106 shown correspond to typical PWM control. The control counter 102 counts from a minimum value, typically zero, up to a maximum value (incrementing), and then starts counting again from the minimum value. This produces a sawtooth pattern. The control counter 102 is compared with two thresholds, a rising edge threshold 108 and a falling edge threshold 110, to produce a rising edge and a falling edge, respectively, in the PWM waveform 106. The rising edge threshold 108 corresponds to the maximum count of the control counter 102, which corresponds to the desired frequency of the PWM waveform 106. The falling edge threshold 110 corresponds to half (1 / 2) of the maximum count of the control counter 102, corresponding to a 50% duty cycle in the PWM waveform 106. The fraction of the falling edge threshold 110 of the adjustable maximum count can be adjusted to adjust the duty cycle of the PWM waveform 106.

[0004] A first desired frequency F1 specified for the time period from time T0 to time T1 corresponds to a maximum count of C = 1000 counts. A second desired frequency F2 specified for the time period from time T1 to time T2 corresponds to a maximum count of C = 400 counts. A third desired frequency F3 specified for the time period from time T2 to time T3 corresponds to a maximum count of C = 1000 (F1 = F3). The rising edge threshold 108 for F1 and F3 is 1000 counts, and the falling edge threshold 110 for F1 and F3 is 500 counts. The rising edge threshold 108 for F2 is 400, and the falling edge threshold 110 for F2 is 200. Times T0, T1, T2, and T3 are atFigure 1A The moments in 1B and 1C are the same.

[0005] The minimum count of control counter 102 is C = 0 count. If the minimum count is higher, e.g., C = 50 count, the corresponding frequency will be higher because the difference between the maximum count and the minimum count is smaller. If the minimum counter is higher, e.g., C = 50 count, the frequency will be the same, and thus the maximum count increases equally to F1 = F3 = 1050 count, and F2 = 450 count. That is, the frequency (and period) of control counter 102 depends on the difference between the maximum count and the minimum count of the period of control counter 102.

[0006] Figure 1B shows an example of the prior art of the count plot 112 of the PWM control counter 114 over time, and an example of the timing diagram 116 of the PWM waveform 118 generated using the control counter 114. The count plot 112 and the timing diagram 116 use the same time axis. Figure 1A The control counter 102 serves as the master control counter relative to the control counter 114 of Figure 1B. This means that the count (except during the period straddling the change in frequency or phase delay or during the next subsequent period after said change), the frequency (the maximum count value and the minimum count value), and the threshold value of the control counter 114 of Figure 1B are the same as Figure 1A the count, frequency, and threshold values of the control counter 102; except that the (slave) control counter 114 of Figure 1B is phase-shifted by +180° relative to Figure 1A the (master) control counter 102.

[0007] As used herein, "phase shift" refers to the rotation angle (fractional offset) of the period of the slave control counter relative to the period of the master control counter. As used herein, "phase delay count" refers to such a count value by which, for the corresponding phase shift applied to the slave control counter and the current frequency of the slave control counter, the period of the slave control counter is offset relative to the period of the master control counter. The phase delay count corresponds respectively to the number of increments of the master control counter after the master control counter reaches a specific value during incrementing or decrementing and before the slave control counter reaches said specific value during incrementing or decrementing. In Figure 1B, between time T0 and T1, and between time T2 and T3, the phase delay count of the control counter 114 relative to the master control counter 102 is 50% of 1000, i.e., 0.5 * 1000 = 500 count (+180° corresponds to a delay of 50% of a single period). Between time T1 and T2, the phase delay count of the control counter 114 relative to the master control counter 102 is 400 * 0.5 = 200 count.

[0008] When the control counter 114 transitions from F1 to F2 at time T1, the count of the control counter 114 is phase-shifted by +180° relative to Figure 1A the count of the control counter 102 at time T1. To maintain the +180° phase shift and the new frequency, the count at time T1 changes from the count corresponding to the previous frequency (C = 499 counts) to the count corresponding to the new frequency (C = 200 counts). (At time T2, when the control counter 114 transitions from F2 to F3, a similar change from C = 199 to C = 500 occurs). As a result, the continued incrementing of the control counter 114 is interrupted, and thus, the falling edge threshold 120 is not reached at time T1 during the transition from F1 to F2 because the count of the control counter 114 jumps (rather than properly increments) to 200 at time T1, and the threshold does not change until the end of the period. Thus, in FIG. 1B, at time T1, when the control counter 114 would increment and reach the falling edge threshold 120 if there were no frequency change, the control counter 114 jumps (rather than increments) to the falling edge threshold 120. Thus, no falling edge is triggered in the PWM waveform 118 at time T1, as shown by the vertical dashed line at time T1 in FIG. 1B, at which time the missed cycle 128 begins. Similarly, at time T2, when the incrementing control counter 114 would reach the falling edge threshold 120 without a frequency change, the control counter 114 does not increment to the falling edge threshold 120, and no falling edge is triggered in the PWM waveform 118 at time T2, as shown by the other vertical dashed line at time T2 in FIG. 1B, at which time the missed cycle 128 begins. (There is also a rising edge threshold 122).

[0009] A frequency change in the PWM control counter results in a discontinuity 124 in the count maintained by the PWM control counter. This discontinuity 124 in turn causes an error in the PWM waveform controlled by the PWM control counter. In FIG. 1B, the dashed line in the PWM waveform 118 shows the intended portion 128 of the PWM waveform 118, and the deviation from this intention (shown by the dashed line) includes the error portion 126 of the PWM waveform 118. The error in the PWM waveform 118 causes the period of the PWM waveform 118 to be extended during a frequency transition. The extended period of the PWM waveform 118 can have an adverse effect on a circuit that uses PWM control. For example, in a circuit that uses PWM to control power delivery to the primary side of a transformer (or other inductor), the alternating interruptions of the PWM waveform 118 can cause overvoltage of a capacitor or oversaturation of an inductor, potentially damaging the corresponding circuit.

[0010] Figure 1C shows an example of the prior art of the count plot 130 of the PWM control counter 132 over time, and an example of the timing diagram 134 of the PWM waveform 136 generated using the control counter 132. The count plot 130 and the timing diagram 134 use the same time axis. Figure 1A The control counter 102 serves as the master control counter relative to the control counter 132 of FIG. 1C. This means that the count (except during the cycle across the change in frequency or phase delay or during the next subsequent cycle after said change), the frequency (the maximum count value and the minimum count value), and the values of the thresholds of the (slave) control counter 132 of FIG. 1C are the same as Figure 1A the frequency and the values of the thresholds of the (master) control counter 102 of Figure 1A ; except that the control counter 132 of FIG. 1C is phase-shifted by +90° relative to SUMMARY OF THE INVENTION

[0011] In the described example, a method of generating a pulse width modulation (PWM) signal includes: repetitively performing a master control count by a master control counter generator, the master control count including either or both of incrementing the master control counter from a minimum value and decrementing the master control counter from a maximum value; and repetitively performing a slave control count having a phase delay relative to the master control count, and during a transition period, the slave control count to a new maximum value or a new phase delay. The maximum count of the transition period is selected such that the transition period reaches a minimum value when the new phase delay count is reached. A PWM signal is generated by generating a rising edge when the slave control counter reaches a rising edge threshold and generating a falling edge when the slave control counter reaches a falling edge threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A An example showing a count plot having an amplitude proportional to the count and representing the count of a pulse width modulation (PWM) control counter (having a variable period) over time, and an example of a timing diagram of a PWM waveform generated using the control counter.

[0013] FIG. 1B shows an example of the prior art of a count plot of a PWM control counter (having a variable period and a fixed +180° phase shift relative to Figure 1A the PWM control counter of) over time, and an example of a timing diagram of a PWM waveform generated using the control counter.

[0014] Figure 1C shows an example of the prior art of a count plot of a PWM control counter (with a variable period and a fixed +90° phase shift relative to Figure 1A ), and an example of a timing diagram of a PWM waveform generated using the control counter.

[0015] Figure 2A An example of a count plot of a PWM control counter (with a variable period) over time, and an example of a timing diagram of a PWM waveform generated using the control counter.

[0016] Figure 2B Figure [X] shows a PWM control counter (with a variable period and a fixed +180° phase shift relative to Figure 2A ), and an example of a timing diagram of a PWM waveform generated using the control counter.

[0017] Figure 2C Figure [X] shows a PWM control counter (with a variable period and a fixed +90° phase shift relative to Figure 2A ), and an example of a timing diagram of a PWM waveform generated using the control counter.

[0018] Figure 3 Figure [X] shows an example of a block diagram of a device for generating the PWM waveform described with respect to Figure 2B and using the PWM waveform to control the power supplied to a power stage.

[0019] Figure 4 Figure [X] shows an example of an exemplary process for generating the PWM waveform described with respect to Figure 2B and using the PWM waveform to control a switch.

[0020] Figure 5A An example of a count plot of a PWM control counter (with a fixed period) over time, and an example of a timing diagram of a PWM waveform generated using the control counter.

[0021] Figure 5B shows an example of the prior art of a count plot of a PWM control counter (with a fixed period and a variable phase shift relative to Figure 5A ), and an example of a timing diagram of a PWM waveform generated using the control counter.

[0022] Figure 5C Figure [X] shows a PWM control counter (with a fixed period and a variable phase shift relative to Figure 5A ), and an example of a timing diagram of a PWM waveform generated using the control counter.

[0023] Figure 6A An example of a count plot of a PWM control counter (with a fixed period) over time, and an example of a timing diagram of a PWM waveform generated using the control counter.

[0024] Figure 6B shows an example of the prior art of a count plot of a PWM control counter (with a fixed period and a variable phase offset relative to Figure 6A the PWM control counter) over time, and an example of a timing diagram of a PWM waveform generated using the control counter.

[0025] Figure 6C An example of a count plot of a PWM control counter (with a fixed period and a variable phase offset relative to Figure 6A the PWM control counter) over time, and an example of a timing diagram of a PWM waveform generated using the control counter.

[0026] Figure 7A An example of a count plot of a PWM control counter (with a fixed period) over time, and an example of a timing diagram of a PWM waveform generated using the control counter.

[0027] Figure 7B shows an example of the prior art of a count plot of a PWM control counter (with a fixed period and a variable phase offset relative to Figure 7A the PWM control counter) over time, and an example of a timing diagram of a PWM waveform generated using the control counter.

[0028] Figure 7C An example of a count plot of a PWM control counter (with a fixed period and a variable phase offset relative to Figure 7A the PWM control counter) over time, and an example of a timing diagram of a PWM waveform generated using the control counter.

[0029] Figure 8A An example of a count plot of a PWM control counter (with a variable period) over time, and an example of a timing diagram of a PWM waveform generated using the control counter.

[0030] Figure 8B shows an example of the prior art of a count plot of a PWM control counter (with a variable period and a fixed +180° phase offset relative to Figure 8A the PWM control counter) over time, and an example of a timing diagram of a PWM waveform generated using the control counter.

[0031] Figure 8C An example of a count plot of a PWM control counter (with a variable period and a fixed +180° phase offset relative to Figure 8AExample of a count plot over time of a PWM control counter with variable period and fixed +180° phase shift, and an example of a timing diagram of a PWM waveform generated using the control counter. Detailed Description

[0032] Figure 2A An example of a count plot 200 over time of an embodiment of a pulse width modulation (PWM) control counter 202, and an example of a timing diagram 204 of a PWM waveform 206 generated using the control counter 202. The plot 200 and the timing diagram 204 use the same time axis. As Figure 2A shown, the control counter 202 is compared with two thresholds, an upper threshold 208 and a lower threshold 210, to generate (respectively) an upper edge and a lower edge in the PWM waveform 206. The upper threshold 208 corresponds to the maximum count of the control counter 202, and the maximum count corresponds to the desired frequency of the PWM waveform 206. Figure 2A The lower threshold 210 shown corresponds to one half (1 / 2) of the maximum count of the control counter 202 at a 50% duty cycle; other duty cycles may be used. The fraction of the maximum count at which the lower threshold 210 is adjusted can be adjusted to adjust the duty cycle of the PWM waveform 206. When the upper threshold 208 is equal to the maximum count of the control counter 202, for example, a 25% duty cycle will correspond to a lower threshold 210 that is one quarter (1 / 4) of the maximum count. A first desired frequency F1 specified for time T0 to time T1 corresponds to a maximum count of C = 1000 counts; a second desired frequency F2 specified for time T1 to time T2 corresponds to a maximum count of C = 400 counts; and a third desired frequency F3 specified for time T2 to time T3 corresponds to a maximum count of C = 1000 (i.e., F1 = F3 in this example).

[0033] Figure 2B An example of a count plot 212 over time of a PWM control counter 214, and an example of a timing diagram 216 of a PWM waveform 218 generated using the control counter 214. The count plot 212 and the timing diagram 216 use the same time axis. Figure 2A The control counter 202 of Figure 2B is used as a master control counter with respect to Figure 2B the control counter 214 of Figure 2A This means that Figure 2B the count (except during a period spanning a change in frequency or phase delay or during the next subsequent period following the change) and the frequency (maximum and minimum count values) of the (slave) control counter 214 of Figure 2AThe control counter 202 is beyond a phase shift of +180° (50%). (The threshold of the control counter 214 is also the same as that of the control counter 202, but this is specific to the examples shown in FIGS. 5A to 7C. In some embodiments, the threshold of the master control counter may be different from the threshold of the slave control counter. This means that when the control counter 214 transitions from F1 to F2 at time T1, the count of the control counter 214 is phase-shifted by +180° (50%) relative to Figures 1A to 2C the count of the control counter 202 at time T1. (The phase shift and phase delay count were described above with reference to FIG. 1B.) In Figure 2A FIGS. 5A to 7C and other slave plotting diagrams, specific phase delay counts are shown using arrows from the moment of transition of the master control counter (e.g., T0, T1, T2) to the end of the respective slave control counter cycle. The arrow is further denoted by Φd as "phase delay count". Figure 2B The moment when the phase or frequency of the master control counter 202 changes (transitions to a new phase or frequency) can be referred to as the "transition moment". The transition moment corresponds to the count of the master control counter 202.

[0034] When the master control counter 202 changes (transitions) in frequency from the current frequency to the next frequency (at times T1 and T2),

[0035] the slave control counter 214 of Figure 2B avoids the discontinuity 124 in FIGS. 1B and 1C from affecting the count of the control counter 214 by extending the duration of the slave cycle of (the control counter 214) that is affected by the transition (immediately before the transition). This causes the slave cycle to transition to the next frequency at a moment after the corresponding (master) PWM control counter 202 transitions. For example, when comparing Figure 2A FIGS. 5A to 7C 2B it should be noted that at time T1, Figure 2A the master cycle in Figure 2B transitions from the current frequency to the next frequency, and before the slave control counter 214 transitions to the next frequency, the corresponding slave cycle is extended so as to maintain the current frequency beyond T1. The entire extended slave cycle at the current frequency is referred to herein as the transitional cycle 220, and as can be easily noted in Figure 2BAs shown. Thus, the conversion cycle 220 causes subsequent cycles to have the correct phase delay count for the new frequency and / or phase offset, avoids count discontinuities at frequency and / or phase offset changes, and helps enable the rising edge threshold 222 and the falling edge threshold 224 to be met, thereby avoiding excessively long PWM waveform 218 cycles. These results can be further improved by adjusting the falling edge threshold 224 of the conversion cycle 220 to maintain the duty cycle (as further described below).

[0036] The expansion of the above switching cycle can also be represented mathematically, where the total period (maximum count) of the switching cycle 220 from the current frequency to the next frequency is T cn Determine as follows:

[0037] T cn =T c -(Φd c -Φd n ) Equation 1

[0038] In Equation 1, T cn is the period of the conversion cycle 220 in counts, T c is the cycle count of the current cycle (the cycle immediately before the frequency and / or phase offset change), Φd c is the phase delay count of the current cycle, and Φd n is the phase delay count of the next frequency or phase offset to which the count is switching. (The period of the sawtooth pattern control counter 214 is equal to the maximum value of the sawtooth pattern control counter 214 minus the minimum value of the sawtooth pattern control counter 214. Figure 2B The minimum value in is zero. )T cn Also known as the "conversion maximum".

[0039] For example, Figure 2B The PWM waveform 218 is relative to Figure 2A The phase delay count of the PWM waveform 206 between T0 and T1 and between T2 and T3 (when the control counter 214 has a frequency F1=F3) is C=500 (0.5×1000) counts. Figure 2B The PWM waveform 218 is relative to Figure 2A The phase delay count of the PWM waveform 206 between T1 and T2 (when the control counter 214 has a frequency F2) is C=200 (0.5×400) counts. Therefore, the duration T of the switching cycle 220 for switching from F1 to F2 at time T1 is cn is 1000-(500-200)=700 counts; and the duration T of the conversion cycle 220 for switching from F2 to F3 at time T2 cnis 400-(200-500)=700 counts. Figure 2B As shown, the resulting transition cycle 220 avoids the discontinuity 124 by aligning the end of the transition cycle with the minimum count in the next frequency, and thus triggering the rising edge threshold 222 and the falling edge threshold 224 appropriately.

[0040] The conversion loop for the sawtooth pattern control counter generated using equation 1 and the conversion loop for the triangle pattern control counter generated using equation 2 (described below with respect to FIG. 6B ) enable discontinuities to be avoided using minimal computational overhead. Equations 1 and 2 may be implemented using software, hardware, or a combination thereof.

[0041] The transition cycle count may not always rise to meet the rising edge threshold and falling edge threshold. Figure 5C (described further below), the transition cycle 534 spanning T2 is too short to trigger either threshold 536, 538. In some embodiments, the falling edge threshold can be adjusted for the transition cycle to maintain the specified duty cycle of the PWM waveform and ensure that the transition cycle meets the rising edge threshold and the falling edge threshold. For example, for a 50% duty cycle, Figure 2B For the switching cycle 220 shown with duration C=700, the falling edge threshold 224 may be adjusted to C=350 (0.5×700) (counts). The adjusted portion 226 of the PWM waveform 218 is indicated by a dashed line.

[0042] Figure 2C An example of a count plot 228 of a PWM control counter 230 over time is shown, along with an example of a timing diagram 232 of a PWM waveform 234 generated using the PWM control counter 230. The count plot 228 and the timing diagram 232 use the same time axis. Figure 2A The control counter 202 is used as a reference to Figure 2C The main control counter of the PWM control counter 230 (see relative Figure 2B Description of the master control counter and slave control counter). Figure 2C The PWM control counter 230 is relative to Figure 2A The control counter 202 is phase-shifted by +90° (25%). (For example, Figure 2C The count of the PWM control counter 230 is Figure 2A The count of the PWM control counter 202 is the same except during a switching cycle spanning a change in frequency or phase delay or during the next subsequent switching cycle of the change.) This means that when the PWM control counter 230 switches from F1 to F2 at time T1, the count of the PWM control counter 230 is phase shifted by +90° (25%; the new phase delay is 100 equals 0.25*400) relative toFigure 2A the count of control counter 202 at time T1. When the frequency of the main (T1 and T2) PWM control counter changes, Figure 2B the (slave) PWM control counter 230 avoids a discontinuity 124 in the count of the (slave) PWM control counter 230 by extending the current cycle of the PWM control counter 230 to generate a transitional cycle 236.

[0043] As shown in Equation 1 above, the period of the transitional cycle 236 is determined. Figure 2C The PWM waveform 234 of Figure 2A relative to the PWM waveform 206 of Figure 2C has a phase delay count between T0 and T1 and between T2 and T3 (when the control counter 230 has a frequency F1 = F3) of C = 250 (0.25 × 1000) counts. Figure 2A The PWM waveform 234 of cn relative to the PWM waveform 206 of cn has a phase delay count between T1 and T2 (when the control counter 230 has a frequency F2) of C = 100 (0.25 × 400) counts. Thus, the duration T of the transitional cycle 236 for switching from F1 to F2 at time T1 Figure 2C is 1000 - (250 - 100) = 850 counts; and the duration T of the transitional cycle 236 for switching from F2 to F3 at time T2 Figure 2C is 400 - (100 - 250) = 550 counts. As Figure 2C shown, the resulting transitional cycle 236 avoids the discontinuity 124 and appropriately triggers the rising edge threshold 238 and the falling edge threshold 240. Additionally, to maintain a 50% duty cycle for the PWM waveform 234, for the transitional cycle 236 with a duration C = 850 counts as

[0044] Figure 3 shown, the falling edge threshold 240 of the transitional cycle 236 spanning T1 can be adjusted to C = 425 (0.5 × 850) counts; and the falling edge threshold 240 of the transitional cycle 236 spanning T2 can be adjusted to C = 275 (0.5 × 550) counts. The adjusted portion 242 of the PWM waveform 234 is shown as a dashed line. (For the PWM control counter 230 in Figure 2BAn example of a block diagram 300 of a device that describes the PWM waveform 218 and uses the PWM waveform 218 to control a device that supplies power to a power stage 302 (such as the primary side of a transformer or other inductor). The control block 304 outputs a control signal to a master control counter generator 308 and a slave control counter generator 306. The control signal controls the period count of the master control counter 202 generated by the master control counter generator 308 and the period count of the (slave) control counter 214 generated by the slave control counter generator 306. The control signal also controls the phase shift of the control counter 214 relative to the master control counter 202. The control block can be, for example, a processor or dedicated hardware. The master control counter generator 308 outputs the master control counter 202 to the slave control counter generator 306. The slave control counter generator 306 uses the master control counter 202 and the control signal to generate the control counter 214 and outputs the control counter 214 to the PWM signal generator 310. The PWM signal generator 310 generates the PWM waveform 218 by generating a signal with a rising edge when the control counter 214 meets the rising edge threshold 222 and generating a signal with a falling edge when the control counter 214 meets the falling edge threshold 224. The PWM signal generator 310 outputs the PWM waveform 218 to the power control switch 312. When the power control switch 312 receives the rising edge and falling edge of the PWM waveform 218, the power control switch 312 closes and opens respectively (and vice versa). The power control switch 312 is connected to the input voltage node (Vin) 314 and the power stage 302 such that when the power control switch 312 is closed, power will be delivered from the input voltage node 314 to the power stage 302.

[0045] Figure 4 An example process 400 is shown for generating a PWM waveform 214 as described with respect to Figure 2B and using the PWM waveform 214 to control a device (such as a switch). In step 402, the control counter 214 is incremented from a minimum count to a maximum count. The difference between the minimum count and the maximum count corresponds to a single count period of the control counter 214. The incrementing of the master control counter 214 is repeated, including during steps 404 and 406. In step 404, if a frequency or phase shift of the count of the control counter 214 occurs, the maximum count of the current period of the slave control counter is made T cn = T c -(Φd c -Φd n )(see Equation 1), where the current period (T c) is equal to the maximum count minus the minimum count. This results in a conversion period 220. In step 406, a PWM waveform 218 is generated using a control counter 214 by generating rising and falling edges based on a rising edge threshold 222 and a falling edge threshold 224. Similarly, the rising edge threshold 222 and the falling edge threshold 224 of the conversion period 220 are adjusted to maintain the duty cycle of the PWM waveform 218. In step 408, the generated PWM waveform 218 is used to control the opening and closing of a switch (e.g., Figure 3 's power control switch 312).

[0046] Figure 5A An example of a count plot 500 of a PWM control counter 502 over time and an example of a timing diagram 504 of a PWM waveform 506 generated using the PWM control counter 502 are shown. The count plot 500 and the timing diagram 504 use the same time axis. As Figure 5A shown, the PWM control counter 502 is compared with two thresholds, a rising edge threshold 508 and a falling edge threshold 510, to generate rising and falling edges (respectively) in the PWM waveform 506. The rising edge threshold 508 corresponds to the maximum count of the PWM control counter 502, which corresponds to the desired frequency of the PWM waveform 506, and the falling edge threshold 510 corresponds to half (1 / 2) (50% duty cycle) of the maximum count of the PWM control counter 502. The control counter 502 has a frequency F1, corresponding to a maximum count of C = 1000 counts.

[0047] FIG. 5B shows an example of the prior art of a count plot 512 of a PWM control counter 514 over time and an example of a timing diagram 516 of a PWM waveform 518 generated using the PWM control counter 514. The count plot 512 and the timing diagram 516 use the same time axis. Figure 5A The PWM control counter 502 of Figure 2B is used as the master control counter for the PWM control counter 514 of FIG. 5B (see Figure 5A the description of the master control counter and the slave control counter; the count (except during the period spanning a change in frequency or phase delay or during the next subsequent period after said change), frequency, and threshold values of the PWM control counter 514 of FIG. 5B are the same as Figure 5A the count, frequency, and threshold values of the PWM control counter 502 of Figure 5AThe count of the PWM control counter 502 at time T1 changes from a phase shift of +90° (25%) to a phase shift of +270° (75%). This also means that at time T2, the count of the PWM control counter 514 is relative to Figure 5A The count of the control counter 502 at time T1 changes from a phase shift of +270° (75%) to a phase shift of +90° (25%). The control counter 514 does not use a conversion loop.

[0048] When the PWM control counter 514 (relative to Figure 5A the PWM control counter 502) changes from a phase shift of +90° to a phase shift of +270° at time T1, in order to maintain the new phase shift, the count changes from the count corresponding to the previous phase shift (C = 750) to the count corresponding to the new phase shift (C = 250). (A similar change in the count from C = 250 to C = 750 occurs at time T2 when there is a phase shift conversion in the PWM control counter 514.) As a result, when changing from +90° to +270°, the falling edge threshold 520 is not reached at time T1 because the count of the control counter 514 jumps from 749 to 250 at time T1. Therefore, at time T1, when the PWM control counter 514 would reach the falling edge threshold 520 without a phase shift change, the PWM control counter 514 does not increment to the falling edge threshold 520, and no falling edge is triggered in the PWM waveform 518 at time T1. Similarly, at time T2, when the PWM control counter 514 would reach the rising edge threshold 522 without a phase shift change, the PWM control counter 514 does not increment to (but jumps to) the rising edge threshold 522, and no rising edge is triggered in the PWM waveform 518 at time T2. Therefore, the PWM waveform 518 cycle is erroneously extended. For example, the timing diagram 516 shows an error 524 that satisfies the rising edge threshold 522, but the PWM waveform 518 is already higher due to the discontinuity 124 in the PWM control counter 514 (no falling edge threshold 520 at time T2).

[0049] Figure 5C An example of a count plot 526 of the PWM control counter 528 over time is shown, as well as an example of a timing diagram 530 of a PWM waveform 532 generated using the PWM control counter 528. The count plot 526 and the timing diagram 530 use the same time axis. Figure 5A The PWM control counter 502 of Figure 5C is used as the master control counter for the PWM control counter 528 of Figure 2B (see the description of the master control counter and the slave control counter regarding Figure 5Cthe count of the PWM control counter 528 (except during a cycle across a change in frequency or phase delay or during the next subsequent cycle after said change), the frequency, and the threshold value are the same as Figure 5A the count, frequency, and threshold value of the PWM control counter 502). Figure 5C The PWM control counter 528 of Figure 5A is phase shifted by +90° (25%) relative to the PWM control counter 502 of Figure 5C during times T0 to T1 and T2 to T3, and by +270° (75%) during time T1 to T2 (similar to that described with respect to Figure 5B). At the phase change (T1 and T2),

[0050] Figure 5C the period of the transitional cycle 534 in Figure 5C The PWM waveform 532 of Figure 5A has a phase delay count of C = 250 (0.25 × 1000) counts relative to the PWM waveform 506 of Figure 5C between T0 and T1 and between T2 and T3 (when the PWM control counter 528 is phase shifted by +90°). Figure 5A The PWM waveform 532 of cn has a phase delay count of C = 750 (0.75 × 1000) counts relative to the PWM waveform 506 of cn between T1 and T2 (when the control counter 528 has a phase shift of +270° relative to the (primary) PWM control counter 502). Thus, the duration T of the transitional cycle 534 for switching from a phase shift of +90° to a phase shift of +270° at time T1 Figure 5CAs shown, the resulting conversion cycle 534 avoids discontinuities 124 and appropriately triggers the rising edge threshold 536 and the falling edge threshold 538. Additionally, to maintain a 50% duty cycle for the PWM waveform 532, the falling edge threshold 538 of the conversion cycle 534 with a duration of C = 1500 counts across T1 can be adjusted to C = 750 (0.5 × 1500) counts; and the falling edge threshold 538 of the conversion cycle 534 with a duration C = 500 counts across T2 can be adjusted to C = 250 (0.5 × 500) counts. The adjusted portion 540 of the PWM waveform 532 is indicated by a dashed line.

[0051] Figure 6A An example of a count plot 600 of the PWM control counter 602 over time and an example of a timing diagram 604 of the PWM waveform 606 generated using the PWM control counter 602 are shown. The count plot 600 and the timing diagram 604 use the same time axis. Figure 6A The PWM control counter 602 of increases upward to a maximum value (increments) and then counts downward to zero (decrements), thus producing a triangular pattern in the count plot 600. The PWM control counter 602 is compared with two thresholds, the rising edge threshold 608 and the falling edge threshold 610 (in Figures 6A to 7C the example shown, the rising edge threshold is the same as the falling edge threshold), to produce a rising edge and a falling edge, respectively, in the PWM waveform 606. The rising edge threshold 608 and the falling edge threshold 610 correspond to the desired frequency of the PWM waveform 606. Both the rising edge threshold 608 and the falling edge threshold 610 are equal to C = 500 counts. The maximum count of the PWM control counter 602 is C = 1000 counts, corresponding to a total PWM control counter 602 period of C = 2000 counts.

[0052] Figure 6B shows an example of a count plot 612 of the PWM control counter 614 over time and an example of a timing diagram 616 of the PWM waveform 618 generated using the PWM control counter 614. The count plot 612 and the timing diagram 616 use the same time axis. Figure 6A The PWM control counter 602 of is used as the master control counter for the (slave) PWM control counter 614 with respect to Figure 6B (see the description of the master control counter and the slave control counter regarding Figure 2B ; the counts, frequencies, and threshold values of the PWM control counter 602 of Figure 6B (except during the period across a change in frequency or phase delay or during the next subsequent period after the change) are the same as the counts, frequencies, and threshold values of the Figure 6A PWM control counter 614. The PWM control counter 614 of Figure 6B is relative to Figure 6AThe PWM control counter 602 has a phase shift of +225° (62.5%) during times T0 to T1 and T2 to T3, and a phase shift of +315° (87.5%) during time T1 to T2. The PWM control counter 614 does not use a conversion loop.

[0053] The PWM control counter 614 shows discontinuities 124 at times T1 (where the count jumps from C = 749 to C = 250) and T2 (where the count jumps from C = 249 to C = 750), which causes the PWM control counter 614 to delay in meeting the rising edge threshold 620 after T1 and skip the rising edge threshold 620 at T2. The skipped rising edge threshold 620 results in an error 624 in the PWM waveform 618, and the PWM waveform 618 is not affected by subsequent falling edges, resulting in another error 624. This means that the PWM waveform 618 skips an entire cycle due to the discontinuity 124 at T2. (There is also a falling edge threshold 622.)

[0054] Figure 6C An example of a count plot 626 of the PWM control counter 628 over time is shown, as well as an example of a timing diagram 630 of the PWM waveform 632 generated using the PWM control counter 628. The count plot 626 and the timing diagram 630 have the same time axis. Figure 6A The PWM control counter 602 serves as the master control counter for the (slave) PWM control counter 628 with respect to Figure 6C (See the description of the master control counter and slave control counter with respect to Figure 2B ; the count (except during a cycle spanning a change in frequency or phase delay or during the next subsequent cycle after said change), frequency, and threshold values of the PWM control counter 628 of Figure 6C are the same as the count, frequency, and threshold values of the PWM control counter 602 of Figure 6A . Figure 6C The PWM control counter 628 of Figure 6A has a phase shift of +225° (62.5%) during times T0 to T1 and T2 to T3 with respect to the PWM control counter 602 of

[0055] Figure 6C The triangular pattern of

[0056]

[0057] For Figure 6C and 7C the triangular pattern, T cnRepresents the maximum value minus the minimum value of the PWM control counter 628 before the change in the frequency or phase shift spanned by the transition cycle 634. The maximum value minus the minimum value of the PWM control counter 628 is equal to half of the period of the (triangular pattern) PWM control counter 628. Figure 6C of the PWM waveform 632 relative to Figure 6A the PWM waveform 606 between T0 and T1 and between T2 and T3 has a phase delay count (when the PWM control counter 628 has a phase shift of +225°) of C = 1250 (0.625 × 2000) counts. Figure 6C of the PWM waveform 632 relative to Figure 6A the PWM waveform 606 between T1 and T2 has a phase delay count (when the control counter 628 has a phase shift of +315° relative to the (main) PWM control counter 602) of C = 1750 (0.875 × 2000) counts. Thus, the maximum value T of the transition cycle 634 for switching from a phase shift of +225° to a phase shift of +315° at time T1 cn is (the duration is 2*T cn = 2500) counts; and the maximum value T of the transition cycle 634 for switching from a phase shift of +315° to a phase shift of +225° at time T2 cn is (the duration is 2*T cn = 1500) counts. The resulting transition cycle 634 avoids discontinuity 124 and appropriately triggers the rising edge threshold 636 and the falling edge threshold 638. In addition, in order to maintain a 50% duty cycle of the PWM waveform 632, the rising edge threshold 636 and the falling edge threshold 638 of the transition cycle 634 spanning the maximum value C = 1250 counts at T1 can be adjusted to C = 625 (0.5 × 1250) counts; and the rising edge threshold 636 and the falling edge threshold 638 of the transition cycle 634 spanning the maximum value C = 750 counts at T2 can be adjusted to C = 325 (0.5 × 750) counts. Thus, in order to maintain the duty cycle of the pulse width modulation waveform generated using the sawtooth pattern control counter, the rising edge threshold and the falling edge threshold of the transition cycle can be set to the maximum value T of the transition cycle cn multiplied by the duty cycle. The adjusted portion 640 of the PWM waveform 632 is shown in dashed lines.

[0058] Figure 7A Shows an example of a count plot 700 of the PWM control counter 702 over time, and an example of a timing diagram 704 of the PWM waveform 706 generated using the PWM control counter 702. The count plot 700 and the timing diagram 704 use the same time axis. Figure 7AThe PWM control counter 702 counts up to a maximum value and then counts down to zero, thereby generating a triangular pattern in the count plot 700. Both the rising edge threshold 708 and the falling edge threshold 710 are equal to C = 500 counts. The maximum count of the PWM control counter 702 is C = 1000 counts, corresponding to a total PWM control counter 702 period of C = 2000 counts.

[0059] FIG. 7B shows an example of a prior art count plot 712 of a PWM control counter 714 over time, and an example of a timing diagram 716 of a PWM waveform 718 generated using the PWM control counter 714. The count plot 712 and the timing diagram 716 use the same time axis. Figure 7A The PWM control counter 702 serves as the master control counter for the (slave) PWM control counter 714 with respect to FIG. 7B (see the description of the master control counter and slave control counter; the count (except during the period straddling a change in frequency or phase delay or in the next subsequent period after said change), frequency, and threshold values of the PWM control counter 702 in FIG. 7B are the same as Figure 2B the count, frequency, and threshold values of the PWM control counter 714). The PWM control counter 714 in FIG. 7B is phase shifted by +225° (62.5%) during times T0 to T1 and T2 to T3 with respect to Figure 7A the PWM control counter 702, and is phase shifted by +45° (12.5%) during time T1 to T2. The PWM control counter 714 does not use a conversion cycle. Figure 7A The PWM control counter 714 shows a discontinuity 124 at time T1, where the count jumps from C = 749 when increasing to C = 250 when decreasing, and at time T2, the count jumps from C = 251 when decreasing to C = 750 when increasing. This results in a PWM half-cycle (a high PWM signal spanning T1 and a low PWM signal spanning T2), which lasts for a full PWM control counter 714 period. The error 720 shown in the timing diagram 716 corresponds to the skipped rising edge threshold 722 and the skipped falling edge threshold 724.

[0060]

[0061] Figure 7C Figure 7A FIG. shows an example of a count plot 726 of a PWM control counter 728 over time, and an example of a timing diagram 730 of a PWM waveform 732 generated using the PWM control counter 728. The count plot 726 and the timing diagram 730 use the same time axis. Figure 7A The PWM control counter 702 serves as the master control counter for Figure 7C the (slave) PWM control counter 728 with respect to Figure 2BDescription of the main control counter and the slave control counter;

[0062] Figure 7C The count of the PWM control counter 728 (except during the period of crossing the change in frequency or phase delay or during the next subsequent period of said change), the values of the frequency and the threshold are the same as Figure 7A the count, frequency and threshold values of the PWM control counter 702 of Figure 7C The PWM control counter 728 of Figure 7A The PWM control counter 702 of has a phase shift of +225° (62.5%) during times T0 to T1 and T2 to T3, and a phase shift of +45° (12.5%) during times T1 to T2.

[0063] As Figure 7C shown, when the phase delay count is less than the maximum count value of the triangular pattern control counter (a control counter that increments from zero to the maximum value and then decrements from the maximum value to zero), for the purposes of the calculations herein, twice the maximum value is added to the phase delay count. Figure 7C The PWM waveform 732 of Figure 7A The PWM waveform 706 of has a phase delay count of C = 1250 (0.625 × 2000) counts between T0 and T1 and between T2 and T3 (when the PWM control counter 728 has a phase shift of +225°). Figure 7C The PWM waveform 732 of Figure 7A The PWM waveform 706 of has a phase delay count (when the control counter 728 has a phase shift of +45° relative to the main control counter 702) between T1 and T2 of C = 2250 (0.125 × 2000 + 2000) counts. (The phase delay count between T1 and T2 is 250, which is less than the maximum count C = 1000; therefore, for calculation purposes, the phase delay count between T1 and T2 is considered C = 250 + 1000 * 2 = 2250.) Thus, the maximum value T of the transition cycle 734 for switching from a phase shift of +225° to a phase shift of +45° at time T1 cn is (the duration is 2 * T cn = 3000) counts; and the maximum value T of the transition cycle 734 for switching from a phase shift of +45° to a phase shift of +225° at time T2 cn is (the duration is 2 * T cnCounting is done up to (say, = 1500). However, since the transitional cycle 734 does not change the period of the cycle spanning time T2 (when the phase delay count changes at time T2, the count of the period of the cycle spanning time T2 decreases), the transitional cycle is the next subsequent cycle to time T2 (for the nth cycle, the next subsequent cycle is the (n + 1)th cycle) - and thus the cycle after the frequency change or the phase delay count change. The resulting transitional cycle 734 avoids discontinuity 124 and appropriately triggers the rising edge threshold 736 and the falling edge threshold 738. Additionally, to maintain a 50% duty cycle for the PWM waveform 732, the rising edge threshold 736 and the falling edge threshold 738 of the transitional cycle 734 with a maximum count of C = 1500 across T1 can be adjusted to C = 750 (0.5 × 1500) counts; and the rising edge threshold 736 and the falling edge threshold 738 of the transitional cycle 734 with a maximum count of C = 500 after T2 can be adjusted to C = 250 (0.5 × 500) counts. The adjusted portion 740 of the PWM waveform 732 is shown as a dashed line.

[0064] Figure 8A An example of a count plot 800 of the PWM control counter 802 over time is shown, as well as an example of a timing diagram 804 of a PWM waveform 806 generated using the PWM control counter 802. The count plot 800 and the timing diagram 804 use the same time axis. Figure 8A The PWM control counter 802 counts down from a maximum value to zero, resulting in a reverse sawtooth pattern in the count plot 800. The first desired frequency F1 specified for time T0 to time T1 corresponds to a maximum count of C = 1000 counts; the second desired frequency F2 specified for time T1 to time T2 corresponds to a maximum count of C = 400 counts; and the third desired frequency F3 specified for time T2 to time T3 corresponds to a maximum count of C = 1000 (i.e., in this example F1 = F3). The rising edge threshold 808 for frequencies F1 and F3 is C = 1000 counts, and the falling edge threshold 810 for frequencies F1 and F3 is equal to C = 500 counts. The rising edge threshold 808 for frequency F2 is C = 400 counts, and the falling edge threshold for frequency F2 is C = 200 counts.

[0065] Figure 8B shows an example of a prior art count plot 812 of a PWM control counter 814 over time, as well as an example of a timing diagram 816 of a PWM waveform 818 generated using the PWM control counter 814. The count plot 812 and the timing diagram 816 use the same time axis. Figure 8A The PWM control counter 802 of... is used as the master control counter for the (slave) PWM control counter 814 with respect to Figure 8B (see regarding Figure 2BDescription of the main control counter and the slave control counter; the count (except during the period of change across the frequency or phase delay or during the next subsequent period after said change), frequency, and threshold values of the PWM control counter 814 in FIG. 8B are the same as Figure 8A the count, frequency, and threshold values of the PWM control counter 802 of Figure 8A . The PWM control counter 814 in FIG. 8B is phase-shifted by +180° (50%) with respect to

[0066] the PWM control counter 802 of

[0067] Figure 8C The PWM control counter 814 shows a discontinuity 124 at time T1, where the count jumps from C = 501 to C = 200, and at time T2, the count jumps from C = 201 to C = 500. The previous cycle does not trigger the corresponding threshold because the count does not properly decrement to the threshold, and the latter cycle does not trigger the corresponding threshold until the old threshold is reached later in the cycle (it does not change until the end of the cycle). This results in a PWM half-cycle (the high PWM signal across T1 and the high PWM signal across T2), which lasts for a full or nearly full period of the PWM control counter 814. The error 820 shown in the timing diagram 816 corresponds to the skipped rising-edge threshold 822 and / or the skipped falling-edge threshold 824, and generates an incorrect portion 826 of the PWM waveform 818. Figure 8A The PWM control counter 802 of Figure 8C is used as the main control counter for the (slave) PWM control counter 830 of Figure 2B (see the description of the main control counter and the slave control counter of Figure 8C . The count (except during the period of change across the frequency or phase delay or during the next subsequent period after said change), frequency, and threshold values of the PWM control counter 830 of Figure 8A are the same as the count, frequency, and threshold values of the PWM control counter 802 of Figure 8C . The PWM control counter 830 of Figure 8A is phase-shifted by +180° (50%) with respect to the PWM control counter 802 of Figure 8CThe PWM control counter 830 avoids discontinuity 124 in the counting of the PWM control counter 830 by extending the current cycle of the PWM control counter 830 to generate a transitional cycle 836.

[0068] As shown in Equation 1, determine Figure 8C the period of the transitional cycle 836 therein. Figure 8C The PWM waveform 834 of Figure 8A relative to the PWM waveform 806 of Figure 8C The phase delay count between T0 and T1 and between T2 and T3 (when the maximum count of the PWM control counter 830 is C = 1000 counts) is C = 500 (0.5 × 1000) counts. Figure 8A The phase delay count of the PWM waveform 834 of cn relative to the PWM waveform 806 of cn between T1 and T2 (when the maximum count of the control counter 830 is C = 400 counts) is C = 200 (0.5 × 400) counts. Therefore, the duration T of the transitional cycle 836 for switching from the maximum count C = 1000 to the maximum count C = 400 at time T1 with a phase shift of +180° Figure 8C is 1000 - (500 - 200) = 700 counts; and the duration T of the transitional cycle 836 for switching from the maximum count C = 400 to the maximum count C = 1000 at time T2 with a phase shift of +180°

[0069] Within the scope of the claims, modifications can be made in the embodiments, and there may be other embodiments.

[0070] In some embodiments, the threshold changes at times other than when a frequency change or a phase shift change occurs.

[0071] In some embodiments using a triangular pattern, the rising edge threshold and the falling edge threshold of one cycle are different.

[0072] In some embodiments, a PWM waveform is used to control a device in response to duty cycle-based and oscillation-based control, such as a switch that controls power delivery to a power stage.

[0073] In some embodiments, a falling edge threshold may be located at a maximum count value of a sawtooth pattern or reverse sawtooth pattern counter.

[0074] In the embodiments described herein, a specific duty cycle is involved. In some embodiments, different duty cycles may be used.

[0075] In some embodiments, power may be delivered to a load when the switch is off, and power delivery to the load may be prevented when the switch is on.

[0076] The embodiments shown herein use a square wave PWM waveform. In some embodiments, other cyclic signals that can maintain a phase relationship between (or among) them may be used to form a PWM waveform corresponding to a master control counter and a slave control counter.

[0077] For the purposes of the above calculations, the minimum count values of the master control counter and the slave control counter are considered zero herein, but in some embodiments, other minimum count values may be used. For example, negative count values or count values greater than zero may be used. In embodiments where the minimum count value is not zero, the count may be made equal to a count with a zero minimum by subtracting the non-zero minimum count value from the count and by subtracting the non-zero minimum count value from the maximum count value.

[0078] Embodiments that increment and decrement the master control counter and / or the slave control counter by a value other than one (e.g., a fraction or an integer greater than one) are generally equivalent to control counters that increment and decrement by one (and thus the counts of these embodiments are proportional to control counters that increment and decrement by one). Thus, for all calculations described herein, control counters that are considered to increment and decrement by a value other than one are rescaled accordingly to increment and decrement by one.

Claims

1. A method for generating a Pulse Width Modulation (PWM) signal, comprising: During a first time period: Counting a main control counter, the main control counter having a first maximum value during the first time period; And Counting a slave control counter, the slave control counter having the first maximum value, the slave control counter having a first phase delay relative to the main control counter during the first time period; During a second time period: Counting the main control counter, the main control counter having a second maximum value during the second time period; And Counting the slave control counter, the slave control counter having the second maximum value during the second time period, the slave control counter having a second phase delay relative to the main control counter during the second time period; And During a transition period between the first time period and the second time period, counting the slave control counter, the slave control counter having a third maximum value during the transition time period, the third maximum value being different from the first maximum value and the second maximum value, the slave control counter completing at least one cycle during the transition period.

2. The method according to claim 1, wherein counting the main control counter during the first time period includes incrementing the main control counter from a minimum value to the first maximum value.

3. The method according to claim 1, wherein counting the main control counter during the first time period includes decrementing the main control counter from the first maximum value to the minimum value.

4. The method according to claim 1, wherein counting the main control counter during the first time period includes incrementing the main control counter from a minimum value to the first maximum value and decrementing the main control counter from the first maximum value to the minimum value.

5. The method according to claim 1, wherein the period of the slave control counter during the conversion time period (T cn ) is set to: T cn = T c -(Φd c -Φd n ) where T c is the period of the main control counter during the first time period, Φd c is the first phase delay, and Φd n is the second phase delay.

6. The method according to claim 1, wherein the period of the slave control counter during the conversion time period (T cn ) is set to: where T c is the period of the main control counter during the first time period, Φd c is the first phase delay, and Φd n is the second phase delay.

7. The method according to claim 1, wherein the third maximum value is between the first maximum value and the second maximum value.

8. The method according to claim 1, wherein the third maximum value is greater than the first maximum value and the second maximum value.

9. The method according to claim 1, wherein the third maximum value is less than the first maximum value and the second maximum value.

10. A circuit for generating a Pulse Width Modulation (PWM) signal, comprising: A main control counter configured to: During a first time period, perform main control counting on the main control counter having a first maximum value during the first time period; And During a second time period, perform main control counting on the main control counter having a second maximum value during the second time period; And A slave control counter coupled to the main control counter, the slave control counter being configured to: During the first time period, slave control counting is performed on the slave control counter having the first maximum value, and the slave control counter has a first phase delay relative to the master control counter during the first time period; During the second time period, slave control counting is performed on the slave control counter having the second maximum value during the second time period, and the slave control counter has a second phase delay relative to the master control counter during the second time period; and During a transition time period between the first time period and the second time period, slave control counting is performed on the slave control counter having a third maximum value during the transition time period, the third maximum value being different from the first maximum value and the second maximum value, and the slave control counter completes at least one cycle during the transition time period.

11. The circuit according to claim 10, wherein counting the master control counter during the first time period includes incrementing the master control counter from a minimum value to the first maximum value.

12. The circuit according to claim 10, wherein counting the master control counter during the first time period includes decrementing the master control counter from the first maximum value to a minimum value.

13. The circuit according to claim 10, wherein counting the master control counter during the first time period includes incrementing the master control counter from a minimum value to the first maximum value and decrementing the master control counter from the first maximum value to the minimum value.

14. The circuit according to claim 10, wherein the period of the slave control counter during the conversion time period (T cn ) is set to: T cn = T c -(Φd c - Φd n ) where T c is the period of the main control counter during the first time period, Φd c is the first phase delay, and Φd n is the second phase delay.

15. The circuit according to claim 10, wherein a period of the slave control counter during the conversion time period (T cn ) is set to: where T c is the period of the main control counter during the first time period, Φd c is the first phase delay, and Φd n is the second phase delay.

16. The circuit according to claim 10, wherein the third maximum value is between the first maximum value and the second maximum value.

17. The circuit according to claim 10, wherein the third maximum value is greater than the first maximum value and the second maximum value.

18. The circuit according to claim 10, wherein the third maximum value is less than the first maximum value and the second maximum value.

19. An apparatus, comprising: A master control counter configured to: During a first time period, perform master control counting on the master control counter having a first maximum value during the first time period; and During a second time period, perform master control counting on the master control counter having a second maximum value during the second time period; and A slave control counter coupled to the master control counter, the slave control counter being configured to: During the first time period, perform slave control counting on the slave control counter having the first maximum value, and the slave control counter has a first phase delay relative to the master control counter during the first time period; During the second time period, perform slave control counting on the slave control counter having the second maximum value during the second time period, and the slave control counter has a second phase delay relative to the master control counter during the second time period; and During a transition time period between the first time period and the second time period, slave control counting is performed on the slave control counter having a third maximum value during the transition time period, the third maximum value being different from the first maximum value and the second maximum value, and the slave control counter completes at least one cycle during the transition time period; and a pulse width modulation (PWM) signal generator coupled to the slave control counter, the PWM signal generator being configured to generate a PWM waveform based on the slave control counter.

20. The apparatus according to claim 19, further comprising a power control switch coupled to the PWM signal generator, the power control switch being configured to operate based on the PWM waveform.

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