Coupled-Inductor Cascade Buck Converter with Fast Transient Response

Abstract

The present invention provides a cascade buck converter for receiving an input voltage (Vin) from an input voltage source (101) and for delivering an output voltage (Vo) to a load (110). The converter comprises: a first inductor (104); a second inductor (108); a coupled inductor (300, 301, 302) having a first winding (301) connected in series with the first inductor and a second winding (302) connected in series with the second inductor; an intermediate decoupling capacitor (105) for receiving energy from the first inductor and the first winding and for supplying energy to the second inductor and the second winding; and an output decoupling capacitor (109) for smoothing the output voltage at the load.

Description

[0001] Cross-references to related patent applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 643,558, filed on March 15, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to power topology circuits, and more particularly to coupled inductor cascade buck converters with fast transient response. Background Art

[0004] The increase in energy consumption in data centers requires improvements in power efficiency. In many markets such as telecommunications, industry, aerospace, and server environments, this requirement has triggered the development of power topologies that can convert power from 48V directly to the point-of-load (PoL) voltage. One attempted solution is the use of a resonant / non-resonant half-bridge / full-bridge plus a current multiplier based on a transformer. Another attempted solution is the use of a buck converter. Non-isolated buck converters have attracted the most attention for this application due to their inherent high efficiency and fast transient response. However, high buck voltage conversion rates mean very low duty cycles, which are difficult to achieve in single-stage buck converters. To overcome this problem, the industry uses emerging gallium nitride (GaN) field effect transistor technology that can have nanosecond switching times. Alternatively, a cascaded buck converter is used to generate an intermediate bus voltage and maintain a reasonable duty cycle that can be achieved using a silicon metal oxide semiconductor field effect transistor (MOSFET).

[0005] Both of the above solutions suffer from the problem of load release transients in the output voltage. In fact, due to the very low output voltage, the achievable current slew rate in the output filter inductor is low, i.e. -Vo / L. Therefore, the output capacitor needs to absorb a very large access charge, and a large output capacitor is required to prevent the output voltage from overshooting.

[0006] FIG. 1 shows a prior art cascade buck converter, which receives an input supply voltage V from an input source 101. IN The input supply voltage is converted to a low output voltage Vo at the load 110. The cascade converter includes an input buck converter stage and an output buck converter stage, wherein the input buck converter stage includes a first high-side switch 102, a first low-side switch 103, a first inductor 104 and an intermediate decoupling capacitor 105, and the output buck converter stage includes a second high-side switch 106, a second low-side switch 107, a second inductor 108 and an output decoupling capacitor 109. The intermediate decoupling capacitor 105 generates an intermediate bus voltage V cThe first high-side switch 102 and the first low-side switch 103 receive gate drive signals G1 and The second high-side switch 106 and the second low-side switch 107 receive the gate drive signal G2 and The first inductor 104 and the second inductor 108 conduct currents I1 and I2, respectively. The output load 110 conducts an output current I o .

[0007] FIG2 shows exemplary waveforms illustrating the prior art converter of FIG1, which operates in a constant on-time (COT) mode, without limiting the generality of the defects it suffers in other control modes. The two buck converter stages operate synchronously, and waveforms 201 and 202 represent gate drive signals G1 and G2, respectively.

[0008] Waveforms 203, 204 and 205 depict currents I2, I1 and Io, respectively. The step in current 203 leaves residual energy in the second inductor 108 that needs to be absorbed by the output decoupling capacitor 109. As shown in FIG. 2, the converter of FIG. 1 operates at a small duty cycle (i.e., ) and according to Therefore, the falling slope conversion rate dl2 / dt = -V o / L2 ratio rising slope dl2 / dt=(V c -V o ) / L2 is much slower. Therefore, the load release transient of the output current Io leaves an asymmetrically large excess charge 207 in the second inductor 108. This charge 207 causes the output voltage V seen in waveform 206 to o The cascaded buck converters shown in Figures 1 and 2 operate at a high step-down voltage ratio, resulting in an asymmetrical and poor response to the load release transient.

[0009] When current 203 is boosted, similar behavior results in an undershoot of voltage 206. However, due to the faster rising slope of current 204, this problem is less severe.

[0010] Therefore, new power topologies and new control methods that can respond faster to the load release transient of 48V to PoL conversion are needed. Summary of the invention

[0011] According to one aspect of the present disclosure, a cascade buck converter for receiving an input voltage from an input voltage source and for delivering an output voltage to a load is provided. The converter includes: a first inductor; a second inductor; a coupled inductor having a first winding connected in series with the first inductor and a second winding connected in series with the second inductor; an intermediate decoupling capacitor for receiving energy from the first inductor and the first winding and for supplying energy to the second inductor and the second winding; and an output decoupling capacitor for smoothing the output voltage at the load. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A more complete understanding of the embodiments of the present disclosure and attendant advantages and features thereof will be more readily appreciated by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0013] FIG1 is a circuit diagram of a cascade buck converter in the prior art;

[0014] FIG2 is a waveform diagram showing waveforms of the prior art converter of FIG1;

[0015] Figure 3 is a circuit diagram of a cascade buck converter according to an embodiment of the present disclosure;

[0016] Figure 4 To show Figure 3 Waveform diagram of the waveform of the cascaded buck converter;

[0017] Figure 5 A circuit diagram showing an alternative embodiment of a cascaded buck converter of the present disclosure; and

[0018] Figure 6 To show Figure 3 Figure 2 is a waveform diagram of the waveform of the cascaded buck converter. DETAILED DESCRIPTION

[0019] Figure 3 The cascaded buck converter of the present disclosure is depicted, wherein a coupled inductor 300 is added to the circuit, wherein the coupled inductor 300 includes an input winding 301 and an output winding 302, with a turns ratio n and a coupling coefficient k≈1 between the input winding 301 and the output winding 302. The windings 301 and 302 are connected in series corresponding to the first inductor 104 and the second inductor 108, and the two windings are connected with the same polarity facing the load 110. In order to avoid excessive ripple steering, n≈1 / d is selected. The output voltage V o Exceeding the threshold voltage V ON When a control pulse is applied at G1 ( Figure 4 As shown), and G2=0.

[0020] According to an embodiment of the present disclosure, the first high-side switch 102 is configured to energize the first inductor 104 and the first winding (i.e., the input winding 301) from the input voltage source 101. The first low-side switch 103 is configured to de-energize the first inductor 104 and the first winding 301 by connecting the first inductor 104 and the first winding 301 across the intermediate decoupling capacitor 105. The second high-side switch 106 is configured to energize the second inductor 108 and the second winding 302 by connecting the second inductor 108 and the second winding 302 across the output decoupling capacitor 109. The second low-side switch 107 is configured to de-energize the second inductor and the second winding by connecting the second inductor 108 and the second winding 302 across the output decoupling capacitor 109. The first high-side switch 102 and the second high-side switch 106 are substantially synchronously activated, and the first low-side switch 103 and the second low-side switch 107 are substantially synchronously activated.

[0021] Figure 4 Shows Figure 3 . Referring to waveform 201, the first high-side switch 102 provides a gate signal that generates a pulse 400 after the load release step in 203. Pulse 400 turns on the first high-side switch 102 and turns off the first low-side switch 103. Under this condition, a voltage V2 of negative polarity appears across the second inductor 108. Without loss of generality, for simplicity, it can be assumed that L2 = L1 / n 2 =L s , where L1 is the inductance of the first inductor 104, and L2 is the inductance of the second inductor 108. Then, solve for the voltage across the second inductor 108:

[0022]

[0023] Where V g =(V IN -V c ) / n,Z s =sL s , and Z m =sL m Here, L m is the inductance of the output winding 302. The voltage V2 can be significantly greater than V o , and current 204 begins to slew downward at a much greater rate (i.e., -V2 / L2). Therefore, current 205 slews at a rate [V IN -V c-n (V2-V o )] / L1 increases. Current I2 (such as Figure 3 ) becomes quickly transferred to the input winding 301, and the excess charge 207 delivered to the output decoupling capacitor 109 becomes minimal.

[0024] Therefore, the load release overshoot in the output voltage 206 is reduced. The excess energy stored in the first inductor 104 and the coupled inductor 300 is further absorbed by the intermediate decoupling capacitor 105. c (like Figure 3 The corresponding overshoot in the regulated output voltage V o The control loop further rejects the V o The impact is minimal.

[0025] Figure 4 It also shows Figure 3 The gate drive signal is activated so that the output voltage V o Exceeding the threshold V ON When V o drops below the threshold V OFF (This threshold is equal to or lower than V ON ), the pulse 400 ends. Therefore, it can be said that the current 204 reverses its direction at the end of the pulse 400, and the output voltage V o V OFF The best choice is to quickly stabilize near its programmed value. o When the first threshold is exceeded, the first high-side switch 102 and the second low-side switch 107 are activated concurrently. o When the voltage drops below the second threshold, the first high-side switch 102 is deactivated.

[0026] Figure 5 Another embodiment of the present disclosure is shown, in which the coupling coefficient k between the input winding 301 and the output winding 302 of the coupled inductor 300 is less than 1. The resulting leakage inductance of the windings 301 and 302 is used as Figure 3 The first inductor 104 and the second inductor 108 of the converter. Those skilled in the art will understand that Figure 3 and Figure 5 The converters are two extreme implementations of the preferred embodiment, and a practical design may utilize the coupled inductor 300 and the leakage inductances of the first inductor 104 and the second inductor 108 .

[0027] In one embodiment, first inductor 104 is partially contributed by the leakage inductance of input winding 301 of coupled inductor 300. In one embodiment, first inductor 104 is completely contributed by the leakage inductance of input winding 301 of coupled inductor 300. In another embodiment, second inductor 108 is partially contributed by the leakage inductance of second winding 302 of coupled inductor 300. In another embodiment, second inductor 108 is completely contributed by the leakage inductance of second winding 302 of coupled inductor 300.

[0028] Wherever applicable, the disclosed apparatus and method may be applied in the opposite case, i.e., to speed up the positive load step response and reduce the corresponding undershoot. Figure 6 205. In this embodiment, gate signal G1 generates a turn-off pulse 600 after a load step, resulting in a rapid increase in current 204 and a corresponding rapid decrease in current 205. In this embodiment, when output voltage V o When the output voltage V o When the fourth threshold is exceeded, the first low-side switch 103 is deactivated.

[0029] In one embodiment, a cascade buck converter for receiving an input voltage from an input voltage source and for delivering an output voltage to a load is provided. The converter includes: a first inductor 104; a second inductor 108; a coupled inductor 300 having a first winding 301 connected in series with the first inductor 104 and a second winding 302 connected in series with the second inductor 108; an intermediate decoupling capacitor 105 for receiving energy from the first inductor 104 and the first winding 301 and for supplying energy to the second inductor 108 and the second winding 302; and an output decoupling capacitor 109 for smoothing the output voltage at the load 110.

[0030] In one embodiment, the cascade buck converter further includes: a first high-side switch 102 for energizing the first inductor 104 and the first winding 301 from the input voltage source 101; a first low-side switch 103 for de-energizing the first inductor 104 and the first winding 301 by connecting the first inductor 104 and the first winding 301 across an intermediate decoupling capacitor 105; a second high-side switch 106 for energizing the second inductor 108 and the second winding 302 from the intermediate decoupling capacitor 105; and a second low-side switch 107 for de-energizing the second inductor 108 and the second winding 302 by connecting the second inductor 108 and the second winding 302 across an output decoupling capacitor 109, wherein the first high-side switch 102 and the second high-side switch 106 are substantially synchronously activated, and wherein the first low-side switch 103 and the second low-side switch 107 are substantially synchronously activated.

[0031] In another embodiment, the first inductor 104 is partially contributed by the leakage inductance of the first winding 301 of the coupled inductor 300 .

[0032] In another embodiment, the first inductor 104 is completely contributed by the leakage inductance of the first winding 301 of the coupled inductor 300 .

[0033] In another embodiment, the second inductor 108 is partially contributed by the leakage inductance of the second winding 302 of the coupled inductor 300 .

[0034] In another embodiment, the second inductor 108 is fully contributed by the leakage inductance of the second winding 302 of the coupled inductor 300 .

[0035] In another embodiment, when the output voltage exceeds a first threshold, the first high-side switch 102 and the second low-side switch 107 are activated concurrently.

[0036] In another embodiment, when the output voltage drops below the second threshold, the first high-side switch 102 is deactivated.

[0037] In another embodiment, when the output voltage drops below the third threshold, the first low-side switch 103 and the second high-side switch 106 are activated concurrently.

[0038] In another embodiment, when the output voltage exceeds a fourth threshold, the first low-side switch 103 is deactivated.

[0039] In another embodiment, the coupling coefficient between the first winding 301 and the second winding 302 is equal to 1.

[0040] In another embodiment, the coupling coefficient between the first winding 301 and the second winding 302 is less than 1.

[0041] In another embodiment, the leakage inductance of the first winding 301 and the second winding 302 is used as the first inductor 104 and the second inductor 108 .

[0042] In another embodiment, the intermediate decoupling capacitor 105 is configured to absorb excess energy stored in the first inductor 104 and the coupled inductor 300 .

[0043] In another embodiment, the first winding 301 and the second winding 302 have a turns ratio substantially equal to the inverse of the duty cycle of the cascaded buck converter 300 .

Claims

1. A cascade buck converter for receiving an input voltage from an input voltage source and for delivering an output voltage to a load, the converter comprising: a first inductor; a second inductor; a coupled inductor having a first winding connected in series with the first inductor and a second winding connected in series with the second inductor; an intermediate decoupling capacitor for receiving energy from the first inductor and the first winding and for supplying energy to the second inductor and the second winding; an output decoupling capacitor for smoothing the output voltage at the load; a first high-side switch for energizing the first inductor and the first winding from the input voltage source; a first low-side switch for de-energizing the first inductor and the first winding by connecting the first inductor and the first winding across the intermediate decoupling capacitor; a second high-side switch for energizing the second inductor and the second winding from the intermediate decoupling capacitor; and a second low-side switch for de-energizing the second inductor and the second winding by connecting the second inductor and the second winding across the output decoupling capacitor, wherein the first high-side switch and the second high-side switch are activated substantially synchronously, and wherein the first low-side switch and the second low-side switch are activated substantially synchronously, When the output voltage exceeds a first threshold, the first high-side switch and the second low-side switch are activated concurrently. 2 . The cascaded buck converter of claim 1 , wherein the first inductor is partially contributed by a leakage inductance of the first winding of the coupled inductor. 3 . The cascaded buck converter of claim 1 , wherein the first inductor is fully contributed by a leakage inductance of the first winding of the coupled inductor. 4 . The cascaded buck converter of claim 1 , wherein the second inductor is partially contributed by a leakage inductance of the second winding of the coupled inductor. 5 . The cascaded buck converter of claim 1 , wherein the second inductor is fully contributed by a leakage inductance of the second winding of the coupled inductor. 6 . The cascaded buck converter of claim 1 , wherein the first high-side switch is deactivated when the output voltage drops below a second threshold. 7 . The cascade buck converter of claim 1 , wherein when the output voltage drops below a third threshold, the first low-side switch and the second high-side switch are activated concurrently. 8 . The cascaded buck converter of claim 7 , wherein the first low-side switch is deactivated when the output voltage exceeds a fourth threshold. 9 . The cascaded buck converter of claim 1 , wherein a coupling coefficient between the first winding and the second winding is substantially equal to 1. 10 . The cascaded buck converter of claim 1 , wherein a coupling coefficient between the first winding and the second winding is less than 1. 11 . The cascaded buck converter of claim 10 , wherein leakage inductances of the first winding and the second winding are used as the first inductor and the second inductor. 12 . The cascaded buck converter of claim 1 , wherein the intermediate decoupling capacitor is configured to absorb excess energy stored in the first inductor and the coupled inductor.

13. The cascaded buck converter of claim 1, wherein the first winding and the second winding have a turns ratio substantially equal to an inverse of a duty cycle of the cascaded buck converter.

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