An IIC isolation circuit for connecting multiple BMS AFE ICs in series

Abstract

The invention discloses an IIC isolation circuit for connecting multiple BMS AFE ICs in series, comprising a ground signal B‑, a power supply L3.3V, a ground signal B11‑, a power supply H3.3V, and also comprising a plurality of BMS AFE IC circuits and a single-chip microcomputer MCU. The plurality of BMS AFE IC circuits are connected to the single-chip microcomputer MCU, the single-chip microcomputer MCU is connected to the ground signal B‑, and the single-chip microcomputer MCU is also connected to the power supply L3.3V. The BMS AFE IC circuit comprises 20 battery strings, a high-side BMS AFE IC chip, a low-side BMS AFE IC chip, and two IIC communication isolation circuits. The circuit of the invention can greatly reduce the circuit cost of the isolated IIC, reduce the circuit complexity, reduce the circuit operation power consumption, improve the product service life, and reduce the battery maintenance cost.

Description

Technical Field

[0001] The invention relates to an IIC isolation circuit for connecting a plurality of BMS AFE ICs in series. Background Art

[0002] Lithium batteries will have safety risks if they exceed a certain temperature, voltage, and current range, so BMS is needed to collect and protect voltage, current, and temperature. The BMS AFE IC chip is a highly integrated analog front-end chip that can mainly collect the voltage of each battery cell in the battery pack, the temperature of the battery pack, and the total current of the battery pack, and provide LDO 3.3V power supply. At the same time, it can be connected to the MCU through the IC's communication interface for data transmission for MCU calculation and protection. Most BMS AFE IC chips use the IIC communication interface to communicate with the MCU. Currently, there are no more than 16 strings of batteries on the market. For products with a high number of strings, such as 20 strings of batteries, 2 BMS AFE IC chips must be cascaded to achieve BMS management.

[0003] like Figure 1 The following is a general technology currently used. Because the ground of the high-side 10S BMS AFE IC chip is B11-, and the ground of the MCU is B1-, all signals of the high-side 10S AFE chip are high voltage relative to the MCU signal, so it is necessary to isolate the IIC signal for communication and transfer it to the signal of the MCU with B1- as the ground for communication. The isolated communication is composed of an isolation chip. Because the IIC signal has a two-way communication function, it cannot simply use the one-way isolation communication solution on the market. It is necessary to use a dedicated isolation chip to isolate the IC, and at the same time increase the isolation power supply to power the isolated IIC chip. Because the power consumption of the isolated power supply is very high, it is necessary to use a total power supply DCDC module to ensure the power supply of the isolated power supply. The cost of the isolated power supply and the isolated IIC chip is very high, because the isolation chip is 12 yuan + the isolation power supply is 10 yuan + the DCDC is 8 yuan, and the static power consumption of the circuit is also very high, which affects the storage performance of the lithium battery. Summary of the invention

[0004] The purpose of the present invention is to overcome the deficiencies in the prior art and provide an IIC isolation circuit for connecting multiple BMS AFE ICs in series.

[0005] In order to achieve the above object, the present invention is achieved through the following technical solutions:

[0006] An IIC isolation circuit for connecting multiple BMS AFE ICs in series, including a ground signal B-, a power supply L3.3V, a ground signal B11-, a power supply H3.3V, and also including several BMS AFE IC circuits and a single-chip microcomputer MCU. The several BMS AFE IC circuits are connected to the single-chip microcomputer MCU, the single-chip microcomputer MCU is connected to the ground signal B-, and the single-chip microcomputer MCU is also connected to the power supply L3.3V. The BMS AFE IC circuit includes 20 battery strings, 1 high-side BMS AFE IC chip, 1 low-side BMS AFE IC chip, and 2 IIC communication isolation circuits. The 20 battery strings are connected in series in sequence, the high-side BMS AFE IC chip and the low-side BMS AFE IC chip are both connected to the 20 battery strings, the high-side BMS AFE IC chip is connected to the low-side BMS AFE IC chip, the high-side BMS AFE IC chip is connected to the single-chip microcomputer MCU through 2 IIC communication isolation circuits, the high-side BMS AFE IC chip is connected to the ground signal B11-, and the high-side BMS AFE The IC chip is also connected to the power supply H3.3V, the low-side BMS AFE IC chip is connected to the ground signal B-, the low-side BMS AFE IC chip is also connected to the power supply L3.3V, the ground signal B11- is a high voltage relative to the ground signal B-, and the power supply H3.3V is a high voltage relative to the power supply L3.3V.

[0007] Preferably, the high-side BMS AFE IC chip is provided with an H_SDA terminal and an H_SCL terminal, and the single-chip microcomputer MCU is provided with an L_SDA terminal and an L_SCL terminal.

[0008] Preferably, the IIC communication isolation circuit includes transistor Q1, transistor Q2, transistor Q3, transistor Q4, resistor R1, resistor R2, resistor R3, resistor R4, and resistor R5, one end of the resistor R1 is connected to the power supply H3.3V, the other end of the resistor R1 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to the power supply L3.3V, the emitter of the transistor Q1 is connected to the collector of the transistor Q2 through the resistor R4, the emitter of the transistor Q2 is connected to the ground signal B-, and the transistor The base of the transistor Q2 is connected to the ground signal B- through the resistor R5, the collector of the transistor Q1 is connected to the base of the transistor Q3 through the resistor R3, the collector of the transistor Q3 is connected to the ground signal B11-, the emitter of the transistor Q3 is connected to the base of the transistor Q4, the collector of the transistor Q4 is connected to the base of the transistor Q2, and the emitter of the transistor Q4 is connected to the power supply H3.3V through the resistor R2. The two IIC communication isolation circuits are a first IIC communication isolation circuit and a second IIC communication isolation circuit.

[0009] Preferably, the collector of the transistor Q2 in the first IIC communication isolation circuit is connected to the L_SCL terminal, and the emitter of the transistor Q3 is connected to the H_SCL terminal.

[0010] Preferably, the collector of the transistor Q2 in the second IIC communication isolation circuit is connected to the L_SDA terminal, and the emitter of the transistor Q3 is connected to the H_SDA terminal.

[0011] Preferably, the transistor Q1 and the transistor Q2 are both NPN transistors, and the transistor Q3 and the transistor Q4 are both PNP transistors.

[0012] Preferably, there is one BMS AFE IC circuit.

[0013] The beneficial effects of the present invention are as follows: the circuit of the present invention can greatly reduce the circuit cost of the isolated IIC, reduce the circuit complexity, reduce the circuit operation power consumption, increase the product life, reduce the battery maintenance cost, and ultimately enhance the market competitiveness of the product, bringing huge benefits to the company. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A module connection diagram for background technology;

[0015] Figure 2 It is a module connection diagram of the present invention;

[0016] Figure 3 It is a circuit schematic diagram of the first IIC communication isolation circuit;

[0017] Figure 4 This is the circuit schematic diagram of the second IIC communication isolation circuit. DETAILED DESCRIPTION

[0018] The technical solution of the present invention is further described below in conjunction with the accompanying drawings:

[0019] like Figure 2As shown, an IIC isolation circuit for connecting multiple BMS AFE ICs in series includes a ground signal B-, a power supply L3.3V, a ground signal B11-, a power supply H3.3V, and also includes a BMS AFE IC circuit and a single-chip microcomputer MCU3. The BMS AFE IC circuit is connected to the single-chip microcomputer MCU3, the single-chip microcomputer MCU3 is connected to the ground signal B-, and the single-chip microcomputer MCU3 is also connected to the power supply L3.3V. The BMS AFE IC circuit includes 20 battery strings, 1 high-side BMS AFE IC chip 1, 1 low-side BMS AFE IC chip 2, and 2 IIC communication isolation circuits. The 20 battery strings are connected in series in sequence, and the 20 battery strings are B1 to B20. The high-side BMS AFE IC chip 1 and the low-side BMS AFE IC chip 2 are both connected to the 20 battery strings. The high-side BMS AFE IC chip 1 is connected to the low-side BMS AFE IC chip 2. The IC chip 1 is connected to the single-chip computer MCU3 through two IIC communication isolation circuits. The high-side BMS AFE IC chip 1 is connected to the ground signal B11-, and the high-side BMS AFE IC chip 1 is also connected to the power supply H3.3V. The low-side BMS AFE IC chip 2 is connected to the ground signal B-, and the low-side BMS AFE IC chip 2 is also connected to the power supply L3.3V. The ground signal B11- is a high voltage relative to the ground signal B-, and the power supply H3.3V is a high voltage relative to the power supply L3.3V.

[0020] like Figure 2 As shown, the high-side BMS AFE IC chip 1 is provided with an H_SDA terminal and an H_SCL terminal, and the single-chip microcomputer MCU3 is provided with an L_SDA terminal and an L_SCL terminal.

[0021] like Figure 3 , Figure 4As shown, the IIC communication isolation circuit includes transistor Q1, transistor Q2, transistor Q3, transistor Q4, resistor R1, resistor R2, resistor R3, resistor R4, and resistor R5. One end of the resistor R1 is connected to the power supply H3.3V, the other end of the resistor R1 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to the power supply L3.3V, the emitter of the transistor Q1 is connected to the collector of the transistor Q2 through the resistor R4, the emitter of the transistor Q2 is connected to the ground signal B-, and the transistor Q2 The base of the transistor is connected to the ground signal B- through the resistor R5, the collector of the transistor Q1 is connected to the base of the transistor Q3 through the resistor R3, the collector of the transistor Q3 is connected to the ground signal B11-, the emitter of the transistor Q3 is connected to the base of the transistor Q4, the collector of the transistor Q4 is connected to the base of the transistor Q2, and the emitter of the transistor Q4 is connected to the power supply H3.3V through the resistor R2. The two IIC communication isolation circuits are the first IIC communication isolation circuit 42 and the second IIC communication isolation circuit 41.

[0022] like Figure 3 As shown, the collector of the transistor Q2 in the first IIC communication isolation circuit 42 is connected to the L_SCL terminal, and the emitter of the transistor Q3 is connected to the H_SCL terminal.

[0023] like Figure 4 As shown, the collector of the transistor Q2 in the second IIC communication isolation circuit 41 is connected to the L_SDA terminal, and the emitter of the transistor Q3 is connected to the H_SDA terminal.

[0024] like Figure 3 , Figure 4 As shown, the transistor Q1 and the transistor Q2 are both NPN transistors, and the transistor Q3 and the transistor Q4 are both PNP transistors.

[0025] One IIC communication isolation circuit can isolate one SDA or SCL communication line, so there are 2 IIC communication isolation circuits, and the BMS AFE IC is the same chip. It just does not support such a high number of batteries, so more than two are needed for cascading. Therefore, one is placed on the high side and one is placed on the low side. The low-side AFE does not need to be isolated because its ground is the same as the MCU. The working ground of the high-side AFE chip is B11-, and the working ground of the MCU is B1-, so it needs to be isolated. All signals generated by the high-side AFE are high-voltage signals relative to the MCU.

[0026] like Figure 3 , Figure 4As shown, resistors R4 and R2 are IIC communication pull-up resistors, and their resistance values ​​should be consistent. The selection range needs to be within the range of 4.7k to 10k to ensure normal IIC communication within the range of 100k. The resistance values ​​of resistors R1, R3, and R5 can be selected from 30k to 100k to ensure power consumption and response speed.

[0027] like Figure 3 , Figure 4 As shown, H3.3V is the H3.3V power supply generated by the high-side BMS AFE IC chip, and L3.3V is the L3.3V power supply generated by the low-side BMSAFE IC chip. After H3.3V is connected to R1, one end of R1 is connected to R3, the other end of R3 is connected to the B pole of Q3, the B pole of Q3 is connected to the B pole of Q4, and the C pole of Q3 is connected to the ground signal B11-. The other end of R1 is connected to the C pole of Q1, the B pole of Q1 is connected to the L3.3V power supply, the E pole of Q1 is connected to one end of R4, and the other end of R4 is connected to the C pole of Q2. The C pole of Q2 is connected to the L_SCL terminal or L_SDA terminal of the MCU. The H3.3V power supply is connected to one end of R2 at the same time, the other end of R2 is connected to the C pole of Q4, the B pole of Q4 is connected to the H_SCL terminal or H_SDA terminal of the high-side BMS AFE IC chip, the C pole of Q4 is connected to the B pole of Q2, and is connected to one end of R5 at the same time, and the other end of R5 and the E pole of Q2 are all connected to the ground signal B-.

[0028] like Figure 3 , Figure 4As shown, the logic control chips of IIC are all OC gate circuits, so they need external pull-up. The pull-up of MCU IIC is completed by the power supply L3.3V through the BE diode of Q1, and then connected to R4 to complete the pull-up. Similarly, the signal pull-up of the high-side BMS AFE IC chip is connected to R3 by H3.3V, and then completed by the BE diode of Q4. Because IIC is a two-way communication, when the MCU needs to send a signal to the high-side BMS AFE IC chip, when sending a high level, the L_SCL end or L_SDA end is pulled up by L3.3V and outputs a high level. At this time, Q1 is not turned on, the C pole of Q1 is equal to the H3.3V voltage, and Q3 cannot be turned on. The signal at the H_SCL end or H_SDA end continues to be pulled up by H_3.3V, so the output is a high level. The isolated high level from the MCU to the high-side BMS AFE IC chip can be transmitted normally, and the power consumption is 0. When the MCU wants to transmit a low level to the high-side BMS AFE IC chip, the L_SCL terminal or the L_SDA terminal is pulled down by the MCU, the BE diode of Q1 has a voltage drop, and the transistor enters the amplification state. The CE pole of Q1 is turned on, and the CE pole is turned on to pull the C pole of Q1 down to the L3.3V level. Because Q1 is pulled low, Q3 is turned on, and the H_SCL or H_SDA terminal is pulled to the B11- signal. The high-side BMS AFE IC chip outputs a low level, and the isolated low level from the MCU to the high-side BMS AFE IC chip can be transmitted normally. Therefore, the patented power can communicate normally from the low side of the MCU to transmit data to the high-side BMS AFE IC chip side. The bus is usually at a high level and the power consumption is 0. The power consumption is limited by R1, R2 and R4 during communication.

[0029] like Figure 3 , Figure 4 As shown, when the signal is transmitted from the high-side BMS AFE IC chip to the low-side MCU, the high-level transmission also consumes 0 power. The bus is usually at a high level and the transmission is normal. When the high-side BMS AFE IC chip needs to transmit a low level, the H_SCL or H_SDA terminal is pulled low, Q4 is turned on, the high-voltage signal enters the B pole of Q2, Q2 is turned on, and the H_SCL or H_SDA signal is pulled low. Therefore, both high and low levels from the high side to the low side can be transmitted normally. The bus consumes 0 power at a high level, and the power consumption is limited by R2, R5, and R4 at a low level. In summary, this patented circuit can realize bidirectional isolated communication between the high side and the low side of IIC. When the bus is idle or transmitting a high level, the power consumption is 0. When the bus transmits a low level, there is a certain power consumption, but it can be limited by resistors, and the power consumption is low.

[0030] Transistor Q1, transistor Q2, transistor Q3, and transistor Q4 can also be replaced by other switching tubes, such as MOSFET / IGBT.

[0031] The circuit of the present invention can greatly reduce the circuit cost of the isolated IIC, reduce the circuit complexity, reduce the circuit operation power consumption, increase the product life, reduce the battery maintenance cost, and ultimately improve the market competitiveness of the product, bringing huge benefits to the company.

[0032] It should be noted that the above is only a specific embodiment of the present invention. Obviously, the present invention is not limited to the above embodiment, and there may be many variations, such as the BMS AFE IC circuit is several. In short, all variations that can be directly derived or associated with the content disclosed by ordinary technicians in this field should be considered as the protection scope of the present invention.

Claims

1. An IIC isolation circuit for connecting multiple BMS AFE ICs in series, including a ground signal B-, a power supply L3.3V, a ground signal B11-, and a power supply H3.3V, characterized in that: The invention also comprises a plurality of BMS AFE IC circuits and a single-chip microcomputer MCU (3). The plurality of BMS AFE IC circuits are connected to the single-chip microcomputer MCU (3). The single-chip microcomputer MCU (3) is connected to a ground signal B-. The single-chip microcomputer MCU (3) is also connected to a power supply L3.3V. The BMS AFE IC circuit comprises 20 battery strings, a high-side BMS AFE IC chip (1), a low-side BMS AFE IC chip (2), and two IIC communication isolation circuits. The 20 battery strings are connected in series in sequence. The high-side BMS AFE IC chip (1) and the low-side BMS AFE IC chip (2) are both connected to the 20 battery strings. The high-side BMS AFE IC chip (1) is connected to the low-side BMS AFE IC chip (2). The high-side BMS AFE IC chip (1) is connected to the single-chip microcomputer MCU (3) via two IIC communication isolation circuits. The high-side BMS AFE IC chip (1) is connected to a ground signal B11-. The high-side BMS AFE The IC chip (1) is also connected to a power supply H3.3V, the low-side BMS AFE IC chip (2) is connected to a ground signal B-, the low-side BMS AFE IC chip (2) is also connected to a power supply L3.3V, the ground signal B11- is a high voltage relative to the ground signal B-, and the power supply H3.3V is a high voltage relative to the power supply L3.3V; The high-side BMS AFE IC chip (1) is provided with an H_SDA terminal and an H_SCL terminal, and the single-chip microcomputer MCU (3) is provided with an L_SDA terminal and an L_SCL terminal; The IIC communication isolation circuit includes transistor Q1, transistor Q2, transistor Q3, transistor Q4, resistor R1, resistor R2, resistor R3, resistor R4, and resistor R5. One end of the resistor R1 is connected to the power supply H3.3V, the other end of the resistor R1 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to the power supply L3.3V, the emitter of the transistor Q1 is connected to the collector of the transistor Q2 through the resistor R4, the emitter of the transistor Q2 is connected to the ground signal B-, and the base of the transistor Q2 is connected to the ground signal B-. The collector of the transistor Q1 is connected to the ground signal B- through the resistor R5, the collector of the transistor Q1 is connected to the base of the transistor Q3 through the resistor R3, the collector of the transistor Q3 is connected to the ground signal B11-, the emitter of the transistor Q3 is connected to the base of the transistor Q4, the collector of the transistor Q4 is connected to the base of the transistor Q2, the emitter of the transistor Q4 is connected to the power supply H3.3V through the resistor R2, and the two IIC communication isolation circuits are a first IIC communication isolation circuit (42) and a second IIC communication isolation circuit (41).

2. According to claim 1, an IIC isolation circuit for connecting multiple BMS AFE ICs in series, characterized in that: The collector of the transistor Q2 in the first IIC communication isolation circuit (42) is connected to the L_SCL terminal, and the emitter of the transistor Q3 is connected to the H_SCL terminal.

3. According to claim 1, an IIC isolation circuit for connecting multiple BMS AFE ICs in series, characterized in that: The collector of the transistor Q2 in the second IIC communication isolation circuit (41) is connected to the L_SDA terminal, and the emitter of the transistor Q3 is connected to the H_SDA terminal.

4. According to claim 1, an IIC isolation circuit for connecting multiple BMS AFE ICs in series, characterized in that: The transistor Q1 and the transistor Q2 are both NPN transistors, and the transistor Q3 and the transistor Q4 are both PNP transistors.

5. According to claim 1, an IIC isolation circuit for connecting multiple BMS AFE ICs in series, characterized in that: The BMS AFE IC circuit is one.

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