Method for manufacturing a semiconductor device
By using a flat frame made of semi-cured thermosetting resin, with recessed patterns and terminal support structures, the problem of tightness between external connection terminals and terminal housing is solved, achieving reliable fixation of external connection terminals, improving the reliability and moisture resistance of semiconductor devices, and reducing manufacturing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-03-25
- Publication Date
- 2026-03-24
Smart Images
Figure CN111916355B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing a semiconductor device. Background Technology
[0002] Semiconductor devices include semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors), which are used, for example, in power conversion devices. Such semiconductor devices are configured such that a circuit board housing semiconductor chips and electronic components is housed within a terminal housing formed by molding external connection terminal inserts such as lead frames using thermoplastic resin. The device is then formed using transfer molding and packaged using encapsulation components.
[0003] Existing technical documents
[0004] Patent documents
[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-146704 Summary of the Invention
[0006] Technical issues
[0007] However, in the terminal housing as described above, since the thermoplastic resin used as its material and the external connecting terminals made of metal do not chemically bond, the external connecting terminals are not fixed to the terminal housing. Therefore, an attempt is made to maintain a tight seal between the external connecting terminals and the terminal housing through an anchoring effect created by the unevenness of the thermoplastic resin on the surface of the external connecting terminals. However, this anchoring effect alone is insufficient to achieve a sufficient seal. In such a case, if wire bonding is performed on the external connecting terminals, the external connecting terminals will wobble due to ultrasonic vibration, making it impossible to reliably connect the wires. Semiconductor devices manufactured in this way may have reduced reliability.
[0008] The present invention was made in view of this situation, and its object is to provide a method for manufacturing a semiconductor device capable of reliably fixing external connection terminals to a terminal housing.
[0009] Technical solution
[0010] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: a preparation step of preparing a substrate and external connection terminals; a flat frame molding step of molding a first semi-cured component comprising a thermosetting resin in a semi-cured state, the first semi-cured component being flat and having an opening extending through a front side and a back side, and having a recessed pattern formed on the front side; and a housing manufacturing step of disposing the substrate on the back side such that it covers the opening of the first semi-cured component, disposing the external connection terminals on the pattern, heating to cure the first semi-cured component, and manufacturing a housing comprising a first flat frame having the substrate and the external connection terminals fixed thereon.
[0011] Technical effect
[0012] According to the disclosed technology, external connection terminals can be reliably fixed to the terminal housing, suppressing the reduction in the reliability of semiconductor devices. Attached Figure Description
[0013] Figure 1 This is a top view of the semiconductor device in the embodiment.
[0014] Figure 2 This is a cross-sectional view of the semiconductor device in the implementation method.
[0015] Figure 3 This is a diagram illustrating the manufacturing method of the semiconductor device in the embodiment.
[0016] Figure 4 This is a top view of the flat plate-shaped frame used in the manufacture of the lower main body of the semiconductor device in the embodiment.
[0017] Figure 5 This is a cross-sectional view of the flat plate frame used in the manufacturing of the lower main body of the semiconductor device in the embodiment.
[0018] Figure 6 This is a top view of the flat frame used in the manufacture of the upper frame portion of the semiconductor device in the embodiment.
[0019] Figure 7 This is one of the diagrams illustrating the arrangement of external connection terminals and insulating substrates relative to the flat frame used for the lower main body in the manufacture of the semiconductor device in the embodiment.
[0020] Figure 8 This is a diagram (part two) illustrating the arrangement of external connection terminals and insulating substrates relative to the flat frame used for the lower main body in the manufacture of the semiconductor device in the embodiment.
[0021] Figure 9This is one of the diagrams illustrating the arrangement of a flat frame for the upper frame portion relative to a flat frame for the lower main body portion in the manufacture of a semiconductor device according to the embodiment.
[0022] Figure 10 This is a diagram (part two) illustrating the arrangement of a flat frame for the upper frame portion relative to a flat frame for the lower main body portion in the manufacture of a semiconductor device in the embodiment.
[0023] Figure 11 This is a diagram illustrating the manufacturing of a terminal housing by heating, which is included in the manufacturing of a semiconductor device in the embodiment.
[0024] Symbol Explanation
[0025] 10: Semiconductor devices
[0026] 20: Semiconductor unit
[0027] 21: The first semiconductor chip
[0028] 22: Second Semiconductor Chip
[0029] 23: Circuit Diagram
[0030] 24: Insulating substrate
[0031] 30: Terminal housing
[0032] 31: Upper frame section
[0033] 32: Lower body part
[0034] 32a: Storage opening
[0035] 32b: Terminal 1
[0036] 32c: Second terminal area
[0037] 33, 34, 35, 36: External connection terminals
[0038] 37: Control IC
[0039] 38: Packaging components
[0040] 40, 50: Flat frame
[0041] 41: Main body
[0042] 41a, 52: Opening
[0043] 41b, 41c, 41d, 41e: Terminal patterns
[0044] 42, 43: Semi-cured terminal support section
[0045] 42b, 42c, 42d, 43e: Terminal support patterns
[0046] 51: Frame section Detailed Implementation
[0047] Next, the embodiments will be described with reference to the accompanying drawings. It should be noted that in the following description, "front" and "top surface" are used interchangeably. Figure 2 In the semiconductor device 10, the surface facing upwards is indicated. Similarly, "upper" is used in... Figure 2 In the semiconductor device 10, the upper side is indicated. "Back side" and "lower surface" are... Figure 2 In the semiconductor device 10, the downward-facing surface is indicated. Similarly, "down" is used in... Figure 2 The direction indicated in semiconductor device 10 is the lower side. The same directionality may be indicated in other figures as needed. The terms "front," "upper surface," "upper," "back side," "lower surface," "lower," and "side" are merely convenient expressions of specific relative positional relationships and do not limit the technical concept of the invention. For example, "upper" and "lower" do not necessarily mean the vertical direction relative to the ground. That is, the directions of "upper" and "lower" are not limited to the direction of gravity.
[0048] use Figure 1 and Figure 2 The semiconductor device in the embodiments will be described. Figure 1 This is a top view of the semiconductor device in the embodiment. Figure 2 This is a cross-sectional view of the semiconductor device in the embodiment. It should be noted that, in Figure 1 The illustration of the packaging components is omitted. Figure 2 yes Figure 1 The cross-sectional view at the single-dotted dashed line XX in the diagram.
[0049] like Figure 1 and Figure 2As shown, the semiconductor device 10 includes: a set of semiconductor units 20, a control IC (Integrated Circuit) 37, and a set of terminal housings 30 housing the set of semiconductor units 20 and the control IC 37 and having external connection terminals 33-36. The semiconductor unit 20 has six sets of first semiconductor chips 21 and second semiconductor chips 22. Furthermore, the semiconductor unit 20 also has six circuit patterns 23 respectively disposed on the front side of the first semiconductor chips 21 and second semiconductor chips 22, and these circuit patterns 23 formed on an insulating substrate 24 on the front side. It should be noted that in such a semiconductor unit 20, the circuit patterns 23 disposed on the front side of the first semiconductor chips 21 and second semiconductor chips 22 are arranged as a set, and for example, six sets are arranged parallel to the long side of the insulating substrate 24. The control IC 37 has one for each of the two sets of first semiconductor chips 21 and second semiconductor chips 22, for a total of three. It should be noted that, unless otherwise specified, this embodiment will only use one example to illustrate the existence of multiple configurations.
[0050] The first semiconductor chip 21 includes switching elements such as IGBTs and power MOSFETs. When the first semiconductor chip 21 is an IGBT, it has a collector as the main electrode on the back side and a gate and emitter as the main electrode on the front side. When the first semiconductor chip 21 is a power MOSFET, it has a drain as the main electrode on the back side and a source as both the gate and main electrode on the front side. The back side of the first semiconductor chip 21 is bonded to the circuit pattern 23 by solder (not shown).
[0051] The second semiconductor chip 2 includes diodes such as SBD (Schottky Barrier Diode) and FWD (Free Wheeling Diode). This second semiconductor chip 22 has an output electrode (cathode) as a main electrode on its back side and an input electrode (anode) as a main electrode on its front side. The back side of the aforementioned second semiconductor chip 22 is bonded to the circuit pattern 23 using solder (not shown).
[0052] Circuit pattern 23 is constructed from a metal with excellent electrical conductivity, such as copper or a copper alloy. It should be noted that... Figure 1 and Figure 2The shape of the circuit pattern 23 is an example. Such a circuit pattern 23 is generated by etching a conductive plate or foil formed on one side of the insulating substrate 24, or by attaching a conductive plate to one side of the insulating substrate 24. It should be noted that the thickness of the circuit pattern 23 is preferably 0.10 mm or more and 1.00 mm or less, more preferably 0.20 mm or more and 0.50 mm or less.
[0053] The insulating substrate 24 can be an organic insulating layer obtained by combining insulating resins with low thermal resistance, such as epoxy resin and liquid crystal polymer, with high thermal conductivity materials such as boron nitride, aluminum oxide, and silicon oxide. Alternatively, an inorganic insulating layer composed of ceramics with excellent thermal conductivity, such as aluminum oxide, aluminum nitride, and silicon nitride, can be used.
[0054] A heat sink (not shown) can be provided on the back side of the insulating substrate 24 of such a semiconductor unit 20. The heat sink is made of materials with excellent thermal conductivity, such as aluminum, iron, silver, copper, or alloys containing at least one of these. Alternatively, to improve corrosion resistance, materials such as nickel can be formed on the surface of the heat sink through electroplating. Specifically, in addition to nickel, nickel-phosphorus alloys, nickel-boron alloys, etc., are also used. Furthermore, a cooler (not shown) can be installed on the back side of the heat sink using solder or silver paste to improve heat dissipation. In this case, the cooler is made of materials with excellent thermal conductivity, such as aluminum, iron, silver, copper, or alloys containing at least one of these. In addition, as a cooler, fins or heat sinks composed of multiple fins and water-cooled cooling devices can be used. Furthermore, the heat sink can be integrated with such a cooler. In this case, it is made of materials with excellent thermal conductivity, such as aluminum, iron, silver, copper, or alloys containing at least one of these. Furthermore, to improve corrosion resistance, materials such as nickel can be formed on the surface of the heat sink integrated with the cooler through electroplating, for example. Specifically, in addition to nickel, there are nickel-phosphorus alloys, nickel-boron alloys, etc. Additionally, when using a heat sink, the combination of circuit pattern 23, insulating substrate 24, and heat sink can be used on DCB (Direct Copper Bond) substrates or AMB (Active Metal Brazed) substrates where copper foil is bonded to both sides of inorganic insulating layers such as alumina, aluminum nitride, and silicon nitride. It should be noted that the shape, arrangement, and number of circuit patterns 23 in the semiconductor unit 20 with such a configuration, as well as the arrangement and number of the first semiconductor chip 21 and the second semiconductor chip 22, are just examples and are not limited to this. Figure 1 and Figure 2 , set appropriately according to design and other factors.
[0055] The control IC 37 is soldered to three locations on the external connection terminal 35 (described later) via solder (illustration omitted). It should be noted that, to achieve the desired function, electronic components such as thermistors, capacitors, and resistors can be used instead of the control IC 37.
[0056] Next, the terminal housing 30 will be described. The terminal housing 30 has an upper frame portion 31 (second flat plate frame) that is a frame-shaped box, a lower main body portion 32 (first flat plate frame) integrally formed with the upper frame portion 31, and external connection terminals 33 to 36 provided on the lower main body portion 32. The lower main body portion 32 is a rectangular flat plate when viewed from above, and has a receiving opening 32a that extends from the front to the back and is formed on the bottom surface, on which a semiconductor unit 20 is mounted. In addition, the lower main body portion 32 has a first terminal area 32b on both sides separated by the receiving opening 32a, on which a first terminal is disposed and a second terminal area 32c on which a second terminal is disposed.
[0057] Multiple external connection terminals 33-36 extend from the opposite side of the terminal housing 30 into the external space. On one long side of the lower main body 32, multiple external connection terminals 33-35 are fixed in a row. One end of each external connection terminal 33 protrudes into the external space from one long side of the lower main body 32, and the other end is exposed in the first terminal area 32b. Additionally, on one long side of the lower main body 32, external connection terminals 34 and 35 are also fixed relative to the multiple external connection terminals 33 in a row. One end of each external connection terminal 34 and 35 protrudes into the external space from one long side of the lower main body 32, and the other end is exposed in the first terminal area 32b and wired along one long side. Thus, the control IC 37 is bonded to three portions of the external connection terminals 35 in the first terminal area 32b by solder (not shown). Furthermore, on the other long side opposite to one long side of the lower main body 32, multiple external connection terminals 36 are integrated in a row. One end of each external connection terminal 36 protrudes outward from the other long side of the lower main body 32 into the external space, and the other end is exposed in the second terminal area 32c.
[0058] The upper frame portion 31 is plate-shaped and annular, corresponding to the outer periphery of the lower main body portion 32. The upper frame portion 31 and the outer periphery of the front surface of the lower main body portion 32 are integrally formed. When viewed from above, the outer periphery of the upper frame portion 31 may be the same as the outer periphery of the lower main body portion 32. Furthermore, when viewed from above, the inner periphery of the upper frame portion 31 may be larger than the inner periphery of the lower main body portion 32. A portion of each of the external connection terminals 33 to 36 can be sandwiched between the back surface of the upper frame portion 31 and the first terminal area 32b and the second terminal area 32c of the lower main body portion 32. Additionally, the external connection terminals 33 to 36 may be exposed on the lower main body portion 32 on the inner periphery side of the upper frame portion 31.
[0059] Both the upper frame portion 31 and the lower main body portion 32 are made of the same type of thermosetting resin. Such resin includes thermosetting resins such as maleimide-modified epoxy resin, maleimide-modified phenolic resin, and maleimide resin, as well as filler materials contained in thermosetting resins. As a specific example, there is epoxy resin containing filler materials such as silicon dioxide, aluminum oxide, boron nitride, or aluminum nitride.
[0060] In the semiconductor unit 20 housed in such a terminal housing 30, the first semiconductor chip 21, the second semiconductor chip 22, the external connection terminals 33-36, and the control IC 37 are electrically connected using wiring components such as wires (symbols omitted). It should be noted that, not limited to wires, conductive wiring components such as strips or lead frames can also be used for connection. Thus, the desired circuit is formed in the semiconductor device 10. Then, the semiconductor unit 20, wires, and control IC 37, housed in the area enclosed by the housing opening 32a of the lower main body 32 and the upper frame 31, are encapsulated using a packaging component 38. The packaging component 38 contains thermosetting resins such as maleimide-modified epoxy resin, maleimide-modified phenolic resin, and maleimide resin, and filler materials contained in the thermosetting resin. As a specific example, epoxy resin is used, and the epoxy resin contains filler materials such as silicon oxide, aluminum oxide, boron nitride, or aluminum nitride as fillers. Alternatively, silicone can be used as the packaging component 38. In this case, after encapsulation with encapsulation component 38, a housing cover (not shown) is provided on terminal housing 30 to close terminal housing 30.
[0061] Next, use Figures 3 to 11 The manufacturing method of such a semiconductor device 10 will be described. Figure 3 This is a diagram illustrating the manufacturing method of the semiconductor device in the embodiment. Figure 4 This is a top view of the flat plate-shaped frame used in the manufacture of the lower main body of the semiconductor device in the embodiment. Figure 5 This is a cross-sectional view of the flat plate-shaped frame used in the manufacture of the lower main body of the semiconductor device in the embodiment. It should be noted that... Figure 5 yes Figure 4 A cross-sectional view at the point YY marked by a single dashed line. Additionally, Figure 6 This is a top view of the flat frame used in the upper frame section of the semiconductor device manufacturing embodiment.
[0062] Figure 7 and Figure 8 This diagram illustrates the arrangement of external connection terminals and an insulating substrate relative to a flat frame used for the lower main body in the manufacture of the semiconductor device in the embodiment. It should be noted that... Figure 8 yes Figure 7 A cross-sectional view at the point marked by a single dashed line XX. Figure 9 and Figure 10 This diagram illustrates the arrangement of a flat frame for the upper frame portion relative to a flat frame for the lower main body portion in the manufacture of the semiconductor device according to the embodiment. It should be noted that... Figure 10 yes Figure 9 A cross-sectional view at the single-dash line YY. Figure 11 This diagram illustrates the process of manufacturing a terminal housing by heating, which is included in the manufacturing of a semiconductor device according to an embodiment. It should be noted that... Figure 11 yes Figure 1 A cross-sectional view of the terminal housing 30 at the dashed line YY.
[0063] First, prepare the following components of the semiconductor device 10, excluding the terminal housing 30: housing material, first semiconductor chip 21, second semiconductor chip 22, control IC 37, lead frame (not shown), connected to external connection terminals 33-36, insulating substrate 24, etc. (step S1). Next, prepare a semi-cured flat frame (step S2). Figure 4 As shown, the flat frame 40 is a flat plate in a semi-cured state (stage B state), comprising a main body 41 (first semi-cured component) and semi-cured terminal support portions 42 and 43 spaced apart from the main body 41. The main body 41 has an opening 41a and terminal patterns 41b, 41c, 41d, and 41e formed on the front side. For example, as... Figure 5 As shown, terminal pattern 41e is formed by a recess on the front surface of the main body 41. The other terminal patterns 41b, 41c, and 41d are also similarly formed by recesses on the front surface of the main body 41. Furthermore, the semi-cured terminal support portions 42 and 43 also have recessed terminal support patterns 42b, 42c, 42d, and 43e formed on their respective front surfaces. It should be noted that the terminal patterns 41b, 41c, and 41d of the main body 41 correspond to the terminal support patterns 42b, 42c, and 42d of the semi-cured terminal support portion 42. The terminal pattern 41e of the main body 41 corresponds to the terminal support pattern 43e of the semi-cured terminal support portion 43. In addition, a... Figure 6 The flat plate frame 50 shown is in a semi-cured state (stage B state) and has an annular frame portion 51 (second semi-cured component) forming an opening 52.
[0064] The following describes the details of preparing the semi-cured flat frame 40, 50 in step S2. First, a liquid resin (stage A) and a filler mixed with the liquid resin are prepared (step S2a). Resins used here include phenolic resin, epoxy resin, melamine resin, etc. Silica filler can be used as a release agent in the filler. High flame retardancy can be ensured by using silica filler without incorporating halogen-based, antimony-based, or metal hydroxide-based flame retardants. Next, more than 90% filler is mixed into the liquid resin. The liquid resin mixed with filler is heated to generate a semi-cured raw material (stage B) (step S2b). It should be noted that the heating and heating time are appropriately set according to the interval and depend on the type of resin catalyst. For example, the heating temperature is 100°C or higher and 200°C or lower. Next, the semi-cured raw material is pulverized (step S2c). Next, the powdered semi-cured material is filled into predetermined molds, pressed, and then the molds are separated. This forms... Figure 4 The flat frame 40 with terminal patterns 41b to 41e and the flat frame 50 with the opening 52 are respectively formed through the opening 41a shown (step S2d). Through the above steps, the preparation of the flat frames 40 and 50 is completed. It should be noted that steps S1 and S2 can be completed before step S3 below, and the order of steps S1 and S2 can be reversed or simultaneous.
[0065] Next, a lead frame (external connection terminals 33-36) is provided on the flat frame 40. Furthermore, a flat frame 50 is provided on the outer periphery of the front side of the main body 41 on which the lead frame is provided (step S3). Specifically, a lead frame containing external connection terminals 33-36 is provided on the flat frame 40 such that the external connection terminals 33-36 are respectively fitted into the terminal patterns 41b-41e of the main body 41 and the terminal support patterns 42b-42d, 43e of the semi-cured terminal support portions 42, 43. Unwanted portions are removed from the lead frame. Additionally, an insulating substrate 24 with a circuit pattern 23 formed on it is mounted from the back side at the opening 41a of the flat frame 40. Thus, as... Figure 7 and Figure 8 As shown, in the flat frame 40, external connection terminals 33-35 are provided in the main body 41 and the semi-cured terminal support 42, and external connection terminal 36 is provided in the main body 41 and the semi-cured terminal support 43. It should be noted that in... Figure 8The illustrations of the semi-cured terminal support portions 42 and 43, which are provided with external connection terminals 33 to 36, are omitted. Furthermore, the circuit pattern 23 is exposed from the opening 41a of the main body 41. It should be noted that in this flat plate-shaped frame 40, the front surface of the main body 41 and the front surface of the external connection terminals 33 to 36 form the same plane. Additionally, the back surface of the main body 41 and the back surface of the insulating substrate 24 form the same plane. Figure 9 As shown, a flat frame 50 is provided on the front side of the main body 41 of the flat frame 40, which is provided with external connection terminals 33-36 and an insulating substrate 24. Thus, the flat frame 50 surrounds the portion of the main body 41 containing the external connection terminals 33-36 and the circuit pattern 23. Furthermore, for example, as... Figure 10 As shown, the external connection terminal 36 of the terminal pattern 41e provided on the main body portion 41 of the flat frame 40 is held by the frame portion 51 of the flat frame 50. The other external connection terminals 33 to 35 are also similarly held by the main body portion 41 of the flat frame 40 and the frame portion 51 of the flat frame 50.
[0066] Next, the flat frame 40 and 50, which are provided with external connection terminals 33-36 and insulating substrate 24 in step S3, are heated to manufacture the terminal housing 30 (step S4). The heating temperature at this time is above 120°C and below 180°C. This allows curing to occur, fixing the external connection terminals 33-36 and insulating substrate 24 to the flat frame 40. Furthermore, as... Figure 11 As shown, the flat frame 50 (frame portion 51) and the flat frame 40 (main body portion 41) are integrated, and the external connection terminals 33-36 are also fixed to the flat frame 50. Therefore, by curing these parts, a terminal housing 30 is manufactured, which includes an upper frame portion 31 and a lower main body portion 32, and contains external connection terminals 33-36 and an insulating substrate 24. Through step S4, the flat frame 50 (frame portion 51) and the flat frame 40 (main body portion 41) can be completely cured. Alternatively, curing can be performed in a process after step S4 to completely cure the flat frame 50 (frame portion 51) and the flat frame 40 (main body portion 41). It should be noted that in this embodiment, the case of manufacturing a terminal housing 30 containing an upper frame portion 31 and a lower main body portion 32 is described as an example. Depending on the situation, the terminal housing 30 may also contain only the lower main body portion 32. In this case, the provision of the flat frame 50 relative to the flat frame 40 is omitted in step S3.
[0067] The terminal housing 30 is manufactured without insert molding. That is, the terminal housing 30 does not require a device containing the precision and large molds used in insert molding, making it simpler to manufacture than insert molding and reducing manufacturing costs. Furthermore, since the terminal housing 30 is manufactured by pressing and reinforcing powdered semi-cured material, fewer air bubbles are generated during insert molding. Therefore, the insulation and moisture resistance reliability of the terminal housing 30 are improved. In insert molding, molten resin flows into the mold, creating confluence points (welds). Welds present in terminal housings formed by insert molding become weak points. On the other hand, since the terminal housing 30 is not formed using insert molding, it does not contain welds, achieving high strength and improved reliability. Moreover, the external connecting terminals 33-36 of the terminal housing 30 are fixed together with the insulating substrate 24. In this method, unlike terminal housings formed by insert molding, it is not necessary to use adhesives to bond the insulating substrate 24, thus omitting that manufacturing process. Because the terminal housing 30 is made of a thermosetting resin with high adhesion to metal, the gap between the terminal housing 30 and the external connection terminals 33-36 can be almost eliminated. Therefore, moisture can be prevented from entering the gap between the terminal housing 30 and the external connection terminals 33-36, and the moisture resistance reliability of the terminal housing 30 can be improved.
[0068] Next, the first semiconductor chip 21, the second semiconductor chip 22, and the control IC 37 are joined within the terminal housing 30, and wiring is performed via wires (step S5). Specifically, the first semiconductor chip 21 and the second semiconductor chip 22 are joined to the circuit pattern 23 within the terminal housing 30 using solder, and the control IC 37 is joined to the external connection terminal 35 using solder (hereinafter referred to as sub-step S5a (illustration omitted)). The first semiconductor chip 21 and the second semiconductor chip 22 on the circuit pattern 23 are electrically connected using wires (hereinafter referred to as sub-step S5b (illustration omitted)). Then, the external connection terminals 33-36, the first semiconductor chip 21, the second semiconductor chip 22, and the circuit pattern 23 are appropriately electrically connected using wires (hereinafter referred to as sub-step S5c (illustration omitted)). In particular, as described above, the external connection terminals 33-36 are reliably fixed to the terminal housing 30. Therefore, when connecting wires to external connection terminals 33 to 36, since external connection terminals 33 to 36 will not be misaligned, the wires can be reliably connected to external connection terminals 33 to 36.
[0069] It should be noted that sub-steps S5a and S5b can be performed before the start of step S4. Alternatively, sub-step S5a can be performed after step S3, combined with the heating of the terminal housing 30 used for manufacturing step S4 using solder. Furthermore, if sub-step S5b is performed after the first semiconductor chip 21 and the second semiconductor chip 22 are bonded to the circuit pattern 23, it can be performed at any time. However, sub-step S5c needs to be performed after steps S1 to S4 and sub-steps S5a and S5b.
[0070] Next, the first semiconductor chip 21, the second semiconductor chip 22, the circuit pattern 23, and the wires inside the upper frame portion 31 and the lower main body portion 32 of the terminal housing 30 are packaged using the packaging component 38 (step S6). Manufactured as described above. Figure 1 and Figure 2 Semiconductor device 10. It should be noted that, in Figure 1 and Figure 2 The diagrams are omitted from the illustrations, which show the components corresponding to the semi-cured terminal support portions 42 and 43 of the flat frame 40, which includes external connection terminals 33 to 36.
[0071] In the above-described method for manufacturing the semiconductor device 10, an insulating substrate 24 with circuit patterns 23 and external connection terminals 33-36 are prepared. Then, a flat frame 40 containing a semi-cured thermosetting resin is formed. The flat frame 40 is flat and has an opening 41a extending through both the front and back sides, and recessed terminal patterns 41b-41e are formed on the front side. Subsequently, the insulating substrate 24 is placed on the back side, covering the opening 41a of the flat frame 40, and the external connection terminals 33-36 are placed on the terminal patterns 41b-41e, followed by heating. As a result, a terminal housing 30, in which the insulating substrate 24 and external connection terminals 33-36 are fixed, can be manufactured from the flat frame 40.
[0072] The external connection terminals 33-36 contained in the terminal housing 30 formed in this way are reliably fixed to the terminal housing 30. Therefore, when connecting wires to the external connection terminals 33-36, since the external connection terminals 33-36 will not misalign, the wires can be reliably connected to the external connection terminals 33-36. In addition, the terminal housing 30 is not manufactured by insert molding. That is, the terminal housing 30 does not require a device containing the precision and large molds used in insert molding, and can be manufactured more easily than insert molding, thus reducing manufacturing costs. In addition, in insert molding, molten resin confluence points (welds) are generated when molten resin flows into the mold. The welds contained in the terminal housing formed by insert molding become weak points of the terminal housing. On the other hand, since the terminal housing 30 is not manufactured by insert molding, it does not contain welds, and high strength and improved reliability can be achieved. Furthermore, the terminal housing 30 is fixed together with the external connection terminals 33-36 and the insulating substrate 24. In this method, unlike the method used for insert molding of terminal housings, adhesives are not required to bond the insulating substrate 24, thus eliminating that manufacturing step. Since the terminal housing 30 is made of a thermosetting resin with high metal adhesion, the gap between the terminal housing 30 and the external connection terminals 33-36 can be virtually eliminated. Therefore, moisture can be prevented from seeping into the gap between the terminal housing 30 and the external connection terminals 33-36, improving the moisture resistance reliability of the terminal housing 30.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: Preparation process: Prepare the substrate and external connection terminals; In the flat frame molding process, a first semi-cured component containing a semi-cured thermosetting resin is molded. The first semi-cured component is flat and has an opening that extends through the front and back sides, and has a recessed pattern that does not extend through the back side on the front side. as well as In the housing manufacturing process, the substrate is disposed on the back side to cover the opening of the first semi-cured component, and the external connection terminal is disposed on the pattern to manufacture a housing comprising a first flat frame on which the substrate and the external connection terminal are fixed. The housing manufacturing process includes a step of heating the first semi-cured component, on which the external connection terminals and the substrate are disposed, to cure the first semi-cured component into the first flat frame on which the external connection terminals and the substrate are fixed.
2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The plate-shaped frame forming process includes a step of mixing liquid thermosetting resin and powdered inorganic filler, and heating the mixture to form a powdered semi-cured raw material.
3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The flat frame forming process includes the steps of filling the semi-cured material into a predetermined first mold and pressing the semi-cured material in the first mold to form the first semi-cured component.
4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The heating temperature in the shell manufacturing process is above 120°C and below 180°C.
5. The method for manufacturing a semiconductor device according to any one of claims 2 to 4, characterized in that, In the flat frame molding process, a second semi-cured component is molded. The second semi-cured component is flat and annular, corresponding to the outer periphery of the first semi-cured component, and contains a semi-cured thermosetting resin. In the housing manufacturing process, the second semi-cured component is disposed on the front side of the first semi-cured component, which is provided with the substrate and the external connection terminal, to manufacture the housing that further includes a second flat frame integrated with the first flat frame.
6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The housing manufacturing process includes a step of heating the first semi-cured component and the second semi-cured component disposed on the front side of the first semi-cured component together to cure the first semi-cured component and the second semi-cured component.
7. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The second flat frame is made of the same material as the first flat frame.
8. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The flat frame forming process includes filling the semi-cured material into a predetermined second mold and pressing the semi-cured material in the second mold to form the second semi-cured component.
9. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The flat frame molding process includes a process of forming a semi-cured terminal support component together with the first semi-cured component. The semi-cured terminal support component is flat and has a recessed support pattern formed on its front side, and contains a semi-cured thermosetting resin. The housing manufacturing process includes a step of placing the portion of the external connection terminal of the first semi-cured component protruding from the first semi-cured component onto the support pattern of the semi-cured terminal support component.
10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The housing manufacturing process includes a step of heating the semi-cured terminal support component and the first semi-cured component together to cure them.
11. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The method for manufacturing the semiconductor device further includes a packaging step in which the area surrounded by the housing is packaged by a packaging component after the housing manufacturing step is completed.