Method of manufacturing a memory device

Abstract

A method of manufacturing a memory device is provided. The method includes the steps of: forming a plurality of lower conductive lines on a substrate; forming a plurality of memory cells on the plurality of lower conductive lines; forming a switching stack defining a plurality of first lines, the plurality of first lines extending in a first direction parallel over the plurality of memory cells; forming an upper conductive layer on the switching stack; forming an etch mask defining a plurality of second lines, the plurality of second lines extending in a second direction parallel over the upper conductive layer, the second direction being different from the first direction; and forming a plurality of upper conductive lines and a plurality of switching cells by etching the upper conductive layer and the switching stack using the etch mask.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0055841, filed on May 13, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The inventive concept relates to a method of manufacturing a memory device. More particularly, the inventive concept relates to a method of manufacturing a phase change memory device. BACKGROUND

[0003] A phase change random access memory (PRAM) is a nonvolatile memory that stores data using a phase change of a material. A memory cell of the PRAM can include a memory cell including a phase change material and a switching cell for selecting the memory cell. The memory cell can be connected to an upper conductive line and a lower conductive line (e.g., a bit line and a word line). SUMMARY

[0004] The inventive concept provides a highly integrated phase change memory device.

[0005] According to an aspect of the inventive concept, a method of manufacturing a memory device can include forming a plurality of lower conductive lines on a substrate; forming a plurality of memory cells on the plurality of lower conductive lines; forming a switching stack defining a plurality of first lines extending in parallel in a first direction on the plurality of memory cells; forming an upper conductive layer on the switching stack; forming an etching mask defining a plurality of second lines extending in parallel in a second direction on the upper conductive layer, the second direction being different from the first direction; and forming a plurality of upper conductive lines and a plurality of switching cells by etching the upper conductive layer and the switching stack using the etching mask.

[0006] According to another aspect of the inventive concept, a method of manufacturing a memory device can include forming a plurality of lower conductive lines; forming a plurality of memory cells on the plurality of lower conductive lines; forming a plurality of switching cells on the plurality of memory cells; forming a plurality of upper conductive lines on the plurality of switching cells; and forming a first insulating layer including a plurality of first recesses extending in parallel, wherein the plurality of upper conductive lines are formed in the plurality of first recesses in the first insulating layer after the first insulating layer is formed.

[0007] According to another aspect of the inventive concept, a method of manufacturing a memory device can include forming a lower conductive line; forming at least one insulating layer on the lower conductive line, the at least one insulating layer including at least one hole; forming a first electrode pattern, a switching pattern, a second electrode pattern, a phase change pattern, and a third electrode pattern in the at least one hole in the at least one insulating layer; and forming an upper conductive line on the third electrode pattern. BRIEF DESCRIPTION OF DRAWINGS

[0008] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figures 1A-11A is a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 1B-11B is a front view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 1C-11C is a side view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept.

[0010] Figures 12A-15A is a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 12B-15B is a front view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 12C-15C is a side view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept.

[0011] Figures 16A-18A is a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 16B-18B is a front view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 16C-18C is a side view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept.

[0012] Figures 19A-21A is a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 19B-21B is a front view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 19C-21C is a side view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept.

[0013] Figure 22A and Figure 23A is a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 22B and Figure 23B is a front view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 22C and Figure 23C is a side view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept.

[0014] Figures 24A-26A is a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept,Figures 24B-26B is a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 24C-26C is a side view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept.

[0015] Figures 27A-29A is a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 27B-29B is a front view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 27C-29C is a side view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept.

[0016] Figure 30A and Figure 31A is a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 30B and Figure 31B is a front view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 30C and Figure 31C is a side view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept.

[0017] Figures 32A-34A is a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 32B-34B is a front view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 32C-34C is a side view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept.

[0018] Figure 35A and Figure 36A is a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 35B and Figure 36B is a front view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 35C and Figure 36C is a side view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept.

[0019] Figure 37A is a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 37B is a front view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 37C is a side view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0020] Hereinafter, the terms "damascene technique" and "etching technique" will be used. As used herein, the term "damascene technique" refers to a process technique in which an insulating layer having a hole and / or a recess is first formed, and then a desired structure is formed in the hole and / or the recess. The step of forming the insulating layer having the hole and / or the recess can include, for example, forming an insulating layer and etching the insulating layer. The step of forming the structure in the hole and / or the recess can include, for example, forming a material layer on the insulating layer and polishing and / or etching the material layer.

[0021] On the other hand, the term "etching technique" refers to a process type in which a desired structure is first formed, and then an insulating layer surrounding a side wall of the structure is formed. For example, the step of forming the structure can include forming a material layer and etching the material layer. The step of forming the insulating layer surrounding the side wall of the structure can include, for example, forming an insulating layer on the structure and etching and / or polishing the insulating layer.

[0022] In addition, ordinal expressions such as "first", "second", "third", etc. used herein refer only to the mentioned ordinal numbers with respect to a specific example embodiment and a set (bundle) of claims of the specification. In addition, the ordinal number of an element mentioned in the detailed description of the specification and the ordinal number of the element mentioned in the set of claims can be different. For example, an element referred to as a second insulating layer in the detailed description of the specification can be referred to as a first insulating layer in the set of claims. Furthermore, the ordinal number of an element referred to in a set of claims and the ordinal number of the element mentioned in another set of claims can be different. Thus, an element referred to as a "first insulating layer" in a set of claims can be different from an element referred to as a "first insulating layer" in another set of claims.

[0023] Figures 1A-11A (i.e., Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A ) are plan views for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 1B-11B (i.e., Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B ,Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B and Figure 11B are front views for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 1C-11C (i.e., Figure 1C 、 Figure 2C 、 Figure 3C 、 Figure 4C 、 Figure 5C 、 Figure 6C 、 Figure 7C 、 Figure 8C 、 Figure 9C 、 Figure 10C and Figure 11C are side views for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept. According to the method of manufacturing a memory device according to an example embodiment of the inventive concept shown in Figures 1A-11C , by etching the upper conductive layer 180L (see Figures 9A-9C ) and the switch stack SS (see Figures 9A-9C ) using the etching mask M (see Figures 9A-9C ), a plurality of upper conductive lines 180 (see Figures 10A-10C ) and a plurality of switch units SU (see Figures 10A-10C ) can be formed.

[0024] Referring to Figures 1A-1C , a plurality of lower conductive lines 110 can be formed on the base 101. Each of the plurality of lower conductive lines 110 can correspond to a word line or a bit line of a phase change random access memory (PRAM). The plurality of lower conductive lines 110 can each extend in parallel along a first direction (X direction). The plurality of lower conductive lines 110 can be formed in the first insulating layer 120a.

[0025] In an example embodiment, the plurality of lower conductive lines 110 can be formed using a damascene technique. That is, the first insulating layer 120a can be first formed, and later the plurality of lower conductive lines 110 can be formed in the first insulating layer 120a. For example, the first insulating layer 120a can be formed on the base 101, and then the first insulating layer 120a can be etched to form a plurality of first recesses Ra that can each extend in parallel along the first direction (X direction) and expose the base 101 in the first insulating layer 120a, and then a lower conductive layer can be formed on the first insulating layer 120a and the base 101, and then the lower conductive layer can be polished and / or etched so that the upper surface of the first insulating layer 120a is exposed.

[0026] In another example embodiment, the plurality of lower conductive lines 110 can be formed using an etching technique. That is, the plurality of lower conductive lines 110 can be formed first, and then the first insulating layer 120a can be formed later. For example, a lower conductive layer can be formed, and then the plurality of lower conductive lines 110 can be formed by etching the lower conductive layer, and then the first insulating layer 120a can be formed on the plurality of lower conductive lines 110, and then the first insulating layer 120a can be polished and / or etched so that the upper surfaces of each of the plurality of lower conductive lines 110 are exposed.

[0027] The substrate 101 can include any material such as an organic material, a ceramic, a semiconductor, or a combination thereof. The substrate 101 can include, for example, a Group IV semiconductor material, a Group III-V semiconductor material, a Group II-VI semiconductor material, or a combination thereof. The Group IV semiconductor material can include, for example, silicon (Si), germanium (Ge), or silicon (Si)-germanium (Ge). The Group III-V semiconductor material can include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), or indium gallium arsenide (InGaAs). The Group II-VI semiconductor material can include, for example, zinc telluride (ZnTe) or cadmium sulfide (CdS). The substrate 101 can include a bulk wafer or an epitaxial layer. The plurality of lower conductive lines 110 can include any conductive material including a metal, a metal nitride, a metal oxide, or a combination thereof. The plurality of lower conductive lines 110 can include, for example, W, Ti, Ta, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, TiCSiN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, Au, Ag, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, Zn, ITO, or a combination thereof. The first insulating layer 120a can include silicon oxide, silicon nitride, or a combination thereof.

[0028] Referring to Figures 2A-2C A second insulating layer 120b can be formed on the plurality of lower conductive lines 110 and the first insulating layer 120a. The second insulating layer 120b can include silicon oxide, silicon nitride, or a combination thereof. In addition, a plurality of second recesses Rb can be formed in the second insulating layer 120b, the second recesses Rb each extending in parallel along the second direction (Y direction) and exposing the plurality of lower conductive lines 110 and the first insulating layer 120a. That is, the second insulating layer 120b can be patterned as a plurality of lines each extending in parallel along the second direction (Y direction).

[0029] Referring to Figures 3A-3CThe plurality of lower electrode patterns BE, the plurality of spacer patterns SP, and the third insulating layer 120c can be formed in a plurality of second recesses Rb in the second insulating layer 120b. For example, a lower electrode layer (not shown), a spacer layer (not shown), and a material layer (not shown) for forming the third insulating layer 120c can be sequentially formed on the first insulating layer 120a, the plurality of lower conductive lines 110, and the second insulating layer 120b, and then the lower electrode layer, the spacer layer, and the material layer for forming the third insulating layer 120c can be polished and / or etched so that the upper surface of the second insulating layer 120b is exposed, the lower electrode patterns BE and the plurality of spacer patterns SP can be formed, and the third insulating layer 120c can be patterned. In some example embodiments, the plurality of spacer patterns SP can be omitted. In this specification, the step of forming the material layer for forming the third insulating layer 120c on the lower electrode layer can include a step of directly forming the material layer for forming the third insulating layer 120c on the lower electrode layer, or can include a step of forming at least one additional layer such as a spacer layer on the lower electrode layer and then forming the material layer for forming the third insulating layer 120c on the at least one additional layer.

[0030] The plurality of lower electrode patterns BE can include a metal, a metal nitride, a carbon-based conductive material, or a combination thereof. For example, the plurality of lower electrode patterns BE can include TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN, or a combination thereof. The plurality of spacer patterns SP can include silicon oxide, silicon nitride, or a combination thereof. The third insulating layer 120c can include silicon oxide, silicon nitride, or a combination thereof.

[0031] Referring to Figures 4A-4C A plurality of third recesses Rc can be formed to extend in parallel along the first direction (X direction) while intersecting the second insulating layer 120b, the plurality of lower electrode patterns BE, the plurality of spacer patterns SP, and the third insulating layer 120c, and exposing the first insulating layer 120a. For example, an etching mask (not shown) having a shape of a plurality of lines extending in parallel along the first direction (X direction) can be formed on the second insulating layer 120b, the plurality of lower electrode patterns BE, the plurality of spacer patterns SP, and the third insulating layer 120c, and then the second insulating layer 120b, the plurality of lower electrode patterns BE, the plurality of spacer patterns SP, and the third insulating layer 120c can be etched by using the etching mask.

[0032] In addition, the fourth insulating layer 120d can be formed in the plurality of third recesses Rc. For example, the fourth insulating layer 120d can be formed on the first insulating layer 120a, the second insulating layer 120b, the plurality of lower electrode patterns BE, the plurality of spacer patterns SP, and the third insulating layer 120c, and then the fourth insulating layer 120d can be polished and / or etched such that the upper surface of the second insulating layer 120b and the upper surface of the third insulating layer 120c are exposed.

[0033] Referring to Figures 5A-5C The upper portion of each of the plurality of lower electrode patterns BE and the upper portion of each of the plurality of spacer patterns SP can be etched. Accordingly, the upper end of each of the plurality of lower electrode patterns BE and the upper end of each of the plurality of spacer patterns SP can be lower than the upper surface of the second insulating layer 120b and the upper surface of the third insulating layer 120c.

[0034] Referring to Figures 6A-6C The plurality of phase change patterns 160 and the plurality of lower intermediate electrode patterns LIE can be formed between the second insulating layer 120b and the third insulating layer 120c. Accordingly, the plurality of memory cells MU can be formed. The plurality of memory cells MU can be formed using a damascene technique. That is, the second insulating layer 120b including the plurality of second recesses Rb is first formed, and then the plurality of memory cells MU can be formed in the plurality of second recesses Rb in the second insulating layer 120b. Each of the plurality of memory cells MU can include each of the plurality of lower electrode patterns BE, each of the plurality of phase change patterns 160, and each of the plurality of lower intermediate electrode patterns LIE. In addition, two adjacent memory cells of the plurality of memory cells MU can share one lower electrode pattern BE.

[0035] The plurality of phase change patterns 160 can include a chalcogenide material such as Ge-Sb-Te (GST). The plurality of lower intermediate electrode patterns LIE can include a metal, a metal nitride, a carbon-based conductive material, or a combination thereof. For example, the plurality of lower intermediate electrode patterns LIE can include TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN, or a combination thereof.

[0036] For example, a phase change layer can be formed on the second insulating layer 120b, the third insulating layer 120c, the plurality of space patterns SP, and the plurality of lower electrode patterns BE, and then the plurality of phase change patterns 160 can be formed by polishing and / or etching the phase change layer such that an upper end of each of the plurality of phase change patterns 160 is lower than an upper surface of the second insulating layer 120b and an upper surface of the third insulating layer 120c. Also, a lower intermediate electrode layer can be formed on the second insulating layer 120b, the third insulating layer 120c, and the plurality of phase change patterns 160, and then the plurality of lower intermediate electrode patterns LIE can be formed by polishing and / or etching the lower intermediate electrode layer such that the upper surface of the second insulating layer 120b and the upper surface of the third insulating layer 120c are exposed.

[0037] In Figures 4A-4C In the above-described example embodiment, the fourth insulating layer 120d is formed before the plurality of phase change patterns 160 and the plurality of lower intermediate electrode patterns LIE are formed, but according to another example embodiment, the fourth insulating layer 120d can be formed after the plurality of phase change patterns 160 and the plurality of lower intermediate electrode patterns LIE are formed. For example, an etching mask (not shown) having a shape of a plurality of lines extending in parallel in the first direction (X direction) can be formed on the second insulating layer 120b, the third insulating layer 120c, and the plurality of lower intermediate electrode patterns LIE, and then the plurality of third recesses Rc extending in parallel in the first direction (X direction) and exposing the first insulating layer 120a can be formed by etching the second insulating layer 120b, the plurality of lower electrode patterns BE, the plurality of space patterns SP, the third insulating layer 120c, the plurality of phase change patterns 160, and the plurality of lower intermediate electrode patterns LIE using the etching mask. Then, the fourth insulating layer 120d can be formed in the plurality of third recesses Rc. For example, the fourth insulating layer 120d can be formed on the second insulating layer 120b, the plurality of lower electrode patterns BE, the plurality of space patterns SP, the third insulating layer 120c, the plurality of phase change patterns 160, and the plurality of lower intermediate electrode patterns LIE, and then the fourth insulating layer 120d can be polished and / or etched such that the upper surface of the second insulating layer 120b, the upper surface of the third insulating layer 120c, and an upper surface of each of the plurality of lower intermediate electrode patterns LIE are exposed.

[0038] Referring to Figures 7A-7C A switch stack SS can be formed on the plurality of memory cells MU, the second insulating layer 120b, and the third insulating layer 120c. The switch stack SS can include an upper intermediate electrode layer UIEL, a switch layer 170L, and a top electrode layer TEL. The switch stack SS can have a shape of a plurality of lines extending in parallel in the first direction (X direction).

[0039] In some example embodiments, the switch stack SS can be formed using an etching technique. That is, the fifth insulating layer 120e can be formed after the switch stack SS is formed. For example, a separate layer for forming the switch stack SS (not shown now) can be formed on the second insulating layer 120b, the third insulating layer 120c, the fourth insulating layer 120d, and the plurality of memory cells MU. An etching mask (not shown) having a shape of a plurality of lines extending in parallel along the first direction (X direction) can be formed on the separate layer for forming the switch stack SS, and then the stack layer for forming the switch stack SS can be etched by using the etching mask to form the switch stack SS. Thereafter, a fifth insulating material (not shown) can be formed on the switch stack SS and the fourth insulating layer 120d, and then the fifth insulating material can be polished and / or etched to form the fifth insulating layer 120e such that the upper surface of the switch stack SS is exposed.

[0040] In another example embodiment, the switch stack SS can be formed using a damascene technique. That is, the fifth insulating layer 120e can be formed first, and then the switch stack SS can be formed in the fifth insulating layer 120e. For example, the fifth insulating layer 120e can be formed first on the second insulating layer 120b, the third insulating layer 120c, the fourth insulating layer 120d, and the plurality of memory cells MU, and then a plurality of recesses extending in parallel along the first direction (X direction) and exposing the second insulating layer 120b, the third insulating layer 120c, and the plurality of memory cells MU can be formed in the fifth insulating layer 120e. Thereafter, the upper intermediate electrode layer UIEL, the switch layer 170L, and the upper electrode layer TEL can be formed in the plurality of recesses in the fifth insulating layer 120e. For example, the upper intermediate electrode layer UIEL can be formed on the second insulating layer 120b, the third insulating layer 120c, the plurality of memory cells MU, and the fifth insulating layer 120e, and then the upper intermediate electrode layer UIEL can be polished and / or etched such that the upper end of the upper intermediate electrode layer UIEL is lower than the upper surface of the fifth insulating layer 120e. Next, the switch layer 170L can be formed on the upper intermediate electrode layer UIEL and the fifth insulating layer 120e, and then the switch layer 170L can be polished and / or etched such that the upper end of the switch layer 170L is lower than the upper surface of the fifth insulating layer 120e. Next, the upper electrode layer TEL can be formed on the switch layer 170L and the fifth insulating layer 120e, and then the upper electrode layer TEL can be polished and / or etched such that the upper surface of the fifth insulating layer 120e is exposed.

[0041] The upper intermediate electrode layer UIEL can include a metal, a metal nitride, a carbon-based conductive material, or a combination thereof. For example, the upper intermediate electrode layer UIEL can include TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN, or a combination thereof. The switching layer 170L can include a chalcogenide switching material. For example, the switching layer 170L can include a bidirectional threshold switching (OTS) material. The upper electrode layer TEL can include a metal, a metal nitride, a carbon-based conductive material, or a combination thereof. For example, the upper electrode layer TEL can include TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN, or a combination thereof. The fifth insulating layer 120e can include silicon oxide, silicon nitride, or a combination thereof.

[0042] Referring to Figures 8A-8C An upper conductive layer 180L can be formed on the switching stack SS and the fifth insulating layer 120e. The upper conductive layer 180L can include W, Ti, Ta, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, TiCSiN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, Au, Ag, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, Zn, ITO, or a combination thereof.

[0043] Referring to Figures 9A-9C An etching mask M can be formed on the upper conductive layer 180L. The etching mask M can be formed in the shape of a plurality of lines extending in parallel along the second direction (Y direction).

[0044] Referring to Figures 10A-10C A plurality of upper conductive lines 180 and a plurality of switching units SU can be formed by etching the upper conductive layer 180L and the switching stack SS (see Figures 9A-9C ) using the etching mask M. The upper conductive lines 180 can each extend in parallel along the second direction (Y direction). The plurality of switching units SU can be formed in the shape of a plurality of columnar portions spaced apart from each other along the first direction (X direction) and the second direction (Y direction) and each extending along the third direction (Z direction). Each of the plurality of upper conductive lines 180 can correspond to a bit line or a word line of the PRAM.

[0045] Referring to Figures 11A-11C A sixth insulating layer 120f and a seventh insulating layer 120g can be formed on the plurality of switching units SU, the plurality of upper conductive lines 180, the second insulating layer 120b, and the third insulating layer 120c, and then the sixth insulating layer 120f and the seventh insulating layer 120g can be polished and / or etched so that upper surfaces of the plurality of upper conductive lines 180 are exposed. The sixth insulating layer 120f and the seventh insulating layer 120g can include silicon oxide, silicon nitride, or a combination thereof.

[0046] According to Figures 1A-11C the method of manufacturing a memory device shown in Figures 9A-9C , the upper conductive layer 180L and the switching stack SS (see Figures 9A-9C ) can be etched by using an etching mask M (see ). Accordingly, misalignment between the plurality of upper conductive lines 180 and the plurality of switching units SU can be mitigated or prevented. Accordingly, a highly integrated phase change memory device can be manufactured.

[0047] Figures 12A-15A (i.e., Figure 12A , Figure 13A , Figure 14A , and Figure 15A ) are plan views for explaining the method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 12B-15B (i.e., Figure 12B , Figure 13B , Figure 14B , and Figure 15B ) are front views for explaining the method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 12C-15C (i.e., Figure 12C , Figure 13C , Figure 14C , and Figure 15C ) are side views for explaining the method of manufacturing a memory device according to an example embodiment of the inventive concept. According to the method of manufacturing a memory device shown in Figures 12A-15C , the plurality of upper conductive lines 180 (see Figures 15A-15C ) can be formed using a damascene technique.

[0048] Referring to Figures 12A-12C , the plurality of lower conductive lines 110, the first insulating layer 120a, the second insulating layer 120b, the third insulating layer 120c, the fourth insulating layer 120d, and the plurality of memory units MU can be formed as described with reference to Figures 1A-6C .

[0049] Next, multiple switching cells SU can be formed on the multiple memory cells MU. The multiple switching cells SU can be formed using an etching technique. That is, after forming the multiple switching cells SU, an eighth insulating layer 120h and a ninth insulating layer 120i (see [reference needed]) can then be formed around the sidewalls of the multiple switching cells SU. Figures 13A-13C For example, an upper intermediate electrode layer, a switch layer, and an upper electrode layer can be formed on the second insulating layer 120b, the third insulating layer 120c, the fourth insulating layer 120d, and a plurality of memory cells MU. Thereafter, the upper intermediate electrode layer, the switch layer, and the upper electrode layer can be etched to form a plurality of switch cells SU in the form of a plurality of columnar portions, the plurality of switch cells SU extending along a third direction (Z direction) and spaced apart from each other along a first direction (X direction) and a second direction (Y direction).

[0050] Reference Figures 13A-13C An eighth insulating layer 120h and a ninth insulating layer 120i may be formed on the second insulating layer 120b, the third insulating layer 120c, the fourth insulating layer 120d, and the plurality of switching units SU. Thereafter, the eighth insulating layer 120h and the ninth insulating layer 120i may be polished and / or etched to expose the upper surface of each of the plurality of switching units SU. The eighth insulating layer 120h and the ninth insulating layer 120i may comprise silicon oxide, silicon nitride, or a combination thereof.

[0051] Reference Figures 14A-14C A tenth insulating layer 120j comprising multiple fourth recesses Rd can be formed. Each of the multiple fourth recesses Rd can extend parallel to the second direction (Y direction) and expose multiple switching units SU. That is, the tenth insulating layer 120j can be patterned as multiple lines extending parallel to the second direction (Y direction). For example, the tenth insulating layer 120j can be formed on the eighth insulating layer 120h, the ninth insulating layer 120i, and the multiple switching units SU, and then the tenth insulating layer 120j can be etched to form multiple fourth recesses Rd within it. The tenth insulating layer 120j can comprise silicon oxide, silicon nitride, or combinations thereof.

[0052] Reference Figures 15A-15C Multiple upper conductive lines 180 can be formed in multiple fourth recesses Rd within the tenth insulating layer 120j. Multiple upper conductive lines 180 can be formed using an damascene technique. That is, multiple upper conductive lines 180 can be formed after the tenth insulating layer 120j is formed. For example, an upper conductive layer can be formed on the tenth insulating layer 120j, and then the upper conductive layer can be polished and / or etched to form the upper conductive lines 180, thereby exposing the upper surface of the tenth insulating layer 120j.

[0053] According to reference Figures 12A-15CThe described method for manufacturing a memory device utilizes a mosaic technique to fabricate multiple upper conductive lines 180. Therefore, even if the aspect ratio of each of the multiple upper conductive lines 180 increases, it is possible to mitigate or prevent some or all of the upper conductive lines 180 from collapsing or breaking, wherein the aspect ratio is the ratio of the height of each of the multiple upper conductive lines 180 along a third direction (Z direction) to the width of each of the multiple upper conductive lines 180 along a first direction (X direction). Thus, a highly integrated phase-change memory device can be manufactured.

[0054] Figures 16A-18A (Right now, Figure 16A , Figure 17A and Figure 18A This is a plan view used to explain a method of manufacturing a memory device according to an exemplary embodiment of the inventive concept. Figures 16B-18B (Right now, Figure 16B , Figure 17B and Figure 18B This is a front view used to explain a method of manufacturing a memory device according to an exemplary embodiment of the inventive concept. Figures 16C-18C (Right now, Figure 16C , Figure 17C and Figure 18C This is a side view used to explain a method of manufacturing a memory device according to an exemplary embodiment of the inventive concept. According to the inventive concept... Figures 16A-18C The method for manufacturing a memory device shown in the figure includes multiple upper conductive lines 180 and multiple switching units SU (see figure). Figures 18A-18C It can be formed in a mosaic type.

[0055] Reference Figures 16A-16C For reference, please refer to Figures 1A-6C As described, multiple lower conductive lines 110, a first insulating layer 120a, a second insulating layer 120b, a third insulating layer 120c, a fourth insulating layer 120d, and multiple memory cells MU are formed.

[0056] Next, a tenth insulating layer 120j can be formed on the second insulating layer 120b, the third insulating layer 120c, and the fourth insulating layer 120d. The tenth insulating layer 120j can include a plurality of fourth recesses Rd each extending in parallel along the second direction (Y direction) and a plurality of first holes Ha connected to the plurality of fourth recesses Rd below the plurality of fourth recesses Rd and exposing the plurality of memory cells MU. The plurality of first holes Ha can be spaced apart from each other along the first direction (X direction) and the second direction (Y direction) and each extend along the third direction (Z direction). For example, the tenth insulating layer 120j can be formed on the second insulating layer 120b, the third insulating layer 120c, the fourth insulating layer 120d, and the plurality of memory cells MU, and then the plurality of fourth recesses Rd and the plurality of first holes Ha can be formed in the tenth insulating layer 120j. In some example embodiments, the plurality of fourth recesses Rd can be formed in the tenth insulating layer 120j, and then the plurality of first holes Ha can be formed in the tenth insulating layer 120j. In another example embodiment, the plurality of first holes Ha can be formed in the tenth insulating layer 120j, and then the plurality of fourth recesses Rd can be formed in the tenth insulating layer 120j.

[0057] Referring to Figures 17A-17C A plurality of switch cells SU can be formed in the plurality of first holes Ha in the tenth insulating layer 120j. For example, an upper intermediate electrode layer (not shown) can be formed on the tenth insulating layer 120j and the plurality of memory cells MU, and then the plurality of upper intermediate electrode patterns UIE can be formed by polishing and / or etching the upper intermediate electrode layer such that upper ends of the upper intermediate electrode layer are lower than bottoms of each of the plurality of fourth recesses Rd. Next, a switch layer (not shown) can be formed on the tenth insulating layer 120j and the plurality of upper intermediate electrode patterns UIE, and then the plurality of switch patterns 170 can be formed by polishing and / or etching the switch layer such that upper ends of the switch layer are lower than the bottoms of each of the plurality of fourth recesses Rd. Further, an upper electrode layer can be formed on the tenth insulating layer 120j and the plurality of switch patterns 170, and then the plurality of upper electrode patterns TE can be formed by polishing and / or etching the upper electrode layer such that the bottoms of each of the plurality of fourth recesses Rd are exposed.

[0058] Referring to Figures 18A-18C A plurality of upper conductive lines 180 can be formed in the plurality of fourth recesses Rd in the tenth insulating layer 120j. For example, an upper conductive layer (not shown) can be formed on the tenth insulating layer 120j and the plurality of switch cells SU, and then the plurality of upper conductive lines 180 can be formed by polishing and / or etching the upper conductive layer such that an upper surface of the tenth insulating layer 120j is exposed.

[0059] According to the reference Figures 16A-18CThe method of manufacturing a memory device described can be such that the plurality of switching units SU can be manufactured in a damascene type. That is, the tenth insulating layer 120j can be formed, and then the plurality of switching units SU can be formed in the plurality of first holes Ha in the tenth insulating layer 120j. Thus, even if the aspect ratio of each of the plurality of switching units SU, which is the ratio of the height of each of the plurality of switching units SU in the third direction (Z direction) to the width of each of the plurality of switching units SU in the first direction (X direction) or in the second direction (Y direction), becomes large, some or all of the plurality of switching units SU can be mitigated or prevented from collapsing or breaking. Thus, a highly integrated phase change memory device can be manufactured.

[0060] Figures 19A-21A (i.e., Figure 19A , Figure 20A and Figure 21A ) are plan views for explaining the method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 19B-21B (i.e., Figure 19B , Figure 20B and Figure 21B ) are front views for explaining the method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 19C-21C (i.e., Figure 19C , Figure 20C and Figure 21C ) are side views for explaining the method of manufacturing a memory device according to an example embodiment of the inventive concept. According to the method of manufacturing a memory device shown in Figures 19A-21C , the plurality of upper conductive lines 180 and the plurality of switching units SU can be formed using a damascene technique (see Figures 21A-21C ).

[0061] Referring to Figures 19A-19C , the plurality of lower conductive lines 110, the first insulating layer 120a, the second insulating layer 120b, the third insulating layer 120c, the fourth insulating layer 120d, and the plurality of memory units MU can be first formed as described with reference to Figures 1A-6C .

[0062] Next, an eleventh insulating layer 120k can be formed on the second insulating layer 120b, the third insulating layer 120c, and the fourth insulating layer 120d. The eleventh insulating layer 120k can include silicon oxide, silicon nitride, or a combination thereof. The eleventh insulating layer 120k can include a plurality of second holes Hb that expose the plurality of memory cells MU and each extend along the third direction (Z direction) while being spaced apart from one another along the first direction (X direction) and the second direction (Y direction). For example, the eleventh insulating layer 120k can be formed on the second insulating layer 120b, the third insulating layer 120c, the fourth insulating layer 120d, and the plurality of memory cells MU, and then the eleventh insulating layer 120k can be etched so that the plurality of second holes Hb are formed in the eleventh insulating layer 120k.

[0063] Referring to Figures 20A-20C A plurality of switching units SU can be formed in the plurality of second holes Hb in the eleventh insulating layer 120k. For example, an upper intermediate electrode layer (not shown) can be formed on the eleventh insulating layer 120k and the plurality of memory cells MU, and then the upper intermediate electrode layer can be polished and / or etched so that an upper end of the upper intermediate electrode layer is lower than an upper surface of the eleventh insulating layer 120k to form a plurality of upper intermediate electrode patterns UIE. Next, a switching layer (not shown) can be formed on the eleventh insulating layer 120k and the plurality of upper intermediate electrode patterns UIE, and then the switching layer can be polished and / or etched so that an upper end of the switching layer is lower than the upper surface of the eleventh insulating layer 120k to form a plurality of switching patterns 170. In addition, an upper electrode layer (not shown) can be formed on the eleventh insulating layer 120k and the plurality of switching patterns 170, and then the upper electrode layer can be polished and / or etched so that the upper surface of the eleventh insulating layer 120k is exposed to form a plurality of upper electrode patterns TE.

[0064] Referring to Figures 21A-21C The tenth insulating layer 120j can be formed to include a plurality of fourth recesses Rd that each extend in parallel along the second direction (Y direction) on the eleventh insulating layer 120k and expose the plurality of switching units SU. For example, the tenth insulating layer 120j can be formed on the eleventh insulating layer 120k and the plurality of switching units SU, and then the tenth insulating layer 120j can be etched to form the plurality of fourth recesses Rd in the tenth insulating layer 120j.

[0065] Next, a plurality of upper conductive lines 180 can be formed in the plurality of fourth recesses Rd in the tenth insulating layer 120j. For example, an upper conductive layer can be formed on the tenth insulating layer 120j and the plurality of switching units SU, and then the upper conductive layer can be polished and / or etched so that an upper surface of the tenth insulating layer 120j is exposed to form the plurality of upper conductive lines 180.

[0066] Figure 22A and Figure 23A is a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 22B and Figure 23B is a front view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 22C and Figure 23C is a side view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept. According to the method of manufacturing a memory device of the inventive concept shown in Figures 22A-23C , a plurality of upper conductive lines 180, a plurality of switching units SU, and a plurality of memory units MU can be formed using a damascene technique (see Figures 23A-23C ).

[0067] Referring to Figures 22A-22C , the plurality of lower conductive lines 110 and the first insulating layer 120a can be formed as described with reference to Figures 1A-1C . Next, a tenth insulating layer 120j can be formed on the plurality of lower conductive lines 110 and the first insulating layer 120a. The tenth insulating layer 120j can include a plurality of fourth recesses Rd each extending in parallel along a second direction (Y direction) and a plurality of first holes Ha connected to the plurality of fourth recesses Rd below the plurality of fourth recesses Rd and exposing the plurality of lower conductive lines 110. The plurality of first holes Ha can be spaced apart from each other along the first direction (X direction) and the second direction (Y direction), and each extend in a third direction (Z direction).

[0068] For example, the tenth insulating layer 120j can be formed on the plurality of lower conductive lines 110 and the first insulating layer 120a, and then the plurality of fourth recesses Rd and the plurality of first holes Ha can be formed in the tenth insulating layer 120j. In some example embodiments, the plurality of fourth recesses Rd can be formed in the tenth insulating layer 120j, and then the plurality of first holes Ha can be formed in the tenth insulating layer 120j. In another example embodiment, the plurality of first holes Ha can be formed in the tenth insulating layer 120j, and then the plurality of fourth recesses Rd can be formed in the tenth insulating layer 120j.

[0069] Referring to Figures 23A-23CA plurality of memory cells MU and a plurality of switching units SU can be formed in the plurality of first holes Ha in the tenth insulating layer 120j. For example, a lower electrode layer (not shown) can be formed on the tenth insulating layer 120j and the plurality of lower conductive lines 110, and then the plurality of lower electrode patterns BE can be formed by polishing and / or etching the lower electrode layer such that the upper end of the lower electrode layer is lower than the bottom of each of the plurality of fourth recesses Rd. Next, a phase change layer (not shown) can be formed on the tenth insulating layer 120j and the plurality of lower electrode patterns BE, and then the plurality of phase change patterns 160 can be formed by polishing and / or etching the phase change layer such that the upper end of the phase change layer is lower than the bottom of each of the plurality of fourth recesses Rd. Next, a lower intermediate electrode layer (not shown) can be formed on the tenth insulating layer 120j and the plurality of phase change patterns 160, and then the plurality of lower intermediate electrode patterns LIE can be formed by polishing and / or etching the lower intermediate electrode layer such that the upper end of the lower intermediate electrode layer is lower than the bottom of each of the plurality of fourth recesses Rd. The plurality of switching units SU and the plurality of upper conductive lines 180 can be formed as described with reference to Figures 17A-18C .

[0070] According to the method of manufacturing a memory device described with reference to Figures 22A-23C , the plurality of memory cells MU can be manufactured using a damascene technique. That is, the tenth insulating layer 120j can be formed first, and then the plurality of memory cells MU can be formed in the plurality of first holes Ha in the tenth insulating layer 120j. Thus, even if the aspect ratio of each of the plurality of memory cells MU, which is the ratio of the height of each of the plurality of memory cells MU in the third direction (Z direction) to the width of each of the plurality of memory cells MU in the first direction (X direction) or in the second direction (Y direction), becomes large, some or all of the plurality of memory cells MU can be prevented from collapsing or breaking. Thus, a highly integrated phase change memory device can be manufactured.

[0071] Figures 24A-26A (i.e., Figure 24A , Figure 25A and Figure 26A ) are plan views for explaining the method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 24B-26B (i.e., Figure 24B , Figure 25B and Figure 26B ) are front views for explaining the method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 24C-26C (i.e., Figure 24C , Figure 25C and Figure 26C ) are side views for explaining the method of manufacturing a memory device according to an example embodiment of the inventive concept. According to the inventive concept, Figures 24A-26CThe method of manufacturing the memory device illustrated in FIG. 10 can form the plurality of upper conductive lines 180, the plurality of switching units SU, and the plurality of memory units MU using a damascene technique (see Figures 26A-26C ).

[0072] Referring to Figures 24A-24C , the plurality of lower conductive lines 110 and the first insulating layer 120a can be formed as described with reference to Figures 1A-1C . Next, an eleventh insulating layer 120k can be formed on the plurality of lower conductive lines 110 and the first insulating layer 120a. The eleventh insulating layer 120k can include a plurality of second holes Hb that expose the plurality of lower conductive lines 110 and each extend in the third direction (Z direction) while being spaced apart from one another in the first direction (X direction) and the second direction (Y direction). For example, the eleventh insulating layer 120k can be formed on the plurality of lower conductive lines 110 and the first insulating layer 120a, and then the eleventh insulating layer 120k can be etched such that the plurality of second holes Hb can be formed in the eleventh insulating layer 120k.

[0073] Referring to Figures 25A-25C , the plurality of memory units MU and the plurality of switching units SU can be formed in the plurality of second holes Hb in the eleventh insulating layer 120k. For example, a lower electrode layer (not shown) can be formed on the eleventh insulating layer 120k and the plurality of lower conductive lines 110, and then the plurality of lower electrode patterns BE can be formed by polishing and / or etching the lower electrode layer such that upper ends of the lower electrode layer are lower than an upper surface of the eleventh insulating layer 120k. Next, a phase change layer (not shown) can be formed on the eleventh insulating layer 120k and the plurality of lower electrode patterns BE, and then the plurality of phase change patterns 160 can be formed by polishing and / or etching the phase change layer such that upper ends of the phase change layer are lower than the upper surface of the eleventh insulating layer 120k. Next, a lower intermediate electrode layer (not shown) can be formed on the eleventh insulating layer 120k and the plurality of phase change patterns 160, and then the plurality of lower intermediate electrode patterns LIE can be formed by polishing and / or etching the lower intermediate electrode layer such that upper ends of the lower intermediate electrode layer are lower than the upper surface of the eleventh insulating layer 120k. The plurality of switching units SU can be formed as described with reference to Figures 20A-20C .

[0074] Referring to Figures 26A-26C , the tenth insulating layer 120j can be formed to include a plurality of fourth recesses Rd that each extend in parallel in the second direction (Y direction) on the eleventh insulating layer 120k and expose the plurality of switching units SU. Next, the plurality of upper conductive lines 180 can be formed in the plurality of fourth recesses Rd in the tenth insulating layer 120j. The tenth insulating layer 120j and the plurality of upper conductive lines 180 can be formed as described with reference to Figures 21A-21C .

[0075] Figures 27A-29A (i.e., Figure 27A , Figure 28A and Figure 29A ) are plan views for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 27B-29B (i.e., Figure 27B , Figure 28B and Figure 29B ) are front views for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 27C-29C (i.e., Figure 27C , Figure 28C and Figure 29C ) are side views for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept. According to the method of manufacturing a memory device shown in Figures 27A-29C , a plurality of upper conductive lines 180, a plurality of switching units SU, and a plurality of memory units MU can be formed using a damascene technique (see Figures 29A-29C ).

[0076] Referring to Figures 27A-27C , the plurality of lower conductive lines 110 and the first insulating layer 120a can be formed as described with reference to Figures 1A-1C . Next, a twelfth insulating layer 120l can be formed on the plurality of lower conductive lines 110 and the first insulating layer 120a. The twelfth insulating layer 120l can include silicon oxide, silicon nitride, or a combination thereof. The twelfth insulating layer 120l can include a plurality of third holes Hc that expose the plurality of lower conductive lines 110 and each extend in a third direction (Z direction) while being spaced apart from one another in the first direction (X direction) and the second direction (Y direction). For example, the twelfth insulating layer 120l can be formed on the plurality of lower conductive lines 110 and the first insulating layer 120a, and then the twelfth insulating layer 120l can be etched so that the plurality of third holes Hc can be formed in the twelfth insulating layer 120l.

[0077] Referring to Figures 28A-28CA plurality of memory cells MU can be formed in a plurality of third holes Hc in the twelfth insulating layer 120l. For example, a lower electrode layer (not shown) can be formed on the twelfth insulating layer 120l and the plurality of lower conductive lines 110, and then a plurality of lower electrode patterns BE can be formed by polishing and / or etching the lower electrode layer such that the upper ends of the lower electrode layer are lower than the upper surface of the twelfth insulating layer 120l. Next, a phase change layer (not shown) can be formed on the twelfth insulating layer 120l and the plurality of lower electrode patterns BE, and then a plurality of phase change patterns 160 can be formed by polishing and / or etching the phase change layer such that the upper ends of the phase change layer are lower than the upper surface of the twelfth insulating layer 120l. Furthermore, a lower intermediate electrode layer (not shown) can be formed on the twelfth insulating layer 120l and the plurality of phase change patterns 160, and then a plurality of lower intermediate electrode patterns LIE can be formed by polishing and / or etching the lower intermediate electrode layer such that the upper surface of the twelfth insulating layer 120l is exposed.

[0078] Referring to Figures 29A-29C A plurality of switching units SU and a plurality of upper conductive lines 180 can be formed on the plurality of memory cells MU. An eleventh insulating layer 120k can be formed on the twelfth insulating layer 120l and a plurality of switching units SU can be formed in a plurality of second holes Hb in the eleventh insulating layer 120k. Thereafter, a tenth insulating layer 120j can be formed on the eleventh insulating layer 120k, and then a plurality of upper conductive lines 180 can be formed in a plurality of fourth recesses Rd in the tenth insulating layer 120j. The plurality of switching units SU and the plurality of upper conductive lines 180 can be formed as described with reference to Figures 19A-21C .

[0079] Figure 30A and Figure 31A are plan views for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 30B and Figure 31B are front views for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 30C and Figure 31C are side views for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept. According to the method of manufacturing a memory device shown in Figures 30A-31C , a plurality of upper conductive lines 180, a plurality of switching units SU, and a plurality of memory cells MU can be formed using a damascene technique (see Figures 31A-31C ).

[0080] Referring to Figures 30A-30C , the plurality of switching units SU and the plurality of upper conductive lines 180 can be formed as described with reference to Figures 1A-1C and Figures 27A-28CThe plurality of lower conductive lines 110, the first insulating layer 120a, the twelfth insulating layer 120l, and the plurality of memory cells MU are formed as described above. Then, the tenth insulating layer 120j including the plurality of fourth recesses Rd and the plurality of first holes Ha can be formed on the twelfth insulating layer 120l. The plurality of switch units SU can be formed in the plurality of first holes Ha in the tenth insulating layer 120j, and then the plurality of upper conductive lines 180 can be formed in the plurality of fourth recesses Rd. The plurality of switch units SU and the plurality of upper conductive lines 180 can be formed as described above with reference to Figures 16A-16C The tenth insulating layer 120j is formed as described above.

[0081] Referring to Figures 31A-31C The plurality of switch units SU can be formed in the plurality of first holes Ha in the tenth insulating layer 120j, and then the plurality of upper conductive lines 180 can be formed in the plurality of fourth recesses Rd. The plurality of switch units SU and the plurality of upper conductive lines 180 can be formed as described above with reference to Figures 17A-18C The plurality of switch units SU and the plurality of upper conductive lines 180 can be formed as described above with reference to

[0082] Figures 32A-34A (i.e., Figure 32A , Figure 33A and Figure 34A ) are plan views for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 32B-34B (i.e., Figure 32B , Figure 33B and Figure 34B ) are front views for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figures 32C-34C (i.e., Figure 32C , Figure 33C and Figure 34C ) are side views for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept. The method of manufacturing a memory device according to the inventive concept shown in Figures 32A-34C The plurality of first electrode patterns Ea, the plurality of switch patterns 170, the plurality of second electrode patterns Eb, the plurality of phase change patterns 160, and the plurality of third electrode patterns Ec can be formed using a damascene technique (see Figures 34A-34C ).

[0083] Referring to Figures 32A-32C The plurality of switch units SU can be formed in the plurality of first holes Ha in the tenth insulating layer 120j, and then the plurality of upper conductive lines 180 can be formed in the plurality of fourth recesses Rd. The plurality of switch units SU and the plurality of upper conductive lines 180 can be formed as described above with reference to Figures 1A-1CThe plurality of lower conductive lines 110 and the first insulating layers 120a are formed as described. Next, a thirteenth insulating layer 120m can be formed on the plurality of lower conductive lines 110 and the first insulating layers 120a. The thirteenth insulating layer 120m can include silicon oxide, silicon nitride, or a combination thereof. The thirteenth insulating layer 120m can include a plurality of fourth holes Hd that expose the plurality of lower conductive lines 110 and each extend in the third direction (Z direction) while being spaced apart from one another in the first direction (X direction) and the second direction (Y direction). For example, the thirteenth insulating layer 120m can be formed on the plurality of lower conductive lines 110 and the first insulating layers 120a, and then the thirteenth insulating layer 120m can be etched such that the plurality of fourth holes Hd can be formed in the thirteenth insulating layer 120m.

[0084] Referring to Figures 33A-33C The plurality of first electrode patterns Ea, the plurality of switching patterns 170, the plurality of second electrode patterns Eb, the plurality of phase change patterns 160, and the plurality of third electrode patterns Ec can be formed in the plurality of fourth holes Hd in the thirteenth insulating layer 120m. Figure 33B It is shown that the plurality of switching patterns 170 are located between the plurality of first electrode patterns Ea and the plurality of second electrode patterns Eb, and the plurality of phase change patterns 160 are formed between the plurality of second electrode patterns Eb and the plurality of third electrode patterns Ec. However, in another example embodiment, the plurality of switching patterns 170 can be located between the plurality of second electrode patterns Eb and the plurality of third electrode patterns Ec, and the plurality of phase change patterns 160 can be formed between the plurality of first electrode patterns Ea and the plurality of second electrode patterns Eb.

[0085] For example, a first electrode layer (not shown) can be formed on the thirteenth insulating layer 120m and the plurality of lower conductive lines 110, and then a plurality of first electrode patterns Ea can be formed by polishing and / or etching the first electrode layer such that the upper ends of the first electrode layer are lower than the upper surface of the thirteenth insulating layer 120m. Next, a switching layer (not shown) can be formed on the thirteenth insulating layer 120m and the plurality of first electrode patterns Ea, and then a plurality of switching patterns 170 can be formed by polishing and / or etching the switching layer such that the upper ends of the switching layer are lower than the upper surface of the thirteenth insulating layer 120m. Thereafter, a second electrode layer (not shown) can be formed on the thirteenth insulating layer 120m and the plurality of switching patterns 170, and then a plurality of second electrode patterns Eb can be formed by polishing and / or etching the second electrode layer such that the upper ends of the second electrode layer are lower than the upper surface of the thirteenth insulating layer 120m. Next, a phase change layer (not shown) can be formed on the thirteenth insulating layer 120m and the plurality of second electrode patterns Eb, and then a plurality of phase change patterns 160 can be formed by polishing and / or etching the phase change layer such that the upper ends of the phase change layer are lower than the upper surface of the thirteenth insulating layer 120m. Next, a third electrode layer (not shown) can be formed on the thirteenth insulating layer 120m and the plurality of phase change patterns 160, and then a plurality of third electrode patterns Ec can be formed by polishing and / or etching the third electrode layer such that the upper surface of the thirteenth insulating layer 120m is exposed.

[0086] The plurality of first electrode patterns Ea, the plurality of second electrode patterns Eb, and the plurality of third electrode patterns Ec can include a metal, a metal nitride, a carbon-based conductive material, or a combination thereof. For example, the plurality of first electrode patterns Ea, the plurality of second electrode patterns Eb, and the plurality of third electrode patterns Ec can include TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN, or a combination thereof.

[0087] Referring to Figures 34A-34C A fourteenth insulating layer 120n and a plurality of upper conductive lines 180 can be formed on the plurality of third electrode patterns Ec and the thirteenth insulating layer 120m. The fourteenth insulating layer 120n can include silicon oxide, silicon nitride, or a combination thereof.

[0088] In some example embodiments, the plurality of upper conductive lines 180 can be formed using a damascene technique. That is, the fourteenth insulating layer 120n can be formed to include a plurality of fifth recesses Re extending in the second direction (Y direction) and exposing the plurality of third electrode patterns Ec, and then the plurality of upper conductive lines 180 can be formed in the plurality of fifth recesses Re in the fourteenth insulating layer 120n. For example, the fourteenth insulating layer 120n can be formed on the thirteenth insulating layer 120m and the plurality of third electrode patterns Ec, and then the plurality of fourteenth insulating layers 120n can be etched to form the plurality of fifth recesses Re in the fourteenth insulating layer 120n. Next, an upper conductive layer can be formed on the plurality of third electrode patterns Ec and the fourteenth insulating layer 120n, and then the upper conductive layer can be polished and / or etched such that the upper surfaces of the fourteenth insulating layer 120n are exposed.

[0089] In another example embodiment, the plurality of upper conductive lines 180 can be formed using an etching technique. That is, the plurality of upper conductive lines 180 can be formed on the thirteenth insulating layer 120m and the plurality of third electrode patterns Ec, and then the fourteenth insulating layer 120n can be formed. For example, an upper conductive layer (not shown) can be formed on the thirteenth insulating layer 120m and the plurality of third electrode patterns Ec, and then the plurality of upper conductive lines 180 can be formed by etching the upper conductive layer such that the plurality of upper conductive lines 180 extend in parallel in the second direction (Y direction). Next, the fourteenth insulating layer 120n can be formed on the plurality of upper conductive lines 180 and the thirteenth insulating layer 120m, and then the fourteenth insulating layer 120n can be polished and / or etched such that the upper surfaces of each of the plurality of upper conductive lines 180 are exposed.

[0090] Figure 35A and Figure 36A is a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 35B and Figure 36B is a front view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 35C and Figure 36C is a side view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept. According to the method of manufacturing a memory device shown in Figures 35A-36C , the plurality of first electrode patterns Ea, the plurality of switching patterns 170, the plurality of second electrode patterns Eb, the plurality of phase change patterns 160, the plurality of third electrode patterns Ec, and the plurality of upper conductive lines 180 can be formed using a damascene technique (see Figures 36A-36C ).

[0091] Referring to Figures 35A-35C , the plurality of upper conductive lines 180 can be formed as described with reference to Figures 1A-1CThe plurality of lower conductive lines 110 and the first insulating layer 120a are formed as described. Next, a fourteenth insulating layer 120n can be formed on the plurality of lower conductive lines 110 and the first insulating layer 120a. The fourteenth insulating layer 120n can include a plurality of fifth recesses Re each extending in parallel along the second direction (Y direction) and a plurality of fifth holes He connected to the plurality of fifth recesses Re below the plurality of fifth recesses Re and exposing the plurality of lower conductive lines 110. The plurality of fifth holes He can be spaced apart from each other along the first direction (X direction) and the second direction (Y direction), and can each extend along the third direction (Z direction).

[0092] Referring to Figures 36A-36C The plurality of first electrode patterns Ea, the plurality of switching patterns 170, the plurality of second electrode patterns Eb, the plurality of phase change patterns 160, and the plurality of third electrode patterns Ec can be formed in the plurality of fifth holes He in the fourteenth insulating layer 120n, and then the plurality of upper conductive lines 180 can be formed in the plurality of fifth recesses Re in the fourteenth insulating layer 120n.

[0093] For example, a first electrode layer (not shown) can be formed on the fourteenth insulating layer 120n and the plurality of lower conductive lines 110, and then the plurality of first electrode patterns Ea can be formed by polishing and / or etching the first electrode layer such that upper ends of the first electrode layer are lower than bottoms of each of the plurality of fifth recesses Re. Next, a switching layer (not shown) can be formed on the fourteenth insulating layer 120n and the plurality of first electrode patterns Ea, and then the plurality of switching patterns 170 can be formed by polishing and / or etching the switching layer such that upper ends of the switching layer are lower than bottoms of each of the plurality of fifth recesses Re. Next, a second electrode layer (not shown) can be formed on the fourteenth insulating layer 120n and the plurality of switching patterns 170, and then the plurality of second electrode patterns Eb can be formed by polishing and / or etching the second electrode layer such that upper ends of the second electrode layer are lower than bottoms of each of the plurality of fifth recesses Re. Next, a phase change layer (not shown) can be formed on the fourteenth insulating layer 120n and the plurality of second electrode patterns Eb, and then the plurality of phase change patterns 160 can be formed by polishing and / or etching the phase change layer such that upper ends of the phase change layer are lower than bottoms of each of the plurality of fifth recesses Re. Next, a third electrode layer (not shown) can be formed on the fourteenth insulating layer 120n and the plurality of phase change patterns 160, and then the plurality of third electrode patterns Ec can be formed by polishing and / or etching the third electrode layer such that bottoms of each of the fifth recesses Re are exposed. Finally, an upper conductive layer (not shown) can be formed on the fourteenth insulating layer 120n and the plurality of third electrode patterns Ec, and then the plurality of upper conductive lines 180 can be formed by polishing and / or etching the upper conductive layer such that an upper surface of the fourteenth insulating layer 120n is exposed.

[0094] Figure 37Ais a plan view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 37B is a front view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept, Figure 37C is a side view for explaining a method of manufacturing a memory device according to an example embodiment of the inventive concept. The method of manufacturing a memory device according to the inventive concept shown in Figures 37A-37C may form the plurality of first electrode patterns Ea, the plurality of switching patterns 170, the plurality of second electrode patterns Eb, the plurality of phase change patterns 160, and the plurality of third electrode patterns Ec using a damascene technique (see Figures 37A-37C ).

[0095] Referring to Figures 37A-37C , the first insulating layer 120a and the plurality of lower conductive lines 110 can be formed as described with reference to Figures 1A-1C . Next, the plurality of first electrode patterns Ea, the plurality of switching patterns 170, the plurality of second electrode patterns Eb, the plurality of phase change patterns 160, the plurality of third electrode patterns Ec, and the plurality of upper conductive lines 180 can be formed in the fifteenth insulating layer 120o, the sixteenth insulating layer 120p, the seventeenth insulating layer 120q, the eighteenth insulating layer 120r, the thirteenth insulating layer 120m, and the fourteenth insulating layer 120n using a damascene technique.

[0096] That is, the plurality of first electrode patterns Ea can be formed in the plurality of sixth holes Hf after the fifteenth insulating layer 120o having the plurality of sixth holes Hf is formed, the plurality of switching patterns 170 can be formed in the plurality of seventh holes Hg after the sixteenth insulating layer 120p having the plurality of seventh holes Hg is formed, the plurality of second electrode patterns Eb can be formed in the plurality of eighth holes Hh after the seventeenth insulating layer 120q having the plurality of eighth holes Hh is formed, the plurality of phase change patterns 160 can be formed in the plurality of ninth holes Hi after the eighteenth insulating layer 120r having the plurality of ninth holes Hi is formed, the plurality of third electrode patterns Ec can be formed in the plurality of fourth holes Hd after the thirteenth insulating layer 120m having the plurality of fourth holes Hd is formed, and then the plurality of upper conductive lines 180 can be formed in the plurality of fifth recesses Re after the fourteenth insulating layer 120n having the plurality of fifth recesses Re is formed.

[0097] For example, a fifteenth insulating layer 120o can be formed on the plurality of lower conductive lines 110 and the first insulating layer 120a, and then the fifteenth insulating layer 120o can be etched to form a plurality of sixth holes Hf which can be spaced apart from each other along the first direction (X direction) and the second direction (Y direction) and extend along the third direction (Z direction) and expose the plurality of lower conductive lines 110. Thereafter, a first electrode layer can be formed on the fifteenth insulating layer 120o and the plurality of lower conductive lines 110, and then a plurality of first electrode patterns Ea can be formed in the plurality of sixth holes Hf by polishing and / or etching the first electrode layer such that the upper surface of the fifteenth insulating layer 120o is exposed. Next, a sixteenth insulating layer 120p can be formed on the fifteenth insulating layer 120o and the plurality of first electrode patterns Ea, and then the sixteenth insulating layer 120p can be etched to form a plurality of seventh holes Hg which expose the plurality of first electrode patterns Ea, the plurality of seventh holes Hg being spaced apart from each other along the first direction (X direction) and along the second direction (Y direction) and each extending along the third direction (Z direction). Thereafter, a switching layer can be formed on the sixteenth insulating layer 120p and the plurality of first electrode patterns Ea, and then a plurality of switching patterns 170 can be formed in the seventh holes Hg by polishing and / or etching the switching layer such that the upper surface of the sixteenth insulating layer 120p is exposed. In addition, a seventeenth insulating layer 120q can be formed on the sixteenth insulating layer 120p and the plurality of switching patterns 170, and then the seventeenth insulating layer 120q can be etched to form a plurality of eighth holes Hh which expose the plurality of switching patterns 170, the plurality of eighth holes Hh being spaced apart from each other along the first direction (X direction) and along the second direction (Y direction) and each extending along the third direction (Z direction). Thereafter, a second electrode layer can be formed on the seventeenth insulating layer 120q and the plurality of switching patterns 170, and then a plurality of second electrode patterns Eb can be formed in the plurality of eighth holes Hh by polishing and / or etching the second electrode layer such that the upper surface of the seventeenth insulating layer 120q is exposed. Next, an eighteenth insulating layer 120r can be formed on the seventeenth insulating layer 120q and the plurality of second electrode patterns Eb, and then the eighteenth insulating layer 120r can be etched to form a plurality of ninth holes Hi which expose the plurality of second electrode patterns Eb, the plurality of ninth holes Hi being spaced apart from each other along the first direction (X direction) and along the second direction (Y direction) and each extending along the third direction (Z direction). Thereafter, a phase change layer can be formed on the eighteenth insulating layer 120r and the plurality of second electrode patterns Eb, and then a plurality of phase change patterns 160 can be formed in the ninth holes Hi by polishing and / or etching the phase change layer such that the upper surface of the eighteenth insulating layer 120r is exposed.In addition, the thirteenth insulating layer 120m can be formed on the eighteenth insulating layer 120r and the plurality of phase change patterns 160, and then the thirteenth insulating layer 120m can be etched to form a plurality of fourth holes Hd exposing the plurality of phase change patterns 160, the plurality of fourth holes Hd being spaced apart from each other along the first direction (X direction) and along the second direction (Y direction) and each extending along the third direction (Z direction). Thereafter, the third electrode layer can be formed on the thirteenth insulating layer 120m and the plurality of phase change patterns 160, and then the third electrode layer can be polished and / or etched so that the upper surface of the thirteenth insulating layer 120m is exposed to form a plurality of third electrode patterns Ec in the plurality of fourth holes Hd. Next, the fourteenth insulating layer 120n can be formed on the thirteenth insulating layer 120m and the plurality of third electrode patterns Ec, and then the fourteenth insulating layer 120n can be etched to form a plurality of fifth recesses Re exposing the plurality of third electrode patterns Ec, the plurality of fifth recesses Re each extending along the second direction (Y direction). Thereafter, the upper electrode layer can be formed on the fourteenth insulating layer 120n and the plurality of third electrode patterns Ec, and then the upper electrode layer can be polished and / or etched so that the upper surface of the fourteenth insulating layer 120n is exposed to form the upper conductive line 180 in the plurality of fifth recesses Re.

[0098] As described with reference to FIGS. 1 to 6, some example embodiments of the inventive concept can include the steps of forming the lower conductive line 110; forming at least one insulating layer (e.g., the thirteenth insulating layer 120m to the eighteenth insulating layer 120r) including at least one hole (e.g., the fourth hole Hd to the ninth hole Hi) on the lower conductive line 110; forming the first electrode pattern Ea, the switching pattern 170, the second electrode pattern Eb, the phase change pattern 160, and the third electrode pattern Ec in the at least one hole (e.g., the fourth hole Hd to the ninth hole Hi) in the at least one insulating layer (e.g., the thirteenth insulating layer 120m to the eighteenth insulating layer 120r); and forming the upper conductive line 180 on the third electrode pattern Ec. Figures 32A-37C In some example embodiments of the inventive concept, it can not be necessary to form all of the at least one insulating layer (e.g., the thirteenth insulating layer 120m to the eighteenth insulating layer 120r) and then to form all of the first electrode pattern Ea, the switching pattern 170, the second electrode pattern Eb, the phase change pattern 160, and the third electrode pattern Ec. For example, as described with reference to FIGS. 1 to 6, the fifteenth insulating layer 120o, the first electrode pattern Ea, the sixteenth insulating layer 120p, the switching pattern 170, the seventeenth insulating layer 120q, the second electrode pattern Eb, the eighteenth insulating layer 120r, the phase change pattern 160, the thirteenth insulating layer 120m, and the third electrode pattern Ec can be formed in this order.

[0099] Figures 37A-37C In some example embodiments of the inventive concept, it can not be necessary to form all of the at least one insulating layer (e.g., the thirteenth insulating layer 120m to the eighteenth insulating layer 120r) and then to form all of the first electrode pattern Ea, the switching pattern 170, the second electrode pattern Eb, the phase change pattern 160, and the third electrode pattern Ec. For example, as described with reference to FIGS. 1 to 6, the fifteenth insulating layer 120o, the first electrode pattern Ea, the sixteenth insulating layer 120p, the switching pattern 170, the seventeenth insulating layer 120q, the second electrode pattern Eb, the eighteenth insulating layer 120r, the phase change pattern 160, the thirteenth insulating layer 120m, and the third electrode pattern Ec can be formed in this order. ​

[0100] While the inventive concept has been particularly shown and described with reference to some example embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the claims.

Claims

1. A method of manufacturing a memory device, the method comprising the steps of: forming a plurality of lower conductive lines on a substrate; forming a plurality of memory cells on the plurality of lower conductive lines; forming a switching stack defining a plurality of first lines extending in parallel in a first direction over the plurality of memory cells, wherein the switching stack comprises an upper intermediate electrode layer, a switching layer, and an upper electrode layer, and wherein the switching layer is formed on the upper intermediate electrode layer; forming an upper conductive layer on the switching stack; forming an etching mask defining a plurality of second lines extending in parallel in a second direction on the upper conductive layer, the second direction being different from the first direction; and forming a plurality of upper conductive lines and a plurality of switching cells by etching the upper conductive layer and the switching stack using the etching mask, and wherein the step of forming the switching stack comprises forming a fourth insulating layer on the first insulating layer, the second insulating layer, the third insulating layer, and the plurality of memory cells, forming a plurality of first recesses extending in parallel in the first direction and exposing the first insulating layer, the second insulating layer, and the plurality of memory cells in the fourth insulating layer, and forming the upper intermediate electrode layer, the switching layer, and the upper electrode layer in the plurality of first recesses in the fourth insulating layer.

2. The method of fabricating a memory device of claim 1, wherein, The step of forming the plurality of memory cells comprises: forming the first insulating layer including a plurality of second recesses extending in parallel on the plurality of lower conductive lines and exposing the plurality of lower conductive lines, and forming a lower electrode layer in the plurality of second recesses.

3. The method of fabricating a memory device of claim 2, wherein, The step of forming the plurality of memory cells further comprises: forming a material layer for forming a second insulating layer on the lower electrode layer, and forming a plurality of lower electrode patterns and the second insulating layer by polishing the lower electrode layer and the material layer for forming the second insulating layer such that an upper surface of the first insulating layer is exposed.

4. The method of fabricating a memory device of claim 3, wherein, The step of forming the plurality of memory cells further comprises forming a spacer layer between the lower electrode layer and the material layer for forming the second insulating layer.

5. The method of fabricating a memory device of claim 3, wherein, The step of forming the plurality of memory cells further comprises: etching an upper portion of each of the plurality of lower electrode patterns, and forming a plurality of phase change patterns between the first insulating layer and the second insulating layer and over a corresponding one of the plurality of lower electrode patterns, respectively.

6. The method of fabricating a memory device of claim 5, wherein, The step of forming the plurality of memory cells further comprises forming a plurality of lower intermediate electrode patterns between the first insulating layer and the second insulating layer and over a corresponding one of the plurality of phase change patterns, respectively.

7. The method of fabricating a memory device of claim 3, wherein, Two adjacent memory cells of the plurality of memory cells share one of the plurality of lower electrode patterns.

8. A method of manufacturing a memory device, the method comprising the steps of: forming a plurality of lower conductive lines; forming a plurality of memory cells on the plurality of lower conductive lines; forming a plurality of switching cells on the plurality of memory cells; forming a plurality of upper conductive lines on the plurality of switching cells; and forming a first insulating layer including a plurality of first recesses extending in parallel, wherein the plurality of upper conductive lines are formed in the plurality of first recesses in the first insulating layer after the first insulating layer is formed, ​ The forming of the first insulating layer includes forming a first insulating layer including a plurality of first holes connected to the plurality of first recesses, and The forming of the plurality of switch units is performed after the forming of the first insulating layer in the plurality of first holes in the first insulating layer.

9. The method of fabricating a memory device of claim 8, wherein, The plurality of first holes are formed after the plurality of first recesses are formed.

10. The method of fabricating a memory device of claim 8, wherein, The plurality of first holes are formed before the plurality of first recesses are formed.

11. The method of claim 8, further comprising the steps of: forming a third insulating layer including a plurality of second recesses extending in parallel and exposing the plurality of lower conductive lines, wherein the forming of the plurality of memory units is performed after the forming of the third insulating layer in the plurality of second recesses in the third insulating layer.

12. The method of claim 8, further comprising the steps of: forming a third insulating layer including a plurality of third holes, wherein the forming of the plurality of memory units is performed after the forming of the third insulating layer in the plurality of third holes in the third insulating layer.

13. The method of fabricating a memory device of claim 8, wherein, The forming of the plurality of memory units is performed after the forming of the first insulating layer in the plurality of first holes in the first insulating layer.

14. A method of manufacturing a memory device, the method comprising the steps of: forming a lower conductive line; forming at least one insulating layer on the lower conductive line, the at least one insulating layer including at least one hole; forming, in the at least one hole in the at least one insulating layer formed on the lower conductive line, in order, a first electrode pattern, a switch pattern, a second electrode pattern, a phase change pattern, and a third electrode pattern; and forming an upper conductive line on the third electrode pattern.

15. The method of fabricating a memory device of claim 14, wherein, The forming of the at least one insulating layer includes forming a first insulating layer including a first hole, wherein the switch pattern and the phase change pattern are formed in the first hole after the first insulating layer is formed.

16. The method of fabricating a memory device of claim 14, wherein, The forming of the at least one insulating layer includes forming a first insulating layer including a first hole and forming a second insulating layer including a second hole, and wherein the switch pattern is formed in the first hole after the first insulating layer is formed, and the phase change pattern is formed in the second hole after the second insulating layer is formed.

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