Error calibration apparatus, method, phase-locked loop and chip

Abstract

The application provides an error calibration device, method, phase-locked loop and chip. The device comprises a phase offset controller configured to input a feedback clock output by a DCO at a second time and a preset reference clock into a TDC; and an output calibrator configured to compare an actual code output by the TDC with a preset check code, and output a comparison result to the digital loop filter; wherein the actual code = a phase difference between the feedback clock output by the DCO at the second time and the preset reference clock / the unit delay of the TDC; the check code is obtained by offsetting the feedback clock output by the DCO at a first time and / or the preset reference clock by the phase offset controller to form a preset phase difference, and inputting the reference clock and the feedback clock with the preset phase difference into the TDC; and the check code = the preset phase difference / the unit delay. By comparing the actual code with the check code, the unit delay contained in both the actual code and the check code can be eliminated, so as to alleviate the jitter of the clock output by the DCO.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to an error calibration device, method, phase-locked loop, and chip. Background Technology

[0002] In a traditional phase-locked loop (PLL), the PLL typically includes: a TDC (Time to Digital Converter), a digital loop filter, a DSM (Delta Sigma Modulator), a thermal encoder, a current generator, a DCO (Digitally Controlled Oscillator), and a frequency divider.

[0003] In this circuit, the preset reference clock of the phase-locked loop (PLL) is input to the time-dividing circuit (TDC), while the signal output from the frequency divider is also input to the TDC as a feedback clock. The TDC determines the phase difference between the feedback clock and the reference clock. Since the TDC is an analog circuit module, it can divide the phase difference by the unit delay of its internal inverter to obtain the output code, which is then output to the digital loop filter for filtering. The digital loop filter outputs the filtered code to the digital signal generator (DSM) and the thermal encoder. The DSM further filters out noise from the fractional part of the filtered code and inputs it to the current generator; the thermal encoder converts the integer part of the filtered code into a thermometer code and also inputs it to the current generator. The current generator controls the oscillation of the digital control unit (DCO) based on the input parameters to adjust the clock output by the DCO. Finally, the clock output by the DCO, after adjustment, is divided by the frequency divider and then input to the TDC as the feedback clock, thus forming a closed-loop regulation until there is no phase difference between the reference clock and the feedback clock, thereby achieving phase-locked loop (PLL).

[0004] It is understandable that, because the TDC is an analog circuit module, the unit delay of its internal inverter varies with PVT ("P" for "Process," referring to the manufacturing process of the TDC, "V" for "Voltage," referring to the voltage applied during TDC operation, and "T" for "Temperature," referring to the operating temperature of the TDC). For example, when the TDC is manufactured using a slower process, its unit delay is larger, resulting in a smaller output code; when the TDC is manufactured using a faster process, its unit delay is smaller, resulting in a larger output code; when the TDC operates at a lower temperature, its unit delay is larger, resulting in a smaller output code; and when the TDC operates at a higher temperature, its unit delay is smaller, resulting in a larger output code. This variation in unit delay leads to instability in the TDC output code, and this unstable code, after the aforementioned series of processing steps, further causes significant jitter in the DCO output clock. Summary of the Invention

[0005] The purpose of this application is to provide an error calibration device, method, phase-locked loop, and chip to ensure that the output to the digital loop filter is not unstable due to the influence of unit delay changes, and to alleviate the jitter of the clock output of the DCO.

[0006] In a first aspect, embodiments of this application provide an error calibration device, the device comprising: a phase offset controller for connecting to the output terminal of the DCO in the phase-locked loop and the input terminal of the TDC; an output calibrator for connecting to the output terminal of the TDC and the input terminal of the digital loop filter in the phase-locked loop; the phase offset controller for inputting a feedback clock output by the DCO at a second time and a preset reference clock into the TDC; the output calibrator for comparing the actual code output by the TDC with a preset verification code, and outputting the comparison result to the digital loop filter; wherein, the actual code = the phase difference between the feedback clock output by the DCO at the second time and the preset reference clock / the unit delay of the TDC; the verification code is obtained by offsetting the feedback clock output by the DCO at the first time and / or the preset reference clock by the phase offset controller to form a preset phase difference, and inputting the reference clock and the feedback clock forming the preset phase difference into the TDC; the verification code = the preset phase difference / the unit delay.

[0007] In this embodiment, the output calibrator is pre-set with a verification code equal to a preset phase difference / unit delay. After being put into practical application, when the TDC output is equal to the actual code of the actual phase difference / unit delay, the output calibrator can eliminate the unit delay contained in both by comparing the actual code with the verification code. This ensures that the result output to the digital loop filter will not be unstable due to the influence of unit delay changes, and alleviates the clock jitter of the DCO output.

[0008] In conjunction with the first aspect, in a first possible implementation, the phase offset controller is configured to advance the feedback clock output by the DCO at the first moment, such that the advance-offset feedback clock is placed half a clock cycle ahead of the preset reference clock, and input the advance-offset feedback clock and the preset reference clock into the TDC; and is further configured to postpone the feedback clock output by the DCO at the first moment, such that the postponed feedback clock is placed half a clock cycle behind the preset reference clock, and input the postponed feedback clock and the preset reference clock into the TDC; the output calibrator is configured to record the first code and the second code output by the TDC, and determine the verification code based on the first code and the second code, wherein the first code = advance half a clock cycle / unit delay, and the second code = postpone half a clock cycle / unit delay.

[0009] In this embodiment, on the one hand, since the phase difference of the overall offset is a complete clock cycle, the phase difference can be used to conveniently calculate the verification code; on the other hand, since the offset is performed in half a clock cycle each time, the accuracy is relatively high, which can reduce the offset error.

[0010] In conjunction with the first possible implementation of the first aspect, in the second possible implementation, the phase offset controller includes: a state machine and a phase offset circuit; the state machine is used to output the feedback clock output by the DCO at a first moment and the preset reference clock to the phase offset circuit, and first send a first instruction to the phase offset circuit, and then send a second instruction to the phase offset circuit; the phase offset circuit is used to, after receiving the feedback clock output by the DCO at the first moment and the preset reference clock, first shift the feedback clock output by the DCO at the first moment forward according to the first instruction, and input the shifted feedback clock and the preset reference clock into the TDC, and then shift the feedback clock output by the DCO at the first moment backward according to the second instruction, and input the shifted feedback clock and the preset reference clock into the TDC; and the state machine is also used to input the feedback clock output by the DCO at the second moment and the preset reference clock into the TDC.

[0011] In this embodiment of the application, a state machine is used to specifically control the timing of the offset execution, which can ensure that the offset operation can be executed in an orderly manner.

[0012] In conjunction with the first aspect, in the third possible implementation, the phase offset controller is configured to shift the feedback clock output by the DCO at the first moment forward and shift the preset reference clock backward, such that the feedback clock shifted forward is placed half a clock cycle ahead of the reference clock shifted backward, and input the feedback clock shifted forward and the reference clock shifted backward into the TDC; and is further configured to shift the feedback clock output by the DCO at the first moment backward and shift the preset reference clock forward, such that the feedback clock shifted backward is placed half a clock cycle behind the reference clock shifted forward, and input the feedback clock shifted backward and the reference clock shifted forward into the TDC;

[0013] The output calibrator is used to record the first code and the second code of the TDC output, and to determine the verification code based on the first code and the second code, wherein the first code = half a clock cycle before the unit delay, and the second code = half a clock cycle after the unit delay.

[0014] In this embodiment, on the one hand, since the phase difference of the overall offset is a complete clock cycle, the phase difference can be used to conveniently calculate the verification code; on the other hand, since the offset is performed in half a clock cycle each time, the accuracy is relatively high, which can reduce the offset error.

[0015] In conjunction with the first aspect, in the fourth possible implementation, the phase offset controller is configured to offset the preset reference clock backward, such that the feedback clock output by the DCO at the first moment is placed half a clock cycle before the offset reference clock, and input the feedback clock output by the DCO and the offset reference clock into the TDC; and is further configured to offset the preset reference clock forward, such that the feedback clock output by the DCO at the first moment is placed half a clock cycle after the offset reference clock, and input the feedback clock output by the DCO at the first moment and the offset reference clock into the TDC; the output calibrator is configured to record the first code and the second code output by the TDC, and determine the verification code based on the first code and the second code, wherein the first code = half a clock cycle before / the unit delay, and the second code = half a clock cycle after / the unit delay.

[0016] In this embodiment, on the one hand, since the phase difference of the overall offset is a complete clock cycle, the phase difference can be used to conveniently calculate the verification code; on the other hand, since the offset is performed in half a clock cycle each time, the accuracy is relatively high, which can reduce the offset error.

[0017] In a fifth possible implementation, combining any of the first to fourth possible implementations of the first aspect, the output calibrator includes: a memory, a subtractor, a divider, and a multiplier. The memory is connected to both the subtractor and the phase offset controller, and the subtractor is connected to the divider. The memory is also connected to the output of the TDC, the divider is connected to the output of the TDC, and the multiplier is connected to the input of the digital loop filter. The memory stores the first code and the second code, and outputs the first code and the second code to the subtractor based on the control of the phase offset controller. The subtractor subtracts the first code from the second code to obtain the check code and outputs the check code to the divider. The divider divides the check code by the actual code to obtain a quotient and outputs the quotient to the multiplier. The multiplier multiplies the quotient by a preset value to obtain the result and outputs the result to the digital loop filter.

[0018] In this embodiment, the calculation of the verification code and the actual code is performed by setting up various computing circuits in the hardware, which is highly efficient and does not consume software resources.

[0019] Secondly, embodiments of this application provide an error calibration method, the method comprising: inputting a feedback clock output by a digital loop controller (DCO) at a second time moment and a preset reference clock into a digital loop controller (TDC) in the PLL; comparing the actual code output by the TDC with a preset verification code, and outputting the comparison result to a digital loop filter in the PLL; wherein, the actual code = the phase difference between the feedback clock output by the DCO at the second time moment and the preset reference clock / the unit delay of the TDC; the verification code is obtained by offsetting the feedback clock output by the DCO at a first time moment and / or the preset reference clock to form a preset phase difference, and inputting the reference clock and the feedback clock forming the preset phase difference into the TDC; the verification code = the preset phase difference / the unit delay.

[0020] In conjunction with the second aspect, in the first possible implementation, the step of determining the verification code includes: shifting the feedback clock output by the DCO at the first moment forward, such that the shifted feedback clock is placed half a clock cycle ahead of the preset reference clock, and inputting the shifted feedback clock and the preset reference clock into the TDC; and shifting the feedback clock output by the DCO at the first moment backward, such that the shifted feedback clock is placed half a clock cycle behind the preset reference clock, and inputting the shifted feedback clock and the preset reference clock into the TDC; recording the first code and the second code output by the TDC, and determining the verification code based on the first code and the second code, wherein the first code = half a clock cycle ahead / the unit delay, and the second code = half a clock cycle behind / the unit delay.

[0021] In conjunction with the second aspect, in the second possible implementation, the step of determining the verification code includes: shifting the feedback clock output by the DCO at the first moment forward and shifting the preset reference clock backward, such that the feedback clock shifted forward is placed half a clock cycle ahead of the reference clock shifted backward, and inputting the feedback clock shifted forward and the reference clock shifted backward into the TDC; and shifting the feedback clock output by the DCO at the first moment backward and shifting the preset reference clock forward, such that the feedback clock shifted backward is placed half a clock cycle behind the reference clock shifted forward, and inputting the feedback clock shifted backward and the reference clock shifted forward into the TDC; recording the first code and the second code output by the TDC, and determining the verification code based on the first code and the second code, wherein the first code = half a clock cycle forward / the unit delay, and the second code = half a clock cycle backward / the unit delay.

[0022] In conjunction with the second aspect, in the third possible implementation, the step of determining the verification code includes: shifting the preset reference clock backward, such that the feedback clock output by the DCO at the first moment is placed half a clock cycle before the shifted reference clock, and inputting the feedback clock output by the DCO and the shifted reference clock into the TDC; and shifting the preset reference clock forward, such that the feedback clock output by the DCO at the first moment is placed half a clock cycle after the shifted reference clock, and inputting the feedback clock output by the DCO at the first moment and the shifted reference clock into the TDC; recording the first code and the second code output by the TDC, and determining the verification code based on the first code and the second code, wherein the first code = half a clock cycle before / the unit delay, and the second code = half a clock cycle after / the unit delay.

[0023] In a fourth possible implementation, combining the second aspect or any of the first to third possible implementations of the second aspect, comparing the actual code output by the TDC with a preset check code and outputting the comparison result to the digital loop filter in the phase-locked loop includes: dividing the check code by the actual code to obtain a quotient; multiplying the quotient by a preset value to obtain the result; and outputting the result to the digital loop filter.

[0024] Thirdly, embodiments of this application provide a phase-locked loop (PLL), comprising: an output calibrator, a digital clock oscillator (DCO), and a digital loop filter (TDC); the output calibrator is connected to the output terminal of the TDC and the input terminal of the digital loop filter; the output terminal of the DCO is connected to the input terminal of the TDC; and the digital loop filter is connected to the input terminal of the DCO. The DCO is used to output a feedback clock to the TDC at a second time. The TDC is used to determine the actual code based on the feedback clock and a preset reference clock, and output the actual code to the output calibrator. The output calibrator is used to compare the actual code with a preset reference clock. The verification code is compared, and the comparison result is output to the digital loop filter; wherein, the actual code = the phase difference between the feedback clock output by the DCO at the second time and the preset reference clock / the unit delay of the TDC; the verification code is obtained by offsetting the feedback clock output by the DCO at the first time and / or the preset reference clock to form a preset phase difference, and inputting the reference clock and feedback clock forming the preset phase difference into the TDC; the verification code = the preset phase difference / the unit delay; the digital loop filter is used to filter the result and input it to the DCO to adjust the output of the DCO.

[0025] In conjunction with the third aspect, in the first possible implementation, the phase-locked loop further includes: a phase offset controller, which is connected to the output of the DCO and the input of the TDC; the phase offset controller is used to offset the feedback clock and / or the preset reference clock output by the DCO at a first moment to form a preset phase difference, and input the reference clock and feedback clock forming the preset phase difference into the TDC.

[0026] Fourthly, embodiments of this application provide a non-volatile computer-readable storage medium storing program code that, when executed by a computer, performs the error calibration method as described in the second aspect or any possible implementation thereof. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A first structural block diagram of an error calibration device provided in an embodiment of this application;

[0029] Figure 2 A second structural block diagram of an error calibration device provided in an embodiment of this application;

[0030] Figure 3A A first waveform diagram of clock offset in an error calibration device provided in an embodiment of this application;

[0031] Figure 3B A second waveform diagram of clock offset in an error calibration device provided in an embodiment of this application;

[0032] Figure 4A A third waveform diagram of clock offset in an error calibration device provided in an embodiment of this application;

[0033] Figure 4B A fourth waveform diagram of clock offset in an error calibration device provided in an embodiment of this application;

[0034] Figure 5A A fifth waveform diagram of clock offset in an error calibration device provided in an embodiment of this application;

[0035] Figure 5BThe sixth waveform diagram of clock offset in an error calibration device provided in this application embodiment;

[0036] Figure 6 A first structural block diagram of a phase-locked loop provided in an embodiment of this application;

[0037] Figure 7 This is a second structural block diagram of a phase-locked loop provided in an embodiment of this application. Detailed Implementation

[0038] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0039] Please see Figure 1 This application provides an error calibration device 100, which can be applied to a phase-locked loop (PLL). The error calibration device 100 may include a phase offset controller 110 and an output calibrator 120. The phase offset controller 110 is connected to the output of the digital circuit controller (DCO) and the input of the digital circuit controller (TDC) in the PLL (in fact, the phase offset controller 110 is not directly connected to the DCO, but indirectly connected through a frequency divider). The output calibrator 120 is connected to the output of the TDC and the digital loop filter in the PLL.

[0040] In this embodiment, the error calibration device 100 achieves calibration by first inputting a clock with a preset phase difference to the TDC to obtain a verification code output by the TDC, which is formed by the preset phase difference / the unit delay of the inverter within the TDC. In subsequent applications, by dividing this verification code by the actual code output by the TDC in the actual application, the unit delay is eliminated. This ensures that the result after comparison, when input to the digital loop filter, will not become unstable due to changes in the unit delay, and also alleviates the jitter of the clock output by the DCO.

[0041] Furthermore, in order to achieve the above-mentioned technical effects, the error calibration device 100 can determine the verification code in the preparation stage before it is put into actual application. The preparation stage can be carried out before the error calibration device 100 leaves the factory, or it can be carried out each time the error calibration device 100 is used in actual application, or it can be carried out every time the PVT of TDC changes.

[0042] Regarding the preparation stage: The phase offset controller 110 can offset the feedback clock and / or the preset reference clock output by the DCO at the first moment to form a preset phase difference, and then input the reference clock and feedback clock that form the preset phase difference into the TDC. The feedback clock output by the DCO at the first moment is actually the feedback clock output by the DCO through the frequency divider. For ease of understanding, the feedback clock output by the DCO through the frequency divider will be uniformly described as the feedback clock output by the DCO at the first moment.

[0043] The output calibrator 120 records the verification code of the TDC output, wherein the verification code = the preset phase difference / the unit delay of the inverter in the TDC.

[0044] Furthermore, after completing the preparation phase, the error calibration device 100 can then enter the practical application phase.

[0045] Regarding the practical application stage: the phase offset controller 110 is used to input the feedback clock output by the DCO at the second moment and the preset reference clock back into the TDC;

[0046] The output calibrator 120 compares the actual code output by the TDC with the check code, and outputs the comparison result to the digital loop filter. The actual code is the actual phase difference between the feedback clock output by the DCO at the second time and the preset reference clock, divided by a unit delay.

[0047] It can be understood that the output calibrator 120 stores a verification code equal to the preset phase difference / unit delay during the preparation stage. After being put into practical application, when the TDC output is equal to the actual code of the actual phase difference / unit delay, the output calibrator 120 can eliminate the unit delay contained in both by comparing the actual code with the verification code. This ensures that the result output to the digital loop filter will not be unstable due to the influence of the unit delay change, and alleviates the clock jitter of the DCO output.

[0048] It should also be noted that the first moment is a certain moment in the preparation phase, while the second moment is a certain moment in the actual application phase, and both can be selected according to actual needs.

[0049] The principle of the error calibration device 100 will be explained in detail below, from the preparation stage and the actual application stage.

[0050] 1. Regarding the preparation stage:

[0051] In this embodiment, for ease of calculation, the preset phase difference can be one clock cycle. To ensure high accuracy of the offset, the phase offset controller 110 can perform two offsets in half a clock cycle to combine and form a preset phase difference of one clock cycle.

[0052] As a first exemplary method of offsetting by half a clock cycle, in each of the two offsets, the phase offset controller 110 may offset only the feedback clock output by the DCO at the first moment.

[0053] For example, the phase offset controller 110 is used to advance the feedback clock output by the DCO at the first moment, so that the advance-offset feedback clock is half a clock cycle ahead of a preset reference clock, and input the advance-offset feedback clock and the preset reference clock into the TDC.

[0054] The phase offset controller 110 is also used to offset the feedback clock output by the DCO at the first moment, so that the offset feedback clock is placed half a clock cycle after the preset reference clock, and input the offset feedback clock and the preset reference clock into the TDC.

[0055] In this way, the first half clock cycle and the second half clock cycle together achieve an overall offset of one clock cycle.

[0056] Please see Figure 2 As a specific method for implementing the two offsets, since two offsets are involved, a phase offset controller 110 is needed to control the timing of the two offsets. Therefore, the phase offset controller 110 may include a state machine 111 and a phase offset circuit 112 connected to the state machine 111. The state machine 111 can be connected to the TDC and DCO respectively, while the phase offset circuit 112 is connected to the TDC.

[0057] State machine 111 is used to control the timing of phase offset circuit 112 to perform two half-clock cycle offsets sequentially through preset control logic. For example, after receiving the feedback clock output by DCO at the first moment and the preset reference clock, state machine 111 outputs the feedback clock output by DCO at the first moment and the preset reference clock to phase offset circuit 112 according to the preset control logic. Then, state machine 111 sends a first instruction to phase offset circuit 112 to instruct phase offset circuit 112 to perform the first half-clock cycle offset, and then sends a second instruction to phase offset circuit 112 to instruct phase offset circuit 112 to perform the second half-clock cycle offset. For ease of control, both the first and second instructions are digital signals.

[0058] It should be noted that the interval between sending the first instruction and the second instruction can be set to be longer, so as to ensure that the phase offset circuit 112 has completed the first half-clock cycle offset according to the first instruction before sending the second instruction.

[0059] Correspondingly, the phase offset circuit 112 is used to sequentially shift the feedback clock output by the DCO at the first moment forward and backward according to the first instruction and the second instruction received in sequence. For example, the phase offset circuit 112 first receives the feedback clock output by the DCO at the first moment and the preset reference clock from the state machine 111; then, the phase offset circuit 112 first receives the first instruction sent by the state machine 111, and under the trigger of the first instruction, shifts the feedback clock output by the DCO at the first moment forward relative to the preset reference clock, so that the shifted feedback clock is half a clock cycle ahead of the preset reference clock. During the shift process, the phase offset circuit 112 can continuously detect the phase difference change between the shifted feedback clock and the preset reference clock. When the phase difference change reaches half a clock cycle ahead, the shift stops; after completing the first shift, the phase offset circuit 112 inputs the shifted feedback clock and the preset reference clock into the TDC. Subsequently, the phase offset circuit 112 receives a second instruction from the state machine 111. Triggered by the second instruction, it shifts the feedback clock output by the DCO at the first moment backward relative to the preset reference clock, so that the shifted feedback clock is placed half a clock cycle behind the preset reference clock. During the shift process, the phase offset circuit 112 can also continuously detect the phase difference change between the shifting feedback clock and the preset reference clock. When the phase difference change is detected to be half a clock cycle behind, the shift stops. After the second shift is completed, the phase offset circuit 112 inputs the shifted feedback clock and the preset reference clock into the TDC.

[0060] In this embodiment, after receiving the feedback clock of the leading offset and the preset reference clock output by the phase offset circuit 112, the TDC can determine a phase difference of half a clock cycle in advance. Since the feedback clock of the leading offset is half a clock cycle in advance of the preset reference clock, the TDC determines this phase difference to be positive. The TDC divides this positive phase difference by its own preset unit delay to determine a positive first code, which is then output to the output calibrator 120. Subsequently, after receiving the feedback clock of the trailing offset and the preset reference clock output by the phase offset circuit 112, the TDC can determine a phase difference of half a clock cycle in the trailing offset. Since the feedback clock of the trailing offset is half a clock cycle behind the preset reference clock, the TDC determines this phase difference to be negative. The TDC divides this negative phase difference by its own preset unit delay to determine a negative second code, which is then output to the output calibrator 120.

[0061] Please see Figure 3A and Figure 3BThe following example illustrates this solution.

[0062] Assumption 1: When the phase-locked loop is in a state of near-lock but not fully locked, calibration begins. The feedback clock output by the DCO at the first moment is almost in phase with the preset reference clock. Then, triggered by the first command, the phase shift circuit 112 does not adjust the preset reference clock, but shifts the feedback clock output by the DCO at the first moment forward by a phase difference of T / 2 along the V1 direction, so that the shifted feedback clock is half a clock cycle T / 2 ahead of the preset reference clock, where T is the clock frequency period output by the DCO. Afterwards, triggered by the second command, the phase shift circuit 112 does not adjust the preset reference clock, but shifts the feedback clock output by the DCO at the first moment backward by a phase difference of T / 2 along the V2 direction, so that the backward-shifted feedback clock is half a clock cycle T / 2 ahead of the preset reference clock.

[0063] In this embodiment, as a second exemplary method of offsetting by half a clock cycle, in each of the two offsets, the phase offset controller 110 offsets both the feedback clock output by the DCO at the first moment and the preset reference clock.

[0064] For example, the phase offset controller 110 is used to advance the feedback clock output by the DCO at the first moment and advance the preset reference clock, so that the advance-offset feedback clock is placed half a clock cycle ahead of the advance-offset reference clock, and input the advance-offset feedback clock and the advance-offset reference clock into the TDC.

[0065] Furthermore, the phase offset controller 110 is also used to offset the feedback clock output by the DCO at the first moment backward and offset the preset reference clock forward, so that the feedback clock of the backward offset is placed half a clock cycle after the reference clock of the forward offset, and input the feedback clock of the backward offset and the reference clock of the forward offset into the TDC.

[0066] In this way, the first half clock cycle and the second half clock cycle together achieve an overall offset of one clock cycle.

[0067] Please also see Figure 2 As a specific method for implementing two offsets, since two offsets are involved, a phase offset controller 110 is also needed to control the timing of the two offsets. Therefore, the phase offset controller 110 may also include a state machine 111 and a phase offset circuit 112 connected to the state machine 111. The state machine 111 can be connected to the TDC and DCO respectively, while the phase offset circuit 112 is connected to the TDC.

[0068] State machine 111 is also used to control the timing of phase offset circuit 112 to perform two half-clock cycle offsets sequentially through preset control logic. For example, after receiving the feedback clock output by DCO at the first moment and the preset reference clock, state machine 111 outputs the feedback clock output by DCO at the first moment and the preset reference clock to phase offset circuit 112 according to the preset control logic. Then, state machine 111 sends a first instruction to phase offset circuit 112 to instruct phase offset circuit 112 to perform the first half-clock cycle offset, and then sends a second instruction to phase offset circuit 112 to instruct phase offset circuit 112 to perform the second half-clock cycle offset, wherein, for ease of control, both the first instruction and the second instruction are digital signals.

[0069] It should be noted that the interval between sending the first instruction and the second instruction can be set to be longer, so as to ensure that the phase offset circuit 112 has completed the first half-clock cycle offset according to the first instruction before sending the second instruction.

[0070] Correspondingly, the phase offset circuit 112 is used to offset the feedback clock output by the DCO at the first moment and the preset reference clock twice in sequence according to the first instruction and the second instruction received successively. For example, the phase offset circuit 112 first receives the feedback clock output by the DCO at the first moment and the preset reference clock from the state machine 111; then, the phase offset circuit 112 first receives the first instruction sent by the state machine 111, and under the trigger of the first instruction, it shifts the feedback clock output by the DCO at the first moment forward relative to the preset reference clock, and shifts the preset reference clock backward relative to the feedback clock output by the DCO at the first moment, so that the feedback clock shifted forward is half a clock cycle ahead of the reference clock shifted backward. After completing the first offset, the phase offset circuit 112 inputs the shifted feedback clock and the shifted reference clock into the TDC. Subsequently, the phase shift circuit 112 receives a second instruction from the state machine 111. Triggered by the second instruction, it shifts the feedback clock output by the DCO at the first moment backward relative to a preset reference clock, and shifts the preset reference clock forward relative to the feedback clock output by the DCO at the first moment, so that the feedback clock shifted backward is placed half a clock cycle after the reference clock shifted forward. After completing the second shift, the phase shift circuit 112 inputs the feedback clock shifted backward and the reference clock shifted forward into the TDC.

[0071] In this embodiment, after receiving the feedback clock of the preceding offset and the reference clock of the following offset from the phase offset circuit 112, the TDC can determine a phase difference of half a clock cycle in advance. Furthermore, since the feedback clock of the preceding offset is half a clock cycle ahead of the reference clock of the following offset, the TDC determines this phase difference to be positive. The TDC uses this positive phase difference divided by its own preset unit delay to determine a positive first code, which is then output to the output calibrator 120. Subsequently, after receiving the feedback clock of the following offset and the reference clock of the preceding offset from the phase offset circuit 112, the TDC can determine a phase difference of half a clock cycle behind. Furthermore, since the feedback clock of the following offset is half a clock cycle behind the reference clock of the preceding offset, the TDC determines this phase difference to be negative. The TDC uses this negative phase difference divided by its own preset unit delay to determine a negative second code, which is then output to the output calibrator 120.

[0072] Please see Figure 4A and Figure 4B The following example will also illustrate this solution.

[0073] Assumption 2: When the phase-locked loop is in a state of near-lock but not fully locked, calibration begins. The feedback clock output by the DCO at the first moment is almost in phase with the preset reference clock. Then, triggered by the first command, the phase shift circuit 112 shifts the feedback clock output by the DCO at the first moment forward along the V1 direction and shifts the preset reference clock backward along the V2 direction, so that the forward-shifted feedback clock is half a clock cycle T / 2 ahead of the backward-shifted reference clock, where T is the clock frequency period output by the DCO. Subsequently, triggered by the second command, the phase shift circuit 112 shifts the feedback clock output by the DCO at the first moment backward along the V2 direction and shifts the preset reference clock forward along the V1 direction, so that the backward-shifted feedback clock is half a clock cycle T / 2 behind the forward-shifted reference clock.

[0074] In this embodiment, as a third exemplary method of offsetting by half a clock cycle, in each of the two offsets, the phase offset controller 110 may offset only the preset reference clock.

[0075] For example, the phase offset controller 110 is used to offset a preset reference clock backward, so that the feedback clock output by the DCO at the first moment is placed half a clock cycle ahead of the offset reference clock, and the feedback clock output by the DCO at the first moment and the offset reference clock are input into the TDC.

[0076] The phase offset controller 110 is also used to shift the preset reference clock forward, so that the feedback clock output by the DCO at the first moment is placed half a clock cycle after the shifted reference clock, and input the feedback clock output by the DCO at the first moment and the shifted reference clock into the TDC.

[0077] In this way, the first half clock cycle and the second half clock cycle together achieve an overall offset of one clock cycle.

[0078] Please see Figure 2 As a specific method for implementing the two offsets, since two offsets are involved, a phase offset controller 110 is also needed to control the timing of the two offsets. Therefore, the phase offset controller 110 may also include a state machine 111 and a phase offset circuit 112 connected to the state machine 111. The state machine 111 can be connected to the TDC and DCO respectively, while the phase offset circuit 112 is connected to the TDC.

[0079] State machine 111 is also used to control the timing of phase offset circuit 112 to perform two half-clock cycle offsets sequentially through preset control logic. For example, after receiving the feedback clock output by DCO at the first moment and the preset reference clock, state machine 111 outputs the feedback clock output by DCO at the first moment and the preset reference clock to phase offset circuit 112 according to the preset control logic. Then, state machine 111 sends a first instruction to phase offset circuit 112 to instruct phase offset circuit 112 to perform the first half-clock cycle offset, and then sends a second instruction to phase offset circuit 112 to instruct phase offset circuit 112 to perform the second half-clock cycle offset. For ease of control, both the first and second instructions are digital signals.

[0080] It should be noted that the interval between sending the first instruction and the second instruction can be set to be longer, so as to ensure that the phase offset circuit 112 has completed the first half-clock cycle offset according to the first instruction before sending the second instruction.

[0081] Correspondingly, the phase offset circuit 112 is used to sequentially offset the preset reference clock backward and forward based on the first and second instructions received in sequence. For example, the phase offset circuit 112 first receives the feedback clock output by the DCO at the first moment and the preset reference clock from the state machine 111; then, the phase offset circuit 112 first receives the first instruction sent by the state machine 111, and under the trigger of the first instruction, it offsets the preset reference clock backward relative to the feedback clock output by the DCO at the first moment, so that the feedback clock output by the DCO at the first moment is placed forward by half a clock cycle of the offset reference clock. After completing the first offset, the phase offset circuit 112 inputs the forward-offset reference clock and the feedback clock output by the DCO at the first moment into the TDC. Then, the phase offset circuit 112 receives the second instruction sent by the state machine 111, and under the trigger of the second instruction, it offsets the preset reference clock forward relative to the feedback clock output by the DCO at the first moment, so that the feedback clock output by the DCO at the first moment is placed backward by half a clock cycle of the forward-offset reference clock. After the second offset is completed, the phase offset circuit 112 inputs the feedback clock output by the DCO at the first moment and the reference clock of the forward offset into the TDC.

[0082] In this embodiment, after receiving the reference clock with a backward offset output from the phase offset circuit 112 and the feedback clock output from the DCO at the first moment, the TDC can determine a phase difference of half a clock cycle in advance. Furthermore, since the feedback clock output from the DCO at the first moment is half a clock cycle in advance of the reference clock with the backward offset, the TDC determines this phase difference to be positive. The TDC uses this positive phase difference divided by its own preset unit delay to determine a positive first code, which it then outputs to the output calibrator 120. Subsequently, after receiving the reference clock with a backward offset output from the phase offset circuit 112 and the feedback clock output from the DCO at the first moment, the TDC can determine a phase difference of half a clock cycle in advance. Furthermore, since the feedback clock output from the DCO at the first moment is half a clock cycle in advance of the reference clock with the backward offset, the TDC determines this phase difference to be negative. The TDC uses this negative phase difference divided by its own preset unit delay to determine a negative second code, which it then outputs to the output calibrator 120.

[0083] Please see Figure 5A and Figure 5B The following example illustrates this solution.

[0084] Assumption 3: When the phase-locked loop is in a state of near-lock but not fully locked, calibration begins. The feedback clock output by the DCO at the first moment is almost in phase with the preset reference clock. Then, triggered by the first command, the phase shift circuit 112 does not adjust the feedback clock output by the DCO at the first moment, but shifts the preset reference clock backward by a phase difference of T / 2 along the V2 direction, so that the feedback clock output by the DCO at the first moment is half a clock cycle T / 2 ahead of the shifted reference clock, where T is the clock frequency period output by the DCO. Subsequently, triggered by the second command, the phase shift circuit 112 also does not adjust the feedback clock output by the DCO at the first moment, but shifts the preset reference clock forward by a phase difference of T / 2 along the V1 direction, so that the feedback clock output by the DCO at the first moment is half a clock cycle T / 2 ahead of the shifted reference clock.

[0085] Please continue reading. Figure 2 The output calibrator 120 may include: a memory 121, a subtractor 122 connected to the memory 121, a divider 123 connected to the subtractor 122, and a multiplier 123 connected to the divider 123. The memory 121 is also connected to the output of the TDC, the divider 123 is also connected to the output of the TDC, and the multiplier 123 is connected to the input of the digital loop filter.

[0086] In this embodiment, since the memory 121 is connected to the phase offset controller 110, such as to the phase offset circuit 112 in the phase offset controller 110, the memory 121 can store the first code and the second code output by the phase offset circuit 112. Based on the control of the phase offset controller 110, for example, when a check code needs to be calculated, the memory 121 receives a third instruction sent by the state machine 111 in the phase offset controller 110. Triggered by the third instruction, the memory 121 outputs the first code and the second code to the subtractor 122. The subtractor 122 then obtains the check code by subtracting the second code from the first code and outputs the check code to the divider 123.

[0087] It should be noted that the divider 123 and the multiplier 123 operate in the practical application stage, so the principles of the divider 123 and the multiplier 123 will be introduced in the practical application stage.

[0088] It should also be noted that the method of performing two offsets in half a clock cycle in this embodiment is only one exemplary method and is not intended to limit the scope. For example, when the accuracy requirement is not very high, the phase offset controller 110 can directly perform one offset to form a preset phase difference for one clock cycle. It can be understood that since the entire process only involves one offset, the state machine 111 does not need to control the timing of the offset, and the output calibrator 120 may not include the subtractor 122 (the memory 121 is directly connected to the divider 123).

[0089] 2. For the practical application stage:

[0090] After the verification code is determined during the preparation phase, the phase offset controller 110 no longer needs to input the feedback clock output by the DCO and the preset reference clock into the TDC. Instead, it can directly input the feedback clock output by the DCO at the second moment and the preset reference clock into the TDC. For example, after receiving the feedback clock output by the DCO at the second moment, the state machine 111 inputs the feedback clock output by the DCO at the second moment and the preset reference clock into the TDC.

[0091] In this embodiment, after receiving the feedback clock output by the DCO at the second moment and the preset reference clock from the state machine 111, the TDC can determine the actual phase difference between the feedback clock output by the DCO at the second moment and the preset reference clock. By dividing the actual phase difference by its own preset unit delay, the TDC can determine the actual code and output it to the output calibrator 120.

[0092] Furthermore, since the divider 123 in the output calibrator 120 is connected to the output of the TDC, the divider 123 can receive the actual code output by the TDC. Because the divider 123 has already obtained the check code output by the subtractor 122 before receiving the actual code, after obtaining the actual code, the divider 123 can divide the check code by the actual code to obtain the quotient.

[0093] It can be understood that the quotient obtained by dividing the check code by the actual code differs significantly from the code output by the TDC with a standard unit delay. Therefore, the quotient cannot be directly input into the digital loop filter. It needs to be multiplied by multiplier 123 to be on the same dimension as the code output by the TDC with a standard unit delay before it can be output. In other words, multiplier 123 has a preset value. The quotient obtained by dividing the check code by the actual code is output to multiplier 123. Multiplier 123 multiplies this quotient by the preset value to obtain the final result, which is then output to the digital loop filter. For example, if the standard unit delay is 2ms and the phase difference determined by the TDC is 300ms, then the code output by the TDC is 150. If the check code is divided by the actual code, the value might be 27. Therefore, it needs to be multiplied by 5 to make the final output 135 and 150 on the same dimension.

[0094] Based on the same inventive concept, this application also provides an error calibration method, the process of which may include:

[0095] Step S100: Input the feedback clock output by the DCO in the phase-locked loop at the second time and the preset reference clock into the TDC in the phase-locked loop;

[0096] Step S200: Compare the actual code output by the TDC with the preset check code, and output the comparison result to the digital loop filter in the phase-locked loop;

[0097] Wherein, the actual code = the phase difference between the feedback clock output by the DCO at the second time and the preset reference clock / the unit delay of the TDC; the verification code is obtained by offsetting the feedback clock output by the DCO at the first time and / or the preset reference clock to form a preset phase difference, and inputting the reference clock and feedback clock forming the preset phase difference into the TDC; the verification code = the preset phase difference / the unit delay.

[0098] Optionally, step S200 may further include: dividing the check code by the actual code to obtain a quotient; multiplying the quotient by a preset value to obtain the result; and outputting the result to the digital loop filter.

[0099] Optionally, the step of determining the verification code includes:

[0100] Step S101: The feedback clock output by the DCO at the first moment is shifted forward by half a clock cycle to the preset reference clock, and the shifted feedback clock and the preset reference clock are input into the TDC; and the feedback clock output by the DCO at the first moment is shifted backward by half a clock cycle to the preset reference clock, and the shifted feedback clock and the preset reference clock are input into the TDC.

[0101] Step S201: Record the first code and the second code of the TDC output, and determine the verification code based on the first code and the second code, wherein the first code = half a clock cycle before the unit delay, and the second code = half a clock cycle after the unit delay.

[0102] Optionally, the step of determining the verification code further includes:

[0103] Step S301: Shift the feedback clock output by the DCO at the first moment forward and shift the preset reference clock backward, such that the feedback clock shifted forward is placed half a clock cycle ahead of the reference clock shifted backward, and input the feedback clock shifted forward and the reference clock shifted backward into the TDC; and shift the feedback clock output by the DCO at the first moment backward and shift the preset reference clock forward, such that the feedback clock shifted backward is placed half a clock cycle behind the reference clock shifted forward, and input the feedback clock shifted backward and the reference clock shifted forward into the TDC.

[0104] Step S401: Record the first code and the second code of the TDC output, and determine the verification code based on the first code and the second code, wherein the first code = half a clock cycle before the unit delay, and the second code = half a clock cycle after the unit delay.

[0105] Optionally, the step of determining the verification code further includes:

[0106] Step S501: Shift the preset reference clock backwards, such that the feedback clock output by the DCO at the first moment is placed half a clock cycle before the shifted reference clock, and input the feedback clock output by the DCO and the shifted reference clock into the TDC; and shift the preset reference clock forwards, such that the feedback clock output by the DCO at the first moment is placed half a clock cycle after the shifted reference clock, and input the feedback clock output by the DCO at the first moment and the shifted reference clock into the TDC.

[0107] Step S601: Record the first code and the second code of the TDC output, and determine the verification code based on the first code and the second code, wherein the first code = half a clock cycle before the unit delay, and the second code = half a clock cycle after the unit delay.

[0108] It should be noted that, as those skilled in the art will readily understand, for the sake of convenience and brevity, the specific working process of the method described above can be referred to the corresponding process in the foregoing device embodiments, and will not be repeated here. It should also be noted that this method can be implemented not only with the foregoing device, but also with other devices.

[0109] Please see Figure 6 Based on the same inventive concept, this application also provides a phase-locked loop 10. The phase-locked loop 10 can be applied in a chip. For example, the phase-locked loop 10 can be connected to the chip core (the chip core is the core processing circuit of the chip) in the chip. The phase-locked loop 10 may include: an output calibrator 120, a DCO 11, a TDC 12, and a digital loop filter 13.

[0110] Of course, in practical applications, the phase-locked loop 10 may also include more components, such as a DSM 14, a thermal encoder 15, a current generator 16, and a frequency divider 17.

[0111] The output calibrator 120 is connected to the output of TDC12 and the input of digital loop filter 13. The output of digital loop filter 13 is connected to the input of DSM14 and thermal encoder 15. The output of DSM14 and thermal encoder 15 are connected to the input of current generator 16. The output of current generator 16 is connected to the control terminal of DCO11. The output of DCO11 is connected to the input of TDC12 through frequency divider 17.

[0112] DCO11 is used to output the feedback clock to TDC12 via divider 17 at the second moment.

[0113] TDC12 is used to determine the actual code based on the feedback clock and the preset reference clock, and output the actual code to the output calibrator 120.

[0114] Output calibrator 120 is used to compare the actual code with a preset verification code and output the comparison result to digital loop filter 13; wherein, actual code = phase difference between the feedback clock output by DCO11 at the second time and the preset reference clock / unit delay of TDC12; verification code is obtained by offsetting the feedback clock output by DCO11 at the first time and / or the preset reference clock to form a preset phase difference, and inputting the reference clock and feedback clock forming the preset phase difference into TDC12; verification code = preset phase difference / unit delay;

[0115] Digital loop filter 13 is used to filter the result and input it into DSM 14 and thermal encoder 15.

[0116] DSM14 is used to filter out noise from the fractional part of the filtered code and then input it to the current generator 16.

[0117] The thermal encoder 15 is used to convert the integer part of the filtered code into a thermometer code, and input the thermometer code into the current generator 16.

[0118] The current generator 16 is used to control the oscillation of DCO11 based on the input parameters, so as to adjust the clock output of DCO11 and thus form a closed-loop regulation.

[0119] like Figure 7 As shown, in this embodiment, the phase-locked loop 10 may further include a phase offset controller 110, which is connected to the input terminal of the DCO 11 and the output terminal of the TDC 12.

[0120] The phase offset controller 110 is used to offset the feedback clock and / or the preset reference clock output by DCO11 at the first moment to form a preset phase difference, and input the reference clock and feedback clock that form the preset phase difference into TDC12.

[0121] It should be noted that, as those skilled in the art will clearly understand, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing device embodiments, and will not be repeated here.

[0122] Some embodiments of this application also provide a computer-readable storage medium containing computer-executable non-volatile program code. This storage medium can be a general-purpose storage medium, such as a removable disk or hard disk. The computer-readable storage medium stores program code that, when executed by a computer, performs the steps of the error calibration method of any of the above embodiments.

[0123] The error calibration method program code product provided in this application includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods in the preceding method embodiments. For specific implementation details, please refer to the method embodiments, which will not be repeated here.

[0124] In summary, the output calibrator is pre-set with a verification code equal to the preset phase difference / unit delay. After being put into practical application, when the TDC output is equal to the actual code of the actual phase difference / unit delay, the output calibrator can eliminate the unit delay contained in both by comparing the actual code with the verification code. This ensures that the result output to the digital loop filter will not be unstable due to the influence of unit delay changes, and alleviates the clock jitter of the DCO output.

[0125] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0126] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0127] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0128] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0129] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An error calibration device, characterized in that, The device includes: A phase offset controller is used to connect to the output of the DCO in the phase-locked loop and the input of the TDC. An output calibrator is used to connect to the output of the TDC and the input of the digital loop filter in the phase-locked loop. The phase offset controller is used to input the feedback clock output by the DCO at the second time and the preset reference clock into the TDC; The output calibrator is used to compare the actual code output by the TDC with a preset check code, and to multiply the comparison result with a preset value so that the result of the multiplication is on the same dimension as the code output by the TDC with a standard unit delay, and to output the result of the multiplication to the digital loop filter. Wherein, the actual code = the phase difference between the feedback clock output by the DCO at the second time and the preset reference clock / the unit delay of the TDC; the verification code is obtained by the phase offset controller offsetting the feedback clock output by the DCO at the first time and / or the preset reference clock to form a preset phase difference, and inputting the reference clock and feedback clock forming the preset phase difference into the TDC; the verification code = the preset phase difference / the unit delay.

2. The error calibration device according to claim 1, characterized in that, The phase offset controller is used to shift the feedback clock output by the DCO at the first moment forward, so that the shifted feedback clock is half a clock cycle ahead of the preset reference clock, and input the shifted feedback clock and the preset reference clock into the TDC. It is also used to offset the feedback clock output by the DCO at the first moment, so that the offset feedback clock is placed half a clock cycle after the preset reference clock, and input the offset feedback clock and the preset reference clock into the TDC. The output calibrator is used to record the first code and the second code of the TDC output, and to determine the verification code based on the first code and the second code, wherein the first code = half a clock cycle before the unit delay, and the second code = half a clock cycle after the unit delay.

3. The error calibration device according to claim 2, characterized in that, The phase offset controller includes: a state machine and a phase offset circuit; The state machine is used to output the feedback clock output by the DCO at the first moment and the preset reference clock to the phase offset circuit, and first send a first instruction to the phase offset circuit, and then send a second instruction to the phase offset circuit. The phase offset circuit is configured to, upon receiving the feedback clock output by the DCO at the first moment and the preset reference clock, first shift the feedback clock output by the DCO at the first moment forward according to the first instruction, and input the shifted feedback clock and the preset reference clock into the TDC; then, according to the second instruction, shift the feedback clock output by the DCO at the first moment backward, and input the shifted feedback clock and the preset reference clock into the TDC. Furthermore, the state machine is also used to input the feedback clock output by the DCO at the second time point and the preset reference clock into the TDC.

4. The error calibration device according to claim 1, characterized in that, The phase offset controller is used to shift the feedback clock output by the DCO at the first moment forward and shift the preset reference clock backward, so that the feedback clock shifted forward is half a clock cycle ahead of the reference clock shifted backward, and input the feedback clock shifted forward and the reference clock shifted backward into the TDC. It is also used to offset the feedback clock output by the DCO at the first moment and offset the preset reference clock forward, so that the feedback clock offset is placed half a clock cycle after the reference clock offset forward, and input the feedback clock offset and the reference clock offset forward into the TDC. The output calibrator is used to record the first code and the second code of the TDC output, and to determine the verification code based on the first code and the second code, wherein the first code = half a clock cycle before the unit delay, and the second code = half a clock cycle after the unit delay.

5. The error calibration device according to claim 1, characterized in that, The phase offset controller is used to shift the preset reference clock backward, so that the feedback clock output by the DCO at the first moment is placed half a clock cycle ahead of the shifted reference clock, and input the feedback clock output by the DCO and the shifted reference clock into the TDC. It is also used to shift the preset reference clock forward, so that the feedback clock output by the DCO at the first moment is placed half a clock cycle after the shifted reference clock, and input the feedback clock output by the DCO at the first moment and the shifted reference clock into the TDC. The output calibrator is used to record the first code and the second code of the TDC output, and to determine the verification code based on the first code and the second code, wherein the first code = half a clock cycle before the unit delay, and the second code = half a clock cycle after the unit delay.

6. The error calibration device according to any one of claims 2-5, characterized in that, The output calibrator includes a memory, a subtractor, a divider, and a multiplier. The memory is connected to both the subtractor and the phase offset controller, and the subtractor is connected to the divider. The memory is also connected to the output of the TDC, the divider is connected to the output of the TDC, and the multiplier is connected to the input of the digital loop filter. The memory is used to store the first code and the second code; and to output the first code and the second code to the subtractor based on the control of the phase offset controller; The subtractor is used to subtract the first code from the second code to obtain the check code, and output the check code to the divider; The divider is used to divide the check code by the actual code to obtain a quotient value, and output the quotient value to the multiplier; The multiplier is used to multiply the quotient by a preset value to obtain the result, and output the result to the digital loop filter.

7. An error calibration method, characterized in that, The method includes: The feedback clock output by the DCO in the phase-locked loop at the second time and the preset reference clock are input into the TDC in the phase-locked loop; The actual code output by the TDC is compared with the preset check code, and the comparison result is multiplied by the preset value so that the result of the multiplication is on the same dimension as the code output by the TDC with a standard unit delay, and the result of the multiplication is output to the digital loop filter in the phase-locked loop. Wherein, the actual code = the phase difference between the feedback clock output by the DCO at the second time and the preset reference clock / the unit delay of the TDC; the verification code is obtained by offsetting the feedback clock output by the DCO at the first time and / or the preset reference clock to form a preset phase difference, and inputting the reference clock and feedback clock forming the preset phase difference into the TDC; the verification code = the preset phase difference / the unit delay.

8. The error calibration method according to claim 7, characterized in that, The steps for determining the verification code include: The feedback clock output by the DCO at the first moment is shifted forward, such that the shifted feedback clock is placed half a clock cycle ahead of the preset reference clock, and the shifted feedback clock and the preset reference clock are input into the TDC; and the feedback clock output by the DCO at the first moment is shifted backward, such that the shifted feedback clock is placed half a clock cycle behind the preset reference clock, and the shifted feedback clock and the preset reference clock are input into the TDC. Record the first code and the second code of the TDC output, and determine the verification code based on the first code and the second code, wherein the first code = half a clock cycle before the unit delay, and the second code = half a clock cycle after the unit delay.

9. The error calibration method according to claim 7, characterized in that, The steps for determining the verification code include: The feedback clock output by the DCO at the first moment is shifted forward and the preset reference clock is shifted backward, such that the feedback clock with the forward shift is placed half a clock cycle ahead of the reference clock with the backward shift, and the feedback clock with the forward shift and the reference clock with the backward shift are input into the TDC; and the feedback clock output by the DCO at the first moment is shifted backward and the preset reference clock is shifted forward, such that the feedback clock with the backward shift is placed half a clock cycle behind the reference clock with the forward shift, and the feedback clock with the backward shift and the reference clock with the forward shift are input into the TDC. Record the first code and the second code of the TDC output, and determine the verification code based on the first code and the second code, wherein the first code = half a clock cycle before the unit delay, and the second code = half a clock cycle after the unit delay.

10. The error calibration method according to claim 7, characterized in that, The steps for determining the verification code include: The preset reference clock is shifted backward, such that the feedback clock output by the DCO at the first moment is placed half a clock cycle ahead of the shifted reference clock, and the feedback clock output by the DCO and the shifted reference clock are input into the TDC; and the preset reference clock is shifted forward, such that the feedback clock output by the DCO at the first moment is placed half a clock cycle behind the shifted reference clock, and the feedback clock output by the DCO at the first moment and the shifted reference clock are input into the TDC. Record the first code and the second code of the TDC output, and determine the verification code based on the first code and the second code, wherein the first code = half a clock cycle before the unit delay, and the second code = half a clock cycle after the unit delay.

11. The error calibration method according to any one of claims 7-10, characterized in that, The process of comparing the actual code output by the TDC with a preset check code and outputting the comparison result to the digital loop filter in the phase-locked loop includes: The quotient is obtained by dividing the verification code by the actual code; The quotient is multiplied by a preset value to obtain the result, and the result is output to the digital loop filter.

12. A phase-locked loop, characterized in that, The phase-locked loop includes: an output calibrator, a digital calibrator (DCO), a digital current collector (TDC), and a digital loop filter; the output calibrator is connected to the output terminal of the TDC and the input terminal of the digital loop filter, the output terminal of the DCO is connected to the input terminal of the TDC, and the digital loop filter is connected to the input terminal of the DCO. The DCO is used to output the feedback clock to the TDC at the second time. The TDC is used to determine the actual code based on the feedback clock and the preset reference clock, and output the actual code to the output calibrator. The output calibrator is used to compare the actual code with a preset verification code, and multiply the comparison result by a preset value so that the multiplied result is on the same dimension as the code output by the TDC with a standard unit delay, and output the multiplied result to the digital loop filter; wherein, the actual code = the phase difference between the feedback clock output by the DCO at the second time and the preset reference clock / the unit delay of the TDC; the verification code is obtained by offsetting the feedback clock output by the DCO at the first time and / or the preset reference clock to form a preset phase difference, and inputting the reference clock and feedback clock forming the preset phase difference into the TDC; the verification code = the preset phase difference / the unit delay; The digital loop filter is used to filter the result and input it into the DCO to adjust the output of the DCO.

13. The phase-locked loop according to claim 12, characterized in that, The phase-locked loop further includes a phase offset controller, which is connected to the output of the DCO and the input of the TDC. The phase offset controller is used to offset the feedback clock and / or the preset reference clock output by the DCO at the first moment to form a preset phase difference, and input the reference clock and feedback clock that form the preset phase difference into the TDC.

14. A chip, characterized in that, include: A chip core, and a phase-locked loop as described in claim 12 or 13 connected to the chip core.

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