Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a substrate (10) having a groove (100) formed on a main surface, a drift region (20) of a first conductivity type having a portion arranged at the bottom of the groove (100), a well region (30) of a second conductivity type connected to the drift region (20) and arranged on one side of the groove (100), a first semiconductor region (40) of a first conductivity type separated from the drift region (20) and arranged on the surface of the well region (30) on the side of the groove (100), a second semiconductor region (50) of a first conductivity type arranged in the groove (100) opposite to the well region (30) with the drift region (20) interposed therebetween, and a gate electrode (60) arranged in a gate trench having an opening formed on the upper surfaces of the well region (30) and the first semiconductor region (40) and extending in the depth direction of the groove (100) and opposite to the well region (30).

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In order to improve the performance of semiconductor devices, technical development has been carried out. For example, a semiconductor device has been disclosed, which forms a drain region at the bottom of a groove formed in a part of the surface layer of a semiconductor substrate in order to reduce the size of the unit cell to improve the trade-off characteristics of voltage resistance-on-resistance, and makes the side of the groove a drift region (see patent document 1). In this semiconductor device, a drain electrode is provided on a conductor buried in the groove. In addition, the base region and the source region are formed in the surface layer of the semiconductor substrate in the non-groove portion, and the drain region and the source region are arranged with a gate electrode between them.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: (Japanese) Patent Publication No. 08-181313 Summary of the invention

[0006] Technical problem to be solved by the invention

[0007] In a structure where the source region and the drain region are arranged with the gate electrode interposed therebetween, the region directly below the source region does not contribute to the operation of the transistor, so that the chip area of ​​the transistor is not effectively used, and there is a problem that an additional area is required.

[0008] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, which can reduce the chip area of ​​a transistor.

[0009] Technical solutions for solving technical problems

[0010] The essence of a semiconductor device of one embodiment of the present invention is that it comprises: a drift region arranged at the bottom of a groove formed in a substrate, a well region and a source region laminated on the side of the groove, and a drain region arranged inside the groove, and a gate electrode is arranged inside a gate trench extending in the depth direction of the groove having an opening portion formed across the upper surfaces of the well region and the source region.

[0011] The gist of a method for manufacturing a semiconductor device in another aspect of the present invention is to include: a process of forming a drift region at the bottom of a groove formed in a substrate, a process of laminating a well region and a source region on the side of the groove, and a process of forming a drain region inside the groove, and forming a gate electrode inside a gate trench extending in a depth direction of the groove having an opening portion formed across the upper surfaces of the well region and the source region.

[0012] Effects of the Invention

[0013] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device in which the chip area of ​​a transistor can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic perspective view showing the structure of a semiconductor device according to the first embodiment of the present invention.

[0015] Figure 2 is a diagram showing a current path of a main current of the semiconductor device according to the first embodiment of the present invention, along Figure 1 Cross-sectional view along the II-II direction.

[0016] Figure 3 It is a schematic diagram for explaining the expansion of the depletion layer of the semiconductor device according to the first embodiment of the present invention.

[0017] Figure 4 This is a schematic plan view showing a gate trench of the semiconductor device according to the first embodiment of the present invention.

[0018] Figure 5 This is a perspective view (part 1) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0019] Figure 6 This is a perspective view (part 2) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0020] Figure 7 This is a perspective view (part 3) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0021] Figure 8 This is a perspective view (part 4) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0022] Fig. 9 This is a perspective view (part 5) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0023] Fig.10 This is a perspective view (part six) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0024] Fig.11 This is a perspective view (part 7) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0025] Fig.12 This is a perspective view (part eight) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0026] Fig.13 This is a perspective view (part 9) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0027] Fig.14 This is a perspective view (part 10) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0028] Fig.15 It is a schematic perspective view showing the structure of a semiconductor device according to a modified example of the first embodiment of the present invention.

[0029] Fig.16 It is a schematic perspective view showing the structure of a semiconductor device according to a second embodiment of the present invention.

[0030] Fig.17 This is a perspective view (part 1) for explaining a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

[0031] Fig.18 This is a perspective view (part 2) for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

[0032] Fig.19 It is a schematic perspective view showing the structure of a semiconductor device according to a third embodiment of the present invention.

[0033] Fig. 20 It is a perspective view for explaining a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[0034] Fig.21 It is a schematic perspective view showing the structure of a semiconductor device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following describes the embodiments with reference to the accompanying drawings. In the description of the accompanying drawings, the same reference numerals are used for the same parts, and the description is omitted. However, the accompanying drawings are schematic diagrams, and the relationship between the thickness and the plane size, the ratio of the thickness of each layer, etc. include parts that are different from the actual situation. In addition, the drawings also include parts with different size relationships and ratios.

[0036] (First Embodiment)

[0037] like Figure 1 As shown, the semiconductor device according to the first embodiment of the present invention includes a substrate 10 having a groove 100 formed on a main surface, and a drift region 20 , a well region 30 , a first semiconductor region 40 , and a second semiconductor region 50 formed on the substrate 10 .

[0038] The drift region 20 is of the first conductivity type and has a portion disposed at the bottom of the trench 100. Figure 1 In the illustrated embodiment, the drift region 20 is continuously arranged from one side surface (hereinafter referred to as “first side surface”) of the trench 100 to the bottom of the trench 100 .

[0039] The well region 30 is of the second conductivity type, connected to the drift region 20 , and disposed on the first side surface of the trench 100 . Figure 1 The well region 30 shown is disposed on the surface of the drift region 20 at the first side surface of the trench 100 , and at the bottom of the trench 100 , the lower end of the well region 30 is connected to the drift region 20 .

[0040] The first semiconductor region 40 is of the first conductivity type and is disposed on the surface of the well region 30 at the first side surface of the trench 100. The first semiconductor region 40 is disposed on the surface of the well region 30 so as to be separated from the drift region 20 and not to exceed the outer edge of the well region 30. Figure 1 As shown, the lower end of the first semiconductor region 40 is located above the lower end of the well region 30 .

[0041] The second semiconductor region 50 is of the first conductivity type and is disposed in the trench 100 to face the well region 30 with the drift region 20 interposed therebetween. The second semiconductor region 50 is connected to the drift region 20 at a position separated from the well region 30. Figure 2 The second semiconductor region 50 shown is close to a side surface of the trench 100 that is opposite to the first side surface (hereinafter referred to as “second side surface”), is adjacent to the drift region 20 , and is arranged at the bottom of the trench 100 .

[0042] It should be noted that the first conductivity type and the second conductivity type are opposite conductivity types. That is, when the first conductivity type is n-type, the second conductivity type is p-type, and when the first conductivity type is p-type, the second conductivity type is n-type. In the following, the case where the first conductivity type is n-type and the second conductivity type is p-type is exemplified.

[0043] As mentioned above, Figure 1 The semiconductor device shown has a drift region 20, a well region 30, and a first semiconductor region 40 laminated on a first side surface of a trench 100 along a surface normal direction of the first side surface (hereinafter referred to as the "width direction" of the trench 100). In addition, a plurality of gate trenches are formed, which have openings formed across the upper surfaces of the drift region 20, the well region 30, and the first semiconductor region 40, and extend in the depth direction of the trench 100, and a gate insulating film 65 is arranged on the inner wall surface of the gate trench. The gate trenches are formed to reach the drift region 20 arranged at the bottom of the trench 100.

[0044] like Figure 1As shown, the gate insulating film 65 is continuously formed in the width direction of the drift region 20, the well region 30, and the first semiconductor region 40. Inside the gate trench, the gate electrode 60 is arranged to face the well region 30 with the gate insulating film 65 interposed therebetween.

[0045] Figure 1 The semiconductor device shown further includes: a first main electrode 70 electrically connected to the first semiconductor region 40, and a second main electrode 80 electrically connected to the second semiconductor region 50. The first main electrode 70 is arranged on the surface of the first semiconductor region 40 at the first side of the groove 100. The second main electrode 80 is arranged on the second side of the groove 100 opposite to the first main electrode 70, and the lower end of the second main electrode 80 is in contact with the second semiconductor region 50 at the bottom of the groove 100.

[0046] The first main electrode 70 is an end of one side of the current path of the main current flowing in the semiconductor device in the on state. The second main electrode 80 is an end of the other side of the current path. The main current of the semiconductor device flows between the first main electrode 70 and the second main electrode 80 via the first semiconductor region 40, the well region 30, the drift region 20, and the second semiconductor region 50.

[0047] Figure 1 The semiconductor device shown in the figure controls the main current by applying a predetermined voltage to the gate electrode 60 arranged in the middle of the current path, as described in detail later, and operates as a transistor. In the following, the semiconductor device is described with the first semiconductor region 40 as the source region, the first main electrode 70 as the source electrode, the second semiconductor region 50 as the drain region, and the second main electrode 80 as the drain electrode.

[0048] The interior of the trench 100 is filled with an isolation insulating film 90. That is, the isolation insulating film 90 is disposed above the drift region 20 disposed at the bottom of the trench 100 and between the source electrode 70 and the drain electrode 80. The isolation insulating film 90 insulates and isolates the source electrode 70 disposed above the drift region 20 from the drift region 20. Figure 1 In order to facilitate understanding of the structure of the semiconductor device, the semiconductor device is shown through the isolation insulating film 90. That is, the isolation insulating film 90 only shows the outer edge (the same is true in the three-dimensional diagram below).

[0049] It should be noted that the outside of the groove 100 , that is, the outside of the side surface portion of the drift region 20 (not shown) and the outside of the drain electrode 80 are regions of the substrate 10 where the groove 100 is not formed.

[0050] Figure 1The portion of the drift region 20 shown in the figure arranged at the bottom of the groove 100 is a structure in which the first conductive type region, namely the n-type drift region 21, and the second conductive type region, namely the p-type drift region 22, are alternately arranged along the direction in which the groove 100 extends parallel to the main surface of the substrate 10. In other words, Figure 1 The semiconductor device shown has a super junction structure (SJ structure) in which a plurality of pn junctions are arranged at a constant period along the direction in which the trench 100 extends (hereinafter referred to as the "length direction" of the trench 100). In the semiconductor device with the SJ structure, the main current flows in the n-type drift region 21 where the concentration of n-type impurities in the drift region 20 increases, which can reduce the on-resistance. On the other hand, when reverse biased, the n-type drift region 21 and the p-type drift region 22 are depleted by the depletion layer extending from the pn junction, thereby ensuring a high withstand voltage.

[0051] exist Figure 1 In the semiconductor device shown in FIG. 1 , in the on state, a channel region is formed in the well region 30 in contact with the gate insulating film 65. Figure 1 The basic operation of the semiconductor device shown will be described.

[0052] In the conduction operation, the potential of the gate electrode 60 is controlled with the potential of the source electrode 70 as a reference while a positive potential is applied to the drain electrode 80, thereby the semiconductor device is used as a transistor. That is, by making the voltage between the gate electrode 60 and the source electrode 70 equal to or higher than a predetermined threshold voltage, an inversion layer is formed in the channel region of the well region 30 on the side of the gate electrode 60. As a result, the semiconductor device is in the conduction state, and the main current flows between the drain electrode 80 and the source electrode 70. At this time, in the well region 30, the main current flows in a direction parallel to the main surface of the substrate 10. Figure 2 In FIG. 1 , the current path of the main current of the semiconductor device in the on state is indicated by arrow I.

[0053] On the other hand, in the off operation, the voltage between the gate electrode 60 and the source electrode 70 is set to a predetermined threshold voltage or less. As a result, the inversion layer disappears and the main current is cut off.

[0054] In addition, in the off state, the depletion layer extends from the pn junction between the well region 30 and the drift region 20 to the drain region 50. Figure 3 As shown by the middle arrow, the depletion layer 200 also extends from the interface between the n-type drift region 21 and the p-type drift region 22. When the reverse voltage increases to a certain extent, both the n-type drift region 21 and the p-type drift region 22 are in a completely depleted state (pinch-off state).

[0055] By pinching off the n-type drift region 21 and the p-type drift region 22 , the electric field distribution of the n-type drift region 21 and the p-type drift region 22 is uniformly rectangular, and the maximum electric field applied to the semiconductor device is greatly reduced. As a result, the withstand voltage of the semiconductor device is improved.

[0056] exist Figure 1 In the semiconductor device shown, the source region 40 and the source electrode 70 are arranged above the drift region 20 arranged at the bottom of the groove 100. Therefore, unlike the structure in which the source electrode and the drain electrode are arranged with the gate electrode interposed therebetween, the area directly below the source electrode 70 is an active area and does not become an area that does not contribute to the operation of the transistor. Figure 1 In the semiconductor device shown, the area that does not contribute to the operation of the transistor is reduced, and the chip area can be suppressed.

[0057] In addition, the source region 40 and the well region 30 are arranged on the first side surface of the groove 100, and a gate groove is formed in the depth direction of the groove 100. Therefore, in the on state, the end of the channel region extends in the depth direction along the first side surface of the groove 100. That is, the channel region is formed with a gate width from the opening of the groove 100 to the bottom of the groove 100. Since the channel region can be formed relatively wide in this way, the on resistance can be reduced.

[0058] In addition, inside the groove 100, the source region 40 is formed along the first side surface, and the source region 40 extends in the depth direction of the groove 100. Therefore, the contact portion between the source region 40 formed along the first side surface of the groove 100 and the source electrode 70 can be expanded in the depth direction of the groove 100. Thus, compared with the case where the contact portion between the source region 40 and the source electrode 70 is formed parallel to the main surface of the substrate 10, the chip area will not be increased, but the contact area can be expanded. Therefore, the contact resistance between the source region 40 and the source electrode 70 can be reduced, thereby reducing the on-resistance.

[0059] in addition, Figure 1 The semiconductor device shown in the figure has a structure in which the drift region 20 is arranged on the first side surface of the groove 100. Therefore, when the channel charge is induced in the well region 30 facing the gate insulating film 65 and the semiconductor device is turned on, Figure 4 In the region surrounded by the dotted line A in FIG. 1 , accumulated charges are generated at the boundary between the drift region 20 and the gate insulating film 65. The current path formed by the accumulated charges is formed in parallel with the channel region formed in the well region 30, thereby achieving the effect of reducing the resistance component of the channel region of the semiconductor device.

[0060] It should be noted that an insulating substrate is suitable for the substrate 10. By using an insulating substrate, the element isolation procedure when a plurality of semiconductor devices are integrated on the same substrate 10 can be simplified. In addition, when the semiconductor device is actually mounted on the cooler, the insulating substrate provided between the substrate 10 and the cooler can be omitted. Here, the so-called "insulating" substrate refers to a substrate having a resistivity of several kΩ·cm or more.

[0061] For example, silicon carbide (SiC) having insulating properties is used as the substrate 10. Although SiC has several polytypes (crystal polytypes), a typical 4H SiC substrate can be used as the substrate 10.

[0062] By using a SiC substrate as the substrate 10, the insulation of the substrate 10 can be improved, and the thermal conductivity can be improved. Therefore, the back side of the substrate 10 can be directly mounted on the cooling mechanism, thereby effectively cooling the semiconductor device. According to this structure, since the thermal conductivity of the SiC substrate is large, the heat generated by the main current can be effectively dissipated when the semiconductor device is in the on state. Since SiC is a wide-bandgap semiconductor and has a small number of intrinsic carriers, it is easy to achieve high insulation and realize a semiconductor device with high voltage resistance.

[0063] Hereinafter, a method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. It should be noted that the method for manufacturing a semiconductor device described below is only an example, and the method can be implemented by various other manufacturing methods including this modified example.

[0064] First, a groove 100 is formed on the main surface of the undoped silicon carbide insulating semiconductor substrate 10. The depth of the groove 100 is, for example, about 10 μm to 20 μm, and the width in the width direction is, for example, about 10 μm.

[0065] In order to form the groove 100 by etching, a mask material 111 of a predetermined shape is formed on the main surface of the substrate 10 (see Figure 5 ). As the mask material 111, for example, a silicon oxide film can be used, and as the deposition method, a thermal CVD method and a plasma CVD method can be used. Furthermore, the photoresist material on the mask material 111 is patterned (not shown). As the method of patterning, a common photolithography technique can be used. The mask material 111 is etched using the patterned photoresist material as a mask. As the etching method, a wet etching method using hydrofluoric acid and a dry etching method such as reactive ion etching are used. Next, the photoresist material is removed using oxygen plasma or sulfuric acid. The mask material 111 formed in this way is used as an etching mask, and the substrate 10 is selectively etched by a dry etching method, such as Figure 5 A slot 100 is shown formed.

[0066] After removing the mask material 111, a portion of the drift region 20 along the first side surface 11 of the trench 100 (hereinafter referred to as a "side surface portion" of the drift region 20) is formed by ion implantation or the like. Figure 6 As shown by the middle arrow, the side portion of the drift region 20 is formed by ion implantation of the first conductive type impurity from the opening of the groove 100 to the first side from obliquely above. At this time, the angle of the impurity implantation relative to the first side of the groove 100 is set according to the aspect ratio determined by the depth of the groove 100 and the width in the width direction, thereby enabling the impurity to be implanted only to the first side of the groove 100. Thus, the side portion of the drift region 20 is formed on the first side of the groove 100. Since the impurity is implanted from obliquely above, the lower end of the side portion of the drift region 20 reaches a position lower than the bottom of the groove 100.

[0067] Next, the n-type drift region 21 is formed in a portion of the drift region 20 disposed at the bottom of the trench 100 (hereinafter referred to as the “bottom portion” of the drift region 20 ). Figure 7 As shown, at the bottom of the groove 100, a mask material 112 is formed by photolithography technology to expose a region to be the n-type drift region 21. Then, using the mask material 112 as a mask, the n-type drift region 21 is selectively formed on the upper part of the substrate 10 by ion implantation of impurities of the first conductivity type. At this time, the impurities are implanted by being slightly inclined toward the first side surface than the surface normal direction of the main surface of the substrate 10, and the impurities are also implanted below the side surface portion of the drift region 20, connecting the side surface portion and the bottom portion of the drift region 20 to each other. Thereafter, the mask material 112 is removed.

[0068] Next, the well region 30 is formed on the first side surface of the trench 100 by ion implantation or the like in connection with the drift region 20. For example, Figure 8 As shown by the middle arrow, by ion implantation of the second conductivity type impurity from the opening of the groove 100 to the first side surface from obliquely upward, the well region 30 is overlapped with the side surface portion of the drift region 20. At this time, the angle of the impurity implantation relative to the first side surface of the groove 100 is set according to the aspect ratio determined by the depth of the groove 100 and the width in the width direction, thereby enabling the impurity to be implanted only to the first side surface of the groove 100. Thus, the well region 30 is formed on the first side surface of the groove 100.

[0069] Since the impurities are injected from the upper side, the lower end of the well region 30 reaches a position lower than the bottom of the groove 100. It should be noted that the conditions of ion injection are adjusted so that the well region 30 does not penetrate the drift region 20. The impurity concentration of the well region 30 is, for example, 1E15 / cm 3 ~1E19 / cm 3 about.

[0070] Then, the p-type drift region 22 is formed at the bottom portion of the drift region 20. Fig. 9 As shown, a mask material 113 is formed to expose the region of the bottom of the groove 100 as the p-type drift region 22, and the mask material 113 is used as a mask to selectively form the p-type drift region 22 on the upper part of the substrate 10 by ion implantation of the second conductive type impurity. Thus, the bottom part of the drift region 20 is formed in which the n-type drift region and the p-type drift region are alternately arranged along the length of the groove 100. Thereafter, the mask material 113 is removed.

[0071] In the ion implantation of the previous step, for example, nitrogen (N) is used as an n-type impurity of the first conductivity type, and aluminum (Al) and boron (B) are used as p-type impurities of the second conductivity type. It should be noted that by performing ion implantation while heating the substrate 10 to about 600° C., the generation of crystal defects in the ion implanted region can be suppressed.

[0072] In addition, in order to completely deplete the SJ structure in the off state and obtain a higher withstand voltage, it is necessary to set the ratio of the total amount of p-type impurities in the p-type drift region 22 to the total amount of n-type impurities in the n-type drift region to be close to 1. Therefore, by making the concentration Nd of the n-type impurities in the n-type drift region 21, the concentration Na of the p-type impurities in the p-type drift region 22, the width Wn of the n-type drift region 21, and the width Wp of the p-type drift region 22 satisfy the following formula (1), a higher withstand voltage can be obtained:

[0073] Na×Wp=Nd×Wn…(1)

[0074] The width Wn and the width Wp are widths in the direction in which the n-type drift regions 21 and the p-type drift regions 22 are repeatedly arranged. In order to satisfy the equation (1), the impurity concentrations of the n-type drift regions 21 and the p-type drift regions are set respectively.

[0075] According to the semiconductor device of the SJ structure having the drift region 20 satisfying the above conditions, the n-type drift region 21 and the p-type drift region 22 can be depleted in the off state, thereby increasing the withstand voltage per unit area of ​​the drift region 20. It should be noted that the impurity concentration of the drift region 20 is, for example, 1E15 / cm 3 ~1E19 / cm 3 about.

[0076] Next, a source region 40 is formed on the first side surface of the trench 100 and on the surface of the well region 30. Fig.10As shown by the middle arrow, by ion implantation of the first conductive type impurity from the opening of the groove 100 to the first side surface from obliquely upward, the source region 40 is formed in the region where the well region 30 is formed. At this time, the angle of the impurity implantation relative to the first side surface of the groove 100 is set according to the aspect ratio determined by the depth and width of the groove 100, thereby only the impurity is implanted into the well region 30 of the groove 100. The impurity concentration of the source region 40 is, for example, 1E18 / cm 3 ~1E21 / cm 3 about.

[0077] It should be noted that the source region 40 is formed by being separated from the drift region 20. For this reason, the impurity injection angle in the ion injection for forming the source region 40 is made shallower than the impurity injection angle in the ion injection for forming the well region 30. As a result, the lower end of the source region 40 is closer to the top than the lower end of the well region 30, which can prevent the source region 40 from protruding outside the well region 30.

[0078] Next, the drain region 50 is formed in the interior of the trench 100, facing the well region 30 with the drift region 20 interposed therebetween. The drain region 50 is connected to the drift region 20 at a position separated from the well region 30. For example, Fig.11 As shown, the mask material 114 formed to expose a predetermined region is used as a mask to implant ions of the first conductivity type impurity, thereby selectively forming the drain region 50 at the bottom of the trench 100. The impurity concentration of the drain region 50 is, for example, 1E18 / cm 3 ~1E21 / cm 3 about.

[0079] Thereafter, the ion-implanted impurities are activated by heat treatment, for example, at about 1700° C. in an argon or nitrogen atmosphere.

[0080] Then, if Fig.12 As shown, a gate trench 600 is formed to have an opening across the side surface of the drift region 20, the upper surface of the well region 30 and the source region 40, and to extend in the depth direction of the groove 100. For example, a mask material formed on the upper surface of the substrate 10 is patterned using a photolithography technique, and the gate trench 600 is formed by etching. The gate trench 600 is formed to have a width reaching the side surface of the drift region 20, the well region 30 and the source region 40, and a depth reaching the drift region 20.

[0081] Next, a gate insulating film 65 is formed on the inner wall surface of the gate trench 600. For example, the inner wall surface of the gate trench 600 is oxidized to form the gate insulating film 65. The gate insulating film 65 can be formed by either a thermal oxidation method or a deposition method. As an example, when using the thermal oxidation method, the substrate 10 is heated to a temperature of about 1100°C in an oxygen environment. After the gate insulating film 65 is formed, in order to reduce the interface energy level of the interface between the well region 30 and the gate insulating film 65, annealing at about 1000°C can also be performed in an environment of nitrogen, argon, N2O, etc. In addition, thermal oxidation can also be performed directly in an NO or N2O environment. The temperature in this case is preferably 1100°C to 1400°C. The thickness of the gate insulating film 65 is about tens of nm.

[0082] Then, if Fig.13 As shown, a gate electrode 60 is formed inside the gate trench 600. The gate electrode 60 faces the well region 30 via a gate insulating film 65. The material of the gate electrode 60 is generally a polysilicon film. Here, a case where the gate electrode 60 uses a polysilicon film will be described.

[0083] As a method for depositing the polysilicon film, a reduced pressure CVD method or the like can be used. For example, the thickness of the deposited polysilicon film is set to a value greater than half of the width of the opening of the gate trench 600 in the longitudinal direction. Since the polysilicon film is formed from the inner wall surface of the gate trench 600, by setting the thickness of the polysilicon film as described above, the gate trench 600 can be completely filled with the polysilicon film. For example, when the width of the gate trench 600 is 2 μm, the polysilicon film is formed to be thicker than 1 μm. In addition, after the polysilicon film is deposited, an n-type polysilicon film is formed by annealing at 950° C. in phosphorus oxychloride POCl3, so that the gate electrode 60 has conductivity.

[0084] Next, the polysilicon film is etched to make it flat. The etching method can be either isotropic etching or anisotropic selective etching. The etching amount is set so that the polysilicon film remains inside the gate trench 600. For example, in the case where a polysilicon film with a thickness of 1.5 μm is deposited on the gate trench 600 with a width of 2 μm, the etching amount of the polysilicon film can be 1.5 μm. However, in the control of etching, for an etching amount of 1.5 μm, over-etching of several % will not be a problem.

[0085] Afterwards, if Fig.14 As shown, an isolation insulating film 90 is deposited on the upper surface of the substrate 10, and the trench 100 is buried by the isolation insulating film 90. A silicon oxide film is generally suitable for the isolation insulating film 90, and a thermal CVD method or a plasma CVD method can be used as a deposition method.

[0086] The resist film (not shown) formed on the upper surface of the isolation insulating film 90 is patterned by using a photolithography technique or the like, and the resist film is used as a mask to selectively remove the isolation insulating film 90 in the region where the source electrode 70 and the drain electrode 80 are formed. By the process of selectively removing the isolation insulating film 90, a contact hole is formed in the isolation insulating film 90, where the contact surface of the source region 40 in contact with the source electrode 70 and the contact surface of the drain region 50 in contact with the drain electrode 80 are exposed. As an etching method for forming the contact hole, a wet etching method using hydrofluoric acid and a dry etching method such as reactive ion etching can be used. Thereafter, the resist film is removed by oxygen plasma and sulfuric acid or the like.

[0087] Then, the contact hole formed in the isolation insulating film 90 is filled, as shown in FIG. Figure 1 The source electrode 70 and the drain electrode 80 are formed as shown. The source electrode 70 and the drain electrode 80 are usually metal films. The source electrode 70 and the drain electrode 80 can be made of metal materials such as nickel (Ni) and manganese (Mo). In addition, a laminated layer such as titanium / nickel / silver (Ti / Ni / Ag) can also be used in the source electrode 70 and the drain electrode 80.

[0088] The source electrode 70 and the drain electrode 80 may also be formed by depositing a metal material on the entire surface by sputtering or electron beam (EB) evaporation, and then etching the metal material by dry etching using a patterned resist film as a mask. Alternatively, the source electrode 70 and the drain electrode 80 may be formed by filling the contact hole formed in the isolation insulating film 90 with a metal material by an electroplating process.

[0089] As mentioned above, complete Figure 1 In the above description, the drift region 20 is formed by ion implanting impurities into the insulating substrate 10. This eliminates the need for an epitaxial growth step and reduces manufacturing costs.

[0090] Similarly, by forming the well region 30 , the source region 40 , and the drain region 50 by ion implantation of impurities into the substrate 10 , the manufacturing cost can be reduced compared to the case where they are formed by epitaxial growth.

[0091] In addition, by ion implantation of impurities obliquely from the opening of the groove 100 toward the first side surface, a side surface portion of the drift region 20, a well region 30 formed on the surface of the side surface portion, and a source region 40 formed on the surface of the well region 30 are formed. Thus, the above-mentioned regions can be formed only on the first side surface while suppressing the manufacturing cost.

[0092] <Modification>

[0093] Fig.15 The semiconductor device of the modified example of the first embodiment shown in FIG. 1 has the drift region 20 disposed only at the bottom of the trench 100. Figure 1The semiconductor device trench 100 shown is different in that no drift region 20 is arranged on the first side surface.

[0094] like Fig.15 As shown, the lower end of the well region 30 disposed on the first side surface of the trench 100 is connected to the drift region 20 at the bottom of the trench 100. In addition, the opening of the gate trench is formed across the upper surfaces of the well region 30 and the first semiconductor region 40, and a gate insulating film 65 and a gate electrode 60 are disposed inside the gate trench. The gate trench extends in the depth direction of the trench 100 and penetrates the well region 30, and is formed so that the lower end reaches the drift region 20.

[0095] according to Fig.15 In the semiconductor device shown, since the drift region 20 is not formed on the first side surface of the trench 100 , the manufacturing process can be shortened and the manufacturing cost can be suppressed.

[0096] exist Fig.15 In the semiconductor device shown, the region directly below the source electrode 70 does not become a region that does not contribute to the operation of the transistor, and the chip area can be suppressed. In addition, since the channel region is formed along the depth direction of the groove 100 in the on state, the on resistance can be reduced. In addition, since the source region 40 extends in the depth direction of the groove 100, the contact resistance between the source region 40 and the source electrode 70 can be suppressed.

[0097] It should be noted that if Fig.15 As shown, the semiconductor device according to the embodiment of the present invention does not need to have the drift region 20 have an SJ structure. That is, the bottom portion of the drift region 20 may be formed of a single layer.

[0098] (Second Embodiment)

[0099] like Fig.16 As shown in FIG. 1 , the semiconductor device of the second embodiment of the present invention has a structure in which the drift region 20 has an n-type drift region 21 and a p-type drift region 22 are alternately laminated along the depth direction of the groove 100 at the bottom of the groove 100. Unlike the first embodiment in which the n-type drift region 21 and the p-type drift region 22 are alternately arranged in the length direction of the groove 100, the n-type drift region 21 and the p-type drift region 22 are each continuously arranged on the entire surface. The other structures are similar to Figure 1 The first embodiment shown is the same.

[0100] Fig.16 The semiconductor device shown is Figure 1The semiconductor device shown in FIG. 1 performs the same operation. That is, by making the voltage between the gate electrode 60 and the source electrode 70 equal to or higher than a predetermined threshold voltage, an inversion layer is formed in the channel region of the well region 30 on the side of the gate electrode 60. As a result, the semiconductor device is in an on state. In the off operation, the voltage between the gate electrode 60 and the source electrode 70 is made lower than a predetermined threshold voltage. As a result, the inversion layer disappears and the main current is cut off.

[0101] In the off state, the depletion layer starts to expand from the interface between the n-type drift region 21 and the p-type drift region 22 laminated along the thickness direction of the groove 100. In addition, by making the n-type drift region 21 and the p-type drift region 22 pinch-off state, the electric field distribution of the n-type drift region 21 and the p-type drift region 22 becomes a uniform rectangular distribution, and the maximum electric field applied to the semiconductor device is greatly reduced. As a result, the voltage resistance of the semiconductor device is improved.

[0102] Next, an example of a method for manufacturing the semiconductor device according to the second embodiment will be described with reference to the drawings.

[0103] In the first embodiment, refer to Figure 5 The method described above is the same, and the groove 100 is formed in the substrate 10. The substrate 10 is made of a non-doped silicon carbide insulating semiconductor substrate or the like.

[0104] Then, by using the mask material 211 patterned by photolithography technology or the like as a mask for ion implantation, as shown in FIG. Fig.17 As shown, the side portion of the drift region 20 and the n-type drift region 21 are formed. That is, the side portion of the drift region 20 is formed on the first side surface of the groove 100 by ion implantation of impurities from obliquely above the first side surface of the groove 100. Then, the n-type drift region 21 is formed on the bottom of the groove 100 by ion implantation of impurities into the main surface of the substrate 10.

[0105] like Fig.18 As shown, after removing the mask material 211, the well region 30 and the p-type drift region 22 are formed by ion implantation using the newly formed mask material 212 as a mask. That is, by ion implantation of impurities from obliquely above the first side surface of the groove 100, the side surface portion of the drift region 20 is laminated with the first side surface of the groove 100 to form the well region 30. Then, by ion implantation of impurities into the main surface of the substrate 10, the n-type drift region 21 is laminated on the bottom of the groove 100 to form the p-type drift region 22.

[0106] Thereafter, as in the first embodiment, Figure 10 to Figure 14 The source region 40, the drain region 50, the gate insulating film 65, the gate electrode 60, the isolation insulating film 90, the source electrode 70 and the drain electrode 80 are formed in the same manner as described above. Fig.16The semiconductor device shown.

[0107] According to the semiconductor device of the second embodiment, as described in the above-mentioned manufacturing method, the mask material for forming the side portion of the drift region 20 and the n-type drift region 21 can also be one kind. In addition, the mask material for forming the well region 30 and the p-type drift region 22 can also be one kind. Therefore, the manufacturing cost can be reduced. In addition, as in the first embodiment, the area directly below the source electrode 70 will not become an area that is not helpful for the operation of the transistor, and the chip area can be suppressed. Moreover, since the channel region is formed along the depth direction of the groove 100 in the on state, the on-resistance can be reduced. In addition, by extending the source region 40 in the depth direction of the groove 100, the contact resistance between the source region 40 and the source electrode 70 can be suppressed.

[0108] It should be noted that the n-type drift region 21 and the p-type drift region 22 may be alternately laminated by repeating the process of forming the n-type drift region 21 and the process of forming the p-type drift region 22. Thus, an SJ structure is formed in which a plurality of pn junctions are arranged at a constant period along the depth direction of the groove 100. With this structure, the voltage resistance of the semiconductor device can be further improved. In addition, since the other structures are substantially the same as those of the first embodiment, repeated descriptions are omitted.

[0109] (Third Embodiment)

[0110] like Fig.19 As shown, in the semiconductor device of the third embodiment of the present invention, the isolation insulating film 90 disposed between the source electrode 70 and the drain electrode 80 to fill the inside of the groove 100 is formed with a dividing groove 900 extending in parallel with the first side surface of the groove 100. The dividing groove 900 is used to divide the portion of the isolation insulating film 90 sandwiched by the source electrode 70 and the drain electrode 80. In other words, Fig.19 The semiconductor device shown is Figure 1 The semiconductor device shown in FIG. 1 is different in that the isolation insulating film 90 is isolated between the source electrode 70 and the drain electrode 80 by the dividing groove 900. The other structures are the same as those of FIG. Figure 1 The first embodiment shown is the same.

[0111] exist Fig.19 In the semiconductor device shown, a space is provided between the source electrode 70 and the drain electrode 80 by forming a dividing groove 900 in the isolation insulating film 90, so that the parasitic capacitance (Cds) between the source electrode 70 and the drain electrode 80 can be reduced. Therefore, in the switching operation of the semiconductor device, the switching loss caused by the charge and discharge of the output capacity (Coss) can be suppressed.

[0112] To reduce parasitic capacitance (Cds), the depth of the dividing groove 900 is set so that the dividing groove 900 is formed at least in the region where the source electrode 70 and the drain electrode 80 face each other. For example, the dividing groove 900 is formed so that the bottom of the dividing groove 900 is lower than the lower end of the source electrode 70.

[0113] It should be noted that the parasitic capacitance (Cds) can be reduced even if a small space is formed between the source electrode 70 and the drain electrode 80 for the isolation insulating film 90. For example, the dividing groove 900 is formed to have a width of about several hundred nm to 1 μm.

[0114] The dividing grooves 900 can be formed in the isolation insulating film 90 by using dry etching or the like. Fig. 20 As shown in the figure, after the isolation insulating film 90 is formed, the resist film 311 formed on the upper surface of the isolation insulating film 90 is patterned by photolithography technology, and the resist film 311 in the region where the dividing groove 900 is to be formed is removed. Then, the isolation insulating film 90 is selectively etched by dry etching using the resist film 311 as a mask to form the dividing groove 900. Other than this, since the other structures are substantially the same as those of the first embodiment, repeated descriptions are omitted.

[0115] (Fourth Embodiment)

[0116] like Fig.21 As shown, in the semiconductor device according to the fourth embodiment of the present invention, two semiconductor devices having the same structure as the semiconductor devices according to the first to third embodiments are formed in one trench 100 .

[0117] That is, the drain region 50 is arranged at the bottom of the central portion of the trench 100 between the first and second side surfaces facing each other, and the drain electrode 80 is arranged on the upper surface of the drain region 50. Then, the two semiconductor devices are integrated by arranging respective source regions 40 on the first and second side surfaces of the trench 100.

[0118] Fig.21 The semiconductor device shown in the figure forms a unit structure 1 including two semiconductor devices that share a drain region 50 and a drain electrode 80. According to the unit structure 1, two semiconductor devices are arranged in one trench 100 along the width direction of the trench 100, so that the integration degree can be improved.

[0119] It should be noted that although Fig.21 Only one unit structure 1 is shown, but a plurality of unit structures 1 may be connected along the width direction of the groove 100 by making the gate electrode 60 of each unit structure 1 common. Other structures are substantially the same as those of the first to third embodiments, and thus repeated descriptions are omitted.

[0120] (Other Embodiments)

[0121] As described above, the present invention is described by way of embodiments, but the discussion and drawings forming part of this disclosure should not be considered as limiting the present invention. Based on this disclosure, various alternative embodiments, examples, and application technologies will be apparent to those skilled in the art.

[0122] For example, although the above description uses an example of a SiC substrate as the substrate 10, the substrate 10 is not limited to the SiC substrate, and a substrate 10 formed of a semiconductor material having a wide band gap may also be used. Examples of semiconductor materials having a wide band gap include GaN, diamond, ZnO, and AlGaN.

[0123] In addition, although an example of using an n-type polysilicon film for the gate electrode 60 is described, a p-type polysilicon film may also be used. In addition, other semiconductor materials may be used for the gate electrode 60, and other conductive materials such as metal materials may also be used. For example, polysilicon carbide, SiGe, Al, etc. of the second conductive type may be used as the material of the gate electrode 60.

[0124] It should be noted that, although an example in which a silicon oxide film is used as the gate insulating film 65 is described, a silicon nitride film may be used as the gate insulating film 65. Alternatively, a laminate of a silicon oxide film and a silicon nitride film may be used as the gate insulating film 65. When the gate insulating film 65 is a silicon nitride film, isotropic etching may be performed by cleaning with hot phosphoric acid at 160°C.

[0125] Furthermore, although the first semiconductor region 40 is described as a source region and the second semiconductor region 50 is described as a drain region, the first semiconductor region 40 may be described as a drain region and the second semiconductor region 50 may be described as a source region to form a semiconductor device.

[0126] Thus, the present invention naturally includes various embodiments and the like that are not described here.

[0127] Industrial Applicability

[0128] The semiconductor device and the method for manufacturing the semiconductor device of the present invention can be applied to the electronic equipment industry including the manufacturing industry for manufacturing a semiconductor device that controls a main current flowing between two main electrodes.

[0129] Description of Reference Numerals

[0130] 10 substrate; 20 drift region; 21 n-type drift region; 22 p-type drift region; 30 well region; 40 first semiconductor region; 50 second semiconductor region; 60 gate electrode; 65 gate insulating film; 70 first main electrode; 80 second main electrode; 90 isolation insulating film.

Claims

1. A semiconductor device, characterized in that: have: a substrate having grooves formed on a main surface thereof; a drift region of a first conductivity type having a portion disposed at a bottom of the trench; A well region of a second conductivity type connected to the drift region and arranged on one side of the groove; A first semiconductor region of a first conductivity type as a source region, which is separated from the drift region and is arranged on the surface of the well region at the side surface of the groove; A second semiconductor region of the first conductivity type as a drain region, which is arranged inside the trench to face the well region with the drift region interposed therebetween; a gate electrode disposed inside a gate trench and facing the well region, wherein the gate trench has an opening formed across the upper surfaces of the well region and the first semiconductor region and extends in a depth direction of the trench; a first main electrode, which is disposed on the surface of the first semiconductor region at the side surface of the groove and is electrically connected to the first semiconductor region; a second main electrode disposed inside the groove opposite to the first main electrode and electrically connected to the second semiconductor region; an isolation insulating film disposed between the first main electrode and the second main electrode to fill the interior of the groove; A portion of the isolation insulating film sandwiched between the first main electrode and the second main electrode is divided by a dividing groove extending in parallel with the side surface of the groove.

2. The semiconductor device according to claim 1, wherein The drift region is arranged continuously from the side surface of the groove to the bottom of the groove, The well region is arranged on the surface of the drift region at the side surface of the trench.

3. The semiconductor device according to claim 1 or 2, wherein: The substrate is an insulating substrate.

4. The semiconductor device according to claim 1, wherein: The portion of the drift region arranged at the bottom of the trench has a structure in which first conductivity type regions and second conductivity type regions are alternately arranged along a length direction of the trench extending along the side surface.

5. The semiconductor device according to claim 1, wherein A portion of the drift region disposed at the bottom of the trench has a structure in which a first conductive type region and a second conductive type region are stacked in a depth direction of the trench.

6. The semiconductor device according to claim 4 or 5, characterized in that The impurity concentrations of the first conductive type region and the second conductive type region are set so that, in a cut-off state in which a main current flowing between the first semiconductor region and the second semiconductor region is cut off, the first conductive type region and the second conductive type region are depleted by a depletion layer extending from a pn junction formed at a boundary between the first conductive type region and the second conductive type region.

7. A method for manufacturing a semiconductor device, characterized in that: include: forming a groove on a main surface of a substrate; forming a drift region of the first conductivity type having a portion disposed at the bottom of the trench; forming a well region of a second conductivity type connected to the drift region on one side surface of the groove; A step of forming a first semiconductor region of a first conductivity type as a source region separated from the drift region on the side surface of the groove and on the surface of the well region; a step of forming a second semiconductor region of the first conductivity type as a drain region in the groove so as to face the well region with the drift region interposed therebetween; forming a gate trench having an opening extending across upper surfaces of the well region and the first semiconductor region and extending in a depth direction of the groove; forming a gate electrode in the gate trench so as to face the well region; a step of forming a first main electrode disposed on the side surface of the groove and electrically connected to the first semiconductor region; forming a second main electrode disposed inside the trench and facing the first main electrode and electrically connected to the second semiconductor region; forming an isolation insulating film disposed between the first main electrode and the second main electrode so as to fill the interior of the groove; and forming the drift region by ion implanting impurities into the substrate, A portion of the isolation insulating film sandwiched between the first main electrode and the second main electrode is divided by a dividing groove extending in parallel with the side surface of the groove.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The well region, the first semiconductor region, and the second semiconductor region are formed by ion implanting impurities into the substrate.

9. The method for manufacturing a semiconductor device according to claim 7 or 8, wherein: The drift region is formed continuously from the side of the groove to the bottom of the groove, By injecting impurity ions obliquely from the opening of the groove toward the side of the groove, a portion of the drift region formed on the side of the groove, the well region formed on the surface of the drift region on the side of the groove, and the first semiconductor region formed on the surface of the well region are formed.

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