Circuit for asynchronous data transfer

Abstract

A circuit for asynchronous data transfer includes a slave device with an asynchronous slave clock, the slave device is used to transfer data to a master device with a master clock. The slave clock is a discontinuous clock signal. The slave device includes a clock detection circuit, a register group, a temporary storage register and a data path selector. The slave device receives a data transfer command from the master device. The clock detection circuit detects the presence of a slave clock signal and generates a synchronization signal. In order to transfer the data to the master device, the data path selector selects one of the temporary storage register and the register group based on the synchronization signal. The slave device ensures seamless data transfer to the master device regardless of the presence or absence of the slave clock signal.

Description

Technical Field

[0001] The present invention relates generally to data communication between electronic devices and, more particularly, to transferring data from a slave device to a master device having an intermittent, non-continuous clock. Background Art

[0002] Integrated circuits such as system on chip (SoC) and application specific integrated circuit (ASIC) usually include multiple clock domains that are asynchronous with each other. For example, a system using a master-slave protocol includes a master device using an asynchronous clock signal and a slave device using a slave clock signal. When asynchronous with each other, the master clock signal and the slave clock signal cause clock domain crossing (CDC) problems during data transfer between the master device and the slave device. Such CDC problems may result in data loss or the transmission of erroneous data.

[0003] Various clock synchronization techniques have been used to solve the incompatibility between the master clock signal and the slave clock signal to overcome the CDC problem. However, when the slave device uses a discontinuous slave clock signal, such clock synchronization techniques may not be able to overcome the CDC problem. In addition, for communication protocols such as serial peripheral interface (SPI) and integrated circuit (I2C), it is critical that the master device receives the requested data from the slave device in a predetermined data transfer cycle. Therefore, it is not appropriate to extend the data transfer cycle and wait for the slave clock signal to be used as a synchronization technique.

[0004] One solution to overcome the above problems includes using a first-in-first-out (FIFO) buffer to transfer data between the master device and the slave device. However, the FIFO buffer increases the size and complexity of the slave device.

[0005] Therefore, it would be advantageous to have a slave device that can seamlessly transfer requested data to a master device regardless of the availability of a slave clock signal. Summary of the invention

[0006] According to one aspect of the present invention, there is provided a circuit for transferring data from a first device to a second device, wherein the first device operates based on a first discontinuous clock signal, and the second device operates based on a second clock signal asynchronous with the first clock signal, the circuit comprising: a clock detection circuit, which (i) receives a data transfer request signal from the second device for transferring data from the first device to the second device, and (ii) generates a synchronization signal, wherein the synchronization signal is invalid when the first clock signal does not exist, and the synchronization signal is asserted when the first clock signal exists and the data transfer request signal is valid; a register group, which stores the data; a temporary storage register, which is connected to the clock detection circuit to receive the synchronization signal, and is connected to the register group to receive the data therefrom, wherein the temporary storage register receives the data when the synchronization signal is asserted; and a data path selector, which is connected to the register group and the temporary storage register, wherein the data path selector outputs the data from one of the temporary storage register and the register group based on the synchronization signal.

[0007] According to one or more embodiments, it also includes: a command decoder, which receives a data transfer command and the second clock signal from the second device, wherein the command decoder decodes the data transfer command to generate a data request signal, an end of transfer (EOT) signal, and a load signal; and a reset trigger, which is connected to the command decoder to receive the EOT signal, wherein the reset trigger also receives the first clock signal and generates a first reset signal based on the EOT signal and the first clock signal to reset the clock detection circuit.

[0008] According to one or more embodiments, the clock detection circuit includes: a trigger circuit, which is connected to the command decoder and the reset trigger, for receiving a data request signal and the first reset signal, respectively, wherein the trigger circuit also receives the first clock signal and synchronizes the data request signal with the first clock signal to generate a synchronization request signal; and a pulse generator, which is connected to the trigger circuit and the reset trigger, for receiving the synchronization request signal and the first reset signal, respectively, wherein the pulse generator also receives the first clock signal and generates the synchronization signal.

[0009] According to one or more embodiments, the trigger circuit includes: a first trigger, which is connected to the command decoder and the reset trigger, and is used to receive a data request signal and the first reset signal, respectively, wherein the first trigger also receives the first clock signal and generates an intermediate request signal based on the data request signal and the first clock signal; and a second trigger, which is connected to the first trigger and the reset trigger, and is used to receive the intermediate request signal and the first reset signal, respectively, wherein the second trigger also receives the first clock signal and generates the synchronization request signal based on the intermediate request signal and the first clock signal.

[0010] According to one or more embodiments, the pulse generator includes: a first trigger, which is connected to the trigger circuit and the reset trigger, and is used to receive the synchronization request signal and the first reset signal, respectively, wherein the first trigger also receives the first clock signal and generates a delay request signal based on the synchronization request signal and the first clock signal; and a first logic circuit, which is connected to the trigger circuit and the first trigger, and is used to receive the synchronization request signal and the delay request signal, respectively, wherein the first logic circuit generates the synchronization signal based on the synchronization request signal and the delay request signal.

[0011] According to one or more embodiments, the data path selector includes: a first trigger, which is connected to the command decoder and is used to receive a data request signal, wherein the first trigger generates a register request signal based on the data request signal and provides it to the register group; a first logic circuit, which is connected to the first trigger and the clock detection circuit, and is used to receive the register request signal and the synchronization signal, respectively, wherein the first logic circuit generates a selection signal based on the register request signal and the synchronization signal; and a multiplexer circuit, which has a first and a second data input terminal connected to the register group and the temporary storage register, respectively, and a selection terminal connected to the first logic circuit for receiving the selection signal, wherein the multiplexer circuit outputs the data stored in one of the temporary storage register and the register group based on the selection signal.

[0012] According to one or more embodiments, when at least one of the synchronization signal and the register request signal is in a valid state, the selection signal is in a valid state, and wherein, when the synchronization signal is in an invalid state and the register request signal is in an invalid state, the selection signal is in the invalid state.

[0013] According to one or more embodiments, when the selection signal is in the valid state, the data path selector selects the register group, and when the selection signal is in the invalid state, the data path selector selects the temporary storage register.

[0014] According to one or more embodiments, the data path selector also includes: a second logic circuit, which is connected to the clock detection circuit and the reset trigger, and is used to receive the synchronization signal and the first reset signal respectively, wherein the second logic circuit generates a second reset signal for resetting the first trigger based on the synchronization signal and the first reset signal.

[0015] According to one or more embodiments, further comprising: a response generator in communication with the second device, wherein the response generator receives the data from the multiplexer circuit based on the load signal and outputs the data to the second device.

[0016] According to one or more embodiments, the first device is a slave device and the second device is a master device.

[0017] According to a second aspect of the present invention, there is provided a system on chip (SoC), comprising: a slave device that transmits data to a master device, wherein the slave device and the master device respectively operate based on a slave clock signal and a master clock signal that are asynchronous with each other, wherein the slave clock signal is a discontinuous clock signal, and wherein the slave device comprises: a clock detection circuit that receives a data request signal for transmitting the data to the master device and generates a synchronization signal, wherein when the slave clock signal does not exist, the synchronization signal remains in an invalid state, and when the slave clock signal exists and the data request signal is in a valid state, the synchronization signal is asserted; a register group, which stores the data; a temporary storage register connected to the clock detection circuit to receive the synchronization signal, and connected to the register group to receive the data therefrom, wherein the temporary storage register receives the data when the synchronization signal is asserted; and a data path selector having a first data input terminal and a second data input terminal respectively connected to the register group and the temporary storage register, and a control terminal connected to the clock detection circuit for receiving the synchronization signal, wherein the data path selector selects between the first data input terminal and the second data input terminal based on the synchronization signal for transmitting the data to the master device.

[0018] According to one or more embodiments, the slave device further includes: a command decoder connected to the master device for receiving a data transfer command and the master clock signal, wherein the command decoder decodes the data transfer command to generate the data request signal, an end of transfer (EOT) signal, and a load signal; and a reset trigger connected to the command decoder for receiving the EOT signal, wherein the reset trigger also receives the slave clock signal and generates a first reset signal based on the EOT signal and the slave clock signal to reset the clock detection circuit.

[0019] According to one or more embodiments, the clock detection circuit includes: a trigger circuit, which is connected to the command decoder and the reset trigger, for receiving the data request signal and the first reset signal respectively, wherein the trigger circuit also receives the slave clock signal and synchronizes the data request signal with the slave clock signal to generate a synchronization request signal; and a pulse generator, which is connected to the trigger circuit and the reset trigger, for receiving the synchronization request signal and the first reset signal respectively, wherein the pulse generator also receives the slave clock signal and generates the synchronization signal.

[0020] According to one or more embodiments, the trigger circuit includes: a first trigger, which is connected to the command decoder and the reset trigger, and is used to receive the data request signal and the first reset signal, respectively, wherein the first trigger also receives the slave clock signal and generates an intermediate request signal based on the data request signal and the slave clock signal; and a second trigger, which is connected to the first trigger and the reset trigger, and is used to receive the intermediate request signal and the first reset signal, respectively, wherein the second trigger also receives the slave clock signal and generates the synchronization request signal based on the intermediate request signal and the slave clock signal.

[0021] According to one or more embodiments, the pulse generator includes: a first trigger, which is connected to the trigger circuit and the reset trigger, and is used to receive the synchronization request signal and the first reset signal, respectively, wherein the first trigger also receives the slave clock signal and generates a delay request signal based on the synchronization request signal and the slave clock signal; and a first logic circuit, which is connected to the trigger circuit and the first trigger, and is used to receive the synchronization request signal and the delay request signal, respectively, wherein the first logic circuit generates the synchronization signal based on the synchronization request signal and the delay request signal.

[0022] According to one or more embodiments, the data path selector includes: a first trigger, which is connected to the command decoder and is used to receive the data request signal, wherein the first trigger generates a register request signal based on the data request signal and provides it to the register group; a first logic circuit, which is connected to the first trigger and the clock detection circuit, and is used to receive the register request signal and the synchronization signal respectively; wherein the first logic circuit generates a selection signal based on the register request signal and the synchronization signal, wherein when at least one of the synchronization signal and the register request signal is in a valid state, the selection signal is in a valid state, and when the synchronization signal is in an invalid state and the register request signal is in an invalid state, the selection signal is in an invalid state, and wherein when the selection signal is in the valid state state, the data path selector selects the register group, and when the selection signal is in the invalid state, the data path selector selects the temporary storage register; a multiplexer circuit, which has the first data input terminal and the second data input terminal respectively connected to the register group and the temporary storage register, and a selection terminal connected to the first logic circuit for receiving the selection signal, wherein the multiplexer circuit outputs the data stored in one of the temporary storage register and the register group based on the selection signal; and a second logic circuit, which is connected to the clock detection circuit and the reset trigger, for receiving the synchronization signal and the first reset signal respectively, wherein the second logic circuit generates a second reset signal for resetting the first trigger based on the synchronization signal and the first reset signal.

[0023] According to one or more embodiments, the slave device further includes a response generator that receives the data from the multiplexer circuit based on the load signal and outputs the data to the master device.

[0024] According to a third aspect of the present invention, there is provided a method for transmitting data from a slave device to a master device, wherein the master device and the slave device operate based on respective master clock signals and slave clock signals which are asynchronous with each other, and wherein the slave clock signal is a discontinuous clock signal, and wherein the method comprises: receiving, by the slave device, a data transfer command issued by the master device; generating, by the slave device, a data request signal based on the data transfer command; detecting, by the slave device, the presence of the slave clock signal based on the data request signal; generating, by the slave device, a synchronization signal based on the detection of the presence of the slave clock signal, wherein the synchronization signal is invalid when the slave clock signal is not present, and is asserted when the slave clock signal is present and the data request signal is valid; selecting, by the slave device, data stored in a temporary storage register and one of the register groups based on the synchronization signal; and transmitting the selected data to the master device.

[0025] According to one or more embodiments, the temporary storage register is selected when the slave clock signal is present, and the register group is selected when the slave clock signal is not present. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The following detailed description of preferred embodiments of the invention will be better understood when read in conjunction with the accompanying drawings.The present invention is illustrated by way of example and not limitation in the accompanying drawings, in which like reference numerals indicate similar elements.

[0027] Figure 1 is a schematic block diagram of a master device and a slave device for transmitting data from a slave device to a master device according to an embodiment of the present invention;

[0028] Figure 2 is a schematic block diagram of a slave device according to an embodiment of the present invention;

[0029] Figure 3 According to an embodiment of the present invention Figure 2 A schematic block diagram of a clock detection circuit of a slave device;

[0030] Figure 4 According to an embodiment of the present invention Figure 2 A schematic block diagram of a data path selector of a slave device;

[0031] Figure 5 is a diagram showing an embodiment of the present invention. Figure 2 A timing diagram of a first data transfer operation in the presence of a slave clock signal of a slave device;

[0032] Figure 6 is a diagram showing an embodiment of the present invention. Figure 2A timing diagram of a second data transfer operation in which a slave clock signal of a slave device does not exist; and

[0033] Figure 7 is a flow chart illustrating a method for transmitting data from a slave device to a master device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] Various other modifications will be apparent to those skilled in the art.

[0035] The detailed description of the accompanying drawings is intended as a description of the currently preferred embodiments of the present invention, and is not intended to represent the only form in which the present invention can be implemented. It should be understood that the same or equivalent functions can be implemented by different embodiments intended to be included in the spirit and scope of the present invention.

[0036] The terms "master" and "slave" may be used interchangeably with the terms "master" and "slave", respectively. The terms "high" and "low" refer to a high logic state and a low logic state. The terms "comprises", "comprising", or variations thereof are intended to cover non-exclusive inclusions such that a module, circuit, device assembly, structure, and method step comprising a series of elements or steps may include not only these elements, but may also include other elements or steps that are not explicitly listed or inherent to these modules, circuits, device assemblies, or steps. Therefore, without further constraints, an element or step performed by "comprising..." does not exclude the presence of additional identical elements or steps that include the element or step.

[0037] In one embodiment, the present invention provides a slave device that operates using a discontinuous slave clock signal for transmitting data to a master device that operates using a master clock signal. The slave device includes a clock detection circuit, a register group, a temporary storage register, and a data path selector. The clock detection circuit receives a data request signal for transmitting data to the master device and generates a synchronization signal. When the slave clock signal does not exist, the synchronization signal is invalid, and when the slave clock signal exists and the data request signal is valid, the synchronization signal is valid. The register group stores data. The temporary storage register is connected to the clock detection circuit and receives the synchronization signal. The temporary storage register is also connected to the register group for receiving data from the register group. When the synchronization signal is asserted, the temporary storage register receives data. The data path selector has a data terminal connected to the register group and the temporary storage register, and a control terminal connected to the clock detection circuit for receiving the synchronization signal. The data path selector outputs data from the temporary storage register and the register group based on the synchronization signal, and the output data is sent to the master device.

[0038] In another embodiment, the present invention provides a system on chip (SoC) including a slave device for transmitting data to a master device. The master device and the slave device operate based on a master clock signal and a slave clock signal that are asynchronous with each other, respectively, and wherein the slave clock signal is a discontinuous clock signal. The slave device includes a clock detection circuit, a register group, a temporary storage register, and a data path selector. The clock detection circuit receives a data request signal for transmitting data to the master device, and generates a synchronization signal. When the slave clock signal does not exist, the synchronization signal is invalid, and when the slave clock signal exists and the data request signal is valid, the synchronization signal is valid. The register group stores data. The temporary storage register is connected to the clock detection circuit for receiving the synchronization signal, and is connected to the register group for receiving data therefrom. When the synchronization signal is asserted, the temporary storage register receives data. The data path selector has data input terminals connected to the register group and the temporary storage register, respectively, and a control terminal connected to the clock detection circuit for receiving the synchronization signal. The data path selector outputs one of the temporary storage register and the register group based on the synchronization signal, and the output data is provided to the master device.

[0039] In yet another embodiment, the present invention provides a method for transferring data from a slave device operating based on a discontinuous slave clock signal to a master device operating based on a master clock signal asynchronous with the slave clock signal. The method includes: receiving, by the slave device, a data transfer command for transferring data to the master device from the master device; and generating, by the slave device, a data request signal based on the data transfer command. The method also includes: detecting, by the slave device, the presence of a slave clock signal based on the data request signal; and generating, by the slave device, a synchronization signal based on the detection of the slave clock signal. When the slave clock signal does not exist, the synchronization signal is in an invalid state, and when the slave clock signal exists and the data request signal is in a valid state, the synchronization signal is asserted. The method also includes, by the slave device, outputting, to the master device, based on the synchronization signal, a temporary storage register of the slave device and one of the register groups.

[0040] Various embodiments of the present invention provide a slave device including a circuit for asynchronous data transmission, so that a slave device with a discontinuous clock signal can transmit data to a master device. The master device and the slave device operate based on corresponding master clock signals and slave clock signals that are asynchronous with each other. The slave clock signal is a discontinuous clock signal. The slave device includes a clock detection circuit, a register group, a temporary storage register, and a data path selector. The register group stores data to be transmitted to the master device. The clock detection circuit receives a data request signal for transmitting data to the master device and generates a synchronization signal. The data request signal is synchronized with the master clock signal, and the synchronization signal is synchronized with the slave clock signal. When the slave clock signal does not exist, the synchronization signal is invalid. When the slave clock signal exists and the data request signal is valid, the clock detection circuit asserts the synchronization signal. When the synchronization signal is asserted, the temporary storage register receives data from the register group. The data path selector receives the synchronization signal and then selects one of the temporary storage register and the register group to transmit data to the master device. The temporary storage register is selected when the slave clock signal exists, and the register group is selected when the slave clock signal does not exist. Thus, the slave device provides seamless data transfer to the master device regardless of the presence or absence of the slave clock signal.

[0041] Reference now Figure 1 , shows a schematic block diagram of a system including a master device 102 communicating with a slave device 104 according to an embodiment of the present invention. The master device 102 is implemented on a first system on a chip (SoC) 106 and operates based on a master clock signal M_CLK. The master clock signal M_CLK is generated by a first clock generator (not shown) associated with the first SoC 106. In one embodiment, the master device 102 may include the first clock generator, although in other embodiments, the first clock generator may be external to the master device 102.

[0042] The master device 102 communicates with the slave device 104 and can receive data from the slave device 104 and write data to the slave device 104. For example, the master device 102 can read sensor data of multiple sensors (not shown) through the slave device 104, and can write sensor configuration data to the slave device 104 to configure the sensor. In order to receive data from the slave device 104, the master device 102 generates and provides a data transfer command to the slave device 104, which includes at least the size of the data to be received and the memory address of the slave device 104 from which the data is retrieved. The master device 102 also provides a master clock signal M_CLK to the slave device 104.

[0043] The slave device 104 is implemented on the second SoC 108 and operates based on a slave clock signal S_CLK generated by a second clock generator (not shown) associated with the second SoC 108. In one embodiment, the slave device 104 may include a second clock generator, although in other embodiments, the second clock generator may be external to the slave device 104. The master clock signal M_CLK and the slave clock signal S_CLK are asynchronous with respect to each other. In addition, the slave clock signal S_CLK is a discontinuous clock signal, that is, the slave clock signal S_CLK may not always be available. For example, the second clock generator may enable (i.e., periodically assert and deassert) the slave clock signal S_CLK during a first period to update the data stored by the slave device 104, and disable (i.e., invalidate) the slave clock signal S_CLK during a second period. Therefore, during the first period, the slave clock signal S_CLK exists, and during the second period, the slave clock signal S_CLK does not exist.

[0044] The slave device 104 is connected to the master device 102 for receiving a data transfer command and the master clock signal M_CLK, and based on the data transfer command, the slave device 104 transmits requested data to the master device 102 regardless of the presence or absence of the slave clock signal S_CLK.

[0045] It is apparent to those skilled in the art that although the master device 102 and the slave device 104 are shown as being implemented on the first SoC 106 and the second SoC 108, respectively, in other embodiments, the master device 102 and the slave device 104 may be implemented on a single SoC (e.g., the first SoC 106 or the second SoC 108).

[0046] Reference now Figure 2 , shows a schematic block diagram of a circuit 200 for transmitting data from a slave device to a master device according to an embodiment of the present invention. The circuit 200 includes a command decoder 202, a reset flip-flop 204, a clock detection circuit 206, a register group 208, a temporary storage register 210, a data path selector 212, and a response generator 214.

[0047] The command decoder 202 is connected to the master device 102 for receiving a data transfer command and a master clock signal M_CLK. The command decoder 202 includes a first buffer register (not shown) that operates based on the master clock signal M_CLK for temporarily storing the data transfer command. The command decoder 202 decodes the data transfer command to generate a data request signal D_REQ synchronized with the master clock signal M_CLK. The data request signal D_REQ corresponds to a request to transfer data to the master device 102. Based on the data transfer command, the command decoder 202 further identifies a memory address and the size of the data requested by the master device 102. The memory address indicates the physical address of a register (not shown) in the register group 208, where the data to be transferred to the master device 102 is stored. The command decoder 202 further generates a load signal and an end of transfer (EOT) signal. During data transfer, the EOT signal is invalid. In one embodiment, when the data has been successfully transferred to the master device 102, the command decoder 202 asserts the EOT signal (i.e., the EOT signal transitions from an invalid state to a valid state) within a predetermined duration. In one example, the predetermined duration is equal to one clock cycle of the master clock signal M_CLK. After the predetermined duration, the command decoder 202 de-asserts the EOT signal (i.e., the EOT signal transitions from a valid state to an invalid state). In another embodiment, when data to be transmitted to the master device 102 is loaded into the response generator 214, the command decoder 202 may assert the EOT signal for a predetermined duration.

[0048] The reset flip-flop 204 is connected to the command decoder 202 and receives the EOT signal. The reset flip-flop 204 also receives the slave clock signal S_CLK and the SoC reset signal. The reset flip-flop 204 generates a first reset signal RST1 based on the EOT signal and the SoC reset signal. When the EOT signal and the SoC reset signal are invalid, the first reset signal RST1 is invalid. When at least one of the EOT signal and the SoC reset signal is asserted, the reset flip-flop 204 asserts the first reset signal RST1 for resetting the clock detection circuit 206 and the temporary storage register 210. When the EOT signal and the SoC reset signal are de-asserted, the reset flip-flop 204 de-asserts the first reset signal RST1 synchronously with the slave clock signal S_CLK. The reset flip-flop 204 further provides the first reset signal RST1 to the data path selector 212.

[0049] The clock detection circuit 206 is connected to the command decoder 202 and the reset flip-flop 204, and receives the data request signal D_REQ and the first reset signal RST1 respectively. The clock detection circuit 206 further receives the slave clock signal S_CLK. When receiving the data request signal D_REQ, the clock detection circuit 206 detects the existence of the slave clock signal S_CLK, and generates a synchronization signal synchronized with the slave clock signal S_CLK. When the slave clock signal S_CLK does not exist, the synchronization signal is invalid. When the slave clock signal S_CLK exists and the data request signal D_REQ is valid, the clock detection circuit 206 asserts the synchronization signal within a predetermined duration (e.g., one cycle of the slave clock signal S_CLK). In other words, when the slave clock signal S_CLK is not available, the synchronization signal is invalid, and when the slave clock signal S_CLK is available and the data request signal D_REQ is valid, the synchronization signal is asserted. The clock detection circuit 206 de-asserts the synchronization signal at the end of the predetermined duration (i.e., one clock cycle of the slave clock signal S_CLK). When the first reset signal RST1 is asserted, the clock detection circuit 206 is reset.

[0050] The register bank 208 is a memory that includes first and second groups of registers (not shown) for storing data in one embodiment, wherein each register can be accessed using a unique memory address. When the register bank 208 receives the slave clock signal S_CLK, the data in the first group of registers is updated, and when the register bank 208 receives the master clock signal M_CLK, the second group of registers is updated with the configuration data. The register bank 208 receives the memory address from the command decoder 202.

[0051] The temporary storage register 210 is an n-bit register (e.g., n=16), and receives the slave clock signal S_CLK, the synchronization signal from the clock detection circuit 206, and the data requested from the master device 102 from the temporary storage 210. The temporary storage register 210 also receives the first reset signal RST1 from the reset flip-flop 204. When the synchronization signal is asserted, the temporary storage register 210 receives data from the register group 208. When the first reset signal RST1 is asserted, the temporary storage register 210 is reset. In the preferred embodiment, when the synchronization signal is asserted, the temporary storage register 210 receives data from the register group 208 at the falling edge of the slave clock signal S_CLK.

[0052] The data path selector 212 is connected to the command decoder 202 and the reset flip-flop 204, and is used to receive the data request signal D_REQ and the first reset signal RST1, respectively. The data path selector 212 has first and second data input terminals connected to the register group 208 and the temporary storage register 210, respectively, and a control terminal connected to the clock detection circuit 206 for receiving the synchronization signal. Based on the data request signal D_REQ and the synchronization signal, the data path selector 212 generates a register request signal R_REQ for accessing the data stored in the register group 208. The data path selector 212 provides the register request signal R_REQ to the register group 208, and based on the register request signal R_REQ, the data path selector 212 receives the data at the memory address stored in the register group 208.

[0053] Based on the register request signal R_REQ and the synchronization signal, the data path selector 212 outputs one of the data stored in the register group 208 and the temporary storage register 210. When the register request signal R_REQ or the synchronization signal is valid (i.e., when a data transfer command is received and the slave clock signal S_CLK exists), the data path selector 212 outputs the data stored in the temporary storage register 210, and when the register request signal R_REQ and the synchronization signal are de-asserted (i.e., when a data transfer command is received and the slave clock signal S_CLK does not exist), the data path selector 212 outputs the data stored in the register group 208.

[0054] The response generator 214 is connected to the main device 102, the command decoder 202 and the data path selector 212, and is used to receive the main clock signal M_CLK, the load signal and the data respectively. The response generator 214 includes a second buffer register (not shown) for temporarily storing the data to be transmitted to the main device 102. The second buffer register operates based on the main clock signal M_CLK. When the load signal is valid, the second buffer register loads the data. The response generator 214 transmits the data received from the data path selector 212 to the main device 102.

[0055] Reference now Figure 3 , shows a schematic block diagram of a clock detection circuit 206 according to an embodiment of the present invention. The clock detection circuit 206 includes a synchronization circuit 302 and a pulse generator 304.

[0056] The synchronization circuit 302 is connected to the command decoder 202 and the reset flip-flop 204, and is used to receive the data request signal D_REQ and the first reset signal RST1 respectively. The synchronization circuit 302 also receives the slave clock signal S_CLK. Based on the data request signal D_REQ and the slave clock signal S_CLK, the flip-flop circuit 302 generates a synchronization request signal S_REQ. When the slave clock signal S_CLK exists, the flip-flop circuit 302 synchronizes the data request signal D_REQ with the slave clock signal S_CLK, and asserts the synchronization request signal S_REQ. When the slave clock signal S_CLK does not exist, the synchronization request signal S_REQ is invalid. The synchronization circuit 302 includes a first flip-flop 306a and a second flip-flop 306b.

[0057] The first flip-flop 306a has a data input terminal and a reset terminal connected to the command decoder 202 and the reset flip-flop 204, respectively, for receiving the data request signal D_REQ and the first reset signal RST1. The first flip-flop 306 further has a clock terminal for receiving the slave clock signal S_CLK and an output terminal for providing the intermediate request signal I_REQ. When the slave clock signal S_CLK exists and the data request signal D_REQ is valid, the first flip-flop 306a asserts the intermediate request signal I_REQ. When the slave clock signal S_CLK does not exist, the intermediate request signal I_REQ is invalid. When the first reset signal RST1 is asserted, the first flip-flop 306a is reset.

[0058] The second flip-flop 306b has a data input terminal and a reset terminal connected to the output terminal of the first flip-flop 306a and the reset flip-flop 204, respectively, for receiving the intermediate request signal I_REQ and the first reset signal RST1. The second flip-flop 306b further has a clock terminal for receiving the slave clock signal S_CLK, and an output terminal for generating the synchronization request signal S_REQ. When the slave clock signal S_CLK exists and the intermediate request signal I_REQ is effective, the second flip-flop 306b asserts the synchronization request signal S_REQ, and when the slave clock signal S_CLK does not exist, the synchronization request signal S_REQ is invalid. When the first reset signal RST1 is asserted, the second flip-flop 306b is reset. It will be apparent to those skilled in the art that the scope of the flip-flop circuit 302 is not limited to two flip-flops, but can include any number of flip-flops without departing from the scope of the present invention.

[0059] The pulse generator 304 is connected to the trigger circuit 302 and the reset trigger 204, and is used to receive the synchronization request signal S_REQ and the first reset signal RST1 respectively. The pulse generator 304 also receives the slave clock signal S_CLK. Based on the synchronization request signal S_REQ and the slave clock signal S_CLK, the pulse generator 304 generates a synchronization signal. When the slave clock signal S_CLK exists and the data request signal D_REQ is valid, the pulse generator 304 asserts the synchronization signal within a predetermined duration, and when the slave clock signal S_CLK does not exist, the synchronization signal is invalid. The pulse generator 304 includes a third trigger 308 and a first logic circuit 310.

[0060] The third flip-flop 308 has a data input terminal connected to the output terminal of the second flip-flop 306b, for receiving the synchronization request signal S_REQ, and a clock terminal for receiving the slave clock signal S_CLK. The third flip-flop 308 also has a reset terminal connected to the reset flip-flop 204, for receiving the first reset signal RST1, and an output terminal for providing the delay request signal DEL_REQ. When the first reset signal RST1 is asserted, the third flip-flop 308 is reset.

[0061] The first logic circuit 310 is connected to the output terminals of the second flip-flop 306b and the third flip-flop 308, and is used to receive the synchronization request signal S_REQ and the delay request signal DEL_REQ respectively. Based on the synchronization request signal S_REQ and the delay request signal DEL_REQ, the first logic circuit 310 generates a synchronization signal. In one embodiment, the first logic circuit 310 includes a first logic gate 312 and a second logic gate 314, which are inverters and AND gates.

[0062] The first logic gate 312 has an input terminal connected to the output terminal of the third flip-flop 308 for receiving the delay request signal DEL_REQ and provides an inverted version of the delay request signal DEL_REQ INV_REQ at its output terminal. The second logic gate 314 receives the synchronization request signal S_REQ and the INV_REQ signal and generates a synchronization signal.

[0063] Those skilled in the art will appreciate that the scope of the first logic circuit 310 is not limited to the first logic gate 312 and the second logic gate 314 , but may be implemented using different combinations of logic gates to achieve the same functionality.

[0064] Reference now Figure 4 , shows a schematic block diagram of a data path selector 212 according to an embodiment of the present invention. The data path selector 212 includes a fourth flip-flop 402, a second logic circuit 404, a third logic circuit 406, and a multiplexer or multiplexer 408.

[0065] The fourth flip-flop 402 has a function of receiving an input signal V DD The data input terminal of the command decoder 202 is connected to the clock terminal for receiving the data request signal D_REQ. DD is a logic high signal (i.e., set to 1). The fourth flip-flop 402 also has a reset terminal connected to the third logic circuit 406, and an output terminal providing a register request signal R_REQ provided to the register group 208. Since the fourth flip-flop 402 is clocked by the data request signal D_REQ, and the input terminal of the fourth flip-flop 402 receives the logic high signal V DD , so when the data request signal D_REQ is asserted, the output of the fourth flip-flop 402 is asserted, that is, the register request signal R_REQ. If the synchronization signal is invalid (that is, if the slave clock signal S_CLK does not exist), the register request signal R_REQ remains asserted during data transmission. However, if the synchronization signal is asserted (that is, if the slave clock signal S_CLK exists), the register request signal R_REQ is de-asserted by the third logic circuit 406 through the reset terminal of the fourth flip-flop 402.

[0066] The second logic circuit 404 may be a dual-input OR gate that receives the R_REQ signal from the fourth flip-flop 402 and the synchronization signal from the second logic gate 314, and generates a selection signal SEL input to the multiplexer 408 to select one of the data from the register group 208 or the temporary storage register 210 to be output to the master device 102. When at least one of the synchronization signal and the register request signal R_REQ is valid, the selection signal SEL is valid, and when both the synchronization signal and the register request signal R_REQ are invalid, the selection signal SEL is invalid. In other words, when the data transfer command is received, that is, when the data request signal D_REQ is asserted, the selection signal is asserted. If the slave clock signal S_CLK does not exist, the selection signal remains asserted, and if the slave clock signal S_CLK exists, the selection signal is deasserted.

[0067] The third logic circuit 406 may also be a dual-input OR gate that receives the synchronization signal and the first reset signal RST1 and generates a second reset signal RST2, which is input to the reset terminal of the fourth flip-flop 402. When the synchronization signal and the first reset signal RST1 are de-asserted, the second reset signal RST2 is also de-asserted, and when at least one of the synchronization signal and the first reset signal RST1 is asserted, the second reset signal RST2 is asserted.

[0068] It is obvious to those skilled in the art that the second logic circuit 404 and the third logic circuit 406 are not limited to OR gates, but may be implemented using different combinations of logic gates to achieve the same functionality.

[0069] As described above, the multiplexer 408 has first and second data input terminals connected to the temporary storage register 210 and the register group 208, respectively, and a selection terminal connected to the second logic circuit 404 for receiving the selection signal SEL. The multiplexer 408 outputs data from one of the temporary storage register 210 and the register group 208 according to the value of the selection signal SEL. When the data transfer command is received and the slave clock signal S_CLK exists, the multiplexer 408 selects the temporary storage register 210, and when the selection signal SEL is invalid, the multiplexer 408 selects the register group 208 for outputting data.

[0070] Reference now Figure 5 , a timing diagram 500 illustrating a first data transfer operation in the presence of a slave clock signal S_CLK is shown. For illustration purposes, it is assumed that the slave clock signal S_CLK is T 0 to T 17 In other words, the slave clock signal S_CLK is present and the slave T 0 to T 17 The data stored in the temporary storage register 210 is hereinafter referred to as "T_Data", and the data stored in the first register (not shown) of the register bank 208 is hereinafter referred to as "R_Data". The data provided by the multiplexer 408 to the response generator 214 is hereinafter referred to as "Out_Data".

[0071] At time T 0 Previously, the master device 102 transmitted a data transfer command to the slave device 104 .

[0072] From time T 0 To time T 1 , the data request signal D_REQ, the first reset signal RST1, the synchronization request signal S_REQ and the delay request signal DEL_REQ are low (ie, invalid). In addition, the EOT signal, the register request signal R_REQ, the synchronization signal, the selection signal SEL and the load signal LD ​​are also low.

[0073] From time T 1 To time T 2, the command decoder 202 receives and decodes the data transfer command, and asserts the data request signal D_REQ at the rising edge of the master clock signal M_CLK. Next, the fourth flip-flop 402 receives the data request signal D_REQ and asserts the register request signal R_REQ. The second logic circuit 404 receives the register request signal R_REQ and asserts the selection signal SEL. Therefore, from time T 1 To time T 2 , the data request signal D_REQ, the register request signal R_REQ and the selection signal SEL are switched from low to high (ie, from invalid to valid). The EOT signal, the first reset signal RST1, the synchronization request signal S_REQ, the delay request signal DEL_REQ, the synchronization signal and the load signal LD ​​remain low.

[0074] From time T 2 To time T 3 , the data request signal D_REQ, the register request signal R_REQ and the selection signal SEL remain high (ie, valid), and the EOT signal, the first reset signal RST1, the synchronization request signal S_REQ, the delay request signal DEL_REQ, the synchronization signal and the load signal LD ​​remain low.

[0075] At time T 3 At the rising edge of the slave clock signal S_CLK, the data request signal D_REQ, the register request signal R_REQ and the selection signal SEL remain high. The EOT signal, the first reset signal RST1, the synchronization request signal S_REQ, the delay request signal DEL_REQ, the synchronization signal and the load signal LD ​​remain low. The first register of the register group 208 is updated with data (e.g., '197b') at the rising edge of the slave clock signal S_CLK. Therefore, R_Data and Out_Data have data values ​​'197b'. The first flip-flop 306a receives the data request signal D_REQ and at time T 3 The intermediate request signal I_REQ is asserted at the rising edge of the slave clock signal S_CLK observed at .

[0076] From time T 3 To time T 5 , the data request signal D_REQ, the register request signal R_REQ and the selection signal SEL are kept high. The EOT signal, the first reset signal RST1, the synchronization request signal S_REQ, the delay request signal DEL_REQ, the synchronization signal and the load signal LD ​​are kept low.

[0077] At time T 5At, the second flip-flop 306b receives the intermediate request signal I_REQ and asserts the synchronization request signal S_REQ. Therefore, the synchronization request signal S_REQ is converted from low to high. When the first logic gate 312 receives the delay request signal DEL_REQ at the logic low state, the first logic gate 312 asserts the inverted request signal INV_REQ, so the second logic gate 314 receives the synchronization request signal S_REQ and the inverted request signal INV_REQ and asserts the synchronization signal. Therefore, the synchronization signal is converted from low to high. The third logic circuit 406 receives the synchronization signal at the logic high state and the first reset signal RST1 at the logic low state, thereby asserting the second reset signal RST2. The fourth flip-flop 402 receives the second reset signal RST2, and therefore de-asserts the register request signal R_REQ. Therefore, the register request signal R_REQ is converted from high to low. The data request signal D_REQ and the selection signal SEL remain high. The EOT signal, the first reset signal RST1 , the delay request signal DEL_REQ, and the load signal LD ​​remain low.

[0078] From time T 5 To time T 6 , the data request signal D_REQ, the synchronization request signal S_REQ, the synchronization signal and the selection signal SEL are high, while the EOT signal, the first reset signal RST1, the delay request signal DEL_REQ, the register request signal R_REQ and the load signal LD ​​are low.

[0079] At time T 6 At 100 , the data request signal D_REQ, the synchronization request signal S_REQ, the synchronization signal and the selection signal SEL are high, while the EOT signal, the first reset signal RST1, the delay request signal DEL_REQ, the register request signal R_REQ and the load signal LD ​​are low. The temporary storage register 210 receives the synchronization signal at a logic high state and loads data, for example, '197b', so T_Data is '197b'.

[0080] From time T 6 To time T 7 , the data request signal D_REQ, the synchronization request signal S_REQ, the synchronization signal and the selection signal SEL remain high, while the EOT signal, the first reset signal RST1, the delay request signal DEL_REQ, the register request signal R_REQ and the load signal LD ​​remain low.

[0081] At time T 7At, the third flip-flop 308 receives the synchronization request signal S_REQ at the logic high, and asserts the delay request signal DEL_REQ. Therefore, the delay request signal DEL_REQ is converted from low to high. The first logic gate 312 receives the delay request signal DEL_REQ at the logic high, and therefore de-asserts the inverted request signal INV_REQ. The second logic gate 314 receives the delay request signal DEL_REQ at the logic high and the inverted request signal INV_REQ at the logic low, and de-asserts the synchronization signal. Therefore, the synchronization signal is converted from high to low. In addition, the second logic circuit 404 receives the synchronization signal and the register request signal R_REQ at the logic low, and de-asserts the selection signal SEL. Therefore, the selection signal SEL is converted from high to low, so the multiplexer 408 outputs data from the temporary storage register 210. The data request signal D_REQ and the synchronization request signal S_REQ remain high. The EOT signal, the first reset signal RST1, the register request signal R_REQ and the load signal LD ​​remain low. The first register of the register group 208 is updated with data, for example, '29ac', so R_Data is '29ac'.

[0082] From time T 7 To time T 8 , the load signal LD ​​switches from low to high at the rising edge of the master clock signal M_CLK. The response generator 214 receives the load signal LD ​​at logic high. Therefore, the second buffer register is loaded with the data received from the multiplexer circuit 408. From time T 7 To time T 8 , when the load signal LD ​​changes from low to high, the multiplexer 408 selects the data from the temporary storage register 210, and the second buffer register is loaded with T_Data, for example, '197b'. In other words, when the load signal LD ​​changes from low to high, Out_Data is the same as T_Data. The response generator 214 sends the loaded data '197b' to the master device 102 based on the master clock signal M_CLK. The data request signal D_REQ, the delay request signal DEL_REQ and the synchronization request signal S_REQ remain high. The EOT signal, the first reset signal RST1, the register request signal R_REQ, the synchronization signal and the selection signal SEL remain low.

[0083] From time T 8 To time T 13 , the data request signal D_REQ, the delay request signal DEL_REQ, the synchronization request signal S_REQ and the load signal LD ​​remain high, and the EOT signal, the first reset signal RST1, the register request signal R_REQ, the synchronization signal and the selection signal SEL remain low.

[0084] The load signal LD ​​remains high for a predetermined time period, such as one clock cycle of the master clock signal M_CLK. The load signal LD ​​then transitions from high to low, and the command decoder 202 asserts the EOT signal. Therefore, from time T 13 To time T 14 , at the rising edge of the master clock signal M_CLK, the EOT signal is converted from low to high, and the data request signal D_REQ is converted from high to low. The reset flip-flop 204 receives the EOT signal at a logic high state, and thus asserts the first reset signal RST1 to reset the flip-flops 306a, 306b, and 308 and the temporary storage register 210. Therefore, the first reset signal RST1 is converted from low to high. Due to the reset of the first to third flip-flops 306a, 306b, and 308, the synchronization request signal S_REQ and the delay request signal DEL_REQ are converted from high to low. In addition, the third logic circuit 406 receives the first reset signal RST1 at a logic high state, and thus asserts the second reset signal RST2 to reset the fourth flip-flop 402. The register request signal R_REQ, the synchronization signal, and the selection signal SEL remain low. Due to the reset of the temporary storage register 210, T_Data is updated to a data value '0'. Therefore, Out_Data is also updated to a data value '0'.

[0085] From time T 14 To time T 15 , the EOT signal and the first reset signal RST1 remain high. The data request signal D_REQ, the synchronization request signal S_REQ, the delay request signal DEL_REQ, the register request signal R_REQ, the synchronization signal, the selection signal SEL and the load signal LD ​​remain low.

[0086] At time T 15 At , the EOT signal and the first reset signal RST1 remain high. The data request signal D_REQ, the synchronization request signal S_REQ, the delay request signal DEL_REQ, the register request signal R_REQ, the synchronization signal, the selection signal SEL and the load signal LD ​​remain low. The first register of the register group 208 is updated with data, for example, '321b', so R_Data is '321b'.

[0087] From time T 15 To time T 17, the EOT signal and the first reset signal RST1 remain high, while the data request signal D_REQ, the synchronization request signal S_REQ, the delay request signal DEL_REQ, the register request signal R_REQ, the synchronization signal, the selection signal SEL and the load signal LD ​​remain low. The EOT signal is de-asserted at the next rising edge of the master clock signal M_CLK. After the EOT signal is de-asserted, the reset flip-flop 204 de-asserts the first reset signal RST1 synchronously with the slave clock signal S_CLK. Then the slave device 104 waits to receive the next data transfer command from the master device 102.

[0088] Reference now Figure 6 , a timing diagram 600 is shown to illustrate a second data transfer operation in the absence of a slave clock signal S_CLK. That is, the slave clock signal S_CLK is at time T 18 To time T 35 The master device 102 transmits a new data transfer command to the slave device 104 to receive data from the first register of the slave device 104 .

[0089] From time T 18 To time T 19 , the data request signal D_REQ, the first reset signal RST1, the synchronization request signal S_REQ and the delay request signal DEL_REQ are low. The EOT signal, the register request signal R_REQ, the synchronization signal, the selection signal SEL and the load signal LD ​​are also low. The first register of the register group 208 stores data, for example, 'a09', so R_Data is 'a09'.

[0090] From time T 19 To time T 20 , the command decoder 202 receives and decodes the data transfer command, and asserts the data request signal D_REQ at the rising edge of the master clock signal M_CLK, so the data request signal D_REQ changes from low to high. The fourth flip-flop 402 receives the data request signal D_REQ, so the fourth flip-flop 402 generates a register request signal R_REQ. Therefore, the register request signal R_REQ changes from low to high. The second logic circuit 404 receives the register request signal R_REQ and asserts the selection signal SEL, so the multiplexer 408 selects the register group 208 data (R_data) to be transmitted to the master device 102. The EOT signal, the first reset signal RST1, the synchronization request signal S_REQ, the delay request signal DEL_REQ, the synchronization signal, and the load signal LD ​​remain low.

[0091] From time T 20 To time T 25, the data request signal D_REQ, the register request signal R_REQ and the selection signal SEL are kept high. The EOT signal, the first reset signal RST1, the synchronization request signal S_REQ, the delay request signal DEL_REQ, the synchronization signal and the load signal LD ​​are kept low.

[0092] From time T 25 To time T 26 , the load signal LD ​​switches from low to high at the rising edge of the master clock signal M_CLK. The response generator 214 receives the load signal LD, so the second buffer register is loaded with the Out_Data (ie, 'a09') received from the multiplexer 408. 25 To time T 26 , when the load signal LD ​​changes from low to high, the multiplexer 408 selects the data (R_data) from the register group 208 to transmit the data to the master device 102, and the second buffer register is loaded with Out_Data, i.e., 'a09'. The response generator 214 starts the transmission of the data 'a09' to the master device 102 based on the master clock signal M_CLK. The data request signal D_REQ, the register request signal R_REQ and the selection signal SEL remain high. The EOT signal, the first reset signal RST1, the synchronization request signal S_REQ, the delay request signal DEL_REQ, the synchronization signal and the load signal LD ​​remain low.

[0093] From time T 26 To time T 31 , the data request signal D_REQ, the register request signal R_REQ, the selection signal SEL and the load signal LD ​​are kept high. The EOT signal, the first reset signal RST1, the synchronization request signal S_REQ, the delay request signal DEL_REQ and the synchronization signal are kept low.

[0094] The load signal LD ​​remains high for a predetermined time period, such as one clock cycle of the master clock signal M_CLK. The load signal LD ​​then transitions from high to low, and the command decoder 202 asserts the EOT signal. Therefore, from time T 31 To time T 32, the reset flip-flop 204 receives the EOT signal and asserts the first reset signal RST1, which resets the first flip-flop 306a, the second flip-flop 306b and the third flip-flop 308 and the temporary storage register 210. The data request signal D_REQ changes from high to low at the rising edge of the main clock signal M_CLK. Since the first to third flip-flops 306a, 306b and 308 are reset, the register request signal R_REQ and the selection signal SEL are converted from high to low. Next, the third logic circuit 406 receives the first reset signal RST1 and asserts the second reset signal RST2, which resets the fourth flip-flop 402, so the register request signal R_REQ changes from high to low. The synchronization request signal S_REQ, the delay request signal DEL_REQ and the synchronization signal remain low.

[0095] From time T 32 To time T 35 , the EOT signal and the first reset signal RST1 remain high. The data request signal D_REQ, the synchronization request signal S_REQ, the delay request signal DEL_REQ, the register request signal R_REQ, the synchronization signal, the selection signal SEL and the load signal LD ​​remain low. The EOT signal is de-asserted at the next rising edge of the master clock signal M_CLK. After de-asserting the EOT signal, the reset flip-flop 204 de-asserts the first reset signal RST1. Then the slave device 104 waits to receive the next data transfer command from the master device 102.

[0096] Reference now Figure 7 , a flowchart 700 illustrating a method for transferring data from a slave device 104 to a master device 102 according to an embodiment of the present invention is shown.

[0097] At step 702, the slave device 104 receives a data transfer command for transferring data to the master device 102. At step 704, the slave device 104 generates a data request signal D_REQ based on the data transfer command. At step 706, the clock detection circuit 206 detects the presence of the slave clock signal S_CLK based on the data request signal D_REQ.

[0098] At step 708, the clock detection circuit 206 generates a synchronization signal based on the detection of the presence of the slave clock signal S_CLK. The synchronization signal remains in an inactive state (ie, not asserted) when the slave clock signal S_CLK is not present, and is asserted when the slave clock signal S_CLK is present.

[0099] At step 710, the data path selector 212 determines whether the sync signal is asserted. If at step 710, the data path selector 212 determines that the sync signal is not asserted, then step 712 is performed. At step 712, the data path selector 212 selects the register group 208 data for transmission to the master device 102.

[0100] If at step 710, data path selector 212 determines that the sync signal is asserted, step 714 is executed. At step 714, temporary storage register 210 is loaded with data received from register bank 208. At step 716, data path selector 212 selects data from temporary storage register 210 for transmission to master device 102.

[0101] The slave device 104 includes a clock detection circuit 206 that continuously detects the presence of the slave clock signal S_CLK and generates a synchronization signal based on the detection. The data path selector 212 receives the synchronization signal as an input and selects one of the register group 208 data and the temporary storage register 210 data to be transmitted to the master device 102. Therefore, the slave device 104 not only overcomes the clock domain crossing (CDC) problem caused by the clock domain incompatibility of the master device 102 and the slave device 104, but also ensures seamless data transmission to the master device 102, regardless of the presence or absence of the slave clock signal S_CLK. Since the slave device 104 does not rely on a first-in-first-out (FIFO) buffer to transmit data to the master device 102, the slave device 104 has a smaller size and less complex circuitry than a conventional slave device using a FIFO buffer.

[0102] Although various embodiments of the present invention have been illustrated and described, it is apparent that the present invention is not limited to these embodiments. Many modifications, changes, variations, substitutions and equivalents will be apparent to those skilled in the art without departing from the spirit and scope of the present invention as described in the claims.

Claims

1. A circuit for transmitting data from a first device to a second device, characterized in that The first device operates based on a first discontinuous clock signal, and the second device operates based on a second clock signal asynchronous to the first discontinuous clock signal, the circuit comprising: a clock detection circuit that (i) receives a data transfer request signal from the second device for transferring data from the first device to the second device, and (ii) generates a synchronization signal that is inactive when the first discontinuous clock signal is not present and is asserted when the first discontinuous clock signal is present and the data transfer request signal is active; a register group storing the data; a temporary storage register connected to the clock detection circuit to receive the synchronization signal and connected to the register bank to receive the data therefrom, wherein the temporary storage register receives the data when the synchronization signal is asserted; and a data path selector connected to the register group and the temporary storage register, wherein when the synchronization signal is asserted, the data path selector outputs the data from the temporary storage register, and when the synchronization signal is in an inactive state, the data path selector outputs the data from the register group.

2. The circuit according to claim 1, characterized in that Also includes: a command decoder receiving a data transfer command and the second clock signal from the second device, wherein the command decoder decodes the data transfer command to generate a data transfer request signal, an end of transfer EOT signal, and a load signal; and A reset flip-flop is connected to the command decoder to receive the EOT signal, wherein the reset flip-flop also receives the first discontinuous clock signal and generates a first reset signal based on the EOT signal and the first discontinuous clock signal to reset the clock detection circuit.

3. The circuit according to claim 2, characterized in that The clock detection circuit comprises: a flip-flop circuit connected to the command decoder and the reset flip-flop, for receiving a data transfer request signal and the first reset signal, respectively, wherein the flip-flop circuit also receives the first discontinuous clock signal and synchronizes the data transfer request signal with the first discontinuous clock signal to generate a synchronization request signal; and A pulse generator is connected to the flip-flop circuit and the reset flip-flop, and is used to receive the synchronization request signal and the first reset signal respectively, wherein the pulse generator also receives the first discontinuous clock signal and generates the synchronization signal.

4. The circuit according to claim 3, characterized in that The trigger circuit comprises: a first flip-flop connected to the command decoder and the reset flip-flop, for receiving a data transfer request signal and the first reset signal, respectively, wherein the first flip-flop also receives the first discontinuous clock signal and generates an intermediate request signal based on the data transfer request signal and the first discontinuous clock signal; and A second trigger, connected to the first trigger and the reset trigger, is used to receive the intermediate request signal and the first reset signal respectively, wherein the second trigger also receives the first discontinuous clock signal and generates the synchronization request signal based on the intermediate request signal and the first discontinuous clock signal.

5. The circuit according to claim 3, characterized in that The pulse generator comprises: a first flip-flop connected to the flip-flop circuit and the reset flip-flop, for receiving the synchronization request signal and the first reset signal, respectively, wherein the first flip-flop also receives the first discontinuous clock signal and generates a delay request signal based on the synchronization request signal and the first discontinuous clock signal; and A first logic circuit is connected to the trigger circuit and the first trigger, and is used to receive the synchronization request signal and the delay request signal respectively, wherein the first logic circuit generates the synchronization signal based on the synchronization request signal and the delay request signal.

6. The circuit according to claim 2, characterized in that The data path selector comprises: a first flip-flop connected to the command decoder and configured to receive a data transfer request signal, wherein the first flip-flop generates a register request signal based on the data transfer request signal and provides it to the register group; a first logic circuit connected to the first flip-flop and the clock detection circuit, for receiving the register request signal and the synchronization signal, respectively, wherein the first logic circuit generates a selection signal based on the register request signal and the synchronization signal; and a multiplexer circuit having first and second data input terminals connected to the register group and the temporary storage register, respectively, and a selection terminal connected to the first logic circuit for receiving the selection signal, wherein the multiplexer circuit outputs the data stored in one of the temporary storage register and the register group based on the selection signal.

7. The circuit according to claim 6, characterized in that The selection signal is in an active state when at least one of the synchronization signal and the register request signal is in an active state, and wherein the selection signal is in an inactive state when the synchronization signal is in an inactive state and the register request signal is in an inactive state.

8. The circuit according to claim 7, characterized in that When the selection signal is in the valid state, the data path selector selects the register group, and when the selection signal is in the invalid state, the data path selector selects the temporary storage register.

9. A system on chip (SoC), characterized in that: Comprising a circuit according to any one of claims 1-8.

10. A method for transmitting data from a slave device to a master device, characterized in that The master device and the slave device operate based on respective master clock signals and slave clock signals that are asynchronous with each other, and wherein the slave clock signal is a discontinuous clock signal, the method comprising: receiving, by the slave device, a data transmission command issued by the master device; generating, by the slave device, a data transfer request signal based on the data transfer command; detecting, by the slave device, the presence of the slave clock signal based on the data transfer request signal; generating, by the slave device, a synchronization signal based on the detection of the presence of the slave clock signal, wherein the synchronization signal is inactive when the slave clock signal is not present and the synchronization signal is asserted when the slave clock signal is present and the data transfer request signal is active; selecting, by the slave device, data stored in one of a temporary storage register and a register bank based on the synchronization signal, wherein the temporary storage register is selected when the slave clock signal is present, and the register bank is selected when the slave clock signal is absent; and The selected data is transmitted to the host device.

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