Clock signal monitor for slave devices on a master-slave bus

Abstract

The present disclosure relates to a clock signal monitor for a slave device on a master-slave bus. The slave device can receive a clock signal from a master device via a bus. The slave device can detect a first pulse of the clock signal. The first pulse indicates a bit to be written to a slave shift register of the slave device. The slave device can identify a timeout threshold associated with the clock signal. The slave device can determine that the timeout threshold expires without detecting a second pulse from the clock signal. The slave device can reset the slave shift register based on the expiration of the timeout threshold to synchronize the slave shift register with the master shift register of the master device.

Description

Technical Field

[0001] The present disclosure relates to a clock signal monitor for a slave device on a master-slave bus. Background Art

[0002] In the master-slave communication bus protocol, the master device performs unidirectional control over one or more slave devices via the bus. The master device and (multiple) slave devices on the bus will synchronize according to a clock signal to send or receive data along the bus. Typically, the master device provides a clock signal to the slave device for data transmission via the bus. Summary of the invention

[0003] According to some implementations, a method may include receiving a clock signal, wherein the clock signal is received from a master device via a bus; detecting a first pulse of the clock signal, wherein the first pulse indicates a bit to be written to or a bit to be written from a slave shift register of the slave device; identifying a timeout threshold associated with the clock signal; determining that the timeout threshold has expired without detecting a second pulse from the clock signal; and resetting the slave shift register based on the expiration of the timeout threshold to synchronize the slave shift register with a master shift register of the master device.

[0004] According to some implementations, a device may include one or more memories and one or more processors communicatively coupled to the one or more memories, the one or more processors configured as: a shift register and a timeout monitor communicatively coupled to the shift register, the timeout monitor configured to: monitor a clock signal associated with a bus, wherein the clock signal is used to store bits of data communication in the shift register, wherein the data communication is received from a master device via the bus; detect a first pulse of the clock signal; determine whether a timeout threshold expires before a second pulse is detected or whether the second pulse is detected before it is determined that the timeout threshold has expired; and when the second pulse is detected before it is determined that the timeout threshold has expired, reset a timeout timer associated with the clock signal or when the timeout threshold expires before the second pulse is detected, reset the shift register to synchronize the shift register with a main shift register of the master device.

[0005] According to some implementations, a system may include a bus, a master device configured to transmit data communications via the bus, and a slave device configured to: monitor a clock signal received from the master device via the bus, wherein the slave device stores bits of the data communications in a slave shift register based on the clock signal; determine that a timeout threshold has expired based on timing associated with pulses of the clock and that the slave shift register includes an empty time slot, wherein the pulses of the clock signal include the most recently detected pulse of the clock signal; and reset the slave shift register based on determining that the timeout threshold has expired to synchronize the slave shift register with a master shift register of the master device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A , Figure 1B , Figure 2 and Figure 3 is a diagram of one or more example implementations described herein;

[0007] Figure 4 is a diagram of an example environment in which the systems and / or methods described herein may be implemented;

[0008] Figure 5 yes Figure 4 diagrams of example components of one or more devices; and

[0009] Figure 6-Figure 8 is a flow chart of an example process associated with a clock signal monitor for a slave device on a master-slave communications bus. DETAILED DESCRIPTION

[0010] The following detailed description of example implementations refers to the accompanying drawings.The same reference numbers in different drawings may identify the same or similar elements.

[0011] In some cases, for the digital interface between the master device and one or more slave devices, all devices on the master-slave bus are synchronized with respect to the clock signal for communication via the bus. However, if the device on the bus becomes asynchronous with the clock signal for the bus (for example, due to glitches, interference, etc. in the clock signal), there must be a means for resynchronizing the device to achieve appropriate communication with the device. Depending on the type of communication protocol used on the bus (and / or the type of device communicating via the bus), such means for resynchronizing can be different. For example, a slave device (referred to herein as "I2C device") utilizing an internal integrated circuit (I2C) communication protocol can utilize start and stop capabilities to withdraw the slave device from data transmission, and enable the slave device to be resynchronized. As another example, a slave device (referred to herein as "SPI device") utilizing a serial peripheral interface (SPI) communication protocol can use a dedicated chip select (CS) line to resynchronize. Although I2C devices can use fewer links to communicate via a master-slave bus (e.g., two lines) than SPI devices (e.g., more than two lines), the communication speed of I2C devices is relatively slow (e.g., less than 4 Mbps per second) compared to SPI devices (which can achieve a communication speed of about 10 megabytes per second (Mbps)). In addition, SPI devices can use relatively simple hardware (e.g., simpler circuit systems) compared to I2C devices. Accordingly, SPI devices may be required to communicate at higher speeds than I2C devices. However, in previous technologies, since one of the communication links needs to be used as a CS line to synchronize the SPI device, the use of SPI devices as slave devices may be limited.

[0012] According to some implementations described herein, a slave device may monitor a timeout associated with a clock signal of a clock signal. A timeout may indicate that the slave device is to resynchronize with the master device (or with the clock signal provided by the master device). For example, a timeout may correspond to a timeout threshold (e.g., a threshold length of a time period) that expires when no subsequent pulses (or clock cycles) of the clock signal are detected after an initial pulse is detected. Accordingly, if a timeout expires without filling the shift register of the slave device and / or without the identified word length of data communication matching the number of bits in the shift register, then the slave device may determine that an error signal associated with the clock has occurred (or may have occurred) and / or that the slave device needs to resynchronize with the master device.

[0013] In some implementations, a timeout monitor (e.g., a component including a retriggerable monostable multivibrator (RMM), a counter, a timer, etc.) may be included from a device to detect a pulse and track the amount of time that has passed since the pulse. If the amount of time that has passed since the pulse is equal to or greater than a timeout threshold, the timeout monitor may detect a timeout associated with the clock signal and cause the slave device to be resynchronized. As described herein, the slave device may be resynchronized by resetting the shift register of the slave device. The slave device may reset the shift register by clearing any or all bits in the shift register. Accordingly, when the data communication from the master device is completed and a timeout is detected after receiving the last bit of the data communication, both the slave device and the master device may include a cleared shift register and thus be synchronized.

[0014] In addition, when the bus is idle (e.g., when data is not being transmitted over the bus), if a clock pulse is erroneously detected (e.g., due to a glitch in the clock signal, due to interference, etc.) and the corresponding bit is erroneously added to the shift register, the slave device can clear the shift register because a timeout may be detected due to the bus being idle (e.g., because another clock pulse will not be detected when the bus is idle). Accordingly, if a pulse is erroneously detected in the clock signal by the slave device when data communication is idle, the slave device can self-trigger a resynchronization process after not receiving another pulse after a duration corresponding to the timeout threshold. In this way, a self-triggered resynchronization process can be performed by the slave device based on a timeout detected in the clock signal.

[0015] In some implementations, the slave device can use the SPI communication protocol. Accordingly, as described herein, the slave device can achieve a relatively high communication speed. In addition, since the slave device performs a self-triggered resynchronization process, it is not necessary to utilize a dedicated CS line to perform the resynchronization of the slave device, so that the slave device can be resynchronized with the master device (for example, because the slave device performs the resynchronization process based on the detection of the timeout associated with the clock signal). In this way, by making the communication link of the slave device (which is originally used as the CS line in the prior art) can be used for one or more other implementations other than the resynchronization slave device, the slave device configured to use the SPI communication protocol can be used more effectively. Accordingly, the slave device utilizing the SPI communication protocol can be configured to not include (or not need) the CS line, and can still be used as a slave device for the master-slave communication via the bus. In addition, hardware resources can be saved, such as conductive materials (for example, metal wires, metal traces, etc.), which would otherwise be used in the prior art to form the CS line connection between the master device and the slave device.

[0016] Figure 1A and 1Bis a diagram of an example implementation 100 described herein. Figure 1A As shown, the example implementation 100 includes a master device and a slave device communicatively coupled via a bus and a clock line (or wire). The bus may include one or more transmit lines and / or receive lines to allow data communication between the master device and the slave device. Figure 1A As further shown, the master device includes a clock and a master shift register, while the slave device includes a timeout monitor and an interface to the slave shift register.

[0017] The timeout monitor may include an RMM, a counter, a timer, etc. As described herein, the timeout monitor monitors the clock signal, and when the timeout monitor detects a timeout associated with a pulse detected in the clock signal, triggers the slave device to perform a resynchronization process (e.g., to synchronize the slave device with the master device). Accordingly, during data communication transmission, the period of the clock signal may be configured to remain within a certain interval. Accordingly, the upper limit T of the period of the clock signal may be based on the upper limit T of the period of the clock signal. max To configure and / or determine the timeout threshold. In some implementations, the timeout threshold is a predetermined and / or preconfigured duration (e.g., based on design, manufacturing, etc.). Whenever the timing between the two clock signals is longer than the timeout threshold T out When the timeout threshold is T, the timeout monitor may reset the slave shift register (eg, the interface block of the slave device's interface). For example, the value for the timeout threshold may correspond to T max Add a certain margin Δt, so that T out =T max +Δt.

[0018] In this manner, the timeout monitor may be configured to detect whether a timeout has occurred between pulses of the clock signal.

[0019] like Figure 1B As shown in the figure mark 110, the slave device receives a clock signal from the master device. As described herein, the clock output is used to time the data communication between the master device and the slave device. The transmission of data can involve transmitting bits between the main shift register and / or the slave shift register. For example, the data transmitted from the master device to the slave device can include shifting the bit from the main shift register to the slave shift register through the bus with each pulse of the clock signal (when the slave device detects a pulse in the clock signal). On the other hand, the data transmitted from the slave device to the master device can include shifting the bit from the slave shift register to the main shift register through the bus with each pulse of the clock signal.

[0020] Accordingly, to transmit a data communication having n bits (e.g., a word, a data set, etc.), the clock signal may include n pulses to transmit the data communication. The data communication may correspond to a control message (e.g., which may be sent from a master device to a slave device to trigger a sensor element of the slave device to capture a measurement result), a measurement result (e.g., which may be sent from a slave device to a master device), etc. In the example implementation 100, the master shift register and the slave shift register are shift registers having the same length n, which allows both the master shift register and the slave shift register to store up to n bits. In some implementations, the master shift register and / or the slave shift register may have shift registers of different lengths.

[0021] In this manner, a slave device may receive a clock signal to allow the slave device to monitor a timeout of the clock signal associated with a detected pulse of the clock signal.

[0022] like Figure 1B As further shown at 120, the timeout monitor detects pulses of the clock signal and / or timeouts associated with the pulses. For example, for each clock pulse detected by the timeout monitor, the timeout monitor may trigger the RMM, which is configured to trigger the RMM at a fixed time (e.g., which may correspond to a timeout threshold T out ) after clearing the shift register. Additionally or alternatively, the timeout monitor can use a counter and an internal clock (or timer), etc. For example, after each pulse, the timeout monitor can trigger the RMM and / or start the counter and increment the counter according to the internal clock, and if the counter reaches a value corresponding to the timeout before the timeout is detected, the timeout monitor can detect a timeout associated with the clock signal. Accordingly, if another pulse is detected before the timeout threshold, the timeout monitor can re-trigger the RMM and / or reset the counter and track the amount of time that has passed since the pulse. However, if the amount of time that has passed since the pulse reaches (or meets) the timeout threshold, the timeout monitor can determine that a timeout associated with the clock signal has occurred.

[0023] Accordingly, as described herein, a timeout monitor may include a time parameter set to T out An RMM (e.g., an asynchronous RMM) and / or a counter utilizing an internal clock, or can be implemented via such an RMM and / or a counter.

[0024] In the example implementation 100, the interface of the slave device is clocked by a clock signal received via a clock line. When a pulse (and / or another type of similar clock event) is detected in the clock signal, the timeout monitor can be triggered (e.g., to begin monitoring for another pulse in the clock signal), and bits are shifted into the slave shift register of the slave device. In some implementations, the timeout can be triggered based on a notification and / or message from the interface. At Tout After each clock event that occurs within a slave shift register, the timeout monitor is retriggered and another bit is shifted into the slave shift register. When the shift register is full, the timeout monitor can be disabled and the data or value in the slave shift register can be interpreted by the slave device (e.g., execute a command, write data to an internal data structure or memory, etc.). In some implementations, when the shift register is full, a data set (e.g., word) of a data communication has been completely transmitted and received, and subsequent data communications can be transmitted immediately (e.g., without resetting the slave shift register).

[0025] Accordingly, the timeout monitor can determine whether the timeout threshold expires before another pulse of the clock signal is detected, or whether another pulse of the clock signal is detected before the timeout threshold expires. When another pulse of the clock signal is detected before the timeout threshold expires, the slave device can shift the bit from the bus to the slave shift register, because the slave device may think that the clock signal is in normal or standard operation. However, when the timeout threshold expires before another pulse of the clock signal is detected, the slave device timeout monitor can indicate that a timeout has occurred, to indicate that an error associated with the clock signal has occurred (or may have occurred) and therefore the slave device is not synchronized with the master device.

[0026] In this way, the slave device may detect a timeout of a detected pulse relative to the clock signal via the timeout monitor to allow the slave device to self-trigger a resynchronization process to resynchronize the slave device with the master device.

[0027] like Figure 1B As further shown at 130, if the timeout monitor detects a timeout from a pulse of the clock signal, the timeout monitor resets the slave shift register. For example, if the timeout monitor detects that the timing between two pulses (or the timing after a pulse) is greater than or equal to the timeout threshold T out , the timeout monitor may reset the slave shift register. In some implementations, to reset the slave shift register, the timeout monitor may cause the interface to clear any or all bits in the slave shift register. With the slave shift register reset, the slave device is resynchronized with the master device and is able to receive subsequent data communications. Thus, whenever the master and slave devices are out of sync (or asynchronous), the master device may wait for the timeout threshold T before starting a new transmission (which has been passed and detected by the timeout monitor of the slave device). out In this manner, when the master and slave devices are out of sync, the master and / or slave devices may spend relatively little or no time to resynchronize.

[0028] In some implementations, one or more communication protocols for bidirectional communication can be implemented. For example, for a bidirectional communication protocol, the first word of a transmission frame can be written from a master device to a slave device. The first word can include a bit indicating whether a subsequent word is to be written to a slave device or read from a slave device. In some implementations, for writing to a slave device, the second word can include a register address to be written by the master device. In this case, subsequent words can be written to a slave shift register starting from the register address. In some implementations, for reading from a slave device, the second word can be transmitted from a master control device to a slave device. The second word can include a register address from which the master device will read. In this case, subsequent words can be read from a slave shift register starting from the register address. Alternatively or additionally, for reading from a slave device, subsequent words can be read from a slave shift register starting from register address zero. In some implementations, in order to prevent the output drivers from the master device and the slave device from driving each other in the case of an erroneous transmission, the output driver can be configured as an open drain and a pull-up resistor of a bus can be used. In this way, data can be cleared from a slave shift register via a pull-up resistor of a bus.

[0029] In this manner, when a slave device becomes out of sync with a master device (eg, due to erroneous transmissions, glitches in the clock signal, interference, etc.), the slave device can resynchronize with the master device.

[0030] like Figure 1B As further shown in the figure 140, the slave device can be configured to indicate to the master device that the slave shift register has been reset. For example, the slave device can use a flag (e.g., a status bit) to notify the master device, which indicates that the slave device has resynchronized with the master device based on the value of the flag (e.g., "0" or "1"). Accordingly, whenever the timeout monitor (e.g., via the RMM) resets the slave shift register, a dedicated flag (e.g., a clear flag when reading) can be set. In this case, after the master device sends each data communication (e.g., after all bits of the data communication have been transmitted), the master device can wait for the timeout threshold T out , and then read the value of the dedicated flag. For example, a value of "0" may indicate that no resynchronization occurred, while a value of "1" may indicate that a resynchronization was performed by the slave device, and / or accordingly, data communications may have failed. In this way, the master device may be notified that one or more actions are to be performed to resolve any potential failed data communications associated with the slave device performing a self-triggered resynchronization. In addition, the flag may be cleared after the master device reads the flag so that subsequent data communications can be received and properly verified.

[0031] In some implementations, the slave device can identify the word length (e.g., the number of bits of data communication) for data communication. The word length can be preconfigured (e.g., based on the length of the shift register). In this case, the slave device can determine that the number of bits in the shift register does not match the word length, and send a notification to the master device (e.g., via subsequent communications, via a flag, etc.) to reflect that the number of bits in the shift register does not match the word length and / or indicate that an error occurs, an error may occur, or an error may have occurred. In some implementations, the master device can include a checksum (e.g., parity check, cyclic redundancy check (CRC), MD5sum, etc.) in the data communication. Accordingly, the slave device can use the checksum in association with the previously received data communication and / or the value of the shift register to verify whether the data associated with the previously received data communication and / or written from the shift register is valid. In this way, the slave device can notify the master device that an error occurs, an error may occur, or an error may have occurred. Alternatively or additionally, before the shift register is reset, the slave device can provide the value in the shift register to the master device. In this case, the master device can use this value to determine whether an error associated with the clock signal has occurred during data communication. In this way, the master device can be notified that an error associated with the slave device has occurred and / or may have occurred. In addition, the master device can determine that an error associated with data communication involving the slave device has occurred.

[0032] In some implementations, after the data communication, the master device can verify one or more data communications by reading the value of the slave shift register (e.g., within a timeout threshold T out After the expiration of the timeout threshold T, the master device may send a read command to the slave device to cause the slave device to load the previously processed data communication (which may or may not correspond to the transmitted or received data communication, depending on whether an error occurred in the data) into the slave shift register and provide the data communication back to the master device. The data communication may correspond to one or more words of a plurality of words transmitted and / or received as data communications (e.g., one or more recently received data communications). In some implementations, the timeout monitor may prevent the interface from clearing the slave shift register until the timeout threshold T is exceeded. out due to allow the master device to read back the value of the slave shift register to verify that the value in the slave shift register matches the data communication.

[0033] Accordingly, as described herein, the slave device can be configured to perform a resynchronization process based on a timeout between pulses of a monitoring clock signal. As described herein, the resynchronization process can be self-triggered and therefore may not need to be initiated by a master device communicating with the slave device. Accordingly, as shown in example implementation 100, a timeout monitor of a slave device allows the slave device to be communicatively coupled to the master device via only a clock line and a bus for data transmission.

[0034] As shown above, Figure 1A and Figure 1B Provided as an example only. Other examples may be found in Figure 1A and Figure 1B Described differently.

[0035] Figure 2 1 is a diagram of an example implementation 200 described herein. Example implementation 200 illustrates an example state machine that may be used by a slave device of example implementation 100 to handle data communications and / or detect timeouts associated with a clock signal. In example implementation 200, the shift register is clocked by a clock signal of a system clock line (SCL), which may correspond to the clock line of FIG. 1 .

[0036] like Figure 2 As shown in the state machine in FIG. 1 , when a pulse is detected in the idle state (wd_en = "0"), data communication starts and the RMM flip-flop is enabled to activate the RMM (rmm_en = "1"). For each subsequent reception (rx) of a bit of data communication by a corresponding SCL pulse, the RMM flip-flop reactivates (e.g., resets) the RMM (rmm_en = "1"). If the configured timeout threshold T out If no other SCL pulses (eg, clock cycles) are detected within 1 second, the RMM resets the shift register (res_if). At the end of a word (end_of_word), the RMM is disabled (rmm_en="0").

[0037] As mentioned above, Figure 2 Provided as an example only. Other examples may be found in Figure 2 Described differently.

[0038] Figure 3 is a diagram of an example implementation 300 described herein. The example implementation 300 includes an example transmission of data communications from a master device to a slave device (which may correspond to the master and slave devices of FIG. 1 ) and a corresponding clock signal that may be monitored by the slave device as described herein.

[0039] like Figure 3310, a normal (or successful) transmission of a (n+1)-bit long data communication from a master device to a slave device is shown. After the transmission of the word, the master shift register of the master device is empty, and the slave shift register of the slave device is completely filled. Accordingly, after the data communication is completed, both the master device and the slave device are synchronized, and subsequent data communications can be transmitted.

[0040] like Figure 3 As further shown in the figure numeral 320, an erroneous transmission of a (n+1)-bit long data communication from the master device to the slave device may occur because the slave device may not correctly interpret the clock cycle. Therefore, after the master device shifts out a complete data communication, the slave device may still be waiting for one more bit. Accordingly, the master device and the slave device become out of sync. In addition, if a subsequent data communication is transmitted, the master device and the slave device will remain out of sync because the bits from the subsequent data communication will be combined with the bits currently in the slave shift register. However, as described herein, after the transmission of the data communication ends, the timeout threshold T out After expiration, the slave device's time-out monitor can reset the slave shift register to resynchronize the slave and master devices.

[0041] like Figure 3 As further shown in FIG. 330, due to a glitch on the clock line, a transmission error may occur. For example, the slave device may interpret the glitch as a pulse and load the first data bit into the slave shift register (which may be equal to the bus idle state). Accordingly, the master device and the slave device become out of sync. At the timeout threshold T from the detected glitch, the master device and the slave device may be out of sync. out Afterwards, the slave device's time-out monitor can reset the slave shift register to resynchronize the slave and master devices.

[0042] As mentioned above, Figure 3 Provided as an example only. Other examples may be found in Figure 3 Described differently.

[0043] Figure 4 4 is a diagram of an example environment 400 in which the systems and / or methods described herein may be implemented. Figure 4 As shown, environment 400 may include a bus 410, a master device 420, and one or more slave devices 430 (referred to herein individually and collectively as "slave devices 430").

[0044] The bus 410 is any suitable bus configured for master-slave communication between the master device 420 and the slave device 430. In some implementations, the bus may include a single wired connection (e.g., for unidirectional communication, for communication in one direction at a time, etc.). In some implementations, the bus may include two or more wired connections (e.g., for bidirectional communication between the master device 420 and the slave device 430 at the same time). In this case, the first wired connection may provide master-to-slave communication (e.g., from the master device 420 to the slave device 430), and the second wired connection may provide slave-to-master communication (e.g., from the slave device 430 to the master device 420).

[0045] As described herein, the master device 420 includes one or more devices that can be used as a master device with respect to a master-slave communication protocol. For example, the master device 420 can be any suitable device configured to control the communication and / or clock of the device in the environment 400. The master device 420 is implemented in hardware, firmware and / or a combination of hardware and software. In some implementations, the master device 420 may include a processor in the form of a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC) or other types of processing components. The master device 420 may include one or more processors that can be programmed to perform a function (e.g., control slave device 430).

[0046] The slave device 430 includes one or more devices that can be used as a slave device with respect to the master-slave communication protocol. For example, the slave device 430 may include a sensor (e.g., a magnetic sensor, a temperature sensor, a pressure sensor, a microphone, a light sensor, etc.), a peripheral device of the system (e.g., an input component, an output component, etc.), etc. As described herein, the slave device 430 can be a device that can communicate via the SPI communication protocol.

[0047] According to some implementations, the master device 420 and the slave device 430 may be the same type of device (e.g., having the same brand, make, model, etc.). In this case, the master device 420 and the slave device 430 may exchange one or more data communications to establish the master device 420 as a master device and the slave device 430 as a slave device for master-slave data communications via the bus 410.

[0048] Figure 4 The number and arrangement of devices and networks shown are provided as one or more examples. In practice, there may be Figure 4 More devices and / or networks, fewer devices and / or networks, different devices and / or networks, or differently arranged devices and / or networks than shown. Figure 4 Two or more of the devices shown may be implemented in a single device, or Figure 4 The single device shown may be implemented as multiple distributed devices.Alternatively or additionally, one set of devices (eg, one or more devices) of environment 400 may perform one or more functions described as being performed by another set of devices of environment 400.

[0049] Figure 5 is a diagram of example components of device 500. Device 500 may correspond to Figure 4 One or more of the slave devices 430. As shown, the device 500 may include a set of sensing elements 510 (which are individually referred to as "sensing elements 510" or collectively referred to as "sensing elements 510" in this document), an analog-to-digital converter (ADC) 520, a digital signal processor (DSP) 530, a memory 540, and a digital interface 550.

[0050] The sensing element 510 includes an element for sensing a component or a set of components of a magnetic field present at the device 500. For example, the sensing element 510 may include a Hall-based sensing element operating based on the Hall effect. As another example, the sensing element 510 may include a magnetoresistance-based (MR-based) sensing element, whose element is composed of a magnetoresistance material (e.g., nickel iron (NiFe)), wherein the resistance of the magnetoresistance material may depend on the strength and / or direction of the magnetic field present at the magnetoresistance material. Here, the sensing element 510 may operate based on anisotropic magnetoresistance (AMR) effect, giant magnetoresistance (GMR) effect, tunnel magnetoresistance (TMR) effect, etc. As an additional example, the sensing element 510 may include a variable magnetoresistance (VR)-based sensing element operating based on induction. In some implementations, the device 500 may include a differential sensor having a plurality of sensing elements 510. For example, the device 500 may include a first sensing element 510 for sensing a first set of components of a magnetic field at a first sensing element and a second sensing element 510 for sensing a second set of components of a magnetic field at a second sensing element. In this case, the device 500 can calculate the difference between the component quantities of the magnetic field to determine the position of the magnet (and / or an actuator or valve connected to the magnet).

[0051] The ADC 520 may include an analog-to-digital converter that converts analog signals from the set of sensing elements 510 into digital signals. For example, the ADC 520 may convert analog signals received from the set of sensing elements 510 into digital signals to be processed by the DSP 530. The ADC 520 may provide the digital signals to the DSP 530. In some implementations, the device 500 may include one or more ADCs 520.

[0052] The DSP 530 may include a digital signal processing device or a collection of digital signal processing devices. In some implementations, the DSP 530 may receive a digital signal from the ADC 520 and may process the digital signal to form an output signal, such as an output signal associated with a bit or value in a shift register. The DSP 530 may include a timeout monitor (e.g., the timeout monitor of the example implementation 100). For example, as described herein, the DSP 530 may include an RMM, a counter, an internal clock, etc. to allow the DSP 530 to monitor a clock signal and / or detect a timeout associated with the clock signal.

[0053] The memory 540 may include a read-only memory (ROM) (e.g., an electrically erasable programmable read-only memory (EEPROM)), a random access memory (RAM), and / or another type of dynamic or static storage device (e.g., flash memory, magnetic memory, optical memory, etc.) that stores information and / or instructions for use by the device 500. In some implementations, the memory 540 may store information associated with processing performed by the DSP 530. Additionally or alternatively, the memory 540 may store configuration values ​​or parameters for the set of sensing elements 510 and / or information for one or more other elements of the device 500 (such as the ADC 520 or the digital interface 550).

[0054] Digital interface 550 may include interfaces via which device 500 may receive data from another device such as Figure 4 The digital interface 550 may include an interface for receiving information from a master device 420 and / or providing information to another device. For example, the digital interface 550 may provide output signals determined by the DSP 530 to the master device 420 and / or may receive information from the master device 420. In some implementations, the digital interface may include registers, such as shift registers, as described herein.

[0055] Figure 5 The number and arrangement of elements shown are provided as examples. In practice, the device 500 may include Figure 5 More elements, fewer elements, different elements, or differently arranged elements than shown.Alternatively or additionally, one set of elements (eg, one or more elements) of device 500 may perform one or more functions described as being performed by another set of elements of device 500.

[0056] Figure 6 is a flow chart of an example process 600 associated with a clock signal monitor for a slave device on a master-slave communication bus. In some implementations, Figure 6 One or more process blocks of may be performed by a slave device (e.g., slave device 430). In some implementations, Figure 6One or more process blocks of may be performed by another device or a group of devices, such as a master device (eg, master device 420), separate from or including the slave device.

[0057] like Figure 6 As shown, process 600 may include receiving a clock signal, wherein the clock signal is received from a master device via a bus (block 610). For example, as described above, the slave device (e.g., using a slave shift register, a timeout monitor, DSP 530, memory 540, digital interface 550, etc.) may receive the clock signal. In some implementations, the clock signal is received from the master device via a bus.

[0058] like Figure 6 As further shown, process 600 may include detecting a first pulse of a clock signal, wherein the first pulse indicates a bit to be written to or from a slave shift register of a slave device (block 620). For example, as described above, a slave device (e.g., using a slave shift register, a timeout monitor, DSP 530, memory 540, digital interface 550, etc.) may detect the first pulse of the clock signal. In some implementations, the first pulse indicates a bit to be written to a slave shift register of a slave device.

[0059] like Figure 6 As further shown, process 600 may include identifying a timeout threshold associated with the clock signal (block 630). For example, as described above, the slave device (e.g., using a slave shift register, a timeout monitor, DSP 530, memory 540, digital interface 550, etc.) may identify a timeout threshold associated with the clock signal.

[0060] like Figure 6 As further shown, process 600 may include determining that a timeout threshold has expired without detecting a second pulse from the clock signal (block 640). For example, as described above, the slave device (e.g., using a slave shift register, a timeout monitor, DSP 530, memory 540, digital interface 550, etc.) may determine that a timeout threshold has expired without detecting a second pulse from the clock signal.

[0061] like Figure 6 As further shown, process 600 may include resetting the slave shift register based on expiration of a timeout threshold to synchronize the slave shift register with a master shift register of the master device (block 650). For example, as described above, the slave device (e.g., using the slave shift register, timeout monitor, DSP 530, memory 540, digital interface 550, etc.) may reset the slave shift register based on expiration of a timeout threshold to synchronize the slave shift register with a master shift register of the master device.

[0062] Process 600 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein.

[0063] In a first implementation, the duration of the timeout threshold is preconfigured based on a period of the clock signal.In a second implementation, alone or in combination with the first implementation, when resetting the slave shift register, the slave device may include clearing all entries of the slave shift register.

[0064] In a third implementation, alone or in combination with one or more of the first and second implementations, a slave device may identify a word length associated with data communications on a bus, determine based on expiration of a timeout threshold that the number of bits in the slave shift register does not match the word length, and send a notification to a master device that an error has occurred based on determining that the number of bits in the slave shift register does not match the word length.

[0065] In a fourth implementation, alone or in combination with one or more of the first to third implementations, the slave device may enable the bit value of the slave shift register to be read by the master device based on receiving a read command from the master device before resetting the slave shift register to allow the master device to detect errors associated with data communication on the bus. In a fifth implementation, alone or in combination with the fourth implementation, the data communication includes a most recently received word of a plurality of words transmitted via the bus.

[0066] In a sixth implementation, either alone or in combination with one or more of the first to fifth implementations, the slave device may set a flag based on resetting the slave shift register to indicate to the master device that the slave shift register has been reset. In a seventh implementation, either alone or in combination with one or more of the first to sixth implementations, the slave device communicates with the master device via a serial peripheral interface (SPI) communication protocol. In an eighth implementation, either alone or in combination with one or more of the first to seventh implementations, the slave shift register is reset using RMM.

[0067] although Figure 6 Example blocks of process 600 are shown, but in some implementations, process 600 may include Figure 6 More blocks, fewer blocks, different blocks, or differently arranged blocks than shown. Alternatively or additionally, two or more blocks of process 600 may be performed in parallel.

[0068] Figure 7 is a flow chart of an example process 700 associated with a clock signal monitor for a slave device on a master-slave communication bus. In some implementations, Figure 7 One or more process blocks of may be performed by a slave device (e.g., slave device 430). In some implementations, Figure 7One or more process blocks of may be performed by another device or a group of devices, such as a master device (eg, master device 420), separate from or including the slave device.

[0069] like Figure 7 As shown, process 700 may include monitoring a clock signal associated with a bus, wherein the clock signal is used to store bits of data communications in a shift register, and wherein the data communications are received from a master device via the bus (block 710). For example, as described above, a slave device (e.g., using a shift register, a timeout monitor, a DSP 530, a memory 540, a digital interface 550, etc.) may monitor a clock signal associated with the bus. In some implementations, the clock signal is used to store bits of data communications in a shift register. In some implementations, the data communications are received from a master device via the bus.

[0070] like Figure 7 As further shown, process 700 may include detecting a first pulse of a clock signal (block 720). For example, as described above, a slave device (e.g., using a slave shift register, a timeout monitor, DSP 530, memory 540, digital interface 550, etc.) may detect the first pulse of the clock signal.

[0071] like Figure 7 As further shown, process 700 may include determining whether a timeout threshold expires before the second pulse is detected or whether the second pulse is detected before determining that the timeout threshold expires (block 730). For example, as described above, the slave device (e.g., using a slave shift register, a timeout monitor, DSP 530, memory 540, digital interface 550, etc.) may determine whether a timeout threshold expires before the second pulse is detected or whether the second pulse is detected before determining that the timeout threshold expires.

[0072] like Figure 7 As further shown, process 700 may include resetting a timeout timer associated with the clock signal when the second pulse is detected before determining that the timeout threshold has expired (block 740). For example, as described above, the slave device (e.g., using a slave shift register, a timeout monitor, DSP 530, memory 540, digital interface 550, etc.) may reset the timeout timer associated with the clock signal when the second pulse is detected before determining that the timeout threshold has expired.

[0073] like Figure 7As further shown, process 700 may include resetting the shift register to synchronize the shift register with the master shift register of the master device when the timeout threshold expires before the second pulse is detected (block 750). For example, as described above, the slave device (e.g., using the slave shift register, timeout monitor, DSP 530, memory 540, digital interface 550, etc.) may reset the shift register to synchronize the shift register with the master shift register of the master device when the timeout threshold expires before the second pulse is detected.

[0074] Process 700 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in combination with one or more other processes described elsewhere herein.

[0075] In a first implementation, when the second pulse is detected before it is determined that the timeout threshold has expired, the slave device can determine whether the timeout threshold has expired before the third pulse is detected or whether the third pulse is detected before it is determined that the timeout threshold has expired; and when the third pulse is detected before it is determined that the timeout threshold has expired, the slave device can reset a timeout timer associated with a clock signal, or when the timeout threshold expires before the third pulse is detected, the slave device can reset a shift register to synchronize the shift register with a master shift register of the master device.

[0076] In a second implementation, either alone or in combination with the first implementation, when the second pulse is detected before determining that the timeout threshold has expired, the slave device may determine that the second pulse is associated with the last bit of data communication based on the shift register being full; write the value associated with the shift register to the data structure; and reset the shift register.

[0077] In a third implementation, alone or in combination with one or more of the first and second implementations, when the timeout threshold expires before the second pulse is detected and before the shift register is reset, the timeout monitor may perform at least one of the following: sending a notification to the master device to indicate an error associated with the clock signal based on a mismatch between the number of bits in the shift register and the word length used for data communication; providing a value to the master device in the shift register, wherein the value indicates that an error associated with the clock signal may have occurred when receiving data communication; or setting a flag to indicate to the master device that the shift register has been reset.

[0078] In a fourth implementation, either alone or in combination with one or more of the first to third implementations, the slave device may include a sensor element, and the bit of the data communication will cause the device to perform an action associated with the sensor element. In a fifth implementation, either alone or in combination with one or more of the first to fourth implementations, the slave device may include a serial peripheral interface device without a dedicated chip select line connection to synchronize a shift register with a master shift register.

[0079] although Figure 7 Example blocks of process 700 are shown, but in some implementations, process 700 may include Figure 7 More blocks, fewer blocks, different blocks, or differently arranged blocks than shown. Additionally or alternatively, two or more blocks of process 700 can be executed in parallel.

[0080] Figure 8 is a flow chart of an example process 800 associated with a clock signal monitor for a slave device on a master-slave communication bus. In some implementations, Figure 8 One or more process blocks of may be performed by a slave device (e.g., slave device 430). In some implementations, Figure 8 One or more process blocks of may be performed by another device or a group of devices, such as a master device (eg, master device 420), separate from or including the slave device.

[0081] like Figure 8 As shown, process 800 may include monitoring a clock signal received from a master device via a bus, wherein the slave device stores bits of data communication in a slave shift register based on the clock signal (block 810). For example, as described above, a slave device (e.g., using a slave shift register, a timeout monitor, DSP 530, memory 540, digital interface 550, etc.) may monitor a clock signal received from a master device via a bus. In some implementations, the slave device stores bits of data communication in a slave shift register based on the clock signal.

[0082] like Figure 8 As further shown, process 800 may include determining that a timeout threshold has expired based on timing associated with pulses of a clock, wherein the pulses of the clock signal include the most recently detected pulses of the clock signal (block 820). For example, as described above, a slave device (e.g., using a slave shift register, a timeout monitor, DSP 530, memory 540, digital interface 550, etc.) may determine that a timeout threshold has expired based on timing associated with pulses of a clock. In some implementations, the pulses of the clock signal include the most recently detected pulses of the clock signal.

[0083] like Figure 8 As further shown, process 800 may include resetting the slave shift register based on determining that the timeout threshold has expired to synchronize the slave shift register with the master shift register of the master device (block 830). For example, as described above, the slave device (e.g., using the slave shift register, timeout monitor, DSP 530, memory 540, digital interface 550, etc.) may reset the slave shift register based on determining that the timeout threshold has expired to synchronize the slave shift register with the master shift register of the master device.

[0084] Process 800 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein.

[0085] In a first implementation, the most recently detected pulse includes at least one of: an erroneous pulse of a clock signal or a pulse for a last bit of data communication. In a second implementation, alone or in combination with the first implementation, the slave device may determine that the second pulse is associated with a last bit of data communication based on the slave shift register being full, write a value associated with the slave shift register to the data structure based on the slave shift register being full, and reset the slave shift register after writing the value to the data structure.

[0086] In a third implementation, alone or in combination with one or more of the first and second implementations, the master device and the slave device are communicatively coupled via only a bus and a clock line, wherein the bus is used for data communication and the clock line is used for transmission of a clock signal. In a fourth implementation, alone or in combination with one or more of the first to third implementations, the master device is a sensor device, or the slave device is a sensor device.

[0087] although Figure 8 An example block diagram of process 800 is shown, but in some implementations, process 800 may include Figure 8 More blocks, fewer blocks, different blocks, or differently arranged blocks than shown. Additionally or alternatively, two or more blocks of process 800 can be executed in parallel.

[0088] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications and variations may be made in light of the above disclosure, or may be acquired from practice of the implementation.

[0089] As used herein, the term "component" is intended to be broadly interpreted as hardware, firmware, and / or a combination of hardware and software.

[0090] Some implementations are described herein in conjunction with thresholds. As used herein, depending on the context, satisfying a threshold may refer to being greater than a threshold, more than a threshold, above a threshold, greater than or equal to a threshold, less than a threshold, less than a threshold, below a threshold, less than or equal to a threshold, equal to a threshold, and the like.

[0091] Obviously, the systems and / or methods described herein can be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods does not limit the implementation. Therefore, the operation and behavior of the systems and / or methods are described herein without reference to specific software codes - it should be understood that software and hardware can be designed to implement the systems and / or methods based on the description herein.

[0092] Even though particular combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of various implementations. In fact, many of these features may be combined in ways not specifically recited in the claims and / or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of various implementations includes each dependent claim in combination with every other claim in the claim set.

[0093] Unless explicitly described, the elements, actions or instructions used in this article should not be interpreted as being key or necessary. In addition, as used in this article, the articles "a" and "an" are intended to include one or more projects, and can be used interchangeably with "one or more". In addition, as used in this article, the article "the" is intended to include one or more projects quoted in conjunction with the article "the", and can be used interchangeably with "one or more". In addition, as used in this article, the term "set" is intended to include one or more projects (for example, related projects, unrelated projects, combinations of related and unrelated projects, etc.), and can be used interchangeably with "one or more". In the case of only intending a project, phrases "only one" or similar language are used. In addition, as used in this article, the terms "has", "have", "having" etc. are intended to be open terms. In addition, unless otherwise expressly stated, phrases "based on" are intended to represent "based at least in part on". Furthermore, as used herein, the term "or" when used in tandem is intended to be inclusive and may be used interchangeably with "and / or" (e.g., when used in conjunction with "either" or "only one of") unless expressly stated otherwise.

Claims

1. A method comprising: The slave device receives the clock signal. wherein the clock signal is received from a master device via a bus; detecting, by the slave device, a first pulse of the clock signal, wherein the first pulse indicates a bit to be written into or written from a slave shift register of the slave device; monitoring, by the slave device, a timeout associated with the clock signal; determining, by the slave device, that a timeout threshold corresponding to the timeout expires without a second pulse from the clock signal being detected; as well as The slave shift register is reset by the slave device and based on expiration of the timeout threshold to synchronize the slave shift register with a master shift register of the master device. 2 . The method of claim 1 , wherein the duration of the timeout threshold is preconfigured based on a period of the clock signal.

3. The method of claim 1 , wherein resetting the slave shift register comprises: Clears all entries in the slave shift register.

4. The method according to claim 1, further comprising: identifying a word length associated with data communications on the bus; determining, based on expiration of the timeout threshold, that the number of bits in the slave shift register does not match the word length; as well as A notification is sent to the master device that an error has occurred based on determining that the number of bits in the slave shift register does not match the word length.

5. The method according to claim 1, further comprising: Prior to resetting the slave shift register and based on receiving a read command from the master device, the bit values ​​of the slave shift register are enabled to be read by the master device to allow the master device to detect errors associated with data communications on the bus.

6. The method of claim 5, wherein the data communication comprises a most recently received word of a plurality of words transmitted via the bus.

7. The method according to claim 1, further comprising: A flag is set upon resetting the slave shift register to indicate to the master device that the slave shift register has been reset.

8. The method of claim 1, wherein the slave device communicates with the master device via a serial peripheral interface (SPI) communication protocol.

9. The method of claim 1, wherein the slave shift register is reset using a retriggerable monostable multivibrator.

10. A device comprising: Shift register; as well as a time-out monitor communicatively coupled to the shift register, the time-out monitor being configured to: Monitors the clock signal associated with the bus, wherein the clock signal is used to store bits of data communication in the shift register, and wherein the data communication is received from a master device via the bus; detecting a first pulse of the clock signal; determining whether a timeout threshold expires before a second pulse is detected, or whether a second pulse is detected before determining that the timeout threshold expires; as well as When the second pulse is detected before determining that the timeout threshold has expired, resetting a timeout timer associated with the clock signal, or When the timeout threshold expires before the second pulse is detected, the shift register is reset to synchronize the shift register with a master shift register of the master device.

11. The apparatus of claim 10, wherein when the second pulse is detected before determining that the timeout threshold has expired, the timeout monitor is further configured to: determining whether the timeout threshold expires before a third pulse is detected, or whether a third pulse is detected before determining that the timeout threshold expires; and When the third pulse is detected before determining that the timeout threshold has expired, resetting the timeout timer associated with the clock signal, or When the timeout threshold expires before a third pulse is detected, the shift register is reset to synchronize the shift register with the master shift register of the master device.

12. The apparatus of claim 10, wherein when the second pulse is detected before determining that the timeout threshold has expired, the timeout monitor is further configured to: determining that the second pulse is associated with a last bit of the data communication based on the shift register being full; writing a value associated with the shift register to a data structure based on the shift register being full; and After writing the value to the data structure, the shift register is reset.

13. The apparatus of claim 10 , wherein when the timeout threshold expires before the second pulse is detected and before the shift register is reset, the timeout monitor is configured to perform at least one of the following: sending a notification to the master device indicating an error associated with the clock signal based on a mismatch between a number of bits in the shift register and a word length used for the data communication; providing a value in the shift register to the master device, wherein the value indicates that an error associated with the clock signal may have occurred while receiving the data communication; or A flag is set to indicate to the master device that the shift register has been reset.

14. The device according to claim 10, wherein the device further comprises a sensor element, The bit of the data communication will cause the device to perform an action associated with the sensor element.

15. The device of claim 10, wherein the device comprises a serial peripheral interface device without a dedicated chip select line connection to synchronize the shift register with the master shift register.

16. A system comprising a bus and a master device configured to transmit data communications via the bus, the system comprising: The slave device is configured as: monitoring a clock signal received from the master device via the bus, wherein the slave device will store bits of the data communication in a slave shift register based on the clock signal; determining that a timeout threshold has expired based on timing associated with pulses of the clock, wherein said pulse of said clock signal comprises a most recently detected pulse of said clock signal; as well as Based on determining that the timeout threshold has expired, resetting the slave shift register to synchronize the slave shift register with a master shift register of the master device.

17. The system of claim 16, wherein the most recently detected pulse comprises at least one of: an erroneous pulse of the clock signal, or Pulse for the last bit of the data communication.

18. The system of claim 16, wherein the slave device is further configured to: determining that the pulse is associated with a last bit of the data communication based on the slave shift register being full; Based on the slave shift register being full, writing a value associated with the slave shift register to a data structure; and After the value is written to the data structure, the slave shift register is reset.

19. The system of claim 16, wherein the master device and the slave device are communicatively coupled via only the bus and clock lines, The bus is used for the data communication, and the clock line is used for transmitting the clock signal.

20. The system of claim 16, wherein the master device is a sensor device or the slave device is a sensor device.

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