Analog vector-matrix multiplication operation circuit and chip

Abstract

The present invention provides an analog vector-matrix multiplication operation circuit and a chip. By using the characteristic that the analog vector-matrix multiplication operation performs matrix multiplication and addition on the received analog current signal and the result is the output current accumulation value, the function of a high-precision DAC is realized by combining multiple low-precision DACs. Each level of DAC converts partial bit positions of the digital input signal into analog current signals respectively; there are no repeated bit positions in the bit positions converted by each level of DAC, and the number of each level of DAC is greater than or equal to the total number of digital input signals to be operated; the conversion device includes multiple levels of conversion circuits corresponding to the multiple levels of DACs. Each level of conversion circuit is used to convert the analog current signal output by the corresponding DAC into an analog voltage signal of the corresponding magnitude, and then the processed signal is sent to the flash memory processing array for operation, so as to realize the function of a high-precision DAC by combining multiple low-precision DACs, and reduce the circuit area and delay.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and particularly to an analog vector-matrix multiplication operation circuit and a chip. Background Art

[0002] Matrix multiplication operations are widely used in data mining fields such as image processing, recommendation systems, and data dimensionality reduction. Vector-matrix multiplication is a commonly used arithmetic operation function. With the pursuit of extremely low performance and low power consumption, more and more systems directly implement vector-matrix multiplication operations using hardware circuits. In particular, analog vector-matrix multiplication operation circuits based on flash memory cells have received the favor of chip designers.

[0003] Existing analog vector-matrix multiplication circuits usually need to set up a DAC (digital-to-analog conversion circuit) to convert a multi-bit digital input signal into an analog current signal, and then use a conversion circuit to convert the analog current signal into an analog voltage signal, and then use a flash memory processing array to perform analog vector-matrix multiplication operations on the analog voltage signal. Among them, each row input of the flash memory processing array needs to correspond to a high-precision DAC (such as 6 bits, 8 bits, 12 bits, etc.). As is known to those skilled in the art, high-precision DACs usually have a relatively large area and a relatively long setup time (the time from the start of input to output stability). Therefore, the existing analog vector-matrix multiplication circuits occupy a large circuit area, seriously affecting the cost and processing frequency of the circuit. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide an analog vector-matrix multiplication operation circuit and a chip, which use a low-precision DAC to synthesize a high-precision DAC to reduce the area and setup time of the circuit, thereby reducing the cost of the circuit and improving the low processing frequency.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] In a first aspect, an analog vector-matrix multiplication operation circuit is provided, including: a DAC module, a conversion device, and a flash memory processing array; wherein,

[0007] The DAC module includes a multi-stage DAC for converting all bit positions of a digital input signal into a plurality of analog current signals, and each stage of the DAC converts a partial bit position of the digital input signal into an analog current signal;

[0008] The bit positions converted by each stage of the DAC do not have duplicate bits, and the number of each stage of the DAC is greater than or equal to the total number of digital input signals to be operated;

[0009] The conversion device includes a multi-stage conversion circuit corresponding to the multi-stage DAC. Each stage of the conversion circuit is used to convert the analog current signal output by the corresponding DAC into an analog voltage signal of the corresponding magnitude;

[0010] The flash memory processing array performs operations on the analog voltage signal.

[0011] Further, for the same input current, the output voltage U m of the m-th stage conversion circuit and the output voltage U n of the n-th stage conversion circuit has a ratio of:

[0012] U m : U n = 2 x-1 : 2 y-1

[0013] where x represents the lowest bit number among the bits converted by the DAC corresponding to the m-th stage conversion circuit, and y represents the lowest bit number among the bits converted by the DAC corresponding to the n-th stage conversion circuit.

[0014] Further, the highest stage conversion circuit includes a current-voltage conversion unit. The n-th stage conversion circuit includes: z current-voltage conversion units connected in parallel, where z represents the ratio of the output voltage of the highest stage conversion circuit to the output voltage of the n-th stage conversion circuit for the same input current.

[0015] Further, the current-voltage conversion unit includes: a transistor. The gate and drain of the transistor are connected and are connected between the output terminal of the corresponding DAC and the input terminal of the flash memory processing array, and the source is connected to a bias voltage;

[0016] where the number of the transistors is greater than or equal to 1.

[0017] Further, the current-voltage conversion unit includes: an operational amplifier and a transistor,

[0018] The inverting input terminal of the operational amplifier is connected to the output terminal of the corresponding DAC and is connected to the drain of the transistor; the non-inverting input terminal of the operational amplifier is connected to a bias voltage; the output terminal of the operational amplifier is connected to the source of the transistor and is connected to the input terminal of the flash memory processing array; the gate of the transistor is connected to a bias voltage;

[0019] where the number of the transistors is greater than or equal to 1.

[0020] Further, the flash memory processing array includes flash memory cells arranged in an array, and the threshold voltage of each flash memory cell is adjustable,

[0021] Among them, the threshold voltages of the flash memory cells of some bit positions corresponding to the same digital input signal in the same column are equal.

[0022] Further, the flash memory processing array includes: a flash memory cell array and a subtractor;

[0023] The flash memory cell array includes: a positive weight column and a constant column. The number of the subtractors is equal to the number of the positive weight columns and they are connected in one-to-one correspondence. The number of the constant columns is less than the number of the positive weight columns;

[0024] The constant column can be one column or multiple replicated columns;

[0025] The minuend input terminal of the subtractor is correspondingly connected to the output terminal of the positive weight column, the subtrahend input terminal is connected to the output terminal of the constant column, and the output terminal outputs the result of the analog vector-matrix multiplication operation;

[0026] Among them, the subtrahend input terminals of multiple subtractors are connected to the same constant column.

[0027] Further, it further includes:

[0028] A programming circuit, connected to the source, gate, and / or substrate of each flash memory cell in the flash memory cell array, for regulating the threshold voltage of the flash memory cell;

[0029] A controller, connected to the programming circuit, controls the number of flash memory cells put into work and the threshold voltages of each flash memory cell by controlling the operation of the programming circuit.

[0030] Further, it further includes:

[0031] An ADC module, connected to the output terminal of the flash memory processing array, for converting the result of the analog vector-matrix multiplication operation output by the flash memory processing array into a digital output signal.

[0032] In a second aspect, a chip is provided, which is characterized by including the above-mentioned analog vector-matrix multiplication operation circuit.

[0033] The analog vector-matrix multiplication operation circuit and chip provided by the present invention utilize the characteristic that the analog vector-matrix multiplication operation performs matrix multiplication and addition on the received analog current signal to obtain the output current accumulation value, and use a multi-stage low-precision DAC combination to achieve the function of a high-precision DAC. Each stage of the DAC converts some bit positions of the digital input signal into analog current signals respectively; there are no repeated bit positions in the bit positions converted by each stage of the DAC, and the number of each stage of the DAC is greater than or equal to the total number of digital input signals to be operated; the conversion device includes multi-stage conversion circuits corresponding to the multi-stage DACs. Each stage of the conversion circuit is used to convert the analog current signal output by the corresponding DAC into an analog voltage signal of the corresponding magnitude, and then the processed signal is sent to the flash memory processing array for operation, so as to achieve the function of using a multi-stage low-precision DAC combination to achieve a high-precision DAC, effectively reducing the area and setup time of the DAC, thereby reducing the cost of the analog vector-matrix multiplication operation circuit and chip, and improving the processing frequency.

[0034] In addition, for the analog vector-matrix multiplication operation circuit and chip provided by the present invention, the flash memory processing array includes: a programming semiconductor device array and a subtractor; the flash memory cell array includes: a positive weight column and a constant column. The number of the subtractors is equal to the number of the positive weight columns and they are connected in one-to-one correspondence. The number of the constant columns is less than the number of the positive weight columns; the constant column can be one column or multiple replicated columns; the minuend input end of the subtractor is correspondingly connected to the output end of the positive weight column, the subtrahend input end is connected to the output end of the constant column, and the output end outputs the analog vector-matrix multiplication operation result; among them, the subtrahend input ends of multiple subtractors are connected to the same constant column. Before writing the weights into the flash memory cells, a constant positive value can be added to each element in the weight array to obtain a weight array to be configured. The constant positive value is greater than or equal to the absolute value of the largest negative weight in the weight array, so that there are no negative weights in the weight array to be configured. Then, the weight array to be configured is written into the positive weight column, and the constant positive value is written into the constant column. Since the minuend input end of the subtractor is correspondingly connected to the output end of the positive weight column and the subtrahend input end is connected to the output end of the constant column, it is equivalent to subtracting the influence of the constant positive value from the operation result. In this way, the flash memory processing array in the analog vector-matrix multiplication operation circuit does not need to set a negative weight column, and multiple positive weight columns share the constant column, which can simplify the circuit structure, effectively reduce the number of components, reduce the circuit area, reduce the cost overhead, and facilitate integration.

[0035] To make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given, and in conjunction with the accompanying drawings, the detailed description is as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0037] Figure 1 Shows the structural diagram of the analog vector-matrix multiplication operation circuit according to an embodiment of the present invention;

[0038] Figure 2 Shows the circuit diagram of the analog vector-matrix multiplication operation circuit according to an embodiment of the present invention;

[0039] Figure 3 Shows the circuit of the current-voltage conversion unit in the analog vector-matrix multiplication operation circuit according to an embodiment of the present invention Figure 1 ;

[0040] Figure 4 Shows the circuit of the current-voltage conversion unit in the analog vector-matrix multiplication operation circuit according to an embodiment of the present invention Figure 2 ;

[0041] Figure 5 Shows the circuit of the flash processing array in the analog vector-matrix multiplication operation circuit according to an embodiment of the present invention Figure 1 ;

[0042] Figure 6 Shows the circuit of the flash processing array in the analog vector-matrix multiplication operation circuit according to an embodiment of the present invention Figure 2 。 Detailed implementation manners

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0044] In the existing analog vector-matrix multiplication circuit, each row input of the flash processing array needs to correspond to a high-precision DAC (such as 6 bits, 8 bits, 12 bits, etc.), and the number of DACs is large. Those skilled in the art know that the area and delay of the DAC are positively correlated with its precision. For example, the circuit scale of an 8-bit DAC is 2 4 times that of a 4-bit DAC. Therefore, the existing analog vector-matrix multiplication circuit has a large area occupied by the DAC circuit, which seriously affects the cost and processing frequency of the circuit.

[0045] To solve the above technical problems, an embodiment of the present invention provides an analog vector-matrix multiplication operation circuit and a chip. By utilizing the characteristic that the analog vector-matrix multiplication operation performs matrix multiplication and addition operation on the received analog current signal to obtain the output current accumulation value, the function of a high-precision DAC is realized by combining multiple low-precision DACs. Each level of DAC converts a partial bit of the digital input signal into an analog current signal; the bits converted by each level of DAC do not have repeated bits, and the number of each level of DAC is greater than or equal to the total number of digital input signals to be operated; the conversion device includes multiple levels of conversion circuits corresponding to the multiple levels of DACs. Each level of conversion circuit is used to convert the analog current signal output by the corresponding DAC into an analog voltage signal of the corresponding magnitude, and then the processed signal is sent to the flash memory processing array for operation, thereby realizing the function of a high-precision DAC by combining multiple low-precision DACs, effectively reducing the area and setup time of the DAC, further reducing the cost of the analog vector-matrix multiplication operation circuit and the chip, and improving the processing frequency.

[0046] Figure 1 FIG. shows the structural diagram of the analog vector-matrix multiplication operation circuit according to an embodiment of the present invention. As Figure 1 shown, the analog vector-matrix multiplication operation circuit includes: a DAC module, a conversion device, and a flash memory processing array 300.

[0047] Among them, the DAC module includes a first-level DAC 100 for converting all bits of the digital input signal into multiple analog current signals 1 to the S-level DAC 100 S , where S is a positive integer greater than or equal to 2. Each level of DAC converts a partial bit of the digital input signal into an analog current signal; the bits converted by each level of DAC do not have repeated bits, and the number of each level of DAC is greater than or equal to the total number of digital input signals to be operated; the conversion device includes a first-level conversion circuit 200 corresponding to the first-level DAC to the S-level DAC 1 to the S-level conversion circuit 200 S . Each level of conversion circuit is used to convert the analog current signal output by the corresponding DAC into an analog voltage signal of the corresponding magnitude; the flash memory processing array performs operations on the analog voltage signal.

[0048] In addition, the flash memory processing array includes flash memory cells arranged in an array, and the threshold voltage of each flash memory cell is adjustable. Among them, the threshold voltages of the flash memory cells corresponding to a partial bit of the same digital input signal in the same column are equal.

[0049] Specifically, when the circuit is working, first, the controller or compiler divides each digital input signal among multiple digital input signals into R parts according to the same division rule based on the precision and number of levels of the DAC. Here, R ≤ S, and the number of bits in each part can be the same or different. The R parts are respectively input into R levels of DAC. Each level of DAC is used to convert the received part of the digital input signal into a corresponding analog current signal. The R levels of DAC convert the multiple parts of the digital input signal into R analog current signals. However, at this time, the multiple analog current signals obtained cannot reflect the difference between the high and low bits of the digital input signal. Therefore, by setting up R levels of conversion circuits, the analog current signals output by the corresponding DAC are converted into analog voltage signals of corresponding magnitudes. Then, after the flash processing array performs matrix multiplication and addition operations on the received analog current signals and accumulates the output currents, the output after being processed by multiple low-precision (or low-bit) DACs and the corresponding multiple levels of conversion circuits is the same as the result after being processed by a high-precision DAC and the corresponding conversion circuit and then through the flash processing array operation. Therefore, the function of a high-precision DAC is realized by using a combination of multiple low-precision DACs, effectively reducing the scale and area of the circuit, saving costs, and increasing the processing frequency.

[0050] It should be noted that for the same input current, the output voltage U m of the m-th level conversion circuit and the output voltage U n of the n-th level conversion circuit have a ratio of:

[0051] U m : U n = 2 x-1 : 2 y-1

[0052] where x represents the lowest number of bits in the bits converted by the DAC corresponding to the m-th level conversion circuit, and y represents the lowest number of bits in the bits converted by the DAC corresponding to the n-th level conversion circuit.

[0053] Specifically, by setting the output voltage of the conversion circuit according to the above ratio, the analog current signal output by the corresponding DAC can be converted into an analog voltage signal of the corresponding magnitude to reflect the difference between the high and low bits of the digital input signal.

[0054] In an optional embodiment, the highest-level conversion circuit (i.e., the R-th level conversion circuit in Figure 1 ) includes a current-voltage conversion unit. The n-th level conversion circuit includes: z current-voltage conversion units connected in parallel, where z represents the ratio of the output voltage of the highest-level conversion circuit to the output voltage of the n-th level conversion circuit for the same input current.

[0055] Specifically, by setting the number of current-voltage conversion units in the nth-level conversion circuit as described above, the multi-level conversion circuit can convert the analog current signal output by the corresponding DAC into an analog voltage signal of the corresponding magnitude.

[0056] Of course, those skilled in the art can understand that for the convenience of design, the number of current-voltage conversion units in each level of the conversion circuit can be set to be greater than or equal to the number of current-voltage conversion units in the lowest-level conversion circuit. During operation, the controller can control the number of current-voltage conversion units turned on in each level of the conversion circuit, as long as the ratio of the output voltages of each level of the conversion circuit satisfies the above relationship.

[0057] Next, taking the execution of analog vector-matrix multiplication operation on H 8-bit digital input signals D 1 ~D H as an example, the analog vector-matrix multiplication operation circuit provided by the embodiments of the present invention will be described in detail. Refer to Figure 2 .

[0058] If an existing analog vector-matrix multiplication operation circuit is used to perform analog vector-matrix multiplication operation on H 8-bit digital input signals, then H 8-bit DACs are required.

[0059] While using the analog vector-matrix multiplication operation circuit provided by the embodiments of the present invention, taking the example of using two 4-bit DACs to configure and implement the function of an 8-bit DAC, the working principle of the circuit will be described.

[0060] The analog vector-matrix multiplication operation circuit provided by the embodiments of the present invention includes: H high 4-bit DACs 100 11 ~100 1H , H low 4-bit DACs 100 21 ~100 2H , H high 4-bit conversion circuits 200 11 ~200 1H correspondingly connected to the H high 4-bit DACs, H low 4-bit conversion circuits 200 21 ~200 2H correspondingly connected to the H low 4-bit DACs, and 2H rows of flash memory cells corresponding to the 2H conversion circuits one by one.

[0061] Among them, the low 4-bit DAC and the high 4-bit DAC can be implemented with the same circuit structure.

[0062] The high 4-bit conversion circuit includes a transistor with an impedance of R. The gate and drain of the transistor are connected and are connected between the output terminal of the corresponding DAC and the input terminal of the flash memory cell, and the source is connected to a bias voltage.

[0063] The low 4-bit conversion circuit includes 16 transistors connected in parallel. The gate and drain of each transistor are connected and are connected between the output terminal of the corresponding DAC and the input terminal of the flash memory cell, and the source is connected to a bias voltage.

[0064] Among them, by setting 16 transistors (also called loads) connected in parallel in the low 4-bit conversion circuit, when the input current is the same, the output current of the high 4-bit conversion circuit is 2 4 times that of the output circuit of the low 4-bit conversion circuit. Of course, J transistors can also be set in the high 4-bit conversion circuit, and 16J transistors can be set in the low 4-bit conversion circuit, as long as the output current of the high 4-bit conversion circuit is 2 4 times that of the output circuit of the low 4-bit conversion circuit.

[0065] In the 2H-row flash memory cells, the gates of all flash memory cells in each row are connected to the output terminal of the same conversion circuit, the sources of all flash memory cells in each column are connected to the same bias voltage, the drains of all flash memory cells in each column are connected together as an analog current output terminal, and N columns of flash memory cells correspond to N analog current output terminals. Among them, the threshold voltage of each flash memory cell can be adjusted. Among them, by dynamically adjusting the threshold voltage V of each flash memory cell according to a certain rule in advance TH , each flash memory cell can be regarded as a variable equivalent analog weight (denoted as W k,j , where 0 < k < 2H and 0 < j < N represent the row number and column number respectively), which is equivalent to storing an analog data, and the flash memory cell array stores an analog data array When the circuit works, an analog voltage signal V 1 ~V 2H is applied to the 2H-row flash memory cells respectively. Among them, all flash memory cells in the Kth row receive an analog voltage signal V k , the drain receives a bias voltage V b , and the sources output current signals I k,1 ~I k,N respectively. According to the characteristics of the flash memory cell, I = V × W. The source output current of each flash memory cell is equal to the gate voltage multiplied by the weight of the flash memory cell, that is, I k,1 = V k W k,1 , I k,N = V k W k,N, since the sources of all flash memory cells in each column are connected to the same analog current output terminal, according to Kirchhoff's law, the current I at this analog current output terminal j is the sum of the source currents of all flash memory cells in this column, that is Multiple analog current output terminals output multiple current sums to implement the matrix multiplication operation function.

[0066] Before the analog vector-matrix multiplication operation circuit works, the D in the H 8-bit digital input signals is preprocessed through a controller or compiler 1 ~D H of each digital input signal is split into a high 4-bit input signal D 高 and a low 4-bit input signal D 低 , thus obtaining 2H 4-bit input signals D 1低 ~D H低 、D 1高 ~D H高 . In addition, the threshold values of the flash memory cells in the same column corresponding to the high 4-bit digital input signal and the low 4-bit digital input signal of the same digital input signal are set to be equal.

[0067] When the circuit works, D 1高 ~D H高 are respectively input to the H high 4-bit DACs 100 11 ~100 1H to obtain I 11 ~I 1H , which are converted into analog voltage signals I 11 ~200 1H ×R~I 11 ×R through the H high 4-bit conversion circuits 200 1H ×R.

[0068] D 1低 ~D H低 are respectively input to the H low 4-bit DACs 100 21 ~100 2H to obtain I 21 ~I 2H , which are converted into analog voltage signals 21 ~200 2H through the H low 4-bit conversion circuits 200

[0069] The 2H rows of flash memory cells perform an analog vector-matrix multiplication operation on the analog voltage signals I 11 ×R~I 1H ×R,

[0070] ​Therefore, in the embodiments of the present invention, by utilizing the characteristic that the analog vector-matrix multiplication operation performs matrix multiplication and addition on the received analog current signal to obtain the output current accumulation value, the function of an 8-bit DAC is realized by combining two 4-bit DACs. When performing analog vector-matrix multiplication on H 8-bit digital input signals, 2H 4-bit DACs are required, and the circuit scale of a 4-bit DAC is 1 / 2 of that of an 8-bit DAC. 4 times. Therefore, the circuit scale of the DAC in the analog vector-matrix multiplication operation circuit of the embodiments of the present invention is 1 / 2 of that of the DAC in the existing analog vector-matrix multiplication operation circuit. 3 times, greatly reducing the circuit scale.

[0071] Those skilled in the art can understand that the higher the precision of the DAC, the more obvious the effect of adopting the solution provided by the embodiments of the present invention.

[0072] Taking the example of implementing the function of an 8-bit DAC circuit by using two 4-bit DAC circuits in the embodiments of the present invention, it includes but is not limited to this. For example, an 8-bit DAC can be split into a 5-bit DAC and a 3-bit DAC, a 6-bit DAC can be split into two 3-bit DACs, a 12-bit DAC can be split into two 6-bit DACs or three 4-bit DACs, etc. The embodiments of the present invention do not limit the number of low-precision DACs obtained by splitting a high-precision DAC and the precision of the low-precision DACs.

[0073] In an alternative embodiment, referring to Figure 2 , the current-voltage conversion unit may include: a transistor, whose gate is connected to the drain and is connected between the output terminal of the corresponding DAC and the input terminal of the flash memory processing array, and the source is connected to a bias voltage.

[0074] Wherein, the number of the transistors is greater than or equal to 1.

[0075] Specifically, the number of transistors can be set to be greater than 1, so that the actual operating point of the conversion circuit is the average value of the operating points of multiple transistors, thereby greatly reducing the influence brought by process deviation. In actual circuit implementation, the number of transistors can be selected according to actual requirements to balance robustness and area overhead.

[0076] In an alternative embodiment, referring to Figure 3 , the current-voltage conversion unit includes: an operational amplifier and a transistor. The inverting input terminal of the operational amplifier is connected to the output terminal of the corresponding DAC and is connected to the drain of the transistor; the non-inverting input terminal of the operational amplifier is connected to a bias voltage; the output terminal of the operational amplifier is connected to the source of the transistor and is connected to the input terminal of the flash memory processing array; the gate of the transistor is connected to a bias voltage.

[0077] In a further embodiment, referring to Figure 4 , the number of the transistors is greater than 1, such that the actual operating point of the conversion circuit is the average of the operating points of multiple transistors, thereby greatly reducing the influence brought by process variations. In actual circuit implementation, the number of transistors can be selected according to actual requirements to balance robustness and area overhead.

[0078] In an alternative embodiment, referring to Figure 5 , the flash processing array 300 includes: the flash processing array includes: a flash memory cell array and subtractors 30 1 ~30 n .

[0079] The flash memory cell array includes: positive weight columns 10 1 ~10 n and constant value columns 20. The number of the subtractors 30 1 ~30 n is equal to the number of the positive weight columns 10 1 ~10 n and they are connected in one-to-one correspondence. The number of the constant value columns 20 is less than the number of the positive weight columns 30 1 ~30 n (in this embodiment, the number of the constant value columns 20 is 1 for illustrative purposes of the solution of the present application).

[0080] The minuend input terminal of the subtractor is correspondingly connected to the output terminal of the positive weight column, the subtrahend input terminal is connected to the output terminal of the constant value column 20, and the output terminal outputs the operation result;

[0081] Among them, the subtrahend input terminals of multiple subtractors 30 1 ~30 n are connected to the same constant value column 20.

[0082] Certainly, the flash memory cell array can also adopt a topology structure of gate coupling and source summation or a topology structure of gate coupling and drain summation, and the embodiments of the present invention do not limit this.

[0083] Next, the principle of the flash processing array will be described:

[0084] Before writing the weight array into the flash memory cells, a constant positive value C is added to each element in the weight array to obtain a weight array to be configured. The constant positive value is greater than or equal to the absolute value of the largest negative-valued weight in the weight array, so that there is no negative-valued weight in the weight array to be configured. Then, the weight array to be configured is written into the positive-valued weight column, and the constant positive value is written into the constant column. The minuend input terminal of a subtractor is correspondingly connected to the output terminal of a positive-valued weight column, and the subtrahend input terminal is connected to the output terminal of the constant column. The output terminal outputs the result of the analog vector-matrix multiplication operation, that is, the influence of the constant positive value is subtracted from the operation result through the subtractor. In this way, there is no need to set a negative-valued weight column, and multiple positive-valued weight columns share a constant column, which can simplify the circuit structure, effectively reduce the number of components, reduce the circuit area, reduce the cost, and facilitate integration.

[0085] Next, for a certain row, taking the weights as [5, -3, 6, -8] and the input voltage as V as an example, the principle of the present application is described (in this example, for the sake of simplicity in explaining the principle of the present application, the simplest weight row is selected. In actual applications, the scale of the weight array depends on the operation requirements. For deep neural network operations, the weight array often has a large scale, and the advantages of the present invention are more obvious).

[0086] Using the flash memory processing array provided by the embodiment of the present invention, first add 9 (greater than or equal to 8 is sufficient) to all the weight values to obtain the weight column to be configured [14, 6, 15, 1]. Then, 14 needs to be written into the first positive-valued weight transistor (corresponding to the 1st positive-valued weight column), 6 into the second positive-valued transistor, 14 into the third positive-valued transistor, 1 into the fourth positive-valued transistor, and 9 into the constant transistor (corresponding to the constant column). After passing through the corresponding subtractor, the final result [5V, -3V, 6V, -8V] is output, which can be realized by a total of 5 transistors, effectively reducing about 38% of the transistors.

[0087] Those skilled in the art can understand that the greater the operation scale, the more obvious the advantages of the present application.

[0088] Figure 6 The circuit of the flash memory processing array in the analog vector-matrix multiplication operation circuit according to the embodiment of the present invention is shown Figure 2 . As Figure 6 shown, the flash memory processing array can be provided with multiple constant columns, and the multiple constant columns are interspersed in the entire flash memory cell array equally or unequally. Thus, when the scale of the flash memory cell array is large, the number of positive-valued weight columns sharing the constant column can be effectively reduced. In this way, the influence of parasitic parameters can be reduced, the driving force can be improved, the use and control of the circuit can be more flexible, and the operation accuracy and speed can be improved.

[0089] Those skilled in the art can understand that when there are multiple constant columns, the weights of the constant columns can be uniformly set. At this time, the weight array is considered as a whole; alternatively, each constant column and its corresponding positive weight column can be regarded as an operation unit. In actual applications, the weight array can be split by column and then distributed to different operation units. Each operation unit sets the weight value of the constant column according to its own operation task and performs its own operations, so as to more flexibly implement the operations. Moreover, multi-operation task parallel processing can also be achieved, which can effectively improve the operation speed and efficiency.

[0090] In an optional embodiment, the flash memory processing array may further include: a current stabilizing module, which is connected to the output end of the constant column.

[0091] Wherein, by setting a current stabilizing module at the output end of the constant column, the influence of parasitic parameters can be effectively reduced, the driving force can be further improved, and the operation accuracy and speed can be improved.

[0092] In an optional embodiment, the analog vector-matrix multiplication operation circuit may further include: a programming circuit, which is connected to the source, gate and / or substrate of each flash memory cell in the flash memory processing array and is used to regulate the threshold voltage of the flash memory cell.

[0093] Wherein, the programming circuit may include: a voltage generating circuit and a voltage control circuit. The voltage generating circuit is used to generate a programming voltage or an erasing voltage, and the voltage control circuit is used to load the programming voltage to the source of the selected flash memory cell, or load the erasing voltage to the gate or substrate of the selected flash memory cell to regulate the threshold voltage of the flash memory cell.

[0094] Specifically, the programming circuit utilizes the hot electron injection effect, applies a high voltage to the source of the flash memory cell according to the threshold voltage requirement data of the flash memory cell, and accelerates the channel electrons to a high speed to increase the threshold voltage of the flash memory cell.

[0095] Moreover, the programming circuit utilizes the tunneling effect, applies a high voltage to the gate or substrate of the flash memory cell according to the threshold voltage requirement data of the flash memory cell, thereby reducing the threshold voltage of the flash memory cell.

[0096] In an optional embodiment, the analog vector-matrix multiplication operation circuit may further include: a controller, which is connected to the programming circuit, controls the number of flash memory cells put into operation and the threshold voltage of each flash memory cell by controlling the operation of the programming circuit; and the controller can also control the operation according to the analog vector-matrix multiplication operation requirements.

[0097] In an optional embodiment, the analog vector-matrix multiplication operation circuit may further include: a row-column decoder, which is used to select and enable the flash memory cells to be programmed.

[0098] In the above embodiments, the flash memory cell may employ a floating gate transistor.

[0099] In the above embodiments, the analog vector-matrix multiplication operation circuit may further include: a bias voltage generation circuit for generating a preset bias voltage and inputting it to the bias voltage input terminal. It can be understood that the analog vector-matrix multiplication operation circuit may not be provided with a bias voltage generation circuit, and by multiplexing the voltage generation circuit in the programming circuit, the voltage generation circuit is controlled to generate a preset bias voltage and input it to the bias voltage input terminal.

[0100] In an alternative embodiment, the analog vector-matrix multiplication operation circuit may further include: an ADC module connected to the output terminal of the flash memory processing array for converting the analog vector-matrix multiplication operation result output by the flash memory processing array into a digital output signal.

[0101] On the other hand, an embodiment of the present invention further provides a chip, which includes the above analog vector-matrix multiplication operation circuit. Among them, the chip may be a memory-computation integrated chip.

[0102] In addition, an embodiment of the present invention further provides an electronic device, which may include the above analog vector-matrix multiplication operation circuit. Specifically, the electronic device may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0103] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, commodity or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, commodity or device comprising the said element.

[0104] In the present invention, specific embodiments are used to elaborate the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. An analog vector-matrix multiplication operation circuit, characterized in that, it includes: a DAC module, a conversion device, and a flash memory processing array; wherein, the DAC module includes a multi-stage DAC, and the number of each stage of DAC in the multi-stage DAC is greater than or equal to the total number of digital input signals to be operated; the Rth stage DAC in the multi-stage DAC is used to convert all bit positions of the digital input signal into multiple analog current signals, and each stage of DAC in the Rth stage DAC respectively converts partial bit positions of the digital input signal into analog current signals, and there are no duplicate bit positions in the bit positions converted by each stage of DAC, where R ≤ S, and S is the number of stages of the multi-stage DAC; the conversion device includes a multi-stage conversion circuit corresponding to the multi-stage DAC, and each stage of conversion circuit corresponding to the Rth stage DAC is used to convert the analog current signal output by the corresponding DAC into an analog voltage signal of the corresponding magnitude; the flash memory processing array performs operations on the analog voltage signal.

2. The analog vector-matrix multiplication operation circuit according to claim 1, characterized in that, For the same input current, the ratio of the output voltage U of the m-th conversion circuit m to the output voltage U of the n-th conversion circuit n is: U m : U n = 2 x-1 : 2 y-1 wherein, x represents the lowest bit number among the bit positions converted by the DAC corresponding to the mth stage conversion circuit, and y represents the lowest bit number among the bit positions converted by the DAC corresponding to the nth stage conversion circuit.

3. The analog vector-matrix multiplication operation circuit according to claim 2, characterized in that, the highest stage conversion circuit includes a current-voltage conversion unit, and the nth stage conversion circuit includes: z current-voltage conversion units connected in parallel, and z represents the ratio of the output voltage of the highest stage conversion circuit to the output voltage of the nth stage conversion circuit for the same input current.

4. The analog vector-matrix multiplication operation circuit according to claim 3, characterized in that, the current-voltage conversion unit includes: a transistor, the gate and drain of the transistor are connected and connected between the output end of the corresponding DAC and the input end of the flash memory processing array, and the source is connected to a bias voltage; wherein, the number of the transistors is greater than or equal to 1.

5. The analog vector-matrix multiplication operation circuit according to claim 3, characterized in that, the current-voltage conversion unit includes: an operational amplifier and a transistor, the inverting input terminal of the operational amplifier is connected to the output end of the corresponding DAC and connected to the drain of the transistor; the non-inverting input terminal of the operational amplifier is connected to a bias voltage; the output terminal of the operational amplifier is connected to the source of the transistor and connected to the input end of the flash memory processing array; the gate of the transistor is connected to a bias voltage; wherein, the number of the transistors is greater than or equal to 1.

6. The analog vector-matrix multiplication operation circuit according to claim 1, characterized in that, the flash memory processing array includes flash memory cells arranged in an array, and the threshold voltage of each flash memory cell is adjustable, wherein, the threshold voltages of the flash memory cells corresponding to partial bit positions of the same digital input signal in the same column are equal.

7. The analog vector-matrix multiplication operation circuit according to claim 1, characterized in that, The flash memory processing array includes: a flash memory cell array and a subtractor; The flash memory cell array includes: a positive weight column and a constant column. The number of the subtractors is equal to the number of the positive weight columns and they are connected in one-to-one correspondence. The number of the constant columns is less than the number of the positive weight columns; The constant column is one column or multiple replicated columns; The minuend input terminal of the subtractor is correspondingly connected to the output terminal of the positive weight column, the subtrahend input terminal is connected to the output terminal of the constant column, and the output terminal outputs the result of the analog vector-matrix multiplication operation; Among them, the subtrahend input terminals of multiple subtractors are connected to the same constant column.

8. The analog vector-matrix multiplication operation circuit according to claim 1, characterized in that it further includes: an ADC module, connected to the output terminal of the flash memory processing array, for converting the result of the analog vector-matrix multiplication operation output by the flash memory processing array into a digital output signal.

9. A chip, characterized in that it includes the analog vector-matrix multiplication operation circuit according to any one of claims 1 to 8.

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