Semiconductor device package and method of manufacturing the same

Abstract

The present invention describes a semiconductor device package, which includes a first substrate, a second substrate, a first support element, a second support element, and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The first substrate has a conductive pad adjacent to the first surface of the first substrate. The second substrate is disposed above the first surface of the first substrate. The first support element is disposed between the first substrate and the second substrate. The first support element is disposed adjacent to an edge of the first surface of the first substrate. The second support element is disposed between the first substrate and the second substrate. The second support element is disposed away from the edge of the first surface of the first substrate. The electronic component is disposed on the second surface of the first substrate. A projection line of a contact point between the second support element and the conductive pad on the second surface of the first substrate is physically spaced apart from a projection line of a side surface of the electronic component on the second surface of the first substrate.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor device package and a method of manufacturing the same, and to a semiconductor device package including two substrates to define a cavity and a method of manufacturing the same. Background Art

[0002] The development of mobile communications has demanded higher data rates and stable communication quality, and high-frequency wireless transmission (e.g., 28 GHz or 60 GHz) has become one of the most important topics in the mobile communications industry. To achieve such high-frequency wireless transmission, signals can be transmitted in a frequency band having a wavelength of approximately ten millimeters to one millimeter (“millimeter wave” or “mmWave”). However, signal attenuation is one of the problems in millimeter-wave transmission. Summary of the Invention

[0003] In one or more embodiments, a semiconductor device package includes a first substrate, a second substrate, a first support element, a second support element, and an electronic component. The first substrate has a first surface and a second surface opposite the first surface.

[0004] The first substrate has a conductive pad adjacent to the first surface of the first substrate. The second substrate is disposed above the first surface of the first substrate. The first support element is disposed between the first substrate and the second substrate. The first support element is disposed adjacent to an edge of the first surface of the first substrate. The second support element is disposed between the first substrate and the second substrate. The second support element is disposed away from an edge of the first surface of the first substrate. The electronic component is disposed on the second surface of the first substrate. A projection line on the second surface of the first substrate of a contact point between the second support element and the conductive pad is physically spaced apart from a projection line on the second surface of the first substrate of a side surface of the electronic component.

[0005] In one or more embodiments, a semiconductor device package includes a first substrate, a second substrate, a first support element, and a second support element. The first substrate has a first surface and a second surface opposite the first surface. The second substrate is disposed above the first surface of the first substrate. The first support element is disposed between the first substrate and the second substrate. The first support element is disposed adjacent to an edge of the first surface of the first substrate. The second support element is disposed between the first substrate and the second substrate. The second support element is disposed away from an edge of the first surface of the first substrate. The first support element and the second support element have no cracks under at least 200 thermal cycle tests. Brief Description of the Drawings

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale, and the dimensions of the various features may be arbitrarily increased or decreased for the sake of clarity of discussion.

[0007] Figure 1A Cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0008] Figure 1B Description of some embodiments of the present invention Figure 1A Top view of the semiconductor device package shown in

[0009] Figure 1C Description of some embodiments of the present disclosure Figure 1A Enlarged view of a portion of the support element shown in

[0010] Figure 2 Cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0011] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E Method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

[0012] Figure 4A , Figure 4B and Figure 4C Method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

[0013] Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. The present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Detailed Description

[0014] Figure 1A Cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure. The semiconductor device package 1 includes substrates 10, 11, support elements 12a, 12b, 13a, 13b, antenna patterns 14, electronic components 15, and electrical contacts 16.

[0015] The substrate 10 can be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. The substrate 10 can include an interconnect structure 10r, such as a redistribution layer (RDL) or a grounding element. In some embodiments, the substrate 10 can be a single-layer substrate or a multi-layer substrate that includes a core layer and conductive materials and / or structures disposed on a surface 101 (also referred to as the first surface) and a surface 102 (also referred to as the second surface) of the substrate 10. The conductive materials and / or structures can include a plurality of traces.

[0016] In some embodiments, as Figure 1CAs shown, it is an enlarged view of a part of the semiconductor device package 1 enclosed by the dotted square 1A. The substrate 10 may include one or more conductive pads 10c that are close to, adjacent to, or embedded and exposed at the surface 101 of the substrate 10. The substrate 10 may include a solder mask 10s (or solder resist) on the surface 101 of the substrate 10 for completely exposing or exposing at least a part of the conductive pads 10c for electrical connection. For example, the solder mask 10s may cover a part of the conductive pads 10c. In some embodiments, the conductive pads 10c are solder mask defined (SMD) pads. In other embodiments, the conductive pads 10c may be non-solder mask defined (NSMD) pads.

[0017] The electronic component 15 is disposed on the surface 102 of the substrate 10. The electronic component 15 may be a chip or die, which includes a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures therein. The integrated circuit devices may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or a combination thereof. The electronic component 15 may be electrically connected to the substrate 10 (e.g., connected to the interconnect structure 10r), and the electrical connection may be obtained by flip-chip or wire bonding technology. The electronic component 15 has an active surface facing the surface 102 of the substrate 10, a back surface opposite to the active surface, and side surfaces extending between the active surface and the back surface. In some embodiments, an underfill (not shown) may be disposed between the active surface of the electronic component 15 and the surface 102 of the substrate 10 to cover the active surface of the electronic component 15. In some embodiments, depending on different design requirements, any number of active components or passive components may be disposed on the surface 102 of the substrate 10.

[0018] The electrical contacts 16 are disposed on the surface 102 of the substrate 10 to provide electrical connection between the semiconductor device package 1 and any other circuit board (e.g., substrate, PCB, motherboard, or the like) or circuit. In some embodiments, the electrical contacts 16 are solder balls or conductive pillars.

[0019] The substrate 11 is disposed above the substrate 10 and spaced apart from the substrate 10. For example, a gap exists between the substrate 10 and the substrate 11. In some embodiments, depending on the design specifications, the substrate 11 may be the same as or different from the substrate 10. The substrate 11 has a surface 111 and a surface 112 opposite to the surface 111. The surface 112 of the substrate 11 faces the surface 101 of the substrate 10. In some embodiments, the surface 101 of the substrate 10 is parallel to the surface 112 of the substrate 11. The substrate 11 may include one or more conductive pads 11c that are close to, adjacent to, or embedded and exposed at the surface 112 of the substrate 11. The substrate 11 may include a solder mask 11s (or solder resist) on the surface 112 of the substrate 11 for exposing at least a part of the conductive pads 11c for electrical connection.

[0020] The antenna pattern 14 is disposed on the surface 111 of the substrate 11. In some embodiments, the antenna pattern 14 includes a plurality of antenna elements. For example, the antenna pattern 14 may include an array of antenna elements. In some embodiments, the antenna pattern 14 may include an M×N array of antenna patterns, where M and N are integers equal to or greater than 1.

[0021] The support elements 12a, 12b, 13a, and 13b are disposed between the substrate 10 and the substrate 11 to define a cavity 10ca (or air cavity) therebetween. In some embodiments, the support elements 12a, 12b, 13a, and 13b may be disposed on the conductive pads 10c and 11c. In some embodiments, the support elements 12a and 12b are disposed adjacent to or near the edge of the surface 101 of the substrate 10. For example, as Figure 1B shown in Figure 1A a top view of the semiconductor device package 1 (some components are omitted for clarity), the support elements 12a and 12b may be disposed along the edge of the surface 101 of the substrate 10. In some embodiments, the support elements 13a and 13b are disposed away from the edge of the surface 101 of the substrate 10. For example, as Figure 1B shown in, the support elements 13a and 13b are disposed inside the support elements 12a and 12b. In some embodiments, the support elements 13a and 13b may be surrounded by the support elements 12a and 12b. As Figure 1B shown in, the support elements 13a and 13b may surround the electronic component 15.

[0022] In some embodiments, the projection of the support element 13a or 13b on the surface 102 of the substrate 10 (e.g., the projection lines L111 and L112 or the projection lines L131 and L132) does not overlap with the projection of the electronic component 15 on the surface 102 of the substrate 10 (e.g., the projection lines L121 and L122). For example, the projection of the support element 13a or 13b on the surface 102 of the substrate 10 is horizontally spaced from the projection of the side surface of the electronic component 15 on the surface 102 of the substrate 10. For example, the projection of the support element 13a or 13b on the surface 102 of the substrate 10 is not within the projection of the electronic component 15 on the surface 102 of the substrate 10. As Figure 1C shown in, in some embodiments, the contact point 13cp between the support element 13a, the solder mask 10cp, and the conductive pad 10c (as Figure 1C shown in) is horizontally spaced from the projection of the side surface of the electronic component 15 on the surface 102 of the substrate 10. For example, the contact point 13cp between the support element 13a, the solder mask 10cp, and the conductive pad 10c (as Figure 1CThe projection on the surface 102 of the substrate 10 (as shown) is not within the projection of the electronic component 15 on the surface 102 of the substrate 10.

[0023] In some embodiments, the support elements 12a, 12b, 13a, and 13b are formed of the same material. In some embodiments, the support elements 12a, 12b, 13a, and 13b may be or include plastic core balls. By using plastic core balls as support elements, the distance between the substrates 10 and 11 can be precisely controlled, which will improve the radiation efficiency of the antenna pattern 14. In some embodiments, the support elements 12a, 12b, 13a, and 13b may be or include metal core balls. For example, the metal core ball may include a core, an inner layer covering the core, and an outer layer covering the inner layer. In some embodiments, the core is formed of or includes copper (Cu), the inner layer is formed of or includes nickel (Ni), and the outer layer is formed of or includes tin (Sn). In some embodiments, the support elements 12a, 12b, 13a, and 13b formed of metal core balls can be used for signal transmission (e.g., feeding signals to the antenna pattern 14).

[0024] In some embodiments, the materials of the support elements 12a and 12b adjacent to the edge of the surface 101 of the substrate 10 are different from the materials of the support elements 13a and 13b surrounded by the support elements 12a and 12b. In some embodiments, the material hardness of the support elements 13a and 13b is greater than the material hardness of the support elements 12a and 12b, and the material hardness can resist stress and prevent the support elements 12a and 12b from cracking. In some embodiments, the support elements 13a and 13b may include metal core balls, and the support elements 12a and 12b may include solder balls, plastic core balls, thermosetting materials (e.g., epoxy resins), B-stage adhesives (or cured B-stage adhesives). In some embodiments, the support elements 13a and 13b may include plastic core balls, and the elements 12a and 12b may include solder balls, thermosetting materials (e.g., epoxy resins), B-stage adhesives (or cured B-stage adhesives).

[0025] In Figures 1A to 1CIn the embodiments, the projection of the support element 13a or 13b on the surface 102 of the substrate 10 (or the projection of the contact point 13cp between the support element 13a, the solder resist 10cp and the conductive pad 10c on the surface 102 of the substrate 10) is horizontally spaced apart from the projection of the side surface of the electronic component 15 on the surface 102 of the substrate 10. Therefore, the maximum stress at the side surface of the electronic component 15 will not be directly applied to the support elements 13a and 13b, which can avoid cracks or voids from appearing on the support elements 13a and 13b. In some embodiments, the support elements 12a, 12b, 13a and 13b have no cracks or voids under at least 200 thermal cycle tests or temperature cycle tests (e.g., JEDEC standard), such as more than 500 times or more than 1000 times.

[0026] Figure 2 A cross-sectional view of a semiconductor device package 2 according to some embodiments of the present disclosure is shown. The semiconductor device package 2 is similar to Figure 1A the semiconductor device package 1 in [reference], and the differences therebetween are described below.

[0027] As Figure 2 shown, the projections of the support elements 13a and 13b on the surface 102 of the substrate 10 (e.g., projection lines L211 and L212) are within the projection of the electronic component 15 on the surface 102 of the substrate 10 (e.g., projection lines L121 and L122), but the projections of the support elements 13a and 13b do not overlap with the projection of the side surface of the electronic component 15 on the surface 102 of the substrate 10. For example, the distance between the projection lines L211 and L212 is less than the distance between the projection lines L121 and L122. Therefore, the maximum stress at the side surface of the electronic component 15 will not be directly applied to the support elements 13a and 13b, which can avoid cracks or voids from appearing on the support elements 13a and 13b. In some embodiments, the support elements 12a, 12b, 13a and 13b have no cracks or voids under at least 200 thermal cycle tests or temperature cycle tests (e.g., JEDEC standard), such as more than 500 times or more than 1000 times.

[0028] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D 、and Figure 3E are cross-sectional views of semiconductor structures at various manufacturing stages according to some embodiments of the present disclosure. The various diagrams have been simplified to provide a better understanding of the aspects of the present disclosure.

[0029] Referring to Figure 3A [reference], a substrate 30 is provided. In some embodiments, the substrate 30 is similar to Figure 1Aa middle substrate 10, and the structure or characteristics of substrate 30 are similar to those of substrate 10. Substrate 30 includes a surface 301 and a surface 302 opposite to surface 301. Solder printing is performed on the surface 301 of substrate 30. In some embodiments, solder printing can be performed on both surfaces 301 and 302 of substrate 30.

[0030] Reference Figure 3B 、 3C and 3D, passive components 35a, solder balls 36 and active components 35b are disposed on the surface 301 of substrate 30. In some embodiments, the passive components 35a and solder balls 36 can be placed on the surface 301 of substrate 30 by surface mount technology (SMT) or any other suitable process. In some embodiments, the active components 35b are placed on the surface 301 of substrate 30 by flip chip or any other suitable process. In some embodiments, depending on different design requirements, the order for disposing the passive components 35a, solder balls 36 and active components 35b can be adjusted or changed. Subsequently, a reflow soldering process can be performed on the passive components 35a, solder balls 36 and active components 35b.

[0031] Reference Figure 3E , an underfill 35u is formed between the active surface of each of the active components 35b and the surface 301 of substrate 30 to protect the active surface of the active components 35b. Subsequently, a reflow soldering process can be performed on the underfill 35u to cure the underfill 35u.

[0032] Figure 4A 、 Figure 4B and Figure 4C are cross-sectional views of semiconductor structures at various manufacturing stages according to some embodiments of the present disclosure. The various diagrams have been simplified to provide a better understanding of aspects of the present disclosure.

[0033] Reference Figure 4A , providing Figure 3E the structure illustrated in. The solder printing process is performed on the surface 302 of substrate 30.

[0034] Reference Figure 4B , providing a substrate 41. In some embodiments, substrate 41 is similar to Figure 1A substrate 11 in, and the structure or characteristics of substrate 41 are similar to those of substrate 11. Substrate 41 includes a surface 411 and a surface 412 opposite to surface 411. Substrate 41 may include an antenna pattern 44 on the surface 411 of substrate 41. In some embodiments, the antenna pattern 44 is similar to Figure 1A antenna pattern 14 in.

[0035] A plurality of support elements 43 are placed on the surface 412 of the substrate 41 by, for example, SMT or any other suitable process. In some embodiments, the support elements 43 are similar to the support elements 12a, 12b and / or the support elements 13a and 13c. Thus, the structure, position, and characteristics of the support elements 12a, 12b and / or the support elements 13a and 13c can be applied to the support elements 43.

[0036] Still referring to Figure 4B , the substrate 41 is placed on the surface 302 of the substrate 30, where the support elements 43 are connected to the surface 302 of the substrate 30. In some embodiments, the substrate 41 can be connected to the substrate 30 by, for example, pick-and-place or any other suitable process. Referring to Figure 4C , subsequently, a reflow soldering process is performed on the structure illustrated in Figure 4B .

[0037] As used herein, the terms "approximate", "substantially", and "about" are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to examples where the event or situation occurs precisely and examples where the event or situation occurs very nearly. For example, when used in conjunction with a numerical value, the term can refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values is less than or equal to ±10% of the average value of the values, for example, less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the two numerical values can be considered "substantially" or "about" the same. For example, "substantially" parallel can refer to an angular variation range of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, "substantially" perpendicular may refer to an angular variation range of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1%, or less than or equal to ±0.05°.

[0038] If the displacement between two surfaces does not exceed 5 μm, does not exceed 2 μm, does not exceed 1 μm, or does not exceed 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar.

[0039] As used herein, the terms "conductive", "electrically conductive", and "conductivity" refer to the ability to transfer current. Conductive materials generally refer to those materials that present little or no opposition to the flow of electric current. A measure of conductivity is Siemens per meter (S / m). Generally, a conductive material has a conductivity greater than about 10 4 S / m, for example, at least 10 5 S / m or at least 10 6 S / m of a material. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0040] As used herein, unless the context clearly dictates otherwise, the singular terms "a / an" and "the" may include plural referents. In the description of some embodiments, a component provided "on" or "above" another component may cover the case where the former component is directly on the latter component (e.g., in physical contact with the latter component), as well as the case where one or more intermediate components are located between the former component and the latter component.

[0041] Although the present disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration do not limit the present disclosure. Those skilled in the art will clearly understand that various changes can be made and equivalent components can be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The drawings may not necessarily be drawn to scale. Due to variables in manufacturing processes and the like, there may be differences between the process reproductions in the present disclosure and actual devices. There may be other embodiments of the present disclosure that are not specifically described. The present specification and drawings should be regarded as illustrative rather than restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered without departing from the teachings of the present disclosure to form equivalent methods. Thus, unless specifically indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. A semiconductor device package, comprising: A first substrate having a first surface and a second surface opposite the first surface, the first substrate having a conductive pad adjacent to the first surface of the first substrate; A second substrate disposed above the first surface of the first substrate; A first support element disposed between the first substrate and the second substrate, the first support element being disposed adjacent to an edge of the first surface of the first substrate; A second support element disposed between the first substrate and the second substrate, the second support element being disposed away from the edge of the first surface of the first substrate; And An electronic component disposed on the second surface of the first substrate, Wherein a projection line of a contact point between the second support element and the conductive pad on the second surface of the first substrate is physically spaced apart from a projection line of a first side surface of the electronic component on the second surface of the first substrate, and Wherein the first support element and the second support element are formed of different materials, and the hardness of the second support element is greater than the hardness of the first support element.

2. The semiconductor device package according to claim 1, wherein the first substrate further comprises a solder mask disposed on the first surface of the first substrate and exposing at least a part of the conductive pad.

3. The semiconductor device package according to claim 2, wherein The solder mask and the conductive pad define a notch; and A part of the second support element is disposed in the notch.

4. The semiconductor device package according to claim 2, wherein the contact point is between the second support element, the conductive pad and the solder mask.

5. The semiconductor device package according to claim 1, wherein each of the first support element and the second support element comprises a core, an inner layer covering the core and an outer layer covering the inner layer.

6. The semiconductor device package according to claim 1, wherein the second support element comprises a plastic core ball, and the first support element comprises a solder ball.

7. The semiconductor device package according to claim 1, wherein the second support element comprises a copper core ball, and the first support element comprises a solder ball or a plastic core ball.

8. The semiconductor device package according to claim 1, further comprising an antenna pattern disposed on a first surface of the second substrate facing away from the first substrate.

9. The semiconductor device package according to claim 1, wherein, when viewed from a top view angle, the second support element is located between the electronic component and the first support element.

10. The semiconductor device package according to claim 1, wherein the electronic component has a second side surface opposite to the first side surface, and the second support element is located between a projection line of the first side surface of the electronic component on the second surface of the first substrate and a projection line of the second side surface of the electronic component on the second surface of the first substrate.

11. The semiconductor device package according to claim 1 further includes a plurality of the first support elements and a plurality of the second support components, wherein the plurality of second support components are surrounded by the plurality of first support components.

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