Semiconductor structure and method for manufacturing the same

Abstract

A semiconductor structure and a method for manufacturing the same are provided. A semiconductor structure includes a first semiconductor substrate, a first interconnect structure, a first conductive pad, a first dielectric layer, and a first conductive connector. The first semiconductor substrate includes a plurality of first semiconductor devices located in the first semiconductor substrate. The first interconnect structure is disposed on the first semiconductor substrate and electrically coupled to the first semiconductor device. The first conductive pad is disposed on the first interconnect structure and electrically coupled to the first interconnect structure. The first dielectric layer covers the first conductive pad and the first interconnect structure, and the first dielectric layer includes a portion extending through the first conductive pad. The first conductive connector is disposed on the first interconnect structure and electrically coupled to the first interconnect structure, and the first conductive connector extends through the portion of the first dielectric layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor structure and a manufacturing method thereof, and more particularly to a semiconductor structure suitable for application in a three-dimensional integrated circuit and a manufacturing method thereof. Background Art

[0002] In recent years, the semiconductor industry has experienced rapid growth due to the continued increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density comes from the continuous reduction in the minimum feature size, which enables more components to be integrated into a given area. For example, the area occupied by the integrated components is close to the surface of the semiconductor wafer, however, there are physical limits to the density that can be achieved in two-dimensional (2D) integrated circuit formation. For example, one of these limits comes from the significant increase in the number and length of the interconnections between semiconductor devices as the number of semiconductor devices increases. Since existing integrated circuit design rules require that the pitch of the conductive wiring arranged in the semiconductor structure be reduced, efforts are constantly being made to develop new mechanisms for forming semiconductor structures. Summary of the invention

[0003] According to some embodiments of the present disclosure, a semiconductor structure includes a first semiconductor substrate, a first interconnect structure, a first conductive pad, a first dielectric layer, and a first conductive connector. The first semiconductor substrate includes a plurality of first semiconductor devices located in the first semiconductor substrate. The first interconnect structure is disposed on the first semiconductor substrate and electrically coupled to the first semiconductor device. The first conductive pad is disposed on the first interconnect structure and electrically coupled to the first interconnect structure. The first dielectric layer covers the first conductive pad and the first interconnect structure, and the first dielectric layer includes a portion extending through the first conductive pad. The first conductive connector is disposed on the first interconnect structure and electrically coupled to the first interconnect structure, and the first conductive connector extends through the portion of the first dielectric layer.

[0004] According to some embodiments of the present disclosure, a semiconductor structure includes a first semiconductor die and a second semiconductor die, the second semiconductor die being stacked on the first semiconductor die and bonded to the first semiconductor die. The first semiconductor die includes: a first interconnect layer; a first conductive pad disposed on the first interconnect layer and electrically coupled to the first interconnect layer; a first dielectric layer disposed on the first interconnect layer and covering the first conductive pad; a first conductive connector embedded in the first dielectric layer and extending toward the first conductive pad to be electrically coupled to the first interconnect layer; and a first dummy connector disposed beside the first conductive connector and embedded in the first dielectric layer. The second semiconductor die includes a second dielectric layer, a second conductive connector, and a second dummy connector. The second dielectric layer is bonded to the first dielectric layer of the first semiconductor die. The second conductive connector and the second dummy connector are embedded in the second dielectric layer and bonded to the first conductive connector of the first semiconductor die and the first dummy connector of the first semiconductor die, respectively.

[0005] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes at least the following steps. A patterned conductive pad having a through hole is formed on an interconnect structure on a semiconductor substrate. A dielectric material on the interconnect structure is patterned to form a patterned dielectric layer having a first opening. The first opening passes through a portion of the dielectric material formed inside the through hole of the patterned conductive pad to expose the interconnect structure in a touchable manner. A conductive material is formed inside the first opening of the patterned dielectric layer and the conductive material contacts the interconnect structure to form a conductive connector. The conductive connector is laterally isolated from the patterned conductive pad by the patterned dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1F are schematic cross-sectional views showing various stages in a method for manufacturing a semiconductor structure according to some exemplary embodiments of the present disclosure.

[0008] Figure 2A and Figure 2B are schematic cross-sectional views showing various stages in a method for manufacturing a semiconductor structure according to some exemplary embodiments of the present disclosure.

[0009] FIG. 3A to FIG. 3Care schematic cross-sectional views showing various stages in a method for manufacturing a semiconductor structure according to some exemplary embodiments of the present disclosure.

[0010] Figure 4A and Figure 4B are schematic cross-sectional views showing various stages in a method for manufacturing a semiconductor structure according to some exemplary embodiments of the present disclosure.

[0011] Figure 5A and Figure 5B are schematic cross-sectional views showing various stages in a method of manufacturing a semiconductor structure according to some exemplary embodiments of the present disclosure.

[0012] Figures 6 to 11 are schematic cross-sectional views illustrating various semiconductor structures according to some exemplary embodiments of the present disclosure.

[0013] Fig.12 is a schematic cross-sectional view illustrating an application of a semiconductor structure according to some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a first feature is formed "above" or "on" a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0015] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0016] Other features and processes may also be included. For example, a test structure may be included to help perform verification testing on a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate so that the 3D package or 3DIC can be tested, probes and / or probe cards can be used, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with a test method that includes intermediate verification of a known good die to improve yield and reduce costs.

[0017] Figures 1A to 1F Schematic cross-sectional views showing various stages in a method for manufacturing a semiconductor structure according to some exemplary embodiments of the present disclosure. Figure 1A and Figure 1B , an interconnect structure 120 is formed on a semiconductor substrate 110. For example, the semiconductor substrate 110 includes a bulk semiconductor that may be doped or undoped, a semiconductor-on-insulator (SOI) substrate, other supporting substrates (e.g., quartz, glass, etc.), combinations thereof, etc. In some embodiments, the semiconductor substrate 110 includes an elemental semiconductor (e.g., silicon or germanium in a crystalline, polycrystalline or amorphous structure), a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, etc.), an alloy semiconductor (e.g., silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.), combinations thereof, or other suitable materials. For example, the compound semiconductor substrate may have a multilayer structure or the substrate may include a multilayer compound semiconductor structure. In some embodiments, alloy SiGe is formed on a silicon substrate. In other embodiments, the SiGe substrate is strained. In some embodiments, the semiconductor substrate 110 is a device wafer. For example, the semiconductor substrate 110 includes a plurality of semiconductor devices 112 formed in the semiconductor substrate 110. The semiconductor devices 112 may be or may include active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, resistors, inductors, etc.) or other suitable electronic components.

[0018] The semiconductor substrate 110 may include a circuit system (not shown) formed in a front-end-of-line (FEOL) process and the interconnect structure 120 may be formed in a back-end-of-line (BEOL) process. In some embodiments, the interconnect structure 120 includes an inter-layer dielectric (ILD) layer formed on the semiconductor substrate 110 and covering the semiconductor device 112 and an inter-metallization dielectric (IMD) layer formed on the ILD layer. In some embodiments, the ILD layer and the IMD layer are formed of a low-k dielectric material such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), SiOxCy, spin-on-glass, spin-on-polymer, silicon-carbon material, compounds thereof, composites thereof, combinations thereof, etc. The ILD layer and the IMD layer may include any suitable number of dielectric material layers, and the number of dielectric material layers is not limited thereto.

[0019] In some embodiments, the interconnect structure 120 interconnects the semiconductor device 112. For example, the interconnect structure 120 includes at least one dielectric layer 124 disposed on the semiconductor substrate 110 and a plurality of interconnect layers 122 embedded in the dielectric layer 124. For example, each of the interconnect layers 122 includes a conductive line, a conductive pad, a via, etc. The material of the interconnect layer 122 may include copper or a copper alloy, but other metals (e.g., aluminum, silver, gold, and combinations thereof) may also be used. In some embodiments, two or more layers of conductive lines of the interconnect layer 122 are interconnected in a vertical direction by vias of the interconnect layer 122 and embedded in the dielectric layer 124. The interconnect layer 122 of the interconnect structure 120 disposed on the semiconductor substrate 110 may electrically couple the semiconductor devices 112 formed in and / or on the semiconductor substrate 110 to each other and electrically couple the semiconductor devices 112 to external components.

[0020] For example, the interconnection layer 122 of the interconnection structure 120 includes a bottom interconnection layer M1, a top interconnection layer Mt, and an intermediate interconnection layer located between the bottom interconnection layer M1 and the top interconnection layer Mt (for example, a second interconnection layer M2 located directly above the bottom interconnection layer M1, a third interconnection layer M3 located directly below the top interconnection layer Mt, and other interconnection layers (not shown) located between the second interconnection layer M2 and the third interconnection layer M3). For ease of explanation, the term "top" is used herein to refer to a layer that is farthest from the semiconductor substrate 110 relative to other layers, and the term "bottom" is used to refer to a layer that is closest to the semiconductor substrate 110 relative to other layers. It should be noted that the four-level interconnection layer structure shown in the figure is only exemplary, and the interconnection structure 120 may include more or fewer interconnection layers according to the requirements of the circuit design. In some embodiments, at least one passivation layer 126' of the interconnect structure 120 is disposed on the dielectric layer 124 and the at least one passivation layer 126' partially covers the top interconnect layer Mt of the interconnect layer 122. In some embodiments, the passivation layer 126' is a non-low-k dielectric layer. For example, the passivation layer 126' is formed of silicon oxide, silicon nitride, undoped silicate glass, polyimide, etc. Alternatively, the passivation layer 126' is omitted. The passivation layer 126' may include an opening (not labeled) that exposes at least a portion of the top interconnect layer Mt in an accessible manner for further electrical connection.

[0021] In some embodiments, a conductive material is formed on the passivation layer 126' and within the opening of the passivation layer 126' to physically and electrically contact the underlying interconnect layer 122 (e.g., the top interconnect layer Mt). Next, a portion of the conductive material is removed to form a patterned conductive pad 130 having a through hole TH. The material of the conductive pad 130 may include aluminum, but other suitable conductive materials (e.g., copper) may be used. In some embodiments, after the conductive material is formed on the passivation layer 126' and within the opening of the passivation layer 126', the conductive material is patterned to form a conductive pad 130'. It should be noted that although only one conductive pad 130' is shown, multiple conductive pads may be formed on the interconnect structure 120. In some embodiments, the conductive pad 130' may be a test pad capable of performing functional testing. Subsequently, a portion of the conductive pad 130' is removed to form a through hole TH of the patterned conductive pad 130. For example, the process of forming the through hole TH is performed after testing. In some embodiments, a portion of the passivation layer 126' is exposed by the through hole TH of the patterned conductive pad 130, such as Figure 1B It should be noted that the combination Figure 1B In other embodiments, a portion of the top interconnect layer Mt of the interconnect layer 122 is exposed by the through hole TH of the patterned conductive pad 130 .

[0022] In some embodiments, after forming the conductive material on the passivation layer 126' and inside the opening of the passivation layer 126', the conductive material is patterned at one time to form a patterned conductive pad 130 having a through hole TH. In some embodiments, after forming the conductive material, lithography and etching can be used to form the patterned conductive pad 130. For example, the lithography technique involves depositing a photoresist material (not shown) on the conductive material, then irradiating (or exposing) the photoresist material and developing the photoresist material to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material from the subsequent etching steps. A suitable etching process (such as reactive ion etching or other dry etching, isotropic or anisotropic wet etching or any other suitable etching or patterning process) can be applied to the conductive material to remove the exposed portion of the conductive material until the underlying passivation layer 126' is exposed, so that a patterned conductive pad 130 including a through hole TH is formed. Subsequently, a stripping solution tailored for the photoresist material is used, followed by etching to remove any photoresist residue. It should be noted that alternative processes may be used to form the patterned conductive pad 130 having the through-hole TH.

[0023] In some embodiments, the outer sidewall 130a of the patterned conductive pad 130 is substantially vertical and substantially perpendicular to the top surface of the passivation layer 126'. In some embodiments, the through-hole TH tapers from the top surface 130t of the patterned conductive pad 130 toward the passivation layer 126'. In some embodiments, one of the through-holes TH includes a top width WH1 that is greater than a bottom width WH2 of the one of the through-holes TH. For example, the width of one of the through-holes TH gradually increases in a direction toward the top surface 130t of the patterned conductive pad 130, thereby forming an inclined inner sidewall 130b of the patterned conductive pad 130. The top surface 130t is connected to the inner sidewall 130b and the outer sidewall 130a. It should be noted that in combination Figure 1B The described structure is merely exemplary, and in other embodiments, the outer sidewall 130 a and / or the inner sidewall 130 b of the patterned conducting pad 130 may be inclined or substantially vertical according to the formation process of the through hole TH.

[0024] Reference Figure 1C and Figure 1D, a dielectric material 140' is formed on the passivation layer 126' to cover the patterned conductive pad 130. For example, the top surface 130t, the outer sidewall 130a and the inner sidewall 130b of the patterned conductive pad 130 are covered by the dielectric material 140'. In some embodiments, the through hole TH of the patterned conductive pad 130 is filled with the dielectric material 140'. The dielectric material 140' may be or may include any suitable electrically insulating material for subsequent bonding processes. In some embodiments, the dielectric material 140' includes a silicon-containing dielectric layer. For example, the dielectric material 140' includes silicon oxide (SiO), silicon oxynitride (SiON), silicon nitride (SiN), etc., and may be formed by a deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.) or other suitable techniques.

[0025] Next, portions of the dielectric material 140' and portions of the underlying passivation layer 126' may be removed to form patterned dielectric layers 140 and patterned passivation layers 126, respectively. For example, a damascene technique or other suitable patterning process may be utilized. In some embodiments, a dual damascene process is performed on the dielectric material 140' and the underlying passivation layer 126'. For example, a plurality of trench openings TR1 and TR2 are formed in the dielectric material 140', and a plurality of through-hole openings VO are formed in the dielectric material 140' and the passivation layer 126' and the plurality of through-hole openings VO extend from the corresponding trench openings TR2. The trench openings TR1 and TR2 may be formed as dispersed recessed patterns distributed on the dielectric material 140'. The through-hole openings VO may pass through the underlying passivation layer 126' to form a patterned passivation layer 126 that exposes the top interconnect layer Mt of the interconnect layer 122 in a touchable manner. In other embodiments, the through hole opening VO may be further extended into the dielectric layer 124 of the interconnect structure 120 to expose any level of the interconnect layer 122 below the top interconnect layer Mt according to design requirements. Figure 1D The dual damascene technique described is merely exemplary, and in other embodiments a single damascene process or other suitable patterning process may be used.

[0026] In some embodiments, a via opening VO and trench openings TR1 and TR2 are formed using photolithography and etching techniques. The via opening VO may be formed before the trench openings TR1 and TR2. For example, a via-first approach includes at least the following steps. A photoresist (not shown) is applied to the dielectric material 140' and the photoresist is patterned. The photoresist may be a single-layer photoresist, a double-layer photoresist, a triple-layer photoresist, etc. Then, a via opening VO is formed at a predetermined position corresponding to the through hole TH of the patterned conductive pad 130 using the photoresist as a mask. For example, a portion of the dielectric material 140' and a portion of the underlying passivation layer 126' are removed by patterning the photoresist until the interconnect layer 122 is exposed. In some embodiments, a selective etching process is used to etch the dielectric material 140' and the underlying passivation layer 126', and the etching process may be performed continuously until the top interconnect layer Mt is exposed. Subsequently, the patterned photoresist is removed as needed by, for example, stripping and / or ashing, and then by cleaning. Additional photoresist may be formed and patterned, and then the trench openings TR1 and TR2 are formed by further etching the dielectric material 140' using the additional patterned photoresist. In some embodiments, the etching process is performed using, for example, a time-mode, so that the trench openings TR1 and TR2 extend from the top portion of the dielectric material 140' to the middle point of the dielectric material 140'. Other detection techniques for etching may be expected. In some other embodiments, a trench-first approach is performed (e.g., the trench openings TR1 and TR2 are formed before the through-hole opening VO). Alternatively, the through-hole opening VO and the trench openings TR1 and TR2 are formed during the same process using, for example, a half tone mask, a multi-tone mask, etc. It should be understood that an etch stop layer (not shown) may be disposed in the interconnect structure 120 or may be disposed between the dielectric material 140 ′ and the interconnect structure 120 according to process requirements.

[0027] Continue to refer to Figure 1D, in some embodiments, the groove opening TR1 may not correspond to any through-hole opening in the through-hole opening in the cross section. For example, the groove opening TR1 can be used to form a conductive line or a dummy pad. Alternatively, the through-hole opening VO is formed to correspond to the groove openings TR1 and TR2. The groove opening TR1 may be formed in the unoccupied top portion of the dielectric material 140' so that the spacing of the groove opening TR2 can be maintained. In some embodiments, the groove opening TR2 is surrounded by the groove opening TR1. The groove openings TR1 and TR2 may taper from top to bottom. The size of the groove opening TR1 may be substantially equal to the size of the groove opening TR2. In some embodiments, the through-hole opening VO may also taper from top to bottom. For example, each of the groove openings TR1 and TR2 includes a top width (or diameter) WT1 that is greater than the bottom width WT2 of each of the groove openings TR1 and TR2. The bottom width WT2 of the groove opening TR2 and the top width WV1 of the corresponding through-hole opening VO may be located at the same plane and overlap. For example, the bottom width WT2 of the trench opening TR2 is slightly larger than the top width WV1 of the corresponding through-hole opening VO. The top width WV1 of each of the through-hole openings VO may be larger than the bottom width WV2 of each of the through-hole openings VO. In some embodiments, the top width WV1 of one of the through-hole openings VO is substantially equal to or larger than about 1.8 μm. In some embodiments, the width WV3 of each of the through-hole openings VO in the plane where the top surface 130t of the patterned conductive pad 130 is located is smaller than the top width WH1 of the through-hole TH of the patterned conductive pad 130. The bottom width WH2 of the through-hole TH of the patterned conductive pad 130 is larger than the width WV4 of each of the through-hole openings VO in the plane where the top surface of the patterned passivation layer 126 is located. The size of the through-hole TH, the size of the through-hole opening VO, and the size of the trench openings TR1 and TR2 may be sized according to the function and process requirements of the connector to be formed subsequently. Alternatively, the patterned dielectric layer 140 includes substantially vertical sidewalls at locations where the trench openings TR1 and TR2 and / or the via opening VO are formed.

[0028] After forming the through hole opening VO and the trench openings TR1 and TR2, a portion of the dielectric material 140′ remains in the through hole TH of the patterned conductive pad 130 and covers the inner sidewall 130b of the patterned conductive pad 130. The portion of the dielectric material 140′ remaining in the through hole TH may also cover a portion of the top surface of the patterned passivation layer 126 corresponding to the through hole TH. In some embodiments, the patterned conductive pad 130 disposed on the top surface of the patterned passivation layer 126 is encapsulated by the patterned dielectric layer 140.

[0029] Reference Figure 1E and Figure 1F, a conductive material CM is formed in the through hole opening VO and the trench openings TR1 and TR2 to form a plurality of conductive connectors 152 and dummy connectors 154. For example, the conductive material CM formed in the trench opening TR1 can be regarded as the dummy connector 154, and the conductive material CM formed in the through hole opening VO and the corresponding trench opening TR2 can be regarded as the conductive connector 152. It should be noted that the conductive connectors and dummy connectors shown herein are only exemplary. For example, the conductive connectors 152 and the dummy connectors 154 are formed as a multilayer structure.

[0030] In an exemplary embodiment, the method of forming the conductive connector 152 and the dummy connector 154 includes at least the following steps. For example, a diffusion barrier layer (not shown) is formed on the patterned dielectric layer 140 in a conformal manner and covers the sidewalls and bottom of the through hole opening VO and the sidewalls and bottom of the trench openings TR1 and TR2. The diffusion barrier layer can physically contact and electrically contact the interconnect layer 122 (e.g., the top interconnect layer Mt) exposed by the through hole opening VO and the corresponding trench opening TR2. For example, the diffusion barrier layer includes a barrier material (e.g., titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof) and can be formed using, for example, physical vapor deposition (PVD) or other suitable deposition processes. Next, a seed layer (not shown) can be formed on the diffusion barrier layer in a conformal manner using sputtering, plating, or other suitable deposition processes. The seed layer can be or can include a copper layer, a titanium / copper bilayer, or other suitable metal layers that help form thicker conductive materials during subsequent processing steps. Subsequently, a conductive material (eg, copper, aluminum, silver, gold, metal alloy, etc.) is formed on the seed layer and inside the via opening VO and the trench openings TR1 and TR2 using plating, printing or other suitable deposition processes.

[0031] Then, the excess conductive material CM may be removed until the underlying patterned dielectric layer 140 is exposed, so that a conductive connector 152 and a dummy connector 154 are formed. For example, a planarization process (e.g., a chemical mechanical polishing (CMP) process) or other suitable process is performed on the excess conductive material CM to form a flat surface. In some embodiments, the top surface 152t of the conductive connector 152 is substantially flush with the top surface 154t of the dummy connector 154. It should be noted that other suitable techniques may be used to form the conductive connector 152 and the dummy connector 154. At this point, a layer TD1 semiconductor structure is substantially formed. In some embodiments, the layer TD1 semiconductor structure is regarded as a semiconductor die or a semiconductor chip. For example, the above-mentioned manufacturing steps of the layer TD1 are performed at the wafer level, and before the next step (e.g., bonding) is performed, the layer TD1 may or may not be singulated into a plurality of semiconductor dies (or chips).

[0032] Still refer to Figure 1F , the layer TD1 includes a first surface S1 and a second surface S2 opposite to the first surface S1. In some embodiments, the top surface 152t of the conductive connector 152, the top surface 154t of the dummy connector 154, and the top surface 140t of the patterned dielectric layer 140 are substantially flush at the first surface S1. In some embodiments, the depth Dd of the dummy connector 154 in the patterned dielectric layer 140 is less than the depth Dc of the conductive connector 152 in the patterned dielectric layer 140 and the patterned passivation layer 126. The dummy connector 154 of the layer TD1 is disposed next to the conductive connector 152 and embedded in the patterned dielectric layer 140. The dummy connector 154 is disposed at the bottom of the patterned dielectric layer 140. Figure 1F The cross section shown may not contact any of the underlying conductive features. For example, the dummy connector 154 may not have an electrical function and may be electrically floating. In some embodiments, during the use of layer TD1, an electrical signal may be connected to the semiconductor device 112 through the interconnect layer 122 of the interconnect structure 120 and the conductive connector 152. However, the dummy connector 154 may not be connected to an electrical signal or voltage. In some embodiments, the dummy connector 154 is distributed at the periphery of the first surface S1, and the conductive connector 152 may be surrounded by the dummy connector 154. In some embodiments, by forming the dummy connector 154, the pattern density in the layer TD1 becomes more uniform, so the pattern-loading effect when forming the conductive connector 152 is reduced.

[0033] In some embodiments, each of the conductive connectors 152 includes a groove portion (or pad portion) 152a, a via portion 152b extending downward from the corresponding groove portion 152a, and a bottom portion 152c extending from the corresponding via portion 152b to contact the interconnect layer 122 (e.g., the top interconnect layer Mt). The groove portion 152a and the via portion 152b are covered in the lateral direction by the patterned dielectric layer 140, and the bottom portion 152c of the conductive connector 152 is covered in the lateral direction by the patterned passivation layer 126. For example, the groove portion 152a of the conductive connector 152 is a portion of the conductive material correspondingly formed in the groove opening TR2, and the via portion 152b and the bottom portion 152c of the conductive connector 152 are conductive materials formed in the via opening VO. In some embodiments, the through hole portion 152b and the corresponding bottom portion 152c of the conductive connector 152 taper from the corresponding groove portion 152a of the conductive connector 152 to the top interconnect layer Mt. The size of the groove portion 152a, the size of the through hole portion 152b, and the size of the bottom portion 152c can be sized according to the corresponding through hole opening VO and the groove opening TR2. In some embodiments, a portion of the through hole portion 152b of the conductive connector 152 corresponds to the through hole TH of the patterned conductive pad 130 and can be isolated from the patterned conductive pad 130 in the lateral direction by the patterned dielectric layer 140. In some embodiments, the conductive connector 152 is not directly connected to the patterned conductive pad 130. For example, the conductive connector 152 is electrically coupled to the patterned conductive pad 130 through the interconnect layer 122 (e.g., the top interconnect layer Mt). In some embodiments, the patterned conductive pad 130 is formed by a test pad. Since placing the test pads will occupy a real-estate on the surface of the semiconductor die, forming a patterned conductive pad 130 through the test pads and forming a through hole TH passing through the patterned conductive pad 130 to reach the conductive connector 152 of the interconnect layer 122 can minimize the impact of the test pads occupying the real-estate on the surface of the semiconductor die.

[0034] Figure 2A and Figure 2B 1 is a schematic cross-sectional view showing various stages in a method for manufacturing a semiconductor structure according to some exemplary embodiments of the present disclosure. The manufacturing method of the embodiment shown is similar to Figures 1A to 1F For ease of understanding, the same elements in all figures are referred to by the same reference numerals and will not be described in detail herein. Figure 2A, an interconnect structure 220 is formed on the semiconductor substrate 110. For example, the interconnect structure 220 includes at least one dielectric layer 224 disposed on the semiconductor substrate 110 and a plurality of interconnect layers 222 embedded in the dielectric layer 224. The interconnect layer 222 can electrically couple the semiconductor devices 112 of the semiconductor substrate 110 to each other and to an external component. The interconnect layer 222 and the dielectric layer 224 can be similar to Figure 1A 1 and 12. The interconnect layer 122 and dielectric layer 124 described in the embodiment of the present invention are different in that the interconnect layer 222 of the interconnect structure 220 includes a dummy pattern DP. In some embodiments, the dummy pattern DP of the interconnect structure 220 is electrically floating. In other embodiments, the dummy pattern DP is electrically coupled to some functional semiconductor devices 112 or provides a short grounding path for grounding the integrated circuit. For example, the dummy pattern DP is formed in the top interconnect layer Mt' of the interconnect layer 222. It should be noted that the dummy pattern DP may or may not be formed in any level of the interconnect layer 222 according to design requirements. In some embodiments, a conductive pattern other than the dummy pattern DP may be regarded as an active pattern AP. For example, the active pattern AP formed in the top interconnect layer Mt' may be surrounded by the dummy pattern DP of the top interconnect layer Mt'. It should be noted that the configuration of the dummy pattern DP and the active pattern AP shown is only exemplary, and other configurations may exist.

[0035] Continue to refer to Figure 2A , a patterned passivation layer 226 of the interconnect structure 220 is formed on the topmost dielectric layer 224 in the dielectric layers 224 and the patterned passivation layer 226 partially covers the top interconnect layer Mt'. In some embodiments, the patterned passivation layer 226 includes a plurality of first openings 226a, a second opening 226b, and a third opening 226c. For example, the first opening 226a and the third opening 226c respectively expose at least a portion of the active pattern AP, and the second opening 226b exposes at least a portion of the dummy pattern DP. A patterned conductive pad 130 is disposed on the top surface of the patterned passivation layer 226 and inside the third opening 226c of the patterned passivation layer 226 to be electrically coupled to the interconnect structure 220. For example, the patterned conductive pad 130 is electrically coupled to the active pattern AP of the interconnect layer 222. The first opening 226a of the patterned passivation layer 226 may correspond to the through hole TH of the patterned conductive pad 130. For example, the bottom width of one of the through holes TH is greater than or substantially equal to the top width of the corresponding first opening 226 a of the patterned passivation layer 226 .

[0036] The patterned dielectric layer 240 covers the patterned conductive pad 130 and the interconnect structure 220. For example, the patterned dielectric layer 240 is formed on the patterned passivation layer 226 and encapsulates the patterned conductive pad 130. In some embodiments, a portion of the patterned dielectric layer 240 extends through the through hole TH of the patterned conductive pad 130 and covers the inner sidewall 130b of the patterned conductive pad 130. For example, the patterned dielectric layer 240 includes a plurality of first openings 240a and second openings 240b. The first opening 240a of the patterned dielectric layer 240 corresponds to the through hole TH of the patterned conductive pad 130 and can be connected to the first opening 226a of the patterned passivation layer 226. The second opening 240b of the patterned dielectric layer 240 is disposed next to the first opening 240a and can be connected to the second opening 226b of the patterned passivation layer 226. In some embodiments, at least a portion of the dummy pattern DP of the top interconnect layer Mt′ is exposed by the second opening 226 b of the patterned passivation layer 226 and the second opening 240 b of the patterned dielectric layer 240 .

[0037] Still refer to Figure 2A , the method for forming the patterned passivation layer 226, the patterned conductive pad 130 and the patterned dielectric layer 240 may include at least the following steps. For example, a passivation material is formed on the top interconnect layer Mt' and the topmost dielectric layer 224 of the dielectric layer 224, and then the passivation material is patterned to form a third opening 226c. Alternatively, the first opening 226a and / or the second opening 226b may be formed together with the third opening 226c to form the patterned passivation layer 226. The passivation material may be similar to the material of the patterned passivation layer 126 described above. Next, a conductive material is formed on the top surface of the passivation material and inside the third opening 226c, and then the conductive material is patterned to form a patterned conductive pad 130 having a through hole TH. Next, a dielectric material may be formed on the passivation material to cover the patterned conductive pad 130 and fill the through hole TH. The dielectric material may be similar to the material of the patterned dielectric layer 140. In some embodiments where the second opening 226b and / or the first opening 226a and the third opening 226c are formed together, a dielectric material may be formed in the first opening 226a and the second opening 226b of the patterned passivation layer 226. Subsequently, the dielectric material may be patterned using, for example, a damascene process to form a patterned dielectric layer 240 having a first opening 240a and a second opening 240b. The underlying passivation material may be patterned during the same process to form the patterned passivation layer 226.

[0038] In some embodiments, the first opening 240a and the second opening 240b of the patterned dielectric layer 240 taper from the top surface 240t of the patterned dielectric layer 240 toward the top interconnect layer Mt'. For example, the width of each of the first opening 240a and the second opening 240b gradually increases in a direction toward the top surface 240t of the patterned dielectric layer 240, thereby forming an inclined inner sidewall of the patterned dielectric layer 240. It should be understood that in combination with Figure 2A The described single damascene technique is only exemplary, and in other embodiments, a dual damascene process or other suitable patterning process may be used. It is also noted that the formation method of the patterned passivation layer 226, the patterned conductive pad 130, and the patterned dielectric layer 240 may be performed in any logical order, which is not limited in the present disclosure.

[0039] Reference Figure 2B , a conductive material is formed in the patterned passivation layer 226 and the patterned dielectric layer 240 to form a conductive connector 252 and a dummy connector 254. In an embodiment, the conductive material may be formed by depositing one or more diffusion barrier layers on the inner sidewalls of the patterned dielectric layer 240 and the inner sidewalls and bottom of the patterned passivation layer 226 to contact the interconnect layer 222 (e.g., the top interconnect layer Mt'), followed by depositing a seed layer. Once the seed layer has been deposited in the patterned dielectric layer 240 and the patterned passivation layer 226, the conductive material is filled into the first opening 240a and the second opening 240b of the patterned dielectric layer 240 and the first opening 226a and the second opening 226b of the patterned passivation layer 226. Excess conductive material and / or dielectric film may be removed from the top surface 240t of the patterned dielectric layer 240. The conductive connection 252 is formed by filling the first openings 240a and 226a, and the dummy connection 254 is formed by filling the second openings 240b and 226b. Thus, a TS1 semiconductor structure is substantially formed.

[0040] Continue to refer to Figure 2B, the layer TS1 includes a first surface S1 and a second surface S2 opposite to the first surface S1. The top surface 254t of the dummy connector 254, the top surface 252t of the conductive connector 252, and the top surface 240t of the patterned dielectric layer 240 may be substantially flush at the first surface S1 of the layer TS1. In some embodiments, the depth Dd' of one of the dummy connectors 254 in the patterned dielectric layer 240 and the patterned passivation layer 226 is substantially equal to the depth Dc of one of the conductive connectors 252 in the patterned dielectric layer 240 and the patterned passivation layer 226. In some embodiments, all the conductive connectors 252 and the dummy connectors 254 of the layer TS1 penetrate the patterned dielectric layer 240 and the patterned passivation layer 226. Alternatively, the dummy connector 254 may be embedded in the patterned dielectric layer 240 and may not pass through the patterned dielectric layer 240. In some embodiments, the conductive connector 252 is surrounded by the dummy connector 254. In some embodiments, the conductive connector 252 of the layer TS1 passes through the portion of the patterned dielectric layer 240 extending into the through hole TH of the patterned conductive pad 130 to physically and electrically contact the active pattern AP of the interconnect structure 220 (for example, located at the top interconnect layer Mt' or other levels of the interconnect layer 222). The conductive connector 252 can be electrically coupled to the patterned conductive pad 130 through the active pattern AP of the interconnect structure 220. In some embodiments, the dummy connector 254 of the layer TS1 passes through the patterned dielectric layer 240 and the patterned passivation layer 226 to contact the dummy pattern DP of the interconnect structure 220 (for example, located at the top interconnect layer Mt' or other levels of the interconnect layer 222).

[0041] The dummy connector 254 and the dummy pattern DP of the interconnect structure may not have an electrical function and may be electrically floating in the layer TS1. In a subsequent step, the layer TS1 may be sawn into semiconductor die. During the use of the semiconductor die, an electrical signal may be connected to the active pattern AP and the conductive connector 252, but the dummy connector 254 and the dummy pattern DP may not be connected to an electrical signal or voltage. In some embodiments, there may be a conductive path between the dummy connector 254 and the dummy pattern DP, but both the dummy connector 254 and the dummy pattern DP may be floating. In some embodiments, the dummy connector 254 and the dummy pattern DP are used for thermal dissipation. In other embodiments, the dummy connector 254 and the dummy pattern DP are used to provide a short ground path for grounding the integrated circuits of the layer TS1.

[0042] FIG. 3A to FIG. 3C 1 is a schematic cross-sectional view showing various stages in a method for manufacturing a semiconductor structure according to some exemplary embodiments of the present disclosure. The manufacturing method of the illustrated embodiment is similar to Figures 1A to 1FFor ease of understanding, the same elements in all figures are referred to by the same reference numerals and will not be described in detail herein. Figure 3A , a dielectric material 340' is formed on the passivation layer 126' of the interconnect structure 120 on the semiconductor substrate 110 to encapsulate the conductive pad 330. For example, a conductive material is formed on the passivation layer 126' and inside the opening of the passivation layer 126' to physically and electrically contact the top interconnect layer Mt, and then the conductive material is patterned to form the conductive pad 330. The conductive pad 330 is electrically coupled to the semiconductor device 112 through the interconnect layer 122 of the interconnect structure 120. In the illustrated embodiment, the conductive pad 330 is not patterned to form a through hole. After the conductive pad 330 is formed, a dielectric material 340' is formed on the passivation layer 126' using a deposition process or other suitable technology to cover the conductive pad 330. The material of the conductive pad 330 and the material of the dielectric material 340' may be similar to the material of the conductive pad 130' and the material of the dielectric material 140', respectively.

[0043] Reference Figure 3B , a portion of the dielectric material 340' is removed to form a patterned dielectric layer 340. In some embodiments, a dual damascene process is performed on the dielectric material 340' to form a patterned dielectric layer 340 having a plurality of trench openings TR1 and TR2 and a plurality of through-hole openings VO' extending from the bottom of the trench opening TR2. The through-hole opening VO' and the trench openings TR1 and TR2 may be formed by a number of methods, such as a through-hole first manufacturing method, a trench first manufacturing method, and other suitable patterning techniques. The trench opening TR2 may correspond to the conductive pad 330 and may be surrounded by the trench opening TR1. In other embodiments, the trench opening TR1 is omitted. Each of the trench openings TR2 may be connected to one of the through-hole openings VO'. The opening depth of one of the trench openings TR1 may be less than the total opening depth of one of the trench openings TR2 and the corresponding through-hole opening VO'. In some embodiments, at least a portion of the conductive pad 330 is exposed in an accessible manner by the trench opening TR2 and the corresponding through-hole opening VO' for further electrical connection. It should be noted that Figure 3B The two groups of trench openings TR2 and via openings VO′ shown are merely exemplary, and there may be more groups of trench openings TR2 and via openings VO′ or only one group of trench openings TR2 and via openings VO′.

[0044] Reference Figure 3C, a conductive material may be formed in the through-hole opening VO' and the trench openings TR1 and TR2 to form a plurality of conductive connectors 352 and dummy connectors 354. For example, the conductive material formed in the trench opening TR1 may be considered as the dummy connector 354, and the conductive material formed in the trench opening TR2 and the through-hole opening VO' and landed on the conductive pad 330 may be considered as the conductive connector 352. The conductive connector 352 physically and electrically contacts the underlying conductive pad 330. It should be noted that the conductive connectors 352 and dummy connectors 354 shown herein are merely exemplary, and the conductive connectors 352 and dummy connectors 354 may be formed as a multilayer structure including a diffusion barrier layer, a seed layer, and a plated metal layer, etc. The formation process of the conductive connectors 352 and the dummy connectors 354 may be similar to that of Figure 1E and Figure 1F The formation process of the conductive connection member 152 and the dummy connection member 154 described in the above will not be described in detail for the sake of brevity. At this point, a layer of TD2 semiconductor structure is substantially formed.

[0045] Continue to refer to Figure 3C , the layer TD2 includes a first surface S1 and a second surface S2 opposite to the first surface S1. In some embodiments, the top surface 352t of the conductive connector 352, the top surface 354t of the dummy connector 354, and the top surface 340t of the patterned dielectric layer 340 are substantially flush at the first surface S1. In some embodiments, the depth Dd of one of the dummy connectors 354 in the patterned dielectric layer 340 is less than the depth Dc' of one of the conductive connectors 352 in the patterned dielectric layer 340. Alternatively, in other embodiments, the depth Dd of one of the dummy connectors 354 may be substantially equal to or greater than the depth Dc' of one of the conductive connectors 352. The conductive connector 352 covered by the patterned dielectric layer 340 in the lateral direction may be electrically coupled to the interconnect layer 122 through the conductive pad 330. The dummy connector 354 disposed next to the conductive connector 352 and embedded in the patterned dielectric layer 340 may not have an electrical function and may be electrically floating. In some embodiments, during use of the layer TD2, an electrical signal may be connected to the semiconductor device 112 through the interconnect layer 122, the conductive pad 330, and the conductive connector 352. However, the dummy connector 354 may not be connected to an electrical signal or voltage. In some embodiments, by forming the dummy connector 354, the pattern density in the layer TD2 becomes more uniform, thereby reducing the pattern loading effect when forming the conductive connector 352.

[0046] Figure 4A and Figure 4B 1 is a schematic cross-sectional view showing various stages in a method for manufacturing a semiconductor structure according to some exemplary embodiments of the present disclosure. The manufacturing method of the illustrated embodiment is similar to Figure 2A to Figure 2Band FIG. 3A to FIG. 3C For ease of understanding, the same elements in all figures are referred to by the same reference numerals and will not be described in detail herein. Figure 4A , an interconnect structure 220' is formed on the semiconductor substrate 110. For example, the interconnect structure 220' includes at least one dielectric layer 224 disposed on the semiconductor substrate 110, a plurality of interconnect layers 222 embedded in the dielectric layer 224 and electrically coupled to the semiconductor device 112, and a patterned passivation layer 226' formed on the topmost dielectric layer 224 of the dielectric layer 224 and partially exposing the top interconnect layer Mt'. The material and formation process of the patterned passivation layer 226' may be similar to Figure 2A The material and formation process of the patterned passivation layer 226 are described in the above. Figure 2A The difference between the patterned passivation layer 226 described in FIG. 2 is that the patterned passivation layer 226 ′ of the illustrated embodiment includes the second opening 226 b and the third opening 226 c , but does not include the first opening 226 a .

[0047] In some embodiments, at least a portion of the dummy pattern DP of the interconnect layer 222 (e.g., the top interconnect layer Mt') is exposed in an accessible manner by the second opening 226b of the patterned passivation layer 226'. The third opening 226c of the patterned passivation layer 226' surrounded by the second opening 226b can expose at least a portion of the active pattern AP of the interconnect layer 222 (e.g., the top interconnect layer Mt') in an accessible manner for connecting to a conductive pad 330 formed subsequently. The conductive pad 330 is formed on the top surface of the patterned passivation layer 226' and inside the third opening 226c of the patterned passivation layer 226'. The material and formation process of the conductive pad 330 are similar to those of the Figure 3A The material and formation process of the conductive pad 330 are described in detail in the accompanying drawings, and therefore will not be described in detail for the sake of brevity.

[0048] Continue to refer to Figure 4A After forming the conductive pad 330, a patterned dielectric layer 440 is formed on the patterned passivation layer 226' and the patterned dielectric layer 440 partially covers the conductive pad 330. The material and formation process of the patterned dielectric layer 440 are similar to those of Figure 2A. In some embodiments, the first opening 440a of the patterned dielectric layer 440 exposes at least a portion of the conductive pad 330 in an accessible manner for further electrical connection. The second opening 440b of the patterned dielectric layer 440 may correspond to the second opening 226b of the patterned passivation layer 226' and may be connected to the second opening 226b, thereby exposing the underlying dummy pattern DP in an accessible manner. In some embodiments, the opening depth of the second opening 440b of the patterned dielectric layer 440 is greater than the opening depth of the first opening 440a of the patterned dielectric layer 440. In some embodiments, the third opening 226c of the patterned passivation layer 226' may be formed before the second opening 226b of the patterned passivation layer 226', and the second opening 440b of the patterned dielectric layer 440 and the second opening 226b of the patterned passivation layer 226' are formed in the same patterning process. It should be noted that the number of openings shown herein is merely exemplary, and there may be more or fewer openings depending on design requirements.

[0049] Reference Figure 4B , a conductive material may be formed in the second opening 226b of the patterned passivation layer 226', the first opening 440a and the second opening 440b of the patterned dielectric layer 440 to form a plurality of conductive connectors 452 and dummy connectors 454. The conductive connectors 452 physically and electrically contact the underlying conductive pads 330. It should be noted that Figure 4B The conductive connector 452 and the dummy connector 454 are shown for illustrative purposes, and the conductive connector 452 and the dummy connector 454 may be formed as a multilayer structure including a diffusion barrier layer, a seed layer, and a plated metal layer. Thus, a layer TS2 semiconductor structure is substantially formed. The layer TS2 includes a first surface S1 and a second surface S2 opposite to the first surface S1. The top surface 454t of the dummy connector 454, the top surface 452t of the conductive connector 452, and the top surface 440t of the patterned dielectric layer 440 may be substantially flush at the first surface S1 of the layer TS2.

[0050] Continue to refer to Figure 4BIn some embodiments, the dummy connector 454 of the layer TS2 penetrates the patterned dielectric layer 440 and the patterned passivation layer 226' to physically contact the dummy pattern DP of the interconnect structure 220' (for example, located at the top interconnect layer Mt' or other levels of the interconnect layer 222). Alternatively, the dummy connector 454 may not pass through the patterned dielectric layer 440 and may not be connected to the interconnect structure 220'. In some embodiments, the conductive connector 452 is surrounded by the dummy connector 454 and may extend from the top surface 440t of the patterned dielectric layer to land on the conductive pad 330. The conductive connector 452 may be electrically coupled to the interconnect structure 220' through the conductive pad 330. In some embodiments, the depth Dd' of one of the dummy connectors 454 in the patterned dielectric layer 440 and the patterned passivation layer 226' is greater than the depth Dc' of one of the conductive connectors 452 in the patterned dielectric layer 440. The dummy connector 454 and the dummy pattern DP connected to the dummy connector 454 may not have an electrical function and may be electrically floating in the layer TS2. In a subsequent step, the layer TS2 may be sawn into semiconductor dies. During the use of the semiconductor dies, electrical signals may be connected to the active pattern AP, the conductive pad 330, and the conductive connector 452, but the dummy connector 454 and the dummy pattern DP may not be connected to electrical signals or voltages. In some embodiments, there may be a conductive path between the dummy connector 454 and the dummy pattern DP, but both the dummy connector 454 and the dummy pattern DP may be floating. In other embodiments, the dummy connector 454 and the dummy pattern DP are used to provide a short ground path for grounding the integrated circuits of the layer TS2 and / or to provide an additional heat dissipation path.

[0051] Figure 5A and Figure 5B Schematic cross-sectional views showing various stages in a method for manufacturing a semiconductor structure according to some exemplary embodiments of the present disclosure. Figure 5A, two of the layers TD1 are bonded together in a face-to-face configuration. For example, the layers TD1 are arranged so that the first surfaces S1 face each other and bond. Alternatively, the layers are arranged in a face-to-back configuration, wherein the first surface of one of the layers is bonded to the second surface of the other of the layers. In some embodiments, the layers TD1 are made separately, and a hybrid bonding process is performed on the layers TD1. It should be noted that various bonding schemes can be used to stack semiconductor structures to form a three-dimensional integrated circuit (3DIC). For example, the bonding interface IF between the layers TD1 includes dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding), metal-to-metal bonding (e.g., copper-to-copper bonding), metal-to-dielectric bonding (e.g., oxide-to-copper bonding), any combination thereof, and / or the like.

[0052] In an exemplary embodiment, the hybrid bonding process of the layer TD1 includes at least the following steps. For example, a surface preparation process for a bonding surface (e.g., the first surface S1 of the layer TD1) is performed to remove particles on the surface. The surface preparation process may include surface cleaning and activation or other suitable processes. In some embodiments, the top surface 152t of the conductive connection 152 and the top surface 154t of the dummy connection 154 may be cleaned by wet cleaning before performing the bonding process. By the chemicals used in the wet cleaning, not only particles are removed, but also native oxides formed on the top surface 152t of the conductive connection 152 and the top surface 154t of the dummy connection 154 of the layer TD1 may be removed. After cleaning, activation of the top surface 140t of the patterned dielectric layer 140 of the layer TD1 may be performed to generate high bonding strength. In some embodiments, plasma activation may be performed to treat the top surface 140t of the patterned dielectric layer 140. In some embodiments, the layers TD1 are aligned with each other and can achieve sub-micron alignment accuracy. Once the layers TD1 are accurately aligned, one of the layers TD1 is placed on the other of the layers TD1 and the one of the layers TD1 contacts the other of the layers TD1. When the activated top surfaces 140t of the patterned dielectric layers 140 of the layers TD1 contact each other, the top surfaces 140t of the patterned dielectric layers 140 of the layers TD1 are pre-bonded. In other words, the layers TD1 are pre-bonded by pre-bonding of the patterned dielectric layers 140. After pre-bonding, the conductive connectors 152 and the dummy connectors 154 of one of the layers TD1 can correspond to and can physically contact the conductive connectors 152 and the dummy connectors 154 of the other of the layers TD1, respectively.

[0053] In some embodiments, after pre-bonding, hybrid bonding of the layer TD1 is performed. Hybrid bonding may include a process of dielectric bonding that enhances bonding between patterned dielectric layers 140 and thermal annealing that facilitates bonding between the conductive connector 152 and the dummy connector 154 of the layer TD1. In some embodiments, the process temperature of the thermal annealing for connector bonding is higher than the process temperature of the process for dielectric bonding. Since the thermal annealing performed on the conductive connector 152 and the dummy connector 154 is performed at a relatively high temperature, metal diffusion and grain growth may occur at the bonding interface IF between the conductive connector 152 and the dummy connector 154 of the two layers TD1. After bonding is performed, the conductive connector 152 of the two layers TD1 provides vertical connection and electrical connection between the two layers TD1. The patterned dielectric layer 140 can be used as a bonding dielectric layer. The conductive connector 152 can be referred to as a bonding connector. The dummy connections 154 of the two layers TD1 are bonded together and may also be referred to as bonding connections, but the dummy connections 154 are electrically isolated from the underlying conductive features. For example, the bonding dummy connections 154 may not have an electrical function and may be electrically floating. Thus, the bonding structure of the two layers TD1 is formed.

[0054] Reference Figure 5B , after bonding, a through semiconductor via (TSV) 70 is formed in the semiconductor substrate 110 and the semiconductor through via 70 extends into the interconnect structure 120 of at least one of the layers TD1. The TSV 70 may extend into the dielectric layer 124 to reach any level of the interconnect layer 122 so that the TSV 70 may be electrically coupled to the semiconductor device 112 through the interconnect layer 122. The formation of the TSV 70 may be performed before or after bonding the layer TD1. In some embodiments, the TSV 70 is formed using a via-first manufacturing method and is formed during the formation of the interconnect structure 120. In other embodiments, the TSV 70 is formed using a via-last approach and may be formed after the formation of the interconnect structure 120. It should be noted that the steps of forming the TSV 70 may be performed in any logical order, which is not limited in the present disclosure. In some embodiments, the TSV 70 tapers from the semiconductor substrate 110 toward the interconnect layer 122. In other embodiments, the width of TSV 70 increases in the direction toward the bonding interface IF. Alternatively, the sidewalls of TSV 70 may be substantially vertical relative to the bonding interface IF. Figure 5BOnly one TSV is shown, however, more TSVs may be provided in the bonding structure to perform one or more functions. It is also noted that any number of the layers TD1 may be stacked in any combination in the vertical direction according to design requirements, and the different layers may be electrically connected to each other through at least conductive connections, TSVs and other conductive features.

[0055] Continue to refer to Figure 5B , a rewiring structure 80 may be formed on the semiconductor substrate 110 and the TSV 70. In some embodiments, before forming the rewiring structure 80, a thinning process (e.g., grinding, polishing and / or etching, etc.) is applied to the second surface S2 of one of the layers TD1, so as to expose the TSV 70 in a touchable manner and reduce the thickness of the semiconductor substrate 110. In some embodiments, before forming the rewiring structure 80, an isolation layer may be formed on the second surface S2 for protection. The rewiring structure 80 may include at least one dielectric pattern 82 and at least one conductive pattern 84 (e.g., line, through hole, pad) disposed in the dielectric pattern 82. The conductive pattern 84 of the rewiring structure 80 may rewire the underlying circuit system and may rewire the electrical signal of the bonding structure. For example, the conductive pattern 84 and the dielectric pattern 82 may be formed using suitable deposition, patterning and metallization techniques (e.g., dielectric deposition, photolithography, etching, seed layer deposition, plating, planarization, etc.) or other suitable processes. The bottommost conductive pattern 84 among the conductive patterns 84 may be embedded in the bottommost dielectric pattern 82 among the dielectric patterns 82, and may physically and electrically contact the underlying TSV 70. The topmost conductive pattern 84 among the conductive patterns 84 may be exposed in a touchable manner by the topmost dielectric pattern 82 among the dielectric patterns 82. In some embodiments, the topmost dielectric pattern 82 among the dielectric patterns 82 may include one or more suitable passivation materials and / or protective materials to provide a certain degree of protection for the underlying conductive pattern 84. In some embodiments, the topmost conductive pattern 84 among the conductive patterns 84 includes an external contact pad for further electrical connection. For example, the external contact pad is an under-bump metallurgy (UBM) pad for a subsequent ball-mounting process. It should be noted that although Figure 5B A two-layer redistribution structure is shown, but the number of dielectric patterns 82 and conductive patterns 84 is not limited thereto.

[0056] Still refer to Figure 5B, an external terminal 90 may be formed on the redistribution structure 80. For example, a plurality of external terminals 90 (e.g., conductive balls / bumps) arranged in an array are formed on the external contact pads of the topmost conductive pattern 84 in the conductive patterns 84. In some embodiments, the external terminal 90 may be a solder ball formed by a ball placement and reflowing process. In some other embodiments, the external terminal 90 may be or may include a copper pillar, a controlled collapse chip connection (C4) bump, a microbump, a copper layer, a nickel layer, a lead free (LF) layer, an electroless nickel electroless palladium immersion gold (ENEPIG) layer, a Cu / LF layer, a Sn / Ag layer, a Sn / Pb layer, a combination thereof, and the like. It should be noted that any suitable external terminal and any suitable process for forming the external terminal may be utilized for the external terminal 90.

[0057] In some embodiments, after forming the external terminals 90, a singulation process may be performed along scribe lines (not shown) to cut the resulting structure into a plurality of semiconductor structures 10A. In some embodiments, the above steps may be performed at a wafer-to-wafer level, wherein the layer TD1 is provided in the form of a wafer for bonding, and then the semiconductor structure 10A may be formed. Figure 5B The structure shown is singulated into multiple semiconductor structures 10A. In other embodiments, the above steps can be performed at the die-to-die level, where the layer TD1 is singulated into multiple semiconductor dies (or chips) from the same or different device wafers before bonding. Alternatively, the above steps can be performed at the die-to-wafer level.

[0058] For advanced technologies, more devices are needed to perform more tasks in a single semiconductor die and the physical area on the semiconductor die is very valuable. By forming a conductive connector 152 that passes through the through hole TH of the patterned conductive pad 130 and inserting the patterned dielectric layer 140 between the conductive connector 152 and the patterned conductive pad 130 to solve the device concerns, valuable space on the semiconductor die can be saved. Therefore, the overall size of the semiconductor structure 10A can be reduced.

[0059] Figures 6 to 11Schematic cross-sectional views showing various semiconductor structures according to some exemplary embodiments of the present disclosure. To discuss variations of the embodiments and for ease of understanding, the same elements in all figures are referred to by the same reference numerals and will not be described in detail herein. Figure 6 , providing a semiconductor structure 10B including the layers TS1 and TD1. The layer TS1 may be stacked on the layer TD1 and used Figure 5A , and bonded to the layer TD1 in a face-to-face configuration by a similar bonding method described in . Alternatively, the layers TS1 and TD1 are arranged in a face-to-back configuration, wherein a first surface of one of the layers TS1 and TD1 is bonded to a second surface of the other of the layers TS1 and TD1. For example, the bonding interface IF between the layer TS1 and the layer TD1 includes a dielectric-to-dielectric bonding (e.g., an oxide-to-oxide bonding), a metal-to-metal bonding (e.g., a copper-to-copper bonding), a metal-to-dielectric bonding (e.g., a copper-to-oxide bonding), any combination thereof, and / or the like.

[0060] In some embodiments, the bonding between the conductive connector 252 of the layer TS1 and the conductive connector 152 of the layer TD1 and / or the bonding between the dummy connector 254 of the layer TS1 and the dummy connector 154 of the layer TD1 may be a via-to-pad bonding. In some embodiments, the via perimeter of the conductive connector 252 and / or the dummy connector 254 overlaps the pad perimeter of the corresponding conductive connector 152 and / or the corresponding dummy connector 154. In some embodiments, the via perimeter may be within the corresponding pad perimeter. In some other embodiments, the via perimeter may be offset in the lateral direction relative to the corresponding pad perimeter. For example, due to formation and / or alignment process variations, the conductive connector 252 and the dummy connector 254 of the layer TS1 may be slightly shifted in one direction (e.g., to the right or to the left) relative to the conductive connector 152 and the dummy connector 154 of the layer TD1. It should be noted that the via perimeter and pad perimeter are not limited in the present disclosure, as long as the conductive connector 252 and the dummy connector 254 of the layer TS1 are bonded to the conductive connector 152 and the dummy connector of the layer TD1 in a reliable manner. It is also noted that any number of the layers TS1 and / or the layers TD1 can be stacked in the vertical direction in any combination according to design requirements, and different layers can be electrically connected to each other through at least conductive connectors, TSVs and other conductive features.

[0061] In some embodiments, TSV 70 is formed in semiconductor substrate 110 and inserted into dielectric layer 224 of interconnect structure 220 of layer TS1 to reach interconnect layer 222. Alternatively, TSV is formed in layer TD1 of semiconductor structure 10B. Rewiring structure 80 is formed on TSV 70 and semiconductor substrate 110, and external terminal 90 is formed on rewiring structure 80 for external electrical connection. Figure 6 As shown, forming the through holes TH through the patterned conductive pads 130 to reach the conductive connections 152 and 252 of the interconnect layers 122 and 222 can increase the available wiring area of ​​the semiconductor structure 10B.

[0062] Reference Figure 7 , providing a semiconductor structure 10C including the layers TD1 and TD2. The layers TD1 can be stacked on each other and used Figure 5A , are bonded to each other in a face-to-face configuration using a similar bonding method described in . Alternatively, the layers TD1 and TD2 are arranged in a face-to-back configuration, wherein a first surface of one of the layers TD1 and TD2 is bonded to a second surface of the other of the layers TD1 and TD2. For example, the bonding interface IF between the layer TD1 and the layer TD2 includes a dielectric-to-dielectric bonding (e.g., an oxide-to-oxide bonding), a metal-to-metal bonding (e.g., a copper-to-copper bonding), a metal-to-dielectric bonding (e.g., a copper-to-oxide bonding), any combination thereof, and / or the like. In some embodiments, the bonding between the conductive connector 352 of the layer TD2 and the conductive connector 152 of the layer TD1 and / or the bonding between the dummy connector 354 of the layer TD2 and the dummy connector 154 of the layer TD1 may be a pad-to-pad bonding. It should be noted that any number of the layers TD1 and / or the layers TD2 may be stacked in any combination in the vertical direction according to design requirements, and different layers may be electrically connected to each other through at least conductive connectors, TSVs and other conductive features. In some embodiments, a TSV 70 is formed in the semiconductor substrate 110 and the TSV 70 is inserted into the dielectric layer 124 of the interconnect structure 120 of the layer TD2 to reach the interconnect layer 122. Alternatively, the TSV is formed in the layer TD1 of the semiconductor structure 10C. A rewiring structure 80 is formed on the TSV 70 and the semiconductor substrate 110, and an external terminal 90 is formed on the rewiring structure 80 for external electrical connection.

[0063] like Figure 7As shown, forming a through hole TH through the patterned conductive pad 130 to reach the conductive connection 152 of the interconnect layer 122 of the layer TD1 can increase the available wiring area of ​​the semiconductor structure 10C. Since the conductive connection 352 lands on the conductive pad 330 of the layer TD2, the heat generated in the semiconductor structure 10C during operation can be conducted to the external terminal 90 through at least the conductive connection 352 and the conductive pad 330, and then dissipated, thereby providing a better vertical heat dissipation channel for the semiconductor structure requiring thermal management.

[0064] Reference Figure 8 , providing a semiconductor structure 10D including the layers TD1 and TS2. The layer TS2 may be stacked on the layer TD1 and used Figure 5A TS2 is bonded to the layer TD1 in a face-to-face configuration by a similar bonding method described in . Alternatively, the layers TD1 and TS2 are arranged in a face-to-back configuration, wherein a first surface of one of the layers TD1 and TS2 is bonded to a second surface of the other of the layers TD1 and TS2. For example, the bonding interface IF between the layer TS2 and the layer TD1 includes a dielectric-to-dielectric bonding (e.g., an oxide-to-oxide bonding), a metal-to-metal bonding (e.g., a copper-to-copper bonding), a metal-to-dielectric bonding (e.g., a copper-to-oxide bonding), any combination thereof, and / or the like. In some embodiments, the bonding between the conductive connector 452 of the layer TS2 and the conductive connector 152 of the layer TD1 and / or the bonding between the dummy connector 454 of the layer TS2 and the dummy connector 154 of the layer TD1 may be a through-hole pad bonding. It should be noted that the via perimeter and the pad perimeter are not limited in the present disclosure, as long as the conductive connector 452 and the dummy connector 454 of the layer TS2 are bonded to the conductive connector 152 and the dummy connector 154 of the layer TD1 in a reliable manner. It is also noted that any number of the layers TD1 and / or the layers TS2 can be stacked in the vertical direction in any combination according to design requirements, and different layers can be electrically connected to each other through at least conductive connectors, TSVs and other conductive features.

[0065] In some embodiments, TSV 70 is formed in semiconductor substrate 110 and inserted into dielectric layer 224 of interconnect structure 220' of layer TS2 to reach active pattern of interconnect layer 222. Alternatively, TSV is formed in layer TD1 of semiconductor structure 10D. Rewiring structure 80 is formed on TSV 70 and semiconductor substrate 110, and external terminal 90 is formed on rewiring structure 80 for external electrical connection. Figure 8As shown, forming a through hole TH through the patterned conductive pad 130 to reach the conductive connector 152 of the interconnect layer 122 of the layer TD1 can increase the available wiring area of ​​the semiconductor structure 10D. The conductive connector 452 of the layer TS2 connected to the conductive pad 330 and the dummy connector 454 of the layer TS2 connected to the dummy pattern of the interconnect structure 220' can provide a larger area for heat dissipation during operation of the semiconductor structure 10D.

[0066] Reference Fig. 9 , a semiconductor structure 10E including two layers TS1 is provided. For example, two of the layers TS1 are used Figure 5A , and are bonded together in a face-to-face configuration using a similar bonding method described in . Alternatively, the layers TS1 are arranged in a face-to-back configuration, wherein a first surface of one of the layers TS1 is bonded to a second surface of another of the layers TS1. For example, the bonding interface IF between the two layers TS1 includes a dielectric-to-dielectric bonding (e.g., an oxide-to-oxide bonding), a metal-to-metal bonding (e.g., a copper-to-copper bonding), a metal-to-dielectric bonding (e.g., a copper-to-oxide bonding), any combination thereof, and / or the like. In some embodiments, the bonding between the conductive connectors 252 of the two layers TS1 and / or the bonding between the dummy connectors 254 of the two layers TS1 may be a via-to-via bonding. It should be noted that the via perimeter is not limited in the present disclosure, as long as the conductive connectors 252 and the dummy connectors 254 of the two layers TS1 are bonded to each other in a reliable manner. It is also noted that any number of the layers TS1 may be stacked in the vertical direction in any combination according to design requirements, and different layers may be electrically connected to each other through at least conductive connectors, TSVs, and other conductive features.

[0067] In some embodiments, a TSV 70 is formed in the semiconductor substrate 110 and is inserted into the dielectric layer 224 of the interconnect structure 220 of one of the layers TS1 to reach the interconnect layer 222. A redistribution structure 80 is formed on the TSV 70 and the semiconductor substrate 110, and an external terminal 90 is formed on the redistribution structure 80 for external electrical connection. Fig. 9 As shown, forming a through hole TH through the patterned conductive pad 130 to reach the bonding connector (such as the conductive connector 252) of the interconnect layer 222 can increase the available wiring area, thereby providing improved wiring feasibility in the semiconductor structure 10E. It should be noted that Fig. 9 The configuration shown is exemplary only. For example, one of the layers TS1 (eg, the one surrounded by the dotted line) may be replaced by any of the layers described above in which the TSVs are provided (eg, Figure 3C The layer TD2 shown, Figure 4BThe layer TS2, etc. shown are replaced, and thus variations of these layers remain within the scope of the claims and the present disclosure.

[0068] Reference Fig.10 , a semiconductor structure 10F including two layers TD2 is provided. For example, two of the layers TD2 are used Figure 5A , and are bonded together in a face-to-face configuration using a similar bonding method described in . Alternatively, the layers TD2 are arranged in a face-to-back configuration, wherein a first surface of one of the layers TD2 is bonded to a second surface of another of the layers TD2. For example, the bonding interface IF between the two layers TD2 includes a dielectric-to-dielectric bonding (e.g., an oxide-to-oxide bonding), a metal-to-metal bonding (e.g., a copper-to-copper bonding), a metal-to-dielectric bonding (e.g., a copper-to-oxide bonding), any combination thereof, and / or the like. In some embodiments, the bonding between the conductive connectors 352 of the two layers TD2 and / or the bonding between the dummy connectors 354 of the two layers TD2 may be a pad-to-pad bonding. It should be noted that the pad perimeter is not limited in the present disclosure, as long as the conductive connectors 352 and the dummy connectors 354 of the two layers TD2 are bonded to each other in a reliable manner. It is also noted that any number of the layers TD2 may be stacked in the vertical direction in any combination according to design requirements, and that different layers may be electrically connected to each other through at least conductive connectors, TSVs, and other conductive features.

[0069] In some embodiments, a TSV 70 is formed in the semiconductor substrate 110 and is inserted into the dielectric layer 124 of the interconnect structure 120 of one of the layers TD2 to reach the interconnect layer 122. A rewiring structure 80 is formed on the TSV 70 and the semiconductor substrate 110, and an external terminal 90 is formed on the rewiring structure 80 for external electrical connection. Fig.10 As shown, providing a conductive connector 352 that lands on the conductive pad 330 from the bonding interface IF can increase the available wiring area, thereby providing improved wiring feasibility in the semiconductor structure 10F. The heat generated in the semiconductor structure 10F during operation can be conducted from at least the conductive connector 352 to the conductive pad 330 to provide a vertical heat dissipation channel for the stacked structure. It should be noted that Fig.10 The configuration shown is exemplary only. For example, one of the layers TD2 (eg, the one surrounded by the dotted line) may be replaced by any of the layers described above in which the TSV is provided (eg, Figure 4B The layer TS2, etc. shown are replaced, and thus variations of these layers remain within the scope of the claims and the present disclosure.

[0070] Reference Fig.11, a semiconductor structure 10G including two layers TS2 is provided. For example, two of the layers TS2 are used Figure 5A , and are bonded together in a face-to-face configuration using a similar bonding method described in . Alternatively, the layers TS2 are arranged in a face-to-back configuration, wherein a first surface of one of the layers TS2 is bonded to a second surface of another of the layers TS2. For example, the bonding interface IF between the two layers TS2 includes a dielectric-to-dielectric bonding (e.g., an oxide-to-oxide bonding), a metal-to-metal bonding (e.g., a copper-to-copper bonding), a metal-to-dielectric bonding (e.g., a copper-to-oxide bonding), any combination thereof, and / or the like. In some embodiments, the bonding between the conductive connectors 452 of the two layers TS2 and / or the bonding between the dummy connectors 454 of the two layers TS2 may be a via-to-via bonding. It should be noted that the via perimeter is not limited in the present disclosure, as long as the conductive connectors 452 and the dummy connectors 454 of the layer TS2 are bonded to each other in a reliable manner. It is also noted that any number of the layers TS2 may be stacked in the vertical direction in any combination according to design requirements, and different layers may be electrically connected to each other through at least conductive connectors, TSVs, and other conductive features.

[0071] In some embodiments, a TSV 70 is formed in the semiconductor substrate 110 and is inserted into the dielectric layer 224 of the interconnect structure 220' of one of the layers TS2 to reach the interconnect layer 222'. A redistribution structure 80 is formed on the TSV 70 and the semiconductor substrate 110, and an external terminal 90 is formed on the redistribution structure 80 for external electrical connection. Fig.11 As shown, providing a conductive connector 452 that lands on the conductive pad 330 from the bonding interface IF can increase the available wiring area, thereby providing improved wiring feasibility in the semiconductor structure 10G. Heat generated in the semiconductor structure 10G during operation can be conducted at least from the conductive connector 452 to the conductive pad 330 and / or from the dummy connector 454 to the interconnect layer 222' to provide a vertical heat dissipation channel for the stacked structure. It should be noted that Fig.11 For example, one of the layers TS2 (eg, the one surrounded by the dashed line) may be replaced by any of the layers described above in which TSVs are disposed, and variations of these layers thus remain within the scope of the claims and the present disclosure.

[0072] Fig.12 is a schematic cross-sectional view showing the application of a semiconductor structure according to some exemplary embodiments of the present disclosure. Fig.12, providing a structure 20 including a first component 22 and a second component 24 disposed on the first component 22. The first component 22 may be or may include a printed circuit board (PCB), a printed wiring board, an interposer, a packaging substrate, and / or other carriers capable of carrying an integrated circuit. In some embodiments, the second component 24 mounted on the first component 22 is similar to one of the semiconductor structures 10A to 10G described above. For example, one or more of the semiconductor structures may be electrically coupled to the first component 22 via a plurality of terminals 24a (e.g., external terminals 90). In some other embodiments, the second component 24 mounted on the first component 22 may be a device including at least one semiconductor structure (e.g., a combination of the above) encapsulated therein. Figure 5B and Figures 6 to 11 10A to 10G) described above. For example, the second component 24 may include a plurality of semiconductor structures (e.g., any combination of semiconductor structures 10A to 10G) individually and laterally encapsulated by an insulating encapsulator (not shown). The second component 24 may also include a fan-out rewiring structure (not shown) formed on the insulating encapsulator and the semiconductor structure encapsulated by the insulating encapsulator, and the fan-out rewiring structure may be electrically coupled to the semiconductor structure. The second component 24 may also include a plurality of terminals 24a formed on the fan-out rewiring structure to be electrically coupled to the first component 22 and the semiconductor structure through the fan-out rewiring structure. Other packaging technologies may be used to form the structure 20, and the packaging technologies are not limited in the present disclosure. The structure 20 may be part of an electronic system such as the following devices: a computer (e.g., a high-performance computer), a computing device used in conjunction with an artificial intelligence system, a wireless communication device, a computer-related peripheral device, an entertainment device, etc. It should be noted that other electronic applications may also exist.

[0073] According to some embodiments of the present disclosure, a semiconductor structure includes a first semiconductor substrate, a first interconnect structure, a first conductive pad, a first dielectric layer, and a first conductive connector. The first semiconductor substrate includes a plurality of first semiconductor devices located in the first semiconductor substrate. The first interconnect structure is disposed on the first semiconductor substrate and electrically coupled to the first semiconductor device. The first conductive pad is disposed on the first interconnect structure and electrically coupled to the first interconnect structure. The first dielectric layer covers the first conductive pad and the first interconnect structure, and the first dielectric layer includes a portion extending through the first conductive pad. The first conductive connector is disposed on the first interconnect structure and electrically coupled to the first interconnect structure, and the first conductive connector extends through the portion of the first dielectric layer.

[0074] In some embodiments, the semiconductor structure further comprises a dummy connector disposed beside the first conductive connector and embedded in the first dielectric layer. In some embodiments, the depth of the dummy connector in the first dielectric layer is less than the depth of the first conductive connector in the first dielectric layer, and the top surface of the dummy connector is substantially flush with the top surface of the first conductive connector. In some embodiments, the dummy connector extends from the dummy pattern of the first interconnect structure and penetrates the first dielectric layer. In some embodiments, the semiconductor structure further comprises a second semiconductor substrate, including a plurality of second semiconductor devices disposed in the second semiconductor substrate; a second interconnect structure disposed on the second semiconductor substrate and electrically coupled to the second semiconductor device; a second conductive pad disposed on the second interconnect structure and electrically coupled to the second interconnect structure; a second dielectric layer covering the second conductive pad and the second interconnect structure, the second dielectric layer being bonded to the first dielectric layer; and a second conductive connector disposed on the second interconnect structure and electrically coupled to the second interconnect structure, the second conductive connector being bonded to the first conductive connector and extending toward the second conductive pad. In some embodiments, the second conductive connector is electrically coupled to the second interconnect structure through the second conductive pad. In some embodiments, a portion of the second dielectric layer extends through the second conductive pad and the second conductive connector extends through the portion of the second dielectric layer. In some embodiments, the semiconductor structure further includes a first dummy connector disposed next to the first conductive connector and embedded in the first dielectric layer, and a second dummy connector disposed next to the second conductive connector and embedded in the second dielectric layer and the second dummy connector is bonded to the first dummy connector. In some embodiments, the first dummy connector penetrates the first dielectric layer to contact the first dummy pattern of the first interconnect structure, and the second dummy connector penetrates the second dielectric layer to contact the second dummy pattern of the second interconnect structure.

[0075] According to some embodiments of the present disclosure, a semiconductor structure includes a first semiconductor die and a second semiconductor die, the second semiconductor die being stacked on the first semiconductor die and bonded to the first semiconductor die. The first semiconductor die includes: a first interconnect layer; a first conductive pad disposed on the first interconnect layer and electrically coupled to the first interconnect layer; a first dielectric layer disposed on the first interconnect layer and covering the first conductive pad; a first conductive connector embedded in the first dielectric layer and extending toward the first conductive pad to be electrically coupled to the first interconnect layer; and a first dummy connector disposed beside the first conductive connector and embedded in the first dielectric layer. The second semiconductor die includes a second dielectric layer, a second conductive connector, and a second dummy connector. The second dielectric layer is bonded to the first dielectric layer of the first semiconductor die. The second conductive connector and the second dummy connector are embedded in the second dielectric layer and bonded to the first conductive connector of the first semiconductor die and the first dummy connector of the first semiconductor die, respectively.

[0076] In some embodiments, the first conductive connector extends from the bonding interface between the first semiconductor die and the second semiconductor die and lands on the first conductive pad, and the first conductive connector is electrically coupled to the first interconnect layer through the first conductive pad. In some embodiments, the first conductive connector extends from the bonding interface between the first semiconductor die and the second semiconductor die and penetrates the first conductive pad to contact the first interconnect layer, and the first conductive connector is laterally isolated from the first conductive pad by the first dielectric layer. In some embodiments, the first dummy connector extends from the bonding interface between the first semiconductor die and the second semiconductor die and penetrates the first dielectric layer to contact the dummy pattern of the first interconnect layer. In some embodiments, the first conductive connector and the first dummy connector taper from the bonding interface between the first semiconductor die and the second semiconductor die toward the first interconnect layer. In some embodiments, the first dummy connector of the first semiconductor die and the second dummy connector of the second semiconductor die are electrically floating. In some embodiments, the first semiconductor die further includes: a semiconductor substrate including a plurality of semiconductor devices in the semiconductor substrate, wherein the first interconnect layer is disposed on the semiconductor substrate and electrically coupled to the semiconductor devices; and a semiconductor via penetrating the semiconductor substrate and electrically coupled to the first interconnect layer.

[0077] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes at least the following steps. A patterned conductive pad having a through hole is formed on an interconnect structure on a semiconductor substrate. A dielectric material on the interconnect structure is patterned to form a patterned dielectric layer having a first opening. The first opening passes through a portion of the dielectric material formed inside the through hole of the patterned conductive pad to expose the interconnect structure in a touchable manner. A conductive material is formed inside the first opening of the patterned dielectric layer and the conductive material contacts the interconnect structure to form a conductive connector. The conductive connector is laterally isolated from the patterned conductive pad by the patterned dielectric layer.

[0078] In some embodiments, the manufacturing method further includes forming a second opening in the dielectric material and adjacent to the first opening, wherein the depth of the second opening is less than the depth of the first opening; and forming the conductive material in the second opening of the patterned dielectric layer to form a dummy connector, wherein the dummy connector is electrically floating. In some embodiments, the manufacturing method further includes forming a second opening through the dielectric material to expose a dummy pattern of the interconnect structure in a touchable manner; and forming the conductive material in the second opening of the patterned dielectric layer and the conductive material contacts the dummy pattern of the interconnect structure to form a dummy connector, wherein the dummy connector is electrically floating. In some embodiments, the manufacturing method further includes locally removing the conductive material until the top surface of the dielectric material is exposed.

[0079] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

[0080] [Explanation of Symbols]

[0081] 10A, 10B, 10C, 10D, 10E, 10F, 10G: Semiconductor structure

[0082] 20: Structure

[0083] 22: First Component

[0084] 24: Second component

[0085] 24a: Terminal

[0086] 70: Semiconductor through-hole via (TSV)

[0087] 80: Rewiring Structure

[0088] 82: Dielectric pattern

[0089] 84: Conductive pattern

[0090] 90: External terminal

[0091] 110: Semiconductor substrate

[0092] 112: Semiconductor devices

[0093] 120, 220, 220': Inner connection structure

[0094] 122, 222: interconnection layer

[0095] 124, 224: Dielectric layer

[0096] 126, 226, 226': patterned passivation layer

[0097] 126': Passivation layer

[0098] 130, 130', 330: Conductive pad

[0099] 130a: Outer wall

[0100] 130b: Inner wall

[0101] 130t, 140t, 152t, 154t, 240t, 252t, 254t, 340t, 352t, 354t, 440t, 452t, 454t: Top surface

[0102] 140, 240, 340, 440: Patterned dielectric layer

[0103] 140', 340': Dielectric material

[0104] 152, 252, 352, 452: Conductive connectors

[0105] 152a: Groove part

[0106] 152b: Through hole part

[0107] 152c: Bottom part

[0108] 154, 254, 354, 454: Virtual connectors

[0109] 226a, 240a, 440a: First opening

[0110] 226b, 240b, 440b: Second opening

[0111] 226c: The third opening

[0112] AP: Active Pattern

[0113] Dc, Dc', Dd, Dd': Depth

[0114] CM: Conductive material

[0115] DP: Virtual Pattern

[0116] IF: Interface

[0117] M1: Bottom inner connection layer

[0118] M2: Second level inner link layer

[0119] M3: The third level inner layer

[0120] Mt, Mt': top inner connecting layer

[0121] S1: First surface

[0122] S2: Second surface

[0123] TD1, TD2, TS1, TS2: Layer

[0124] TH: Through hole

[0125] TR1, TR2: Groove opening

[0126] VO, VO': through hole opening

[0127] WH1, WT1, WV1: Top width

[0128] WH2, WT2, WV2: Bottom width

[0129] WV3, WV4: Width

Claims

1. A semiconductor structure comprising: A first semiconductor substrate including a plurality of first semiconductor devices located in the first semiconductor substrate; a first interconnect structure disposed on the first semiconductor substrate and electrically coupled to the first semiconductor device; a first conductive pad disposed on the first interconnect structure and electrically coupled to the first interconnect structure; a first dielectric layer covering the first conductive pad and the first interconnect structure, the first dielectric layer including a portion extending through the first conductive pad; a first conductive connector disposed on and electrically coupled to the first interconnect structure, the first conductive connector extending through the portion of the first dielectric layer; a second semiconductor substrate, comprising a plurality of second semiconductor devices disposed in the second semiconductor substrate; a second interconnect structure disposed on the second semiconductor substrate and electrically coupled to the second semiconductor device; a second conductive pad disposed on the second interconnect structure and electrically coupled to the second interconnect structure; a second dielectric layer, covering the second conductive pad and the second interconnect structure, the second dielectric layer being bonded to the first dielectric layer; as well as The second conductive connection member is disposed on the second interconnect structure and electrically coupled to the second interconnect structure, and the second conductive connection member is bonded to the first conductive connection member and extends toward the second conductive pad.

2. The semiconductor structure according to claim 1, further comprising: A dummy connection is disposed beside the first conductive connection and embedded in the first dielectric layer.

3. The semiconductor structure of claim 2, wherein a depth of the dummy connector in the first dielectric layer is less than a depth of the first conductive connector in the first dielectric layer, and a top surface of the dummy connector is substantially flush with a top surface of the first conductive connector. 4 . The semiconductor structure of claim 2 , wherein the dummy connector extends from a dummy pattern of the first interconnect structure and penetrates the first dielectric layer. The semiconductor structure of claim 2 , wherein the dummy connection is electrically floating. 6 . The semiconductor structure of claim 1 , wherein the second conductive connector is electrically coupled to the second interconnect structure through the second conductive pad. 7 . The semiconductor structure of claim 1 , wherein a portion of the second dielectric layer extends through the second conductive pad and the second conductive connector extends through the portion of the second dielectric layer.

8. The semiconductor structure according to claim 1, further comprising: a first dummy connector, disposed beside the first conductive connector and embedded in the first dielectric layer; as well as A second dummy connector is disposed beside the second conductive connector and embedded in the second dielectric layer, and the second dummy connector is bonded to the first dummy connector.

9. The semiconductor structure of claim 8, wherein: The first dummy connector penetrates the first dielectric layer to contact the first dummy pattern of the first interconnect structure, and The second dummy connector penetrates the second dielectric layer to contact the second dummy pattern of the second interconnect structure.

10. A semiconductor structure comprising: A first semiconductor die comprising: First inner layer; a first conductive pad disposed on the first interconnect layer and electrically coupled to the first interconnect layer; A first dielectric layer, disposed on the first interconnect layer and covering the first conducting pad; a first conductive connection embedded in the first dielectric layer and extending toward the first conductive pad to be electrically coupled to the first interconnect layer; and a first dummy connector disposed beside the first conductive connector and embedded in the first dielectric layer; and A second semiconductor die stacked on and bonded to the first semiconductor die, the second semiconductor die comprising: a second dielectric layer bonded to the first dielectric layer of the first semiconductor die; and A second conductive connector and a second dummy connector are embedded in the second dielectric layer and bonded to the first conductive connector of the first semiconductor die and the first dummy connector of the first semiconductor die, respectively.

11. The semiconductor structure of claim 10, wherein the first conductive connector extends from a bonding interface between the first semiconductor die and the second semiconductor die and lands on the first conductive pad, and the first conductive connector is electrically coupled to the first interconnect layer through the first conductive pad.

12. The semiconductor structure of claim 10, wherein: The first conductive connector extends from a bonding interface between the first semiconductor die and the second semiconductor die and penetrates the first conductive pad to contact the first interconnect layer, and The first conductive connection is laterally isolated from the first conductive pad by the first dielectric layer. 13 . The semiconductor structure of claim 10 , wherein the first dummy connector extends from a bonding interface between the first semiconductor die and the second semiconductor die and penetrates the first dielectric layer to contact a dummy pattern of the first interconnect layer. 14 . The semiconductor structure of claim 10 , wherein the first conductive connector and the first dummy connector taper from a bonding interface between the first semiconductor die and the second semiconductor die toward the first interconnect layer. 15 . The semiconductor structure of claim 10 , wherein the first dummy connection of the first semiconductor die and the second dummy connection of the second semiconductor die are electrically floating.

16. The semiconductor structure of claim 10, wherein the first semiconductor die further comprises: a semiconductor substrate comprising a plurality of semiconductor devices disposed in the semiconductor substrate, wherein the first interconnect layer is disposed over the semiconductor substrate and electrically coupled to the semiconductor devices; as well as The semiconductor through via penetrates the semiconductor substrate and is electrically coupled to the first interconnect layer.

17. A semiconductor structure comprising: A first semiconductor die comprising: A first dielectric layer covering the first conducting pad; and a first conductive connector that penetrates the first dielectric layer to contact the first interconnect structure, and the first conductive connector is disposed in a through hole of the first conductive pad, wherein a portion of the first dielectric layer disposed in the through hole of the first conductive pad separates the first conductive pad from the first conductive connector; and A second semiconductor die stacked on the first semiconductor die and comprising: a second conductive pad bonded to the first conductive pad; a second dielectric layer covering the second conducting pad and bonded to the first dielectric layer; and The second conductive connecting member is bonded to the first conductive connecting member and extends toward the second conductive pad.

18. The semiconductor structure of claim 17, wherein the first semiconductor die further comprises: a semiconductor substrate, disposed on the first interconnect structure opposite to the first conductive pad; and The semiconductor through-hole penetrates the semiconductor substrate to connect the first interconnect structure. 19 . The semiconductor structure according to claim 17 , wherein the second conductive connection penetrates the second conductive pad, and a portion of the second dielectric layer is disposed within the second conductive pad to laterally cover the second conductive connection.

20. The semiconductor structure of claim 17, wherein the second conductive connection lands on the second conductive pad.

21. A method for manufacturing a semiconductor structure, comprising: Forming the first part, including: forming a first patterned conductive pad having a first through hole on a first interconnect structure above the first semiconductor substrate; patterning a dielectric material on the first interconnect structure to form a first patterned dielectric layer having a first opening, wherein the first opening penetrates a portion of the dielectric material formed inside the first through hole of the first patterned conductive pad to expose the first interconnect structure in an accessible manner; and forming a conductive material in the first opening of the first patterned dielectric layer and in contact with the first interconnect structure to form a first conductive connector laterally isolated from the first patterned conductive pad by the first patterned dielectric layer; and A singulation process is performed on the first portion to cut through the first patterned dielectric layer, the first interconnect structure below the first patterned dielectric layer, and the first semiconductor substrate below the first interconnect structure to form a continuous sidewall of a semiconductor structure.

22. The method for manufacturing a semiconductor structure according to claim 21, further comprising: forming a second opening in the dielectric material and adjacent to the first opening, wherein a depth of the second opening is less than a depth of the first opening; as well as The conductive material is formed within the second opening of the first patterned dielectric layer to form a dummy connection, wherein the dummy connection is electrically floating.

23. The method for manufacturing a semiconductor structure according to claim 21, further comprising: forming a second opening through the dielectric material to tactilely expose the dummy pattern of the first interconnect structure; as well as The conductive material is formed in the second opening of the first patterned dielectric layer and contacts the dummy pattern of the first interconnect structure to form a dummy connector, wherein the dummy connector is electrically floating.

24. The method for manufacturing a semiconductor structure according to claim 21, wherein before performing the singulation process, the method further comprises: Providing a second portion, wherein the second portion includes a second semiconductor substrate, a second interconnect structure on the second semiconductor substrate, a second conductive connector on the second interconnect structure, and a second patterned dielectric layer on the second interconnect structure and laterally covering the second conductive connector; as well as The second portion is bonded to the first portion, wherein the first conductive connector of the first portion is in contact with the second conductive connector of the second portion.

25. The method for manufacturing a semiconductor structure according to claim 24, wherein when bonding the second portion to the first portion, the method further comprises: aligning the second conductive connector of the second portion with the first conductive connector of the first portion; placing the second portion on the first portion, wherein the first conductive connector is in direct contact with the second conductive connector and the first patterned dielectric layer is in direct contact with the second patterned dielectric layer; and The interface between the second portion and the first portion is heat treated.

26. The method for manufacturing a semiconductor structure according to claim 24, wherein after bonding the second portion to the first portion and before performing the singulation process, the method further comprises: A semiconductor through via is formed on the second semiconductor substrate, wherein the semiconductor through via penetrates the second semiconductor substrate to contact the second interconnect structure.

27. The method for manufacturing a semiconductor structure according to claim 26, wherein after forming the semiconductor through hole and before performing the singulation process, the method further comprises: forming a redistribution layer on the back side of the second semiconductor substrate and the semiconductor through-hole; as well as An external terminal is formed on the redistribution layer to be electrically coupled to the semiconductor through via.

28. The method for manufacturing a semiconductor structure according to claim 24, wherein providing the second portion comprises: forming a second patterned conductive pad having a second through hole on the second interconnect structure; forming the second patterned dielectric layer having a third opening, wherein a portion of the second patterned dielectric layer extends into the second through hole of the second patterned conductive pad, and the third opening is aligned with the second through hole of the second patterned conductive pad to expose the second interconnect structure in an accessible manner; as well as The second conductive connector is formed in the third opening of the second patterned dielectric layer to be laterally isolated from the second patterned conductive pad.

29. The method for manufacturing a semiconductor structure according to claim 24, wherein providing the second portion comprises: forming the second conductive connector on the contact pad above the second interconnect structure; as well as The second patterned dielectric layer is formed on the second interconnect structure to cover the contact pad and the second conductive connector.

30. A method for manufacturing a semiconductor structure, comprising: Forming the first part, including: forming a first patterned dielectric layer on the first interconnect structure over the first semiconductor substrate to partially cover a contact pad on the first interconnect structure, wherein a first opening of the first patterned dielectric layer exposes a portion of the contact pad in an accessible manner; and forming a plurality of first conductive connectors in the first opening of the first patterned dielectric layer and correspondingly landing on the contact pads in a one-to-one manner; forming a second portion including a plurality of second conductive connections coupled to a second interconnect structure over a second semiconductor substrate; and The second conductive connectors of the second portion are joined to the first conductive connectors of the first portion in a one-to-one correspondence.

31. The method for manufacturing a semiconductor structure according to claim 30, wherein forming the second portion comprises: forming a patterned conductive pad having a through hole on the second interconnect structure above the second semiconductor substrate; forming a second patterned dielectric layer having a second opening on the second interconnect structure, wherein a portion of the second patterned dielectric layer extends into each of the through holes of the patterned conductive pad to expose the second interconnect structure in a touchable manner; as well as The second conductive connector is formed in the second opening of the second patterned dielectric layer to be laterally spaced apart from the patterned conductive pad.

32. The method for manufacturing a semiconductor structure according to claim 31, wherein bonding the second portion to the first portion comprises: The second patterned dielectric layer of the second portion is bonded to the first patterned dielectric layer of the first portion.

33. The method for manufacturing a semiconductor structure according to claim 30, further comprising: A semiconductor through via is formed on the first semiconductor substrate of the first portion, wherein the semiconductor through via penetrates the first semiconductor substrate to contact the first interconnect structure.

34. The method for manufacturing a semiconductor structure according to claim 33, further comprising: forming a redistribution layer on the back side of the first semiconductor substrate and the semiconductor through-hole; as well as An external terminal is formed on the redistribution layer to be electrically coupled to the semiconductor through via.

35. The method for manufacturing a semiconductor structure according to claim 30, further comprising: After bonding the second portion to the first portion, a singulation process is performed to cut through the second portion and the first portion to form a continuous sidewall of the semiconductor structure.

36. A method for manufacturing a semiconductor structure, comprising: The second part is joined to the first part, wherein: The first portion includes a patterned conductive pad, a first conductive connection penetrating the patterned conductive pad, a first patterned dielectric layer covering the patterned conductive pad and laterally separating the first conductive connection from the patterned conductive pad, and The second portion includes a second conductive connector bonded to the first conductive connector and a second patterned dielectric layer bonded to the first patterned dielectric layer; and The first portion and the second portion are cut through to form a continuous sidewall of the semiconductor structure.

37. The method for manufacturing a semiconductor structure according to claim 36, wherein before bonding the second portion to the first portion, forming the first portion comprises: Removing a portion of a conductive pad formed on an interconnect structure above a semiconductor substrate to form the patterned conductive pad, wherein a portion of the interconnect structure is exposed in an accessible manner by a through hole of the patterned conductive pad; covering the patterned conductive pads with a dielectric material; removing a portion of the dielectric material to form the first patterned dielectric layer, wherein a portion of the first patterned dielectric layer extends into the through hole of the patterned conductive pad; as well as The first conductive connector is formed in the through hole of the patterned conductive pad, and the portion of the first patterned dielectric layer is interposed between the first conductive connector and the patterned conductive pad.

38. The method for manufacturing a semiconductor structure according to claim 36, wherein before bonding the second portion to the first portion, forming the second portion comprises: covering contact pads formed on the interconnect structure above the semiconductor substrate with a dielectric material; removing a portion of the dielectric material to form the second patterned dielectric layer having an opening, the opening exposing a portion of the contact pad in an accessible manner; as well as A second conductive connector is formed in the opening of the second patterned dielectric layer to land on the contact pad.

39. The method for manufacturing a semiconductor structure according to claim 36, wherein the first portion further comprises a semiconductor substrate and an interconnect structure on a front side of the semiconductor substrate, the patterned conductive pad of the first portion is formed on the interconnect structure, and before cutting through the first portion and the second portion, the method further comprises: A semiconductor through via is formed on the semiconductor substrate of the first portion, wherein the semiconductor through via penetrates the semiconductor substrate to contact the interconnect structure.

40. The method for manufacturing a semiconductor structure according to claim 39, wherein before cutting through the first portion and the second portion, the method further comprises: forming a redistribution layer over the semiconductor through-via of the first portion and a back side of the semiconductor substrate; as well as An external terminal is formed on the redistribution layer to be electrically coupled to the semiconductor through via.

Images