Integrated circuit device and method for manufacturing the same

Abstract

An integrated circuit device and a method for manufacturing the same are provided. The integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate; an upper memory stack located on the lower memory stack and including a plurality of upper word lines; at least one first lower interconnect layer extending in a horizontal direction at a first vertical height between the lower memory stack and the upper memory stack and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines; a separate insulating film covering the at least one first lower interconnect layer; and at least one first upper interconnect layer extending in a horizontal direction at a second vertical height higher than the upper memory stack and configured to be electrically connected to at least one upper word line selected from the upper word lines.

Description

[0001] Citation of priority application

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0058311 filed on May 17, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to an integrated circuit device and / or a method of manufacturing the same, and more particularly, to an integrated circuit device including a nonvolatile vertical memory device and / or a method of manufacturing the same. Background Art

[0004] As information communication devices become more multifunctional, there is a desire and / or demand for an integrated circuit device including a memory device having enhanced capacity and integration. As the size of a memory cell decreases due to a higher integration, an operating circuit and a wiring structure included in the memory device for operation and electrical connection of the memory device become more complex. Therefore, there is a desire and / or demand for an integrated circuit device including a memory device having improved electrical characteristics while improving integration. Summary of the invention

[0005] The present invention is conceived to provide an integrated circuit device and a method for manufacturing the same, wherein in a vertical memory device, even when the number of stacked word lines increases to obtain a higher degree of integration, and the number of contacts connected to the word lines and the number of interconnects increase, the area occupied by the memory device is reduced, and thus the area of ​​the chip is also reduced. This may enable higher-level chip manufacturing and / or higher yields. In addition, the degree of freedom of interconnect arrangement is increased, and even when the number of stacked word lines increases, a simplified process can be performed without increasing the process difficulty for contact formation.

[0006] According to some example embodiments of the inventive concept, an integrated circuit device is provided, the integrated circuit device comprising: a substrate including a memory cell region and a connection region; a lower memory stack including a plurality of lower word lines located on the memory cell region and the connection region of the substrate, the plurality of lower word lines extending in a horizontal direction parallel to a main surface of the substrate, the plurality of lower word lines overlapping each other in a vertical direction; an upper memory stack located on the lower memory stack, the upper memory stack including a plurality of upper word lines overlapping each other in the vertical direction; at least one first lower interconnect layer between the lower memory stack and the upper memory stack on the connection region Located at a first vertical height, the at least one first lower interconnect layer extends in a horizontal direction and is configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines; a separate insulating film covering the at least one first lower interconnect layer so that an upper surface of the at least one first lower interconnect layer does not contact other conductors on a connection region; and at least one first upper interconnect layer located at a second vertical height higher than an upper memory stack on the connection region, the at least one first upper interconnect layer extends in a horizontal direction, and the at least one first upper interconnect layer is configured to be electrically connected to at least one upper word line selected from the plurality of upper word lines.

[0007] According to some example embodiments of the inventive concept, there is provided an integrated circuit device, the integrated circuit device comprising: a substrate including a memory cell region and a connection region; a peripheral circuit region spaced apart from the memory cell region and including a plurality of circuits; a lower memory stack including: (i) a plurality of lower word lines located on the memory cell region and extending in a horizontal direction parallel to a main surface of the substrate, the plurality of lower word lines overlapping each other in a vertical direction, and (ii) a plurality of lower pad regions connected to the plurality of lower word lines and corresponding to stepped lower connection portions on the connection region; an upper memory stack located on the memory cell region; A memory cell region is provided above a lower memory stack on a memory cell region, and includes: (i) a plurality of upper word lines extending in a horizontal direction and overlapping each other in a vertical direction, and (ii) a plurality of upper pad regions connected to the plurality of upper word lines and corresponding to the stepped upper connection portions on the connection region; a lower insulating film located on the connection region, the lower insulating film covering the stepped lower connection portions; a plurality of lower contact plugs extending from the plurality of lower pad regions through the lower insulating film to a first vertical height, the first vertical height being lower than the upper memory stack; and a plurality of first lower interconnect layers located between the lower memory stack and the upper memory stack. At least one first lower interconnect layer selected from the plurality of first lower interconnect layers includes: (i) a first partial portion connected to at least one of the plurality of lower contact plugs; and (ii) a second partial portion connected to at least one of the plurality of circuits.

[0008] According to some example embodiments conceived in the present invention, there is provided an integrated circuit device, which includes: a first substrate, which includes a memory cell area and a connection area; a lower memory stack, which includes: (i) a plurality of lower word lines, which extend in a horizontal direction parallel to a main surface of the first substrate on the memory cell area, the plurality of lower word lines overlap each other in a vertical direction, and (ii) a plurality of lower pad areas, which are located on the connection area, the plurality of lower pad areas are connected to the plurality of lower word lines; and an upper memory stack, which is located on the lower memory stack, the upper memory stack including: (i) a plurality of upper word lines, which are located on the memory cell area and overlap each other in the vertical direction, and (ii) a plurality of upper pad areas, which are connected to the plurality of upper word lines and are located on the connection area. At least one first lower interconnect layer extends in a horizontal direction at a first vertical height between the lower memory stack and the upper memory stack on the connection area, at least one lower contact plug is connected between at least one lower pad area selected from the plurality of lower pad areas and the at least one first lower interconnect layer, and a separate insulating film covers the at least one first lower interconnect layer so that an upper surface of the at least one first lower interconnect layer does not contact other conductors on the connection area.

[0009] According to some example embodiments of the inventive concept, there is provided a method for manufacturing an integrated circuit device, the method comprising: preparing a substrate; forming a lower memory stack, the lower memory stack comprising: (i) a plurality of lower word lines extending in a horizontal direction parallel to a main surface of the substrate and stacked on each other in a vertical direction on the substrate, and (ii) a plurality of lower pad regions connected to the plurality of lower word lines; forming a plurality of lower contact plugs, the plurality of lower contact plugs comprising a plurality of first lower contact plugs connected to a plurality of first lower pad regions selected from the plurality of lower pad regions; forming a plurality of lower interconnect layers on the substrate, the plurality of lower interconnect layers comprising a plurality of first lower interconnect layers extending in a horizontal direction at a first vertical height higher than the lower memory stack, the first lower interconnect layers being connected to the plurality of lower word lines; a plurality of first lower contact plugs; forming a separate insulating film on the plurality of lower interconnect layers, the separate insulating film covering the plurality of lower interconnect layers; forming an upper memory stack, the upper memory stack being spaced apart from the lower memory stack in a vertical direction, and the separate insulating film being interposed therebetween, the upper memory stack comprising: (i) a plurality of upper word lines stacked one on top of the other in a vertical direction, and (ii) a plurality of upper pad regions connected to the plurality of upper word lines; forming a plurality of upper contact plugs, the plurality of upper contact plugs comprising a plurality of first upper contact plugs connected to the plurality of upper pad regions; and forming a plurality of upper interconnect layers, the plurality of upper interconnect layers extending in a horizontal direction at a second vertical height higher than the first vertical height, the plurality of upper interconnect layers being connected to the plurality of lower contact plugs.

[0010] According to some example embodiments of the inventive concept, there is provided a method for manufacturing an integrated circuit device, the method comprising: forming a lower memory stack on a substrate, the lower memory stack comprising: (i) a plurality of lower word lines extending in a horizontal direction parallel to a main surface of the substrate and overlapping each other in a vertical direction, and (ii) a plurality of lower pad regions connected to the plurality of lower word lines; forming a plurality of lower contact plugs on the substrate, the plurality of lower contact plugs connected to the plurality of lower pad regions; forming a plurality of lower interconnect layers on the substrate, the plurality of lower interconnect layers extending in a horizontal direction at a first vertical height higher than the lower memory stack and connected to the plurality of lower contact plugs; forming a separate insulating film, the separate insulating film covering the lower memory stack on the substrate; A lower memory stack and a lower interconnect layer; forming an upper memory stack, the upper memory stack comprising: (i) a plurality of upper word lines located on a bonding substrate, the plurality of upper word lines being stacked one on another in a vertical direction, and (ii) a plurality of upper pad regions connected to the plurality of upper word lines; forming a plurality of upper contact plugs on the bonding substrate, the plurality of upper contact plugs being connected to the plurality of upper pad regions; forming a plurality of upper interconnect layers on the bonding substrate, the plurality of upper interconnect layers extending in a horizontal direction at a second vertical height higher than the upper memory stack and being connected to the plurality of upper contact plugs; and bonding the separated insulating film and the bonding substrate to allow the lower memory stack and the upper memory stack to face each other with the bonding substrate interposed therebetween. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Some example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 shows a plan view showing an integrated circuit device according to some example embodiments of the inventive concept including some of its main components;

[0013] Figure 2A A cross-sectional view taken along line A1-A1' and line A2-A2' is shown, as well as Figure 1 A cross-sectional view of a portion of a peripheral circuit region of an integrated circuit device shown in FIG. Figure 2B Shows Figure 1 A cross-sectional view of the integrated circuit device shown in FIG. 1 taken along line BB′;

[0014] FIG. 3A to FIG. 3D sectional views of gate dielectric films included in integrated circuit devices according to some example embodiments of the inventive concept are shown for explaining various structures of the gate dielectric films;

[0015] Figure 4 Shown for explanation Figure 1 , Figure 2A and Figure 2BA schematic block diagram of an example configuration of an integrated circuit device shown in FIG.

[0016] Figure 5 Shows the display Figure 2A A plan view of an example plan layout of multiple lower interconnect layers shown in FIG.

[0017] Figure 6 Shows the display Figure 2A A plan view of an example plan layout of multiple upper interconnect layers shown in FIG.

[0018] Figure 7 Shows the display Figure 2A A plan view of an example plan layout of multiple lower peripheral interconnect layers shown in FIG.

[0019] Figures 8 to 20 shows cross-sectional views of integrated circuit devices according to some example embodiments of the inventive concept;

[0020] FIG. 21A to FIG. 21J sectional views shown in order of processes for explaining a method of manufacturing an integrated circuit device according to some example embodiments of the inventive concept; and

[0021] Fig.22A and Fig. 22B Cross-sectional views shown according to process order are shown to explain a method of fabricating an integrated circuit device according to some example embodiments of the inventive concept. DETAILED DESCRIPTION

[0022] Figure 1 A plan view showing an integrated circuit device 100 according to some example embodiments of the inventive concept including some of its main components is illustrated. Figure 2A A cross-sectional view taken along line A1-A1', line A2-A2' and Figure 1 A cross-sectional view of a portion of a peripheral circuit region PERI of an integrated circuit device. Figure 2B Shown along Figure 1 A cross-sectional view taken along line BB'.

[0023] Reference Figure 1 , Figure 2A and Figure 2B , the integrated circuit device 100 includes a substrate 102 having a memory cell region MEC, a connection region CON, and a peripheral circuit region PERI. The substrate 102 may have a main surface 102M extending in a horizontal direction along an XY plane. The substrate 102 may include a semiconductor, such as (but not limited to) Si, Ge, and SiGe. The substrate 102 may be single crystal and / or may be doped (e.g., lightly doped) with boron. The memory cell array MCA may be formed on the active region AC of the memory cell region MEC.

[0024] The connection region CON may be disposed adjacent to an edge side of the memory cell region MEC. The memory cell region MEC may be spaced apart from the peripheral circuit region PERI with the connection region CON interposed therebetween. Figure 1 and Figure 2A It is shown that the connection region CON is located only on one side of the memory cell region MEC, but example embodiments are not limited thereto. For example, the connection region CON may be located on both sides of the memory cell region MEC in the first horizontal direction (X direction).

[0025] The lower memory stack STA may be located on the substrate 102. The lower memory stack STA may include a plurality of lower word lines WLA and a plurality of lower pad regions 112 connected to the lower word lines WLA (see FIG. Figure 2A ). The lower word lines WLA are located on the memory cell region MEC, extend in a horizontal direction parallel to the main surface 102M of the substrate 102, and overlap each other in a vertical direction (Z direction). For example, the lower word lines WLA may be stacked sequentially. The lower pad region 112 is located on the connection region CON and constitutes a stepped lower connection portion 110 or is included therein.

[0026] The upper memory stack STB is located on the lower memory stack STA. The upper memory stack STB includes a plurality of upper word lines WLB and a plurality of upper pad regions 122 (see FIG. Figure 2A ). The upper word lines WLB are located on the memory cell region MEC, extend in a horizontal direction parallel to the main surface 102M of the substrate 102, and overlap each other in the vertical direction (Z direction). For example, the upper word lines WLB may be stacked sequentially. A plurality of upper pad regions 122 are located on the connection region CON and constitute a stepped upper connection portion 120 or are included therein.

[0027] The lower memory stack STA may include 48, 64, or 98 lower word lines WLA, and the upper memory stack STB may include 48, 64, or 98 upper word lines WLB, but the lower memory stack STA and the upper memory stack STB are not limited thereto. In some example embodiments, the sum of the number of lower word lines WLA and the number of upper word lines WLB may be at least 192, and may be any number between 2 and 192 (including 2 and 192). In addition, in some example embodiments, the number of lower word lines WLA may be the same as or different from the number of upper word lines WLB.

[0028] The lower word line WLA and the upper word line WLB may include a plurality of word lines WL: WL1, WL2 to WLn-1 and WLn, at least one ground selection line GSL, and at least one string selection line SSL. Figure 2A and Figure 2B, the lower word line WLA and the upper word line WLB include two ground selection lines GSL and two string selection lines SSL. However, the inventive concept is not limited thereto. The number of the ground selection lines GSL may be the same as or different from the number of the string selection lines SSL.

[0029] In the horizontal direction, the area occupied by the lower memory stack STA may be larger than the area occupied by the upper memory stack STB. Figure 1 and Figure 2A As shown in FIG. 1 , at least a portion of the stepped lower connecting portion 110 may protrude farther from the memory cell region MEC than the stepped upper connecting portion 120 in the horizontal direction.

[0030] The plurality of word line cutting regions WLC may extend in a first horizontal direction (X direction) parallel to the main surface 102M of the substrate 102 (see FIG. 1 ). Figure 1 and Figure 2B The word line cutting region WLC may define a width of each of the lower word line WLA and the upper word line WLB in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction). The lower word line WLA and the upper word line WLB may be repeatedly spaced apart from each other at regular intervals by the word line cutting region WLC.

[0031] The substrate 102 may have (e.g., may include) a plurality of common source regions 106 extending along a first horizontal direction (X direction). In some example embodiments, the common source region 106 may be or may include an impurity region doped with a high concentration of n-type impurities. For example, the common source region 106 may be doped with a high concentration of phosphorus (P) and / or arsenic (As). The common source regions 106 may each serve as a source region for supplying current to a vertical memory cell. On the common source region 106, a plurality of common source lines CSL may extend along the first horizontal direction (X direction). The common source line CSL may fill a portion of the word line cutting region WLC on one side of each of the lower word line WLA and the upper word line WLB. Each of the common source lines CSL may include a lower common source line CSLA passing through the lower memory stack STA and an upper common source line CSLB passing through the upper memory stack STB (see Figure 2B). In the word line cutting area WLC, the lower common source line CSLA may be surrounded by the lower insulating spacer 192A, and the upper common source line CSLB may be surrounded by the upper insulating spacer 192B. The lower common source line CSLA and the lower insulating spacer 192A may constitute a lower word line cutting structure WCA passing through the lower memory stack STA or may be included therein, and the upper common source line CSLB and the upper insulating spacer 192B may constitute an upper word line cutting structure WCB passing through the upper memory stack STB. The lower surface of the upper word line cutting structure WCB may contact the upper surface of the lower word line cutting structure WCA. In the second horizontal direction (Y direction), the width of the lower surface of the upper word line cutting structure WCB may be less than the width of the upper surface of the lower word line cutting structure WCA. Either or both of the lower word line cutting structure WCB and the upper word line cutting structure WCB may be tapered in the vertical direction (Z direction).

[0032] In the second horizontal direction (Y direction), two adjacent string selection lines SSL may be spaced apart with the string selection line cutting region SSLC interposed therebetween (see FIG. Figure 2B ). The string selection line cut region SSLC may be filled with an insulating film 174. The insulating film 174 may include an oxide film, a nitride film, or a combination thereof. Alternatively or additionally, in some example embodiments, at least a portion of the string selection line cut region SSLC may be filled with an air gap.

[0033] The lower word line WLA and the upper word line WLB may each include a metal, a metal silicide, a semiconductor doped with impurities, or a combination thereof. For example, the lower word line WLA and the upper word line WLB may each include a metal (such as tungsten, nickel, cobalt, tantalum, etc.), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide, etc.), doped polysilicon, or a combination thereof. The lower word line WLA and the upper word line WLB may include the same material and / or may include different materials.

[0034] A pair of insulating films 156A and 156B may be located between the substrate 102 and the ground selection line GSL, between a pair of ground selection lines GSL, between word lines WL: WL1, WL2 to WLn-1, WLn, and between a pair of string selection lines SSL. The insulating films 156A and 156B may include an insulating film 156A constituting or included in the lower memory stack STA and an insulating film 156B constituting or included in the upper memory stack STB. In the insulating film 156A constituting the lower memory stack STA (or included therein), the insulating film closest to the substrate 102 may have a smaller thickness than other insulating films. In the insulating film 156B constituting the upper memory stack STB (or included therein), the insulating film farthest from the substrate 102 may cover the upper surface of one of the pair of string selection lines SSL that is farthest from the substrate 102. Each of the insulating films 156A and 156B may include silicon oxide, silicon nitride, and / or SiON. The insulating films 156A and 156B may include the same material and / or different materials.

[0035] The interlayer insulating film 130 and the separated insulating film 140 may be located between the lower memory stack STA and the upper memory stack STB. The interlayer insulating film 130 and the separated insulating film 140 may each include a silicon oxide film. The interlayer insulating film 130 and the separated insulating film 140 may include the same material and / or different materials.

[0036] In the memory cell region MEC, a plurality of channel structures 180 may extend in a vertical direction (Z direction) through the lower word line WLA, the interlayer insulating film 130, the separated insulating film 140, the upper word line WLB, and the insulating films 156A and 156B. The channel structures 180 may be spaced apart from each other at certain intervals along the X direction and the Y direction.

[0037] The channel structures 180 may each include a lower channel structure 180A passing through the lower word line WLA and an upper channel structure 180B passing through the upper word line WLB. The lower channel structure 180A and the upper channel structure 180B may each include a gate dielectric film 182, a channel region 184, a buried insulating film 186, and a drain region 188, respectively. The gate dielectric film 182, the channel region 184, the buried insulating film 186, and the drain region 188 in the lower channel structure 180A may each include materials that are the same and / or different from those of the gate dielectric film 182, the channel region 184, the buried insulating film 186, and the drain region in the upper channel structure 180B, respectively. The channel region 184 may include doped polysilicon and / or undoped polysilicon. The channel region 184 may have a cylindrical shape. The inner space of the channel region 184 may be filled with a buried insulating film 186. The buried insulating film 186 may include an insulating material. For example, the buried insulating film 186 may include silicon oxide, silicon nitride, SION, or a combination thereof. In some example embodiments, the buried insulating film 186 may be omitted, and in this case, the channel region 184 may have a column structure including an empty internal space. The drain region 188 may include doped polysilicon, a metal, a conductive metal nitride, or a combination thereof. Examples of metals that may constitute the drain region 188 include tungsten, nickel, cobalt, tantalum, and the like.

[0038] The drain regions 188 constituting the lower channel structure 180A or included therein are insulated from each other by the lower intermediate insulating film 187A, and the drain regions 188 constituting the upper channel structure 180B or included therein are insulated from each other by the upper intermediate insulating film 187B. The lower intermediate insulating film 187A and the upper intermediate insulating film 187B may each include an oxide film, a nitride film, or a combination thereof. The lower surface of the upper channel structure 180B may contact the upper surface of the lower channel structure 180A. In the horizontal direction (X direction and / or Y direction), the width of the lower surface of the upper channel structure 180B may be smaller than the width of the upper surface of the lower channel structure 180A.

[0039] Reference Figure 2A and Figure 2B , each of the lower channel structure 180A and the upper channel structure 180B includes a gate dielectric film 182, and the gate dielectric film 182 extends in a vertical direction (Z direction) along the channel region 184. However, the inventive concept is not limited thereto, and various modifications and changes may be made to the embodiments provided herein.

[0040] Figure 3A For detailed explanation Figure 2A and Figure 2B A cross-sectional view of the gate dielectric film 182 shown in FIG. Figure 2B Magnified view of the area indicated by "BX" in FIG.

[0041] Reference Figure 3AThe gate dielectric film 182 may have a structure including a tunnel dielectric film TD, a charge storage film CS, and a blocking dielectric film BD sequentially formed on the channel region 184. The relative thicknesses of the tunnel dielectric film TD, the charge storage film CS, and the blocking dielectric film BD are not limited to Figure 3A The relative thicknesses are shown in and may be modified differently.

[0042] The tunneling dielectric film TD may include at least one of silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage film CS may be or correspond to a region in which electrons having passed through the tunneling dielectric film TD from the charge storage film CS are stored, and may include at least one of silicon nitride, boron nitride, boron nitride, and doped polysilicon. The blocking dielectric film BD may include at least one of silicon oxide, silicon nitride, and metal oxide having a larger dielectric constant than silicon oxide. The metal oxide may include at least one of hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and a combination thereof.

[0043] FIG. 3B to FIG. 3D is shown as an alternative Figure 3A 180A, 182B, and 182C of the gate dielectric film 182. The gate dielectric film in the lower channel structure 180A may correspond to one of the gate dielectric films 182, 182A, 182B, and 182C, and the gate dielectric film in the upper channel structure 180B may correspond to one of the gate dielectric films 182, 182A, 182B, and 182C that is the same as or different from the lower channel structure 180A.

[0044] In some example embodiments, the integrated circuit device 100 may include Figure 3B The gate dielectric film 182A shown in FIG. 1 may replace the gate dielectric film 182, or may include, in addition to the gate dielectric film 182, Figure 3B The gate dielectric film 182A shown in FIG. The gate dielectric film 182A has Figure 3A 182A has a substantially same structure as that of the gate dielectric film 182 shown in . However, the gate dielectric film 182A includes a first blocking dielectric film BD1 and a second blocking dielectric film BD2 instead of the blocking dielectric film BD. The first blocking dielectric film BD1 may extend parallel to the channel region 184, and the second blocking dielectric film BD2 may surround the lower word line WLA. The first blocking dielectric film BD1 and the second blocking dielectric film BD2 may each include at least one of silicon oxide, silicon nitride, and metal oxide. For example, the first blocking dielectric film BD1 may include a silicon oxide film, and the second blocking dielectric film BD2 may include a metal oxide film having a larger dielectric constant than the silicon oxide film, and may not include a silicon oxide film.

[0045] In some example embodiments, the integrated circuit device 100 may include Figure 3C The gate dielectric film 182B shown in FIG. 1 may replace the gate dielectric film 182, or may include, in addition to the gate dielectric film 182, Figure 3C 182B. The gate dielectric film 182B may be formed to cover the surface of the lower word line WLA facing the channel region 184 and the surface of the lower word line WLA facing the insulating films 156A and 156B. The gate dielectric film 182B may include a tunneling dielectric film TD, a charge storage film CS, and a blocking dielectric film BD sequentially formed on the channel region 184.

[0046] In some example embodiments, the integrated circuit device 100 may include Figure 3D The gate dielectric film 182C shown in FIG. 1 may replace the gate dielectric film 182, or may include, in addition to the gate dielectric film 182, Figure 3D 182C. The gate dielectric film 182C may cover the sidewall of the lower word line WLA between the lower word line WLA and the channel region 184, and may not cover the lower surface and the upper surface of the lower word line WLA. The gate dielectric film 182C may include a tunneling dielectric film TD, a charge storage film CS, and a blocking dielectric film BD sequentially formed on the channel region 184 (e.g., conformally formed on the channel region 184).

[0047] The configuration and shape of the gate dielectric film included in the integrated circuit device according to some example embodiments of the inventive concept are not limited to FIG. 3A to FIG. 3D The gate dielectric films 182, 182A, 182B, and 182C shown in FIG. 1 are preferably configured as described above, and various changes and modifications may be made thereto within the scope of the inventive concept.

[0048] Reference Figure 1 , Figure 2A and Figure 2B , on the connection region CON, a width of the lower pad region 112 constituting the stepped lower connection portion 110 or included therein and a width of the upper pad region 122 constituting the stepped upper connection portion 120 or included therein may gradually decrease as they move away from the substrate 102 in a horizontal direction.

[0049] In some example embodiments, on the connection region CON, a plurality of dummy channel structures (not shown) may be located on the stepped lower connection portion 110 and the stepped upper connection portion 120. The dummy channel structures may support the lower and upper word lines WLA and WLB and edge portions of the lower and upper pad regions 112 and 122 to prevent or reduce the possibility of undesirable structural deformation such as bending and / or cracking.

[0050] On the memory cell area MEC, a plurality of bit lines BL may be arranged above the upper memory stack STB. A plurality of bit line contact pads 194 may be located between the channel structure 180 and the bit line BL. The drain region 188 of each upper channel structure 180B may be connected to a corresponding one of the bit lines BL through a corresponding bit line contact pad in the bit line contact pads 194. The bit line contact pads 194 may be insulated from each other by an insulating film 193. The bit lines BL may be insulated from each other by an upper interlayer insulating film 195. The bit line contact pads 194 and the bit line BL may each include a metal, a metal nitride, or a combination thereof. For example, the bit line contact pads 194 and the bit line BL may each include at least one of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, and a combination thereof. The bit line contact pads 194 and the bit line BL may include the same material and / or may include different materials. The insulating film 193 and the upper interlayer insulating film 195 may each include an oxide film, a nitride film, or a combination thereof. The insulating film 193 and the upper interlayer insulating film 195 may include the same material and / or different materials.

[0051] On the connection region CON, a lower insulating film 114 covering the stepped lower connection portion 110 is located between the substrate 102 and the lower intermediate insulating film 187A. The lower insulating film 114 may cover the lower pad region 112 and the insulating film 156A.

[0052] On the connection region CON, the upper insulating film 124 covering the stepped upper connection portion 120 is located between the separated insulating film 140 and the upper intermediate insulating film 187B. The upper insulating film 124 may cover the upper pad region 122 and the insulating film 156B. The lower insulating film 114 and the upper insulating film 124 may include the same material and / or different materials.

[0053] On the connection region CON, a plurality of lower contact plugs 116 may be connected to the stepped lower connection portion 110. The lower contact plugs 116 may extend upward from the lower pad region 112 through the lower insulating film 114 and the lower intermediate insulating film 187A away from the substrate 102 to a first vertical height LV1, wherein the first vertical height LV1 is higher than the lower memory stack STA and lower than the upper memory stack STB. The lower contact plug 116 connected to the lower pad region 112 farthest from the substrate 102 in the lower pad region 112 may extend from the lower pad region 112 through the insulating film 156A and the lower intermediate insulating film 187A to the first vertical height LV1. The term "level" used herein refers to a distance from the upper surface of the substrate 102 along a vertical direction (Z direction or -Z direction).

[0054] A plurality of lower interconnection layers MA may be formed on the lower contact plugs 116. The lower interconnection layers MA may be connected to the lower contact plugs 116 and may extend in a horizontal direction at a first vertical height LV1. The lower interconnection layers MA may be configured to be electrically connected to at least one of the lower word lines WLA through the lower contact plugs 116. On the connection region CON, the lower interconnection layers MA may be insulated from each other by an interlayer insulating film 130.

[0055] like Figure 2A As shown in FIG. 1 , the upper surface of each lower interconnect layer MA may be covered by a separate insulating film 140 so as not to contact other conductors. The separate insulating film 140 may extend continuously in the horizontal direction (X direction and / or Y direction) in a local area where the separate insulating film 140 and the lower interconnect layer MA are vertically overlapped.

[0056] On the connection region CON, a plurality of upper contact plugs 126 may be connected to the stepped upper connection portion 120. The upper contact plugs 126 may extend upward from the upper pad region 122 through the upper insulating film 124, the upper intermediate insulating film 187B, and the insulating film 193 away from the substrate 102 to a second vertical height LV2, wherein the second vertical height LV2 is higher than the upper memory stack STB. The upper contact plug 126 connected to the upper pad region 122 farthest from the substrate 102 in the upper pad region 122 may extend from the upper pad region 122 through the insulating film 156B, the upper intermediate insulating film 187B, and the insulating film 193 to the second vertical height LV2. The second vertical height LV2 may be located at a level higher than the level of the uppermost surface of the channel structure 180 passing through the upper memory stack STB. The lower surface of each upper contact plug 126 may be located at a level higher than the lower surface of the upper word line WLB closest to the lower memory stack STA in the upper word line WLB. All upper contact plugs 126 passing through the upper insulating film 124 may not pass through the separate insulating film 140 in the vertical direction (Z direction). None of the upper contact plugs 126 passing through the upper insulating film 124 is connected to one of the lower interconnection layers MA extending at the first vertical height LV1.

[0057] On the connection region CON, an upper interconnection layer MB may be formed on the upper contact plug 126. The upper interconnection layer MB may be connected to the upper contact plug 126 and may extend in the horizontal direction (X direction and / or Y direction) at the second vertical height LV2. The upper interconnection layer MB may be electrically connected to at least one upper word line WLB selected from the upper word lines WLB through the upper contact plug 126. The upper interconnection layer MB on the connection region CON may be located at the same level as the bit line BL on the memory cell region MEC. On the connection region CON, the upper interconnection layers MB may be insulated from each other by an upper interlayer insulating film 195.

[0058] Each of the lower contact plug 116 , the lower interconnection layer MA, the upper contact plug 126 , and the upper interconnection layer MB may include at least one of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, and combinations thereof.

[0059] like Figure 1 and Figure 2A , the lower interconnection layer MA may be formed on the lower contact plug 116 extending from a portion of the stepped lower connection portion 110 that protrudes in a direction in which the stepped lower connection portion 110 is farther from the memory cell region MEC in the horizontal direction than the stepped upper connection portion 120. Therefore, the lower interconnection layer MA may not include a portion vertically overlapping the upper memory stack STB.

[0060] like Figure 2A As shown in FIG. 1 , on the connection region CON, an interconnection structure for electrically connecting the lower interconnection layer MA and the upper interconnection layer MB to each other may not be arranged between the lower interconnection layer MA and the upper interconnection layer MB. In some example embodiments, the interconnection structure may not pass through the local region 124P of the upper insulating film 124 vertically overlapping the lower interconnection layer MA.

[0061] On the peripheral circuit region PERI, a plurality of circuits CT1 may be formed. The circuit CT1 may be formed at a level higher than or equal to the level of the substrate 102, and may include components such as a peripheral source / drain region PSD and / or a device isolation film 103 at a level lower than the upper surface of the substrate 102. Figure 4 The detailed configuration of the circuit CT1 is described.

[0062] On the peripheral circuit region PERI of the substrate 102, a device isolation film 103 defining a peripheral active region PAC may be formed. On the peripheral active region PAC, a peripheral transistor TR may be formed. The peripheral transistor TR may constitute a part of the circuit CT1 formed on the peripheral circuit region PERI or be included therein. The peripheral transistor TR may be electrically connected to the memory cell region MEC through an interconnect structure located on the connection region CON. The peripheral transistor TR may include a peripheral gate PG and a peripheral source / drain region PSD formed in the peripheral active region PAC on either side of the peripheral gate PG. The peripheral transistor TR may be of n-type, or alternatively, of p-type. In some example embodiments, unit devices such as resistors, capacitors, etc. may also be located on the peripheral circuit region PERI.

[0063] A plurality of lower peripheral contact plugs P116 may be located on the peripheral circuit region PERI. The lower peripheral contact plugs P116 may extend from the peripheral transistor TR in the vertical direction (Z direction) through the lower insulating film 114 to a first vertical height LV1. A plurality of lower peripheral interconnection layers PMA connected to the lower peripheral contact plugs P116 may be located on the lower peripheral contact plugs P116. The lower peripheral interconnection layers PMA may extend in the horizontal direction at the first vertical height LV1 (which is the same level as the level of the lower interconnection layer MA formed on the connection region CON). Each lower peripheral interconnection layer PMA may be connected to one of the peripheral gate PG and the peripheral source / drain region PSD through one of the lower peripheral contact plugs P116. At least one lower peripheral interconnection layer PMA may be configured to be connected to other circuits or interconnections located on the peripheral circuit region PERI. The lower peripheral interconnection layers PMA may be insulated from each other by the interlayer insulating film 130.

[0064] A plurality of upper peripheral contact plugs P126 connected to the lower peripheral interconnect layer PMA may be located on the lower peripheral interconnect layer PMA. The upper peripheral contact plugs P126 may extend from the lower peripheral interconnect layer PMA through the separated insulating film 140 and the upper insulating film 124 to a second vertical height LV2. Figure 2A , the lower peripheral interconnect layer PMA is shown as being connected to one of the upper peripheral contact plugs P126, but the inventive concept is not limited thereto. For example, at least some of the lower peripheral interconnect layers PMA may not be connected to the upper peripheral contact plugs P126. In some example embodiments, the lower peripheral interconnect layer PMA may be omitted. Figure 2A At least some of the upper peripheral contact plugs P126 shown in FIG.

[0065] A plurality of upper peripheral interconnection layers PMB connected to the upper peripheral contact plugs P126 may be located on the upper peripheral contact plugs P126. The upper peripheral interconnection layers PMB may extend in the horizontal direction at a second vertical height LV2 (which is the same level as the level of the upper interconnection layers MB formed on the connection region CON). Each or at least some of the upper peripheral interconnection layers PMB may be configured to be connected to other circuits or interconnections located on the peripheral circuit region PERI. The upper peripheral interconnection layers PMB may be insulated from each other by an upper interlayer insulating film 195.

[0066] Each of the lower peripheral contact plug P116, the lower peripheral interconnection layer PMA, the upper peripheral contact plug P126, and the upper peripheral interconnection layer PMB may include at least one of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, and combinations thereof. The lower peripheral contact plug P116, the lower peripheral interconnection layer PMA, the upper peripheral contact plug P126, and the upper peripheral interconnection layer PMB may include the same material and / or different materials.

[0067] Figure 4 Shown for explanation Figure 1 , Figure 2A and Figure 2B A schematic block diagram of an example configuration of an integrated circuit device 100 is shown in FIG.

[0068] Reference Figure 4 The peripheral circuit region PERI of the integrated circuit device 100 includes a circuit CT1 ( Figure 2A Each circuit CT1 may include at least one of a row decoder 20 , a page buffer 30 , a column decoder 40 , and a control circuit 50 .

[0069] The memory cell area MEC may include a plurality of memory blocks BLK. Each memory block BLK may include a plurality of memory cells. The memory cells included in the memory cell area MEC may include Figure 1 , Figure 2A and Figure 2B The memory cells may be configured to be electrically connected to the row decoder 20 through the lower word lines WLA, the upper word lines WLB, the lower contact plugs 116, the lower interconnection layer MA, the upper contact plugs 126, and the upper interconnection layer MB, and may be configured to be electrically connected to the page buffer 30 and the column decoder 40 through the bit lines BL.

[0070] The row decoder 20 may be commonly connected to the memory block BLK, and may provide a driving signal (such as a driving voltage) to a plurality of word lines WL: WL1, WL2 to WLn-1, WLn (see Figure 2A and Figure 2B For example, the row decoder 20 receives address information ADDR from the outside and decodes the received address information ADDR to determine the address information supplied to the lower word line WLA and the upper word line WLB electrically connected to the memory block BLK (see Figure 2A and Figure 2B ) are selected from at least some of the voltages.

[0071] The page buffer 30 may be configured to be electrically connected to the memory cell area MEC through the bit line BL. The page buffer 30 may be connected to the bit line BL selected according to the address decoded by the column decoder 40. According to the operation mode, the page buffer 30 may temporarily store data to be stored in the memory cells included in the memory cell area MEC, or sense data stored in the memory cells. In some example embodiments, the page buffer 30 may operate as a write driver circuit in a program operation mode, and operate as a sense amplifier circuit in a read operation mode. The page buffer 30 may receive a signal including at least one of power, voltage, and current from the control logic, and provide the received signal to the selected bit line BL.

[0072] The column decoder 40 may provide a data transmission path between the page buffer 30 and an external device such as a memory controller. The column decoder 40 may decode an externally provided input address to select one of the bit lines BL. The column decoder 40 may be commonly connected to the memory block BLK, and may provide data information to the bit line BL of the memory block selected according to the block selection signal.

[0073] The control circuit 50 may control the overall operation of the integrated circuit device 100. The control circuit 50 receives a control signal and an external voltage, and may operate according to the received control signal. The control circuit 50 may include a voltage generator that generates a voltage for internal operation (such as a program voltage, a read voltage, an erase voltage, etc.) by using an external voltage. The control circuit 50 may control read, write, and / or erase operations in response to the control signal.

[0074] Figure 5 Shows the display Figure 2A A plan view of an example plan layout of the lower interconnect layer MA is shown in FIG.

[0075] Reference Figure 2A and Figure 5 , the lower interconnection layer MA may extend over the connection area CON and the peripheral circuit area PERI. On the connection area CON, some of the lower interconnection layers MA may include: a first horizontal extension portion MA11 extending in a first direction from an upper surface of the lower contact plug 116 at a first vertical height LV1; a second horizontal extension portion MA12 extending in a second direction different from the first direction from the first horizontal extension portion MA11 at a first vertical height LV1; and a bent portion MA13 located between the first horizontal extension portion MA11 and the second horizontal extension portion MA12. In some example embodiments, the first horizontal extension portion MA11 may extend in the second horizontal direction (Y direction), and the second horizontal extension portion MA12 may extend in the first horizontal direction (X direction), but the inventive concept is not limited thereto. Some of the lower interconnection layers MA may not include a bent portion, and may, for example, extend in a straight line shape only in the first direction or the second direction. In addition, although the bent portion MA13 is shown as a right angle between the first direction and the second direction, the inventive concept is not limited thereto.

[0076] In some example embodiments, the lower interconnection layer MA may be constructed to be electrically connected to an interconnection structure (not shown) constituting or included in the circuit CT1 located on the peripheral circuit area PERI. For example, the lower interconnection layers MA may each include: a first local portion P1 connected to the lower contact plug 116 on the connection area CON; and a second local portion P2 connected to the peripheral contact PCA included in some circuits selected from the circuit CT1 located on the peripheral circuit area PERI. The lower interconnection layer MA may be connected to the lower word line WLA on the memory cell area MEC through the lower contact plug 116, and connected to the circuit CT1 located on the peripheral circuit area PERI through a plurality of peripheral contacts PCA (see Figure 2A ). In some example embodiments, the circuit CT1 connected to the peripheral contact PCA may be selected from the combined Figure 4 The row decoder 20 , the page buffer 30 , the column decoder 40 , and the control circuit 50 are described, but are not limited thereto.

[0077] Figure 6 Shows the display Figure 2A A plan view of an example plan layout of an upper interconnect layer MB is shown in FIG.

[0078] Reference Figure 2A and Figure 6 , the upper interconnection layer MB may extend over the connection region CON and the peripheral circuit region PERI. On the connection region CON, some of the upper interconnection layers MB may include: a first horizontal extension portion MB11 extending in a first direction from the upper surface of the upper contact plug 126 at a second vertical height LV2; a second horizontal extension portion MB12 extending in a second direction different from the first direction from the first horizontal extension portion MB11 at a second vertical height LV2; and a bent portion MB13 located between the first horizontal extension portion MB11 and the second horizontal extension portion MB12. In some example embodiments, the first horizontal extension portion MB11 may extend in the second horizontal direction (Y direction), and the second horizontal extension portion MB12 may extend in the first horizontal direction (X direction), but the inventive concept is not limited thereto. Some of the upper interconnection layers MB may not include a bent portion, and may extend in a straight line shape in the first direction or the second direction. In addition, although the bent portion MB13 is shown as a right angle between the first direction and the second direction, the inventive concept is not limited thereto.

[0079] In some example embodiments, the upper interconnection layer MB may be an interconnection structure (not shown) configured to be electrically connected to the circuit CT1 located on the peripheral circuit region PERI. For example, the upper interconnection layers MB may each include: a first local portion Q1 connected to the upper contact plug 126 on the connection region CON; and a second local portion Q2 connected to the circuit CT1 located on the peripheral circuit region PERI (see FIG. Figure 2A ) in some circuits selected in the peripheral contact PCB. The upper interconnect layer MB can be connected to the upper word line WLB on the memory cell area MEC through the upper contact plug 126, and is connected to the circuit CT1 located on the peripheral circuit area PERI through a plurality of peripheral contacts PCB (see Figure 2A ). In some example embodiments, the circuit CT1 connected to the peripheral contact PCB may be selected from the already combined Figure 4 The row decoder 20 , the page buffer 30 , the column decoder 40 , and the control circuit 50 are described, but are not limited thereto.

[0080] Figure 7 Shows the display Figure 2A A plan view of an example plan layout of a lower peripheral interconnect layer PMA is shown in FIG.

[0081] Reference Figure 2A and Figure 7 , the lower peripheral interconnect layer PMA may extend in a first horizontal direction (X direction) and a second horizontal direction (Y direction) at a first vertical height LV1 on the peripheral circuit area PERI. The lower peripheral interconnect layers PMA may each include a first horizontal extension portion PMA1, a second horizontal extension portion PMA2, ​​and a bent portion PMA3 located therebetween. The first horizontal extension portion PMA1 may extend in the second horizontal direction (Y direction), and the second horizontal extension portion PMA2 may extend in the first horizontal direction (X direction), but the inventive concept is not limited thereto. In some example embodiments, each lower peripheral interconnect layer PMA may be configured to be electrically connected to a circuit CT1 (see FIG. 1 ) located on the peripheral circuit area PERI. Figure 2A ) of at least two interconnect structures (not shown) of different circuits selected from the lower peripheral interconnect layer PMA. For example, each lower peripheral interconnect layer PMA may include: a first local portion R1 connected to the lower peripheral contact plug P116 on the peripheral circuit area PERI; and a second local portion R2 connected to the circuit CT1 (see FIG. 1 ) included in the lower peripheral contact plug P116 located on the peripheral circuit area PERI; Figure 2A ) in some selected circuits. The lower peripheral interconnect layer PMA can be connected to the circuit CT1 located on the peripheral circuit region PERI through the lower peripheral contact plug P116 (see Figure 2A ) and is connected to circuit CT1 (see Figure 2A) in any other circuit different from the above-mentioned circuit. In some example embodiments, the circuit CT1 to which the lower peripheral contact plug P116 and the peripheral contact PCC are connected can be selected from the combined Figure 4 The row decoder 20 , the page buffer 30 , the column decoder 40 , and the control circuit 50 are described, but are not limited thereto.

[0082] Figure 8 A cross-sectional view of an integrated circuit device 200 according to an embodiment of the inventive concept is shown. Figure 8 shows that along with Figure 1 The structure of a portion of the cross section corresponding to the section taken along the line A1-A1' Figure 1 The structure of a portion corresponding to the cross section taken along the line A2-A2' and the Figure 1 The cross section of the peripheral circuit region PERI corresponds to a portion of the structure.

[0083] Reference Figure 8 , the integrated circuit device 200 and the reference Figures 1 to 7 The described integrated circuit device 100 has substantially the same configuration. The difference between the integrated circuit device 200 and the integrated circuit device 100 is that the integrated circuit device 200 includes a plurality of lower interconnection layers MA2 connected to the lower contact plugs 116 and extending in the horizontal direction at a first vertical height LV1.

[0084] The lower interconnection layer MA2 includes a first lower interconnection layer MA21 connected to one lower contact plug selected from the lower contact plugs 116 , and a second lower interconnection layer MA22 connected to some of the lower contact plugs 116 . Figure 8 An example embodiment is shown in which the second lower interconnect layer MA22 is connected to two lower contact plugs 116. However, the inventive concept is not limited thereto. For example, the second lower interconnect layer MA22 may be connected to three or more lower contact plugs 116. In some example embodiments, two or more lower word lines selected from the lower word lines WLA may be connected to one second lower interconnect layer MA22 through two or more lower contact plugs 116. At least one lower word line selected from the lower word lines WLA connected to the second lower interconnect layer MA22 may be a dummy word line that does not perform a normal function of a memory cell substantially formed on the memory cell area MEC. For example, during operation of the memory cell area MEC, the dummy word line may be electrically isolated and / or may be electrically floating. Detailed construction of the lower interconnect layer MA22 and reference Figure 2A and Figure 5 The detailed configuration described for the lower interconnect layer MA is substantially the same.

[0085] As combined Figure 5As in the lower interconnection layer MA described above, each lower interconnection layer MA2 may extend over the connection area CON and the peripheral circuit area PERI, and may include: a first local portion connected to the lower contact plug 116 on the connection area CON; and a second local portion connected to the circuit CT1 located on the peripheral circuit area PERI (see Figure 2A ) selected from some circuits. At least some of the lower interconnect layers MA2 may include shapes similar to Figure 5 The shape of the bent portion MA13 shown in FIG.

[0086] Fig. 9 A cross-sectional view of an integrated circuit device 300 according to some example embodiments of the inventive concepts is shown. Fig. 9 Shown along with Figure 1 The structure of a portion of the cross section corresponding to the line A1-A1' taken along Figure 1 The structure of a portion corresponding to the cross section taken along the line A2-A2' and Figure 1 A cross section of a portion of the peripheral circuit region PERI corresponds to a portion of the structure.

[0087] Reference Fig. 9 , the integrated circuit device 300 and the reference Figures 1 to 7 The described integrated circuit device 100 has substantially the same construction. The difference between the integrated circuit device 300 and the integrated circuit device 100 is that the integrated circuit device 300 includes a plurality of upper interconnection layers MB3 extending in the horizontal direction at the second vertical height LV2 on the connection region CON.

[0088] The upper interconnection layer MB3 may include: a plurality of first upper interconnection layers MB31 configured to be electrically connected to at least one upper word line selected from the upper word lines WLB; and at least one second upper interconnection layer MB32 configured to be electrically connected to at least one lower word line selected from the lower word lines WLA. Fig. 9 An example embodiment in which the upper interconnection layer MB3 includes two second upper interconnection layers MB32 is shown, but the inventive concept is not limited thereto. The upper interconnection layer MB3 may include one or at least three upper interconnection layers MB32.

[0089] The first upper interconnection layer MB31 may be configured to be electrically connected to the upper word line WLB through a plurality of first upper contact plugs 326. At least one upper interconnection layer MB32 may be configured to be electrically connected to the lower word line WLA through at least one second upper contact plug 336. Details and combinations of the first upper contact plug 326 and the second upper contact plug 336 Figure 2AThe details of the upper contact plug 126 described above are substantially the same. The difference between the first upper contact plug 326 and the second upper contact plug 336 and the upper contact plug 126 is that the second upper contact plug 336 may extend in the vertical direction (Z direction) through the lower intermediate insulating film 187A, the interlayer insulating film 130, the separated insulating film 140, the upper insulating film 124, the upper intermediate insulating film 187B, and the insulating film 193.

[0090] As combined Figure 6 As with the upper interconnection layers MB described above, each upper interconnection layer MB3 may extend over the connection region CON and the peripheral circuit region PERI, and may include: a first partial portion connected to the first upper contact plug 326 or the second upper contact plug 336 over the connection region CON; and a second partial portion connected to the circuit CT1 (see FIG. Figure 2A At least some of the upper interconnect layers MB3 may include a bent portion having a horizontal direction with respect to Figure 6 The shape of the bent portion MB13 shown in FIG.

[0091] Each of the upper interconnection layers MB3 may be insulated from each other by the upper interlayer insulating film 195. The second upper contact plug 336 may be spaced apart from the lower interconnection layer MA in a horizontal direction with the interlayer insulating film 130 interposed therebetween.

[0092] Fig.10 A cross-sectional view of an integrated circuit device 400 according to some example embodiments of the inventive concepts is shown.

[0093] Reference Fig.10 , the integrated circuit device 400 and the reference Figures 1 to 7 The described integrated circuit device 100 has substantially the same construction. The difference between the integrated circuit device 400 and the integrated circuit device 100 is that the integrated circuit device 400 includes an upper memory stack STB4 located on the lower memory stack STA. In a horizontal direction parallel to the main surface 102M of the substrate 102, the area occupied by the upper memory stack STB4 may be substantially the same as the area occupied by the lower memory stack STA.

[0094] The upper memory stack STB4 may include an upper word line WLB located on the memory cell region MEC and a stepped upper connection portion 420 located on the connection region CON and connected to the upper word line WLB. The stepped upper connection portion 420 may include a plurality of upper pad regions 422.

[0095] The upper memory stack STB4 may include a portion vertically overlapping at least a portion of the lower interconnect layer MA. At least a portion of the stepped upper connection portion 420 of the upper memory stack STB4 may be located between the lower interconnect layer MA and the upper interconnect layer MB. At least one of the lower interconnect layers MA may vertically overlap with the upper memory stack STB4. At least a portion of the stepped lower connection portion 110 may be located between the substrate 102 and the stepped upper connection portion 420, and at least one of the lower interconnect layers MA may vertically overlap with the stepped upper connection portion 420.

[0096] A portion of the separated insulating film 140 covering the lower interconnection layer MA may fill a space between the lower interconnection layer MA and the stepped upper connection portion 420 .

[0097] Detailed structure and combination of upper memory stack STB4 Figure 1 , Figure 2A and Figure 2B The detailed construction described on the memory stack STB is basically the same.

[0098] Fig.11 A cross-sectional view of an integrated circuit device 500 according to some example embodiments of the inventive concepts is shown.

[0099] Reference Fig.11 , the integrated circuit device 500 and the reference Figures 1 to 7 The described integrated circuit device 100 has a substantially same configuration. The difference between the integrated circuit device 500 and the integrated circuit device 100 is that the integrated circuit device 500 includes an upper memory stack STB5 located on the lower memory stack STA. In a horizontal direction parallel to the main surface 102M of the substrate 102, the area occupied by the upper memory stack STB5 may be smaller than the area occupied by the lower memory stack STA.

[0100] The upper memory stack STB5 may include an upper word line WLB located on the memory cell region MEC and a stepped upper connection portion 520 located on the connection region CON and connected to the upper word line WLB. The stepped upper connection portion 520 may include a plurality of upper pad regions 522 .

[0101] The upper memory stack STB5 may include a portion vertically overlapping at least a portion of the lower interconnect layer MA. At least a portion of the stepped upper connection portion 520 of the upper memory stack STB5 may be located between the lower interconnect layer MA and the upper interconnect layer MB. At least one of the lower interconnect layers MA may vertically overlap the upper memory stack STB5. At least a portion of the stepped lower connection portion 110 may be located between the substrate 102 and the stepped upper connection portion 520, and at least one of the lower interconnect layers MA may vertically overlap the stepped upper connection portion 520.

[0102] A portion of the separated insulating film 140 covering the lower interconnection layer MA may fill a space between the lower interconnection layer MA and the stepped upper connection portion 520 .

[0103] Detailed structure and combination of upper memory stack STB5 Figure 1 , Figure 2A and Figure 2B The detailed construction described on the memory stack STB is basically the same.

[0104] Fig.12 A cross-sectional view of an integrated circuit device 600 according to some example embodiments of the inventive concepts is shown.

[0105] Reference Fig.12 , the integrated circuit device 600 and the reference Figures 1 to 7 The described integrated circuit device 100 has a substantially same configuration. The difference between the integrated circuit device 600 and the integrated circuit device 100 is that the integrated circuit device 600 includes an upper memory stack STB6 located on the lower memory stack STA. In the horizontal direction (X direction and / or Y direction) parallel to the main surface 102M of the substrate 102, the area occupied by the upper memory stack STB6 may be larger than the area occupied by the lower memory stack STA.

[0106] The upper memory stack STB6 may include an upper word line WLB located on the memory cell region MEC and a stepped upper connection portion 620 located on the connection region CON and connected to the upper word line WLB. The stepped upper connection portion 620 may include a plurality of upper pad regions 622. In the horizontal direction, at least a portion of the stepped upper connection portion 620 may protrude further from the memory cell region MEC than the stepped lower connection portion 110.

[0107] The upper memory stack STB6 may include a portion vertically overlapped with the lower interconnect layer MA. In some example embodiments, at least a portion of the stepped upper connection portion 620 of the upper memory stack STB6 may be located between the lower interconnect layer MA and the upper interconnect layer MB. In some example embodiments, the upper interconnect layer MB may be positioned farther from the memory cell region MEC in the horizontal direction than an end of the stepped lower connection portion 110.

[0108] At least one of the lower interconnection layers MA may vertically overlap the upper memory stack STB 6 . The stepped lower connection portion 110 may be located between the substrate 102 and the stepped upper connection portion 620 , and the lower interconnection layer MA may vertically overlap the stepped upper connection portion 620 .

[0109] A portion of the separated insulating film 140 covering the lower interconnection layer MA may fill a space between the lower interconnection layer MA and the stepped upper connection portion 620 .

[0110] Detailed structure and combination of upper memory stack STB6 Figure 1 , Figure 2A and Figure 2B The detailed construction described on the memory stack STB is basically the same.

[0111] Fig.13 A cross-sectional view of an integrated circuit device 700 according to some example embodiments of the inventive concepts is shown.

[0112] Reference Fig.13 , the integrated circuit device 700 is similar to the reference Figures 1 to 7 The described integrated circuit device 100 has substantially the same configuration. The difference between the integrated circuit device 700 and the integrated circuit device 100 is that the integrated circuit device 700 includes a peripheral circuit region PERI7 formed at a level lower than that of the substrate 102 and a plurality of lower interconnection layers MA7 extending in a horizontal direction at a first vertical height LV1 on the connection region CON.

[0113] Memory cell area MEC (see Figure 2A and Figure 2B ) and the connection region CON may vertically overlap the peripheral circuit region PERI7.

[0114] The peripheral circuit area PERI7 may include a peripheral circuit board 702 located below the substrate 102 and a plurality of circuits CT2 located between the peripheral circuit board 702 and the substrate 102. Figure 2A and Figure 2B The detailed structure of the substrate 102 described above is basically the same.

[0115] In the peripheral circuit board 702, a peripheral circuit active area PAC7 may be defined by a device isolation film 704. A plurality of transistors TR7 may be formed on the peripheral circuit active area PAC7. The transistors TR7 may each include a peripheral gate PG7 and a peripheral source / drain area PSD7 formed in the peripheral active area PAC7 on either side of the peripheral gate PG7. In some example embodiments, unit devices such as resistors, capacitors, etc. may also be located on the peripheral circuit area PERI7. A peripheral interlayer insulating film 710 may be formed on the transistors TR7. The peripheral interlayer insulating film 710 may include silicon oxide, SiON, SiOCN, etc.

[0116] The peripheral circuit region PERI7 may include a plurality of peripheral circuit interconnect layers 708 and a plurality of peripheral circuit contacts 709. Some of the peripheral circuit interconnect layers 708 may be configured to be electrically connected to the transistor TR7. The peripheral circuit contacts 709 may be configured to interconnect some of the peripheral circuit interconnect layers selected from the peripheral circuit interconnect layers 708. The peripheral circuit interconnect layers 708 and the peripheral circuit contacts 709 may be covered by a peripheral interlayer insulating film 710. Some of the peripheral circuit interconnect layers 708 may face the lower memory stack STA, with the substrate 102 interposed therebetween.

[0117] The peripheral circuit interconnect layer 708 and the peripheral circuit contact 709 may each include a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, the peripheral circuit interconnect layer 708 and the peripheral circuit contact 709 may each include a conductive material such as at least one of tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, nickel silicide, etc. Fig.13 , the peripheral circuit interconnection layer 708 is arranged in the vertical direction (Z direction) to constitute a three-layer interconnection structure or is included therein. However, the present invention is not limited to Fig.13 For example, the peripheral circuit interconnect layer 708 may have a two-layer or four-layer or more-layer interconnect structure.

[0118] The lower interconnection layer MA7 located on the connection region CON may include: at least one first lower interconnection layer MA71 configured to be electrically connected to at least one lower word line selected from the lower word lines WLA; at least one second lower interconnection layer MA72 configured to be electrically connected to at least one peripheral circuit interconnection layer selected from the peripheral circuit interconnection layers 708 included in the peripheral circuit region PERI7; and a third lower interconnection layer MA73 connected between the lower word line WLA and the peripheral circuit interconnection layer 708. The lower interconnection layer MA7 may extend in a horizontal direction at a first vertical height LV1 between the lower memory stack STA and the upper memory stack STB.

[0119] In the integrated circuit device 700, the interconnection structure located on the connection region CON may be configured to be electrically connected to the peripheral circuit interconnection layer 708 located on the peripheral circuit region PERI7 through at least one connection plug PP7 extending in the vertical direction (Z direction). In some example embodiments, on the connection region CON, at least some of the lower interconnection layers MA7 and at least some of the upper interconnection layers MB may be configured to be electrically connected to the peripheral circuit interconnection layer 708 located on the peripheral circuit region PERI7 through at least one connection plug PP7. In some example embodiments, on the connection region CON, at least some of the lower interconnection layers MA7 and at least some of the upper interconnection layers MB may be configured to be electrically connected to a unit device such as a resistor, a capacitor, etc. located on the peripheral circuit region PERI7 through at least one connection plug PP7.

[0120] In the integrated circuit device 700, a plurality of through-holes 102H may be formed in the substrate 102. At least one landing plug PP7 may extend from one peripheral circuit interconnection layer selected from the peripheral circuit interconnection layers 708 through the substrate 102 to outside the substrate 102. The through-holes 102H may be filled with a substrate-buried insulating film 712. The substrate-buried insulating film 712 may include a silicon oxide film.

[0121] The connection plug PP7 may include a lower peripheral interconnection layer PMA7 at a first vertical height LV1, which is the same level as that of the lower interconnection layer MA7, and an upper peripheral interconnection layer PMB7 at a second vertical height LV2, which is the same level as that of the upper interconnection layer MB.

[0122] The connection plug PP7 may further include a lower peripheral contact plug P716. The lower peripheral contact plug P716 may extend from one peripheral circuit interconnect layer selected from the peripheral circuit interconnect layer 708 to the lower peripheral interconnect layer PMA7 in the vertical direction (Z direction) through the peripheral interlayer insulating film 710 and the substrate-buried insulating film 712. The lower peripheral contact plug P716 may pass through the substrate 102 via the through hole 102H and may be surrounded by the substrate-buried insulating film 712 in the through hole 102H.

[0123] The connection plug PP7 may further include an upper peripheral contact plug P726. The upper peripheral contact plug P726 may extend from the lower peripheral interconnection layer PMA7 to the upper peripheral interconnection layer PMB7 through the separated insulating film 140, the upper insulating film 124, the upper intermediate insulating film 187B, and the insulating film 193 in the vertical direction (Z direction).

[0124] As combined Figure 7 As described above, the lower peripheral interconnection layer PMA7 may extend in the first horizontal direction (X direction) and the second horizontal direction (Y direction) at the first vertical height LV1. In some example embodiments, the lower peripheral interconnection layer PMA7 may include a partial portion connected to at least one lower interconnection layer selected from the lower interconnection layer MA7 at the first vertical height LV1. In this case, if necessary, the upper peripheral contact plug P726 may be omitted from the connection plug PP7. The lower peripheral interconnection layer PMA7 may be insulated from the lower interconnection layer MA7 by the interlayer insulating film 130.

[0125] As combined Figure 7As described above with respect to the lower peripheral interconnection layer PMA, the upper peripheral interconnection layer PMB7 may extend in the first horizontal direction (X direction) and the second horizontal direction (Y direction) at the second vertical height LV2. In some example embodiments, the upper peripheral interconnection layer PMB7 may include a partial portion connected to at least one upper interconnection layer selected from the upper interconnection layers MB at the second vertical height LV2. The upper peripheral interconnection layer PMB7 may be insulated from the upper interconnection layer MB by the upper interlayer insulating film 195.

[0126] The lower peripheral interconnection layer PMA7, the upper peripheral interconnection layer PMB7, the lower peripheral contact plug P716, and the upper peripheral contact plug P726 constituting the connection plug PP7 may each include tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

[0127] In the integrated circuit device 700, the lower memory stack STA may have a lower memory stack through hole SAH passing through the lower memory stack STA. The lower memory stack through hole SAH may be filled by a stack filling insulating film 714. The stack filling insulating film 714 may extend through the lower word line WLA in the vertical direction (Z direction). The stack buried insulating film 714 may include a silicon oxide film.

[0128] The integrated circuit device 700 may further include at least one through contact plug P718 extending to the peripheral circuit interconnect layer 708 through the lower memory stack STA and the substrate 102 in the vertical direction (Z direction). The second lower interconnect layer MA72 and the third lower interconnect layer MA73 may each contact the upper surface of the through contact plug P718. The third lower interconnect layer MA73 may include a portion connected to the through contact plug P718 and a portion connected to the lower contact plug 116. The third lower interconnect layer MA73 may extend in the horizontal direction at a first vertical height LV1 between the lower memory stack STA and the upper memory stack STB.

[0129] The through contact plug P718 may pass through the lower memory stack STA through the lower memory stack through hole SAH and may be surrounded by the stack-buried insulation film 714 in the lower memory stack through hole SAH. The stack-buried insulation film 714 may vertically overlap the upper memory stack STB.

[0130] Fig.14 A cross-sectional view of an integrated circuit device 800 according to some example embodiments of the inventive concepts is shown. Fig.14 Shown along with Figure 1 The structure of a portion of the cross section corresponding to the line A1-A1' taken along Figure 1 The structure of a portion corresponding to the cross section taken along the line A2-A2' and Figure 1A cross section of a portion of the peripheral circuit region PERI corresponds to a portion of the structure.

[0131] Reference Fig.14 , the integrated circuit device 800 and the reference Figures 1 to 7 The integrated circuit device 100 described has substantially the same construction. The difference between the integrated circuit device 800 and the integrated circuit device 100 is that the integrated circuit device 800 includes a plurality of channel structures 880 instead of the channel structures 180 .

[0132] The channel structure 880 may be Figure 2A and Figure 2B 1 has substantially the same configuration. The difference between the channel structure 880 and the channel structure 180 is that in the channel structure 880, the gate dielectric film 182, the channel region 184, and the buried insulating film 186 extend in the vertical direction (Z direction) through the lower word line WLA, the interlayer insulating film 130, the separated insulating film 140, the upper word line WLB, and the insulating films 156A and 156B, and the drain region 188 is located only on the uppermost portion of the channel structure 880. Each channel structure 880 may not include a drain region 188 located horizontally between the lower memory stack STA and the upper memory stack STB.

[0133] In the channel structure 880, a portion passing through the lower memory stack STA and a portion passing through the upper memory stack STB may each have a horizontal width that increases as they are away from the substrate 102. In the channel structure 880, the horizontal width of the channel structure 880 surrounding a portion between the lower memory stack STA and the upper memory stack STB (for example, an interface between the lower intermediate insulating film 187A and the uppermost insulating film among the insulating films 156A of the lower memory stack STA) may change relatively greatly.

[0134] Fig.15 A cross-sectional view of an integrated circuit device 900 according to some example embodiments of the inventive concepts is shown. Fig.15 Shown along with Figure 1 The structure of a portion of the cross section corresponding to the line A1-A1' taken along Figure 1 The structure of a portion corresponding to the cross section taken along the line A2-A2' and Figure 1 A cross section of a portion of the peripheral circuit region PERI corresponds to a portion of the structure.

[0135] Reference Fig.15 , the integrated circuit device 900 is similar to the reference Figures 1 to 7The described integrated circuit device 100 has a substantially same configuration. The difference between the integrated circuit device 900 and the integrated circuit device 100 is that the integrated circuit device 900 further includes a bonding substrate 902 between the lower memory stack STA and the upper memory stack STB. The bonding layer BDL may be located between the bottom surface 902B of the bonding substrate 902 and the separated insulating film 140. The upper base insulating film 940 may be located between the upper surface 902T of the bonding substrate 902 and the upper memory stack STB.

[0136] The bonding substrate 902 may have a bonding Figure 2A and Figure 2B The substrate 102 of the present invention may be constructed in a substantially similar manner to that described above. The bonding layer BDL may include at least one of silicon oxide, silicon nitride, SiCN, SiC, a polymer, and a combination thereof. The polymer may include at least one of polyimide, polyamide, polyacrylate, polyaramide, and a combination thereof. The upper base insulating film 940 may include a silicon oxide film.

[0137] The lower memory stack STA and the upper memory stack STB may be spaced apart from each other with the bonding substrate 902 and the bonding layer BDL interposed therebetween. The lower interconnection layer MA and the upper interconnection layer MB may be spaced apart from each other with the bonding substrate 902 and the bonding layer BDL interposed therebetween.

[0138] On the memory cell region MEC, a plurality of contact pads 194C connected to the drain region 188 of the lower channel structure 180A and a plurality of conductive lines 990 connected to the contact pads 194C may be formed on the lower channel structure 180A. The contact pads 194C may be formed at the same level (i.e., the first vertical height LV1) as the lower interconnect layer MA. The contact pads 194C may pass through the interlayer insulating film 130 and may contact the upper surface of the drain region 188 of the lower channel structure 180A. The conductive line 990 may pass through the separated insulating film 140 and may contact the upper surface of the contact pads 194C. Figure 1 , Figure 2A and Figure 2B 94C, the conductive line 990 may extend in the Y direction, just like the bit line BL shown in FIG. 1 . In some example embodiments, the contact pad 194C may be configured to be electrically connected to the bit line BL through the conductive line 990. The contact pad 194C and the conductive line 990 may each include a metal, a metal nitride, or a combination thereof. For example, the contact pad 194C and the conductive line 990 may each include at least one of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, and a combination thereof. The contact pad 194C and the conductive line 990 may include the same material and / or may include different materials.

[0139] On the peripheral circuit region PERI, a plurality of circuits CT3 may be formed. The circuit CT3 may include a peripheral transistor TR, a lower peripheral contact plug P116, a lower peripheral interconnection layer PMA, an upper peripheral contact plug P126, and an upper peripheral interconnection layer PMB. The upper peripheral contact plug P126 may extend in the vertical direction (Z direction) through a through hole 902H passing through the bonding substrate 902. The through hole 902H may be filled with a buried insulating film 912. The upper peripheral contact plug P126 may be surrounded by the buried insulating film 912 in the through hole 902H. The lower peripheral interconnection layer PMA and the upper peripheral interconnection layer PMB may be spaced apart from each other, and the bonding substrate 902 and the bonding layer BDL may be interposed therebetween.

[0140] In some example embodiments, the circuit CT3 formed on the peripheral circuit region PERI may not include an upper peripheral contact plug P126 passing through the bonding substrate 902 and the bonding layer BDL.

[0141] Fig.16 A cross-sectional view of an integrated circuit device 1100 according to some example embodiments of the inventive concepts is shown. Fig.16 Shown along with Figure 1 The structure of a portion corresponding to the cross section taken along the line A2-A2' and Figure 1 A cross section of a portion of the peripheral circuit region PERI corresponds to a portion of the structure.

[0142] Reference Fig.16 , the integrated circuit device 1100 is similar to the reference Figures 1 to 7 The integrated circuit device 100 described above has substantially the same configuration. The difference between the integrated circuit device 1100 and the integrated circuit device 100 is that the integrated circuit device 1100 includes a plurality of circuits CT11 formed on the peripheral circuit region PERI. The circuit CT11 may include a plurality of unit devices UD formed on the substrate 102. In some example embodiments, the unit device UD may be at least one of a transistor, a resistor, and a capacitor. In some example embodiments, the unit device UD may constitute a device selected from a plurality of transistors, resistors, and capacitors. Figure 4 One of the described row decoder 20 , page buffer 30 , column decoder 40 , and control circuit 50 may be included therein.

[0143] The lower peripheral contact plug P116 may be connected to the unit devices UD. In some example embodiments, at least one of the unit devices UD may be Figure 2A , and a portion of the unit device UD to which the lower peripheral contact plug P116 is connected may be a peripheral gate PG of the peripheral transistor TR. However, the inventive concept is not limited thereto.

[0144] The lower peripheral interconnection layer PMA11 may be formed on the lower peripheral contact plug P116. The lower peripheral contact plug P116 may be connected to one lower peripheral interconnection layer PMA11. Fig.16 An embodiment in which two lower peripheral contact plugs P116 are connected to one lower peripheral interconnection layer PMA11 is illustrated, but the inventive concept is not limited thereto. In some example embodiments, three or more lower peripheral contact plugs P116 may be connected to one lower peripheral interconnection layer PMA11.

[0145] At least one of the lower interconnection layers MA formed on the connection region CON may include a lower interconnection layer MA111 integrally extending from the connection region CON to the peripheral circuit region PERI. The lower interconnection layer MA111 may include a portion connected to the lower contact plug 116 on the connection region CON and a portion connected to the lower peripheral contact plug P116 on the peripheral circuit region PERI. The lower peripheral interconnection layer PMA11 and the lower interconnection layer MA111 may each extend in a horizontal direction at a first vertical height LV1.

[0146] The upper peripheral contact plug P126 may be formed on the lower interconnection layer MA111 and the lower peripheral interconnection layer PMA11. The upper peripheral contact plug P126 may include an upper peripheral contact plug P126 connected to the lower peripheral interconnection layer PMA11 and an upper peripheral contact plug P126 connected to the lower interconnection layer MA111. A plurality of upper peripheral interconnection layers PMB11 connected to the upper peripheral contact plug P126 may be located on the upper peripheral contact plug P126. The upper peripheral interconnection layer PMB11 may extend in the horizontal direction at a second vertical height LV2 (which is the same level as that of the upper interconnection layer MB formed on the connection region CON). Each upper peripheral interconnection layer PMB11 may be configured to be connected to other circuits or interconnections located on the peripheral circuit region PERI. The upper peripheral interconnection layers PMB11 may be insulated from each other by an upper interlayer insulating film 195.

[0147] The lower peripheral interconnection layer PMA11, the lower interconnection layer MA111, and the upper peripheral interconnection layer PMB11 may each include at least one of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, and combinations thereof. The lower peripheral interconnection layer PMA11, the lower interconnection layer MA111, and the upper peripheral interconnection layer PMB11 may include the same material and / or different materials.

[0148] Fig.17 A cross-sectional view of an integrated circuit device 1200 according to some example embodiments of the inventive concepts is shown. Fig.17 Shown along with Figure 1 The structure of a portion corresponding to the cross section taken along the line A2-A2' and Figure 1 A cross section of a portion of the peripheral circuit region PERI corresponds to a portion of the structure.

[0149] Reference Fig.17 , the integrated circuit device 1200 and the reference Fig.16 The integrated circuit device 1100 described above has substantially the same configuration. The difference between the integrated circuit device 1200 and the integrated circuit device 1100 is that in the integrated circuit device 1200, a plurality of lower peripheral contact plugs P116 on the peripheral circuit region PERI may be connected to one lower peripheral contact plug P116 of the peripheral active region PAC. In some example embodiments, at least one of the unit devices UD may be Figure 2A , and a portion of the peripheral active region PAC to which the lower peripheral contact plug P116 is connected may be a peripheral source / drain region PSD of the peripheral transistor TR. However, the inventive concept is not limited thereto.

[0150] At least one of the upper interconnection layers MB formed on the connection region CON may include an upper interconnection layer MB122 integrally extending from the connection region CON to the peripheral circuit region PERI. The upper interconnection layer MB122 may include a portion connected to the upper contact plug 126 on the connection region CON and a portion connected to the upper peripheral contact plug P126 on the peripheral circuit region PERI. The upper interconnection layer MB122 may extend in the horizontal direction at a second vertical height LV2.

[0151] Fig.18 A cross-sectional view of an integrated circuit device 1300 according to some example embodiments of the inventive concepts is shown.

[0152] Reference Fig.18 , the integrated circuit device 1300 and the reference Fig.13The described integrated circuit device 700 has substantially the same construction. The difference between the integrated circuit device 1300 and the integrated circuit device 700 is that the integrated circuit device 1300 includes a plurality of lower interconnection layers MA13 instead of the lower interconnection layer MA7. The lower interconnection layer MA13 may extend in the horizontal direction at a first vertical height LV1 between the lower memory stack STA and the upper memory stack STB. The lower interconnection layer MA13 may include: at least one first lower interconnection layer MA71 configured to be electrically connected to at least one lower word line selected from the lower word lines WLA; a second lower interconnection layer MA132 configured to be electrically connected to at least one peripheral circuit interconnection layer 708 selected from the peripheral circuit interconnection layers 708 included in the peripheral circuit area PERI7; and a third lower interconnection layer MA73 connected between the lower word line WLA and the peripheral circuit interconnection layer 708. The second lower interconnection layer MA132 may extend in the horizontal direction to be connected to a plurality of through contact plugs P718. The through contact plug P718 connected to the one second lower interconnection layer MA132 may be a different unit device selected from the circuit CT2 included in the peripheral circuit area PERI7, for example, a different transistor, resistor, or capacitor. Fig.18 An embodiment in which two through contact plugs P718 are connected to one second lower interconnection layer MA132 is illustrated, but the inventive concept is not limited thereto. In some example embodiments, three or more through contact plugs P718 may be connected to one second lower interconnection layer MA132.

[0153] Fig.19 A cross-sectional view of an integrated circuit device 1400 according to some example embodiments of the inventive concepts is shown.

[0154] Reference Fig.19 , the integrated circuit device 1400 is similar to the reference Figures 1 to 7 The integrated circuit device 100 described above has substantially the same structure. The difference between the integrated circuit device 1400 and the integrated circuit device 700 is that: Fig.13 Like the integrated circuit device 700 described above, the integrated circuit device 1400 may include a peripheral circuit region PERI7 formed at a level lower than that of the substrate 102. The memory cell region MEC (see Figure 2A and Figure 2B ) and the connection region CON may vertically overlap the peripheral circuit region PERI7.

[0155] In the integrated circuit device 1400 , the interconnection structure on the connection region CON may be configured to be electrically connected to the peripheral circuit interconnection layer 708 on the peripheral circuit region PERI7 through at least one connection plug PP14 extending in the vertical direction (Z direction).

[0156] The connection plug PP14 may extend from one peripheral circuit interconnection layer selected from the peripheral circuit interconnection layers 708 through the substrate 102 to outside the substrate 102 .

[0157] The connection plug PP14 may include a lower peripheral interconnection layer PMA14 located at a first vertical height LV1 (which is the same level as that of the lower interconnection layer MA) and an upper peripheral interconnection layer PMB14 located at a second vertical height LV2 (which is the same level as that of the upper interconnection layer MB). The connection plug PP14 may also include a lower peripheral contact plug P116. The lower peripheral contact plugs P116 may each extend from one peripheral circuit interconnection layer selected from the peripheral circuit interconnection layer 708 in the vertical direction (Z direction) through the peripheral interlayer insulating film 710 and the substrate-buried insulating film 712 to the lower peripheral interconnection layer PMA14. The lower peripheral contact plugs P116 may pass through the substrate 102 via the through hole 102H and may be surrounded by the substrate-buried insulating film 712 in the through hole 102H.

[0158] The lower peripheral contact plug P116 may be connected to a lower peripheral interconnection layer PMA14 . Fig.19 An embodiment in which two lower peripheral contact plugs P116 are connected to one lower peripheral interconnection layer PMA14 is illustrated, but the inventive concept is not limited thereto. In some example embodiments, three or more lower peripheral contact plugs P116 may be connected to one lower peripheral interconnection layer PMA14.

[0159] The connection plug PP14 may further include an upper peripheral contact plug P126. The upper peripheral contact plug P126 may extend from the lower peripheral interconnection layer PMA14 to the upper peripheral interconnection layer PMB14 through the separated insulating film 140, the upper insulating film 124, the upper intermediate insulating film 187B, and the insulating film 193 in the vertical direction (Z direction).

[0160] Combined with Figure 7 Like the lower peripheral interconnect layer PMA described above, the lower peripheral interconnect layer PMA14 may extend in the first horizontal direction (X direction) and the second horizontal direction (Y direction) at a first vertical height LV1. The upper peripheral interconnect layer PMB14 may extend in the first horizontal direction (X direction) and the second horizontal direction (Y direction) at a second vertical height LV2. The lower peripheral interconnect layer PMA14 and the upper peripheral interconnect layer PMB14 may each include at least one of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, and combinations thereof. The lower peripheral interconnect layer PMA14 and the upper peripheral interconnect layer PMB14 may include the same material and / or may include different materials.

[0161] Fig. 20 A cross-sectional view of an integrated circuit device 1500 according to some example embodiments of the inventive concepts is shown.

[0162] Reference Fig. 20 , the integrated circuit device 1500 and the reference Fig.19 The integrated circuit device 1400 described has substantially the same configuration. The difference between the integrated circuit device 1500 and the integrated circuit device 1400 is that in the integrated circuit device 1500, the peripheral circuit interconnection layer 708 located on the peripheral circuit area PERI7 may include a peripheral circuit interconnection layer 708A having a lower surface contacting the peripheral circuit contact 709, and one lower peripheral contact plug P116 selected from the lower peripheral contact plugs P116 constituting the connection plug PP14 may extend in the vertical direction to interconnect the peripheral circuit interconnection layer 708A and the lower peripheral interconnection layer PMA14 between them.

[0163] The inventive concepts are not limited to the example embodiments described in the integrated circuit devices 100, 200, 300, 400, 500, 600, 700, 800, 900, 1100, 1200, 1300, 1400, and 1500. For example, the integrated circuit devices 100, 200, 300, 400, 500, 600, 700, 800, 900, 1100, 1200, 1300, 1400, and 1500 are not exclusive of each other, and the integrated circuit devices according to some example embodiments may include features from a plurality of the integrated circuit devices 100, 200, 300, 400, 500, 600, 700, 800, 900, 1100, 1200, 1300, 1400, and 1500.

[0164] According to reference Figures 1 to 20The described integrated circuit devices 100, 200, 300, 400, 500, 670, 700, 800, 900, 1100, 1200, 1300, 1400, and 1500, even when the number of word lines WL: WL1, WL2 to WLn-1 and WLn included in the lower word lines WLA and the upper word lines WLB is increased in order to increase the integration of the integrated circuit device, and the number of contact plugs and the number of interconnection layers connected to the lower word lines WLA and the upper word lines WLB is increased, because the plurality of lower contact plugs and the plurality of lower interconnection layers connected to the lower word lines WLA and the plurality of upper contact plugs and the plurality of upper interconnection layers connected to the upper word lines WLB are arranged at different vertical heights, the plurality of contact plugs and the plurality of interconnection layers connected to the lower word lines WLA and the upper word lines WLB can be effectively arranged, and the area occupied by the desired number of the plurality of contact plugs and the plurality of interconnection layers can be reduced, and therefore, the area of ​​the chip can be reduced. The reduction in chip area can lead to an improvement in manufacturing yield. In detail, since the multiple lower contact plugs and the multiple lower interconnection layers connected to the lower memory stack STA are arranged at a lower level than the upper memory stacks STB, STB4, STB5 and STB6, the area occupied by the step-shaped connection portions of each of the multiple memory stacks vertically spaced apart from each other is reduced, thereby helping to reduce the chip size and / or improve the manufacturing yield.

[0165] FIG. 21A to FIG. 21J The cross-sectional views are shown in order of process sequence for explaining a method of manufacturing an integrated circuit device according to some example embodiments of the present invention. In the example embodiment, as an example, the manufacturing Figure 1 , Figure 2A and Figure 2B The method of the integrated circuit device 100 is shown in FIG.

[0166] Reference Fig.21A , an active region AC is defined in the memory cell region MEC of the substrate 102 , and a peripheral active region PAC is defined in the peripheral circuit region PERI. The peripheral active region PAC may be defined by a device isolation film 103 .

[0167] A plurality of insulating films 156A and a plurality of sacrificial films PL are alternately stacked one by one on the memory cell region MEC and the connection region CON of the substrate 102, and a peripheral transistor TR is formed on the peripheral circuit region PERI of the substrate 102. The plurality of insulating films 156A and the plurality of sacrificial films PL may be formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process; however, the inventive concept is not limited thereto. The peripheral active region PAC may be formed using a CMOS integration process such as a planar CMOS integration process; however, the inventive concept is not limited thereto.

[0168] The sacrificial film PL may include at least one of silicon nitride, silicon carbide, and polysilicon. The sacrificial film PL may secure a space for forming the lower word line WLA in various subsequent processes.

[0169] Reference Fig.21B , a portion of each of the insulating film 156A and the sacrificial film PL is removed so that the insulating film 156A and the sacrificial film PL form a lower step-shaped structure STP1, and then a lower insulating film 114 covering the lower step-shaped structure STP1 and the peripheral transistor TR is formed on the substrate 102. The portion of each of the insulating film 156A and the sacrificial film PL may be removed using an etching process such as a reactive ion etching (RIE) process; however, the inventive concept is not limited thereto. The lower insulating film 114 may be formed using a CVD process such as a plasma enhanced CVD (PECVD) process and / or a low pressure CVD (LPCVD) process; however, the inventive concept is not limited thereto.

[0170] Then, on the memory cell region MEC, a plurality of lower channel holes 180H1 extending through the insulating film 156A and the sacrificial film PL in the vertical direction (Z direction) are formed, and a gate dielectric film 182, a channel region 184, and a buried insulating film 186 are formed in each of the lower channel holes 180H1 to form a plurality of lower channel hole filling structures. The plurality of lower channel holes 180H1 may be formed using an etching process. The gate dielectric film 182 may be formed using a CVD process or an ALD process.

[0171] Then, on the memory cell region MEC, the connection region CON, and the peripheral circuit region PERI, a lower intermediate insulating film 187A covering the lower channel hole filling structure, the lower stepped structure STP1, and the lower insulating film 114 is formed, and a plurality of contact holes 187AH are formed in the lower intermediate insulating film 187A to expose the upper surface of the lower channel hole filling structure, and a plurality of drain regions 188 are formed inside the contact holes 187AH. The lower intermediate insulating film 187A may be formed to have a planarized upper surface above the memory cell region MEC, the connection region CON, and the peripheral circuit region PERI. The lower intermediate insulating film 187A may be deposited using a CVD process, and the lower intermediate insulating film 187A may be planarized using a chemical mechanical planarization (CMP) process and / or an etch-back process; however, the inventive concept is not limited thereto.

[0172] Reference Fig. 21C For example, a reactive ion etching (RIE) process is used to form a through-insulating film 156A and a sacrificial film PL (see Fig.21B ) and expose the word line cutting region WLC (see Figure 1 and Figure 2B), then, impurity ions such as at least one of boron ions, arsenic ions, phosphorus ions, and carbon ions are implanted into the substrate 102 through the word line cutting region WLC to form a common source region 106 (see Figure 2B ), and the sacrificial film PL is replaced by the lower word line WLA (see Fig.21B ).

[0173] In some example embodiments, in order to replace the sacrificial film PL with the lower word line WLA (see Fig.21B ), selectively remove the sacrificial film PL exposed by the word line cutting region WLC (see Fig.21B ) to provide a space between adjacent films selected from the insulating film 156A, and then, fill the space with a conductive material to form a lower word line WLA. In this case, the lower word line WLA can be formed by using a metal material such as at least one of tungsten, tantalum, cobalt, nickel, etc.

[0174] In some example embodiments, when the sacrificial film PL includes polysilicon, a silicidation process is performed on the sacrificial film PL to replace the sacrificial film PL with the lower word line WLA (see FIG. 1 ). Fig.21B ). In this case, the lower word lines WLA may each include at least one of tungsten silicide, tantalum silicide, cobalt silicide, and nickel silicide.

[0175] Afterwards, in the word line cutting area WLC (see Figure 1 and Figure 2B ) to form a lower word line cutting structure WCA. The lower insulating spacer 192A may include at least one of silicon oxide, silicon nitride, SiON, SiOCN, SiCN, and combinations thereof. The lower common source line CSLA may include: a metal (such as at least one of tungsten, copper, and aluminum); a conductive metal nitride (such as at least one of titanium nitride, tantalum nitride, etc.); a transition metal (such as at least one of titanium, tantalum, etc.); or a combination thereof. In some example embodiments, a metal silicide film (not shown) may be located between the common source region 106 and the lower common source line CSLA to reduce the contact resistance therebetween. The metal silicide film may include cobalt silicide, but is not limited thereto. In some example embodiments, when the common source line (not shown) is buried in the substrate 102, the word line cutting region WLC may be filled with only an insulator, and the process for forming the lower common source line CSLA may be omitted.

[0176] By using the step-like structure STP1 (see Fig.21B ) by replacing the sacrificial film PL with the lower word line WLA in FIG. 1 , a lower memory stack STA including a stepped lower connection portion 110 located on the connection region CON can be obtained.

[0177] Reference Fig.21D, by using a mask pattern (not shown) as an etching mask, the lower intermediate insulating film 187A and the lower insulating film 114 are anisotropically etched (for example, anisotropically etched by an RIE process) on the connection region CON and the peripheral circuit region PERI to form a plurality of lower contact holes H11 exposing the lower pad region 112 on the connection region CON, and a plurality of peripheral lower contact holes H12 exposing the peripheral gate PG and the peripheral source / drain region PSD on the peripheral circuit region PERI. The lower contact holes H11 and the peripheral lower contact holes H12 may be formed simultaneously. With regard to the formation of the lower contact holes H11 and the peripheral lower contact holes H12, after the lower memory stack STA is formed and before the upper memory stack STB is formed (see Figure 2A ), an etching process such as an RIE process for forming the lower contact hole H11 and the peripheral lower contact hole H12 is performed. Figure 2A ) is performed after the etching process for forming a plurality of contact holes for exposing the lower pad area 112, the lower contact hole H11 and the peripheral lower contact hole H12 may be formed to have a relatively small aspect ratio. For example, the difference in aspect ratios between different lower contact holes H11 may be reduced, and the range therein may be reduced. Therefore, the process difficulty may be reduced. During the formation of the lower contact hole H11, some portions of the lower word line WLA exposed to the lower surface of the lower contact hole H11 may be over-etched, resulting in the formation of a recess R on the upper surface of each of the lower word lines WLA corresponding to the lower contact hole H11. In some cases, the recess R may not be formed on the upper surface of each of the plurality of lower word lines WLA. Similarly, on the peripheral circuit region PERI, a recess (not shown) may be formed on some portions of the upper surfaces of the peripheral gate PG and the peripheral source / drain region PSD corresponding to the peripheral lower contact hole H12, or a recess (not shown) may not be formed on some portions of the upper surfaces of the peripheral gate PG and the peripheral source / drain region PSD corresponding to the peripheral lower contact hole H12.

[0178] Reference Fig.21E , fill the lower contact hole H11 and the peripheral lower contact hole H12 with a conductive material to form a lower contact plug 116 and a lower peripheral contact plug P116. The lower contact plug 116 and the lower peripheral contact plug P116 may be formed simultaneously or at different times. The lower contact plug 116 and the lower peripheral contact plug P116 may be formed using a CVD process and / or using a physical vapor deposition (PVD) process such as a sputtering process. A planarization process such as a CMP process may be included in the formation of the lower contact plug 116 and the lower peripheral contact plug P116.

[0179] Reference Fig.21F ,exist Fig.21EOn the resultant, for example, an interlayer insulating film 130 is formed using a CVD process, and a portion of the interlayer insulating film 130 is etched to form a plurality of interconnection holes 130H that expose the lower contact plugs 116 and the lower peripheral contact plugs P116, and then the interconnection holes 130H are filled with a conductive material to form a lower interconnection layer MA and a lower peripheral interconnection layer PMA. The interconnection holes 130H may be filled by a CVD process and / or a PVD process. A planarization process such as a CMP process may be included in the formation of the lower interconnection layer MA and the lower peripheral interconnection layer PMA.

[0180] Reference Figure 21G ,exist Fig.21F On the resultant, a separate insulating film 140 is formed (for example, formed using a CVD process) to cover the lower interconnection layer MA and the lower peripheral interconnection layer PMA.

[0181] Reference Fig.21H ,exist Figure 21G On the resultant, sacrificial films PL and insulating films 156B are alternately stacked one by one, and then, a portion of each of the sacrificial films PL and the insulating films 156B is removed so that the sacrificial films PL and the insulating films 156B form an upper stepped structure STP2. Then, an upper insulating film 124 is formed to cover the upper stepped structure STP2 and the separated insulating film 140 on the connection region CON and the separated insulating film 140 on the peripheral circuit region PERI.

[0182] On the memory cell region MEC, a plurality of upper channel holes 180H2 extending through the insulating film 156B, the sacrificial film PL, the separated insulating film 140, and the interlayer insulating film 130 in the vertical direction (Z direction) are formed. Also, a gate dielectric film 182, a channel region 184, and a buried insulating film 186 are formed in each of the upper channel holes 180H2 to form a plurality of upper channel hole filling structures. The method for forming the sacrificial film PL, the upper insulating film 156B, the gate dielectric film 182, the channel region 184, and the buried insulating film 186 may be the same as that described above with reference to Fig.21B The processes described for forming the sacrificial film PL, the lower insulating film 156A, the gate dielectric film 182, the channel region 184, and the buried insulating film 186 are the same or similar.

[0183] After that, follow the combination with Fig.21B The same or similar method as described for forming the lower intermediate insulating film 187A and the drain region 188 is used to form the upper intermediate insulating film 187B and the drain region 188 that contacts the upper channel hole filling structure through the upper intermediate insulating film 187B to form the upper channel structure 180B.

[0184] Reference Fig.21I , a layer of insulating film 156B and sacrificial film PL (see FIG. Fig.21H ) to expose the word line cutting region WLC of the lower word line cutting structure WCA (see Figure 1 and Figure 2B ), then, according to the combination with Fig. 21C The sacrificial film PL (see Fig.21H ) is replaced by the upper word line WLB through the word line cutting area WLC. Then, according to the combination with Fig. 21C The upper insulating spacer 192B and the upper common source line CSLB are formed on the lower word line cutting structure WCA to form an upper word line cutting structure WCB (see Figure 2B ). The material used to form the upper insulating spacer 192B and the upper common source line CSLB may be combined with Fig. 21C The lower insulating spacer 192A and the lower common source line CSLA may be made of the same or substantially the same material as described above.

[0185] Then, an insulating film 193 is formed to cover the drain region 188 and the upper intermediate insulating film 187B, and a bit line contact pad 194, an upper contact plug 126, and an upper peripheral contact plug P126 are formed.

[0186] In some example embodiments, the Fig.21D and Fig.21E The lower contact plug 116 and the upper peripheral contact plug P126 are formed by a method similar to the method for forming the lower contact plug 116 and the lower peripheral contact plug P116. In some example embodiments, before forming the bit line contact pad 194, the lower portion of each of the upper contact plug 126 and the upper peripheral contact plug P126 is formed, and then the upper portion of each of the upper contact plug 126 and the upper peripheral contact plug P126 and the bit line contact pad 194 may be formed simultaneously.

[0187] Reference Fig.21J , forming a covering layer on the memory cell area MEC, the connection area CON and the peripheral circuit area PERI Fig.21I The resultant upper interlayer insulating film 195 is formed, and then, the bit lines BL, the upper interconnection layer MB, and the upper peripheral interconnection layer PMB passing through some portions of the upper interlayer insulating film 195 are formed.

[0188] Already referred to FIG. 21A to FIG. 21J Describes the manufacturing Figure 1 , Figure 2A and Figure 2B However, those skilled in the art will appreciate that various changes and modifications may be made within the scope of the inventive concept to produce Figures 8 to 20The integrated circuit devices 200, 300, 400, 500, 600, 700, 800, 900, 1100, 1200, 1300, 1400 and 1500 shown in the drawings and the integrated circuit devices having various structures to which various changes and modifications are made within the concept of the present invention.

[0189] For example, in order to form Fig.13 The integrated circuit device 700 shown in FIG. 7 may form a peripheral circuit region PERI7, on which a circuit CT2 is formed on a peripheral circuit board 702. The circuit CT2 may include at least one of a transistor TR7, a peripheral circuit interconnection layer 708, and a peripheral circuit contact 709. The transistor TR7, the peripheral circuit interconnection layer 708, and the peripheral circuit contact 709 may be covered by a peripheral interlayer insulating film 710.

[0190] A substrate 102 is formed on the peripheral circuit region PERI7, and then a through hole 102H is formed on the substrate 102, and then the through hole 102H is filled with a substrate buried insulating film 712. Then, according to the combination with FIG. 21A to FIG. 21E In a method similar to the method described above, a lower memory stack STA including a stepped lower connection portion 110 is formed on the memory cell region MEC and the connection region CON of the substrate 102, and a lower memory stack through hole SAH is formed passing through the lower memory stack STA, and then, the lower memory stack through hole SAH can be filled by the stack buried insulating film 714. Then, at least one through contact plug P718, a lower contact plug 116, and a lower peripheral contact plug P716 can be formed simultaneously. At least one through contact plug P718 can be formed to be connected to the peripheral circuit interconnect layer 708 through the stack buried insulating film 714, the substrate buried insulating film 712, and the peripheral interlayer insulating film 710. The lower peripheral contact plug P716 can be formed to be connected to the peripheral circuit interconnect layer 708 through the lower insulating film 114, the substrate buried insulating film 712, and the peripheral interlayer insulating film 710.

[0191] An interlayer insulating film 130 may be formed on the resultant in which at least one through contact plug P718, the lower contact plug 116, and the lower peripheral contact plug P716 are formed. Thereafter, a lower interconnection layer MA7 and a lower peripheral interconnection layer PMA7 each passing through the interlayer insulating film 130 may be simultaneously formed. Next, the memory cell region MEC and the connection region CON of the substrate 102 may be subjected to the same process as described with reference to FIG. FIG. 21G to FIG. 21J Here, the upper peripheral contact plug P726 and the upper contact plug 126 may be formed at the same time, and the upper peripheral interconnection layer PMB7 and the upper interconnection layer MB may be formed at the same time.

[0192] Fig.22A and Fig. 22BThe cross-sectional views are shown in order of process sequence for explaining a method of manufacturing an integrated circuit device according to some exemplary embodiments of the present invention. In this embodiment, as an example, the manufacturing Fig.14 The method of the integrated circuit device 800 is shown in FIG.

[0193] Reference Fig.22A , an active area AC is defined on the memory cell area MEC of the substrate 102, and a peripheral active area PAC is defined on the peripheral circuit area PERI, then, a lower memory stack STA including a stepped lower connection portion 110 is formed on the connection area CON of the substrate 102, and a peripheral transistor TR is formed on the peripheral circuit area PERI, and a lower insulating film 114 covering the lower memory stack STA and the peripheral transistor TR can be formed.

[0194] On the memory cell region MEC, a plurality of lower channel holes 880H1 passing through the lower memory stack STA are formed, and the lower channel holes 880H1 may be filled with a sacrificial layer 880F. In some example embodiments, the sacrificial layer 880F may include silicon oxide, but is not limited thereto. In some example embodiments, the lower word line WLA constituting the lower memory stack STA or included therein may include a metal silicide film. In order to form such a structure, after the lower channel hole 880H1 is formed and before the lower channel hole 880H1 is filled with the sacrificial layer 880F, a silicidation process for forming a metal silicide film may be additionally performed.

[0195] Reference Fig. 22B ,exist Fig.22A After forming the lower intermediate insulating film 187A on the resultant, the FIG. 21D to FIG. 21F The lower contact plug 116, the lower peripheral contact plug P116, the lower interconnection layer MA and the lower peripheral interconnection layer PMA are formed by a method similar to the method described above. Figure 21G In a similar manner to the described method, a separate insulating film 140 covering the lower interconnection layer MA and the lower peripheral interconnection layer PMA may be formed.

[0196] Then, on the separated insulating film 140, an upper memory stack STB including a stepped upper connection portion 120 and an upper insulating film 124 covering the stepped upper connection portion 120 may be formed. On the memory cell region MEC, a plurality of upper channel holes 880H2 passing through the upper memory stack STB, the separated insulating film 140, the interlayer insulating film 130, and the lower intermediate insulating film 187A are formed, and the sacrificial layer 880F is removed through the upper channel holes 180H2 to form a plurality of channel holes 880H including lower channel holes 880H1 and upper channel holes 880H2. The horizontal width of each of the lower channel holes 880H1 and the upper channel holes 880H2 may increase as it is further away from the substrate 102. The horizontal width of the lowermost portion of each of the upper channel holes 880H2 may be smaller than the horizontal width of the lowermost portion of each of the lower channel holes 880H1.

[0197] A gate dielectric film 182, a channel region 184, and a buried insulating film 186 are formed in each of the channel holes 880H, and bonding may be performed thereon. FIG. 21H to FIG. 21J Describe the process to manufacture Fig.14 The integrated circuit device 800 is shown in FIG.

[0198] Executable and Reference FIG. 21A to FIG. 21J The process described is similar to the process to manufacture Fig.15 900 shown in FIG. 1 . For example, a lower structure including a lower memory stack STA, a lower contact plug 116, and a lower interconnect layer MA may be formed on the substrate 102. To form the lower structure, the reference FIG. 21A to FIG. 21E After the described process, the Fig.21F The interlayer insulating film 130 and the lower interconnection layer MA and the lower peripheral interconnection layer PMA passing through the interlayer insulating film 130 are formed by the method described in the foregoing. Therefore, during the formation of the lower interconnection layer MA and the lower peripheral interconnection layer PMA, a contact pad 194C passing through the interlayer insulating film 130 may be formed on the memory cell region MEC. Then, the contact pad 194C may be formed by using the same method as in reference 1. Figure 21G A separate insulating film 140 covering the contact pad 194C is formed in a method similar to the described method, and then a conductive line 990 passing through the separate insulating film 140 may be formed on the memory cell region MEC.

[0199] Alternatively or additionally, a through hole 902H is formed on the bonding substrate 902 and the through hole 902H is filled with a buried insulating film 912, and then an upper structure including an upper memory stack STB may be formed on the upper bonding substrate 902. In order to form the upper structure, after forming an upper base insulating film 940 on the bonding substrate 902, a reference may be performed on the resultant in which the upper base insulating film 940 is formed. FIG. 21H to FIG. 21JIn this case, however, before forming the bit line contact pad 194, the upper contact plug 126, and the upper peripheral contact plug P126, the lower structure on the substrate 102 may be bonded on the bonding substrate 902 by using the bonding layer BDL. After the bit line contact pad 194, the upper contact plug 126, and the upper peripheral contact plug P126 are formed on the resultant of bonding the lower structure on the bonding substrate 902, bonding is performed thereon. Fig.21J Describe the process to complete Fig.15 8. The fabrication of the integrated circuit device 900 is shown in FIG.

[0200] In some example embodiments, a process for forming an upper peripheral contact plug P126 passing through the bonding substrate 902 and the bonding layer BDL on the peripheral circuit region PERI may be omitted. In this case, a process for bonding an upper structure formed on the substrate 102 on the bonding substrate 902 by using the bonding layer BDL may be performed after forming the upper interconnection layer MB.

[0201] According to reference FIG. 21A to FIG. 22B According to the method of manufacturing an integrated circuit device conceived according to the present invention, since the lower memory stack STA and the upper memory stack STB are separated in the vertical direction, and the contact plugs and interconnections connected to the lower memory stack STA and the contact plugs and interconnections connected to the upper memory stack STB are formed at multiple different vertical heights, even if the number of lower word lines WLA and the number of upper word lines WLB are increased to manufacture a highly integrated vertical memory device, a suitable aspect ratio and / or a suitable range of heights of the lower contact plug 116 and / or a suitable range of heights of the upper contact plug 126 can be maintained during the etching process for forming the contact hole, thereby not increasing the process difficulty, and the process for forming the contact plug and the process for forming the interconnection can be performed in a simple and / or effective method. Alternatively or additionally, the possibility of problems caused by the collapse of the lower word line WLA and the upper word line WLB during the manufacture of the integrated circuit device can be prevented or reduced, so that the integrated circuit device manufacturing efficiency is higher and the manufacturing cost is lower.

[0202] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device comprising: a substrate including a memory cell region and a connection region; a lower memory stack including a plurality of lower word lines located on the memory cell region and the connection region, the plurality of lower word lines extending in a horizontal direction parallel to a main surface of the substrate, the plurality of lower word lines overlapping each other in a vertical direction; an upper memory stack located on the lower memory stack, the upper memory stack comprising a plurality of upper word lines stacked one on another in the vertical direction; at least one first lower interconnect layer, the at least one first lower interconnect layer being located at a first vertical height between the lower memory stack and the upper memory stack on the connection region, the at least one first lower interconnect layer extending in the horizontal direction and being configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines; a separate insulating film covering the at least one first lower interconnect layer so that an upper surface of the at least one first lower interconnect layer does not contact other conductors on the connection region; as well as At least one first upper interconnect layer is located at a second vertical height higher than the upper memory stack on the connection region, the at least one first upper interconnect layer extends in the horizontal direction, and the at least one first upper interconnect layer is configured to be electrically connected to at least one upper word line selected from the plurality of upper word lines.

2. The integrated circuit device according to claim 1, wherein: The separated insulating film continuously extends in the horizontal direction in a partial region including the separated insulating film vertically overlapping the at least one first lower interconnection layer.

3. The integrated circuit device according to claim 1, further comprising: At least one second upper interconnection layer extends in the horizontal direction on the connection region at the second vertical height, the at least one second upper interconnection layer being configured to be connected to at least one lower word line selected from the plurality of lower word lines.

4. The integrated circuit device according to claim 1, wherein: the lower memory stack includes a stepped lower connection portion connected to the plurality of lower word lines, The upper memory stack includes a stepped upper connection portion connected to the plurality of upper word lines, and At least a portion of the stepped upper connection portion is located between the at least one first lower interconnection layer and the at least one first upper interconnection layer.

5. The integrated circuit device according to claim 1, wherein: In the horizontal direction, a first area of ​​a first region occupied by the lower memory stack is larger than a second area of ​​a second region occupied by the upper memory stack.

6. The integrated circuit device according to claim 5, wherein: The upper memory stack vertically overlaps the at least one first lower interconnection layer.

7. The integrated circuit device according to claim 1, wherein: In the horizontal direction, a first area of ​​a first region occupied by the lower memory stack is substantially smaller than or equal to a second area of ​​a second region occupied by the upper memory stack.

8. The integrated circuit device according to claim 1, wherein: The upper memory stack includes a portion protruding farther from the memory cell area than the lower memory stack, and The upper memory stack includes a portion vertically overlapping the at least one first lower interconnection layer.

9. The integrated circuit device according to claim 1, wherein: The substrate also includes a peripheral circuit region, and The at least one first lower interconnect layer comprises: a first partial portion connected to at least one lower word line among the plurality of lower word lines through a first lower contact plug on the connection region, and A second local portion is connected to one of a plurality of circuits formed on the peripheral circuit region.

10. The integrated circuit device according to claim 1, further comprising: a peripheral circuit region including a peripheral circuit interconnect layer, the peripheral circuit region facing the lower memory stack, and the substrate being interposed between the peripheral circuit region and the lower memory stack; a through contact plug extending in the vertical direction through the lower memory stack and the substrate to the peripheral circuit interconnect layer; as well as A second lower interconnect layer extends in the horizontal direction between the lower memory stack and the upper memory stack at the first vertical height, the second lower interconnect layer contacting an upper surface of the through contact plug.

11. The integrated circuit device according to claim 10, further comprising: a stack-buried insulating film located on the connection region and extending through the lower memory stack in the vertical direction, The insulating film buried in the stack surrounds the through contact plug.

12. An integrated circuit device comprising: a substrate including a memory cell region and a connection region; a peripheral circuit region spaced apart from the memory cell region and comprising a plurality of circuits; a lower memory stack, comprising: (i) a plurality of lower word lines located on the memory cell region and extending in a horizontal direction parallel to a main surface of the substrate, the plurality of lower word lines being stacked one on another in a vertical direction; and (ii) a plurality of lower pad regions connected to the plurality of lower word lines and corresponding to stepped lower connection portions on the connection region; an upper memory stack located above the lower memory stack on the memory cell region and comprising: (i) a plurality of upper word lines extending in the horizontal direction and overlapping each other in the vertical direction; and (ii) a plurality of upper pad regions connected to the plurality of upper word lines and corresponding to the stepped upper connection portions on the connection region; a lower insulating film located on the connection region, the lower insulating film covering the stepped lower connection portion; a plurality of lower contact plugs extending from the plurality of lower pad regions through the lower insulating film to a first vertical height, the first vertical height being lower than the upper memory stack; and a plurality of first lower interconnect layers located between the lower memory stack and the upper memory stack, Wherein, at least one first lower interconnection layer selected from the plurality of first lower interconnection layers includes: (i) a first local portion connected to at least one of the plurality of lower contact plugs; and (ii) a second local portion connected to at least one of the plurality of circuits.

13. The integrated circuit device according to claim 12, further comprising: a separate insulating film between the lower memory stack and the upper memory stack, the separate insulating film covering an upper surface of each of the plurality of first lower interconnect layers; an upper insulating film located on the connection region, the upper insulating film covering the separated insulating film; a plurality of upper contact plugs located in the connection region, the plurality of upper contact plugs passing through the upper insulating film; as well as a plurality of first upper interconnection layers connected to the plurality of upper contact plugs and extending in the horizontal direction at a second vertical height, wherein, The plurality of upper contact plugs are connected to at least one of the plurality of upper pad regions.

14. The integrated circuit device according to claim 13, wherein: In the connection region, the plurality of upper contact plugs do not pass through the separate insulating film and are not connected to the plurality of first lower interconnection layers.

15. The integrated circuit device according to claim 13, wherein: In the horizontal direction, at least a portion of the stepped lower connection portion protrudes farther from the memory cell region than the stepped upper connection portion, and In the connection region, a partial region of the upper insulating film vertically overlapping the plurality of first lower interconnection layers includes an insulating region through which the interconnection structure does not pass.

16. The integrated circuit device according to claim 13, wherein: At least a portion of the stepped lower connecting portion is located between the substrate and the stepped upper connecting portion, and At least one of the plurality of first lower interconnection layers vertically overlaps the stepped upper connection portion.

17. The integrated circuit device according to claim 16, wherein: The separated insulating film fills: (i) a first space between at least a portion of the plurality of first lower interconnect layers and the stepped upper connection portion; and (ii) a second space located between the lower memory stack and the upper memory stack.

18. The integrated circuit device according to claim 12, wherein: The plurality of circuits are formed at a height higher than or equal to that of the substrate, and A circuit selected from the plurality of circuits comprises: (i) a lower peripheral contact plug extending to a first vertical height through the lower insulating film on the peripheral circuit region, and (ii) a lower peripheral interconnect layer located at the first vertical height and connected to the lower peripheral contact plugs on the peripheral circuit region, wherein: The lower peripheral interconnection layer includes a first partial portion connected to the lower peripheral contact plug and a second partial portion connected to another circuit selected from the plurality of circuits.

19. The integrated circuit device according to claim 12, wherein: The plurality of circuits include a peripheral circuit interconnect layer facing the lower memory stack, and the substrate is interposed between the peripheral circuit interconnect layer and the lower memory stack, and The integrated circuit device also includes a through contact plug extending through each of the lower memory stack and the substrate in the vertical direction, the through contact plug connecting between (i) at least one first lower interconnect layer selected from the plurality of first lower interconnect layers and (ii) the peripheral circuit interconnect layer.

20. The integrated circuit device according to claim 12, further comprising: A channel structure extending in the vertical direction through the plurality of lower word lines and the plurality of upper word lines on the memory cell region, wherein: The channel structure includes a lower channel structure passing through the multiple lower word lines and an upper channel structure passing through the multiple upper word lines, wherein the lower surface of the upper channel structure contacts the upper surface of the lower channel structure, and in the horizontal direction, the width of the lower surface of the upper channel structure is smaller than the width of the upper surface of the lower channel structure.

21. The integrated circuit device according to claim 12, further comprising: a plurality of word line cutting regions extending in a first horizontal direction, the plurality of word line cutting regions defining a width of each of the plurality of lower word lines and the plurality of upper word lines in a second horizontal direction perpendicular to the first horizontal direction; as well as A plurality of word line cutting structures fill the plurality of word line cutting regions, wherein: The plurality of word line cutting structures include a lower word line cutting structure and an upper word line cutting structure, the lower word line cutting structure passing through the lower memory stack, the upper word line cutting structure vertically overlapping the lower word line cutting region and passing through the upper memory stack, and In the second horizontal direction, a width of a lower surface of the upper word line cutting structure is smaller than a width of an upper surface of the lower word line cutting structure.

22. An integrated circuit device comprising: A first substrate including a memory cell region and a connection region; a lower memory stack, comprising: (i) a plurality of lower word lines extending in a horizontal direction parallel to a main surface of the first substrate on the memory cell region, the plurality of lower word lines being stacked one on another in a vertical direction; and (ii) a plurality of lower pad regions located on the connection region, the plurality of lower pad regions being connected to the plurality of lower word lines; and an upper memory stack located on the lower memory stack, the upper memory stack comprising: (i) a plurality of upper word lines located on the memory cell region and overlapping each other in the vertical direction; and (ii) a plurality of upper pad regions connected to the plurality of upper word lines and located on the connection region, wherein: at least one first lower interconnect layer extending in the horizontal direction at a first vertical height between the lower memory stack and the upper memory stack on the connection region, At least one lower contact plug is connected between at least one lower pad region selected from the plurality of lower pad regions and the at least one first lower interconnection layer, and A separate insulating film covers the at least one first lower interconnect layer so that an upper surface of the at least one first lower interconnect layer does not contact other conductors on the connection region.

23. The integrated circuit device according to claim 22, further comprising: an upper insulating film covering the separated insulating film and the plurality of upper pad regions on the connection region; at least one upper interconnect layer located on the connection region and extending in the horizontal direction at a second vertical height above the upper memory stack; as well as at least one upper contact plug that passes through the upper insulating film and is connected between at least one upper pad region selected from the plurality of upper pad regions and the at least one upper interconnection layer, The upper insulating film includes a local region vertically overlapping the at least one lower interconnection layer, and the local region includes an insulating region, and the at least one upper interconnection layer does not pass through the insulating region.

24. The integrated circuit device according to claim 22, further comprising: a peripheral circuit region, which is spaced apart from the memory cell region and includes a plurality of circuits, Wherein, the at least one first lower interconnection layer comprises: a first partial portion connected to the at least one lower contact plug on the connection region, and A second partial portion is connected to one circuit among the plurality of circuits.

25. The integrated circuit device according to claim 22, wherein: The at least one first lower interconnection layer extends in the horizontal direction between the lower memory stack and the upper memory stack, and includes a bent portion.

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