Imaging device

Abstract

The present invention provides an imaging device that does not use a color filter and does not require an external processing circuit to perform arithmetic processing. The first circuit includes a first photoelectric conversion element, a first transistor and a second transistor, the second circuit includes a second photoelectric conversion element, a third transistor and a fourth transistor, the third circuit includes a fifth transistor, a sixth transistor, a seventh transistor and a second capacitor, the spectrometer is arranged on the first photoelectric conversion element or the second photoelectric conversion element, and the first circuit and the second circuit are connected to the third circuit through the first capacitor.

Description

Technical Field

[0001] One embodiment of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification, etc., relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product, or a composition of matter. Therefore, specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, storage devices, imaging devices, driving methods of these devices, or manufacturing methods of these devices can be cited.

[0003] In this specification, etc., a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one form of a semiconductor device. In addition, a storage device, a display device, an imaging device, and an electronic device may include a semiconductor device. Background Art

[0004] As a semiconductor device in which pixels having a photoelectric sensor are arranged in a matrix, a CMOS (Complementary Metal Oxide Semiconductor) image sensor is known. As an imaging element, a CMOS image sensor is provided in many portable devices such as digital cameras or mobile phones. In recent years, the clarity of imaging has increased, portable devices have been miniaturized, and power consumption has been reduced, so the pixels in the CMOS image sensor have been made smaller.

[0005] In a CMOS image sensor, a color filter is formed on a photoelectric sensor, and the color filter is used to split the incident light, and then the light of each color is detected by the photoelectric sensor, thereby obtaining color imaging data. However, since the color filter transmits light in a specific wavelength range and absorbs light of other wavelengths, the utilization efficiency of the incident light is low. Therefore, Patent Document 1 discloses a technology that uses a component that splits the incident light instead of a color filter.

[0006] [Patent Document 1] International Publication No. 2009 / 153937 Pamphlet

[0007] In the structure of Patent Document 1, in order to obtain imaging data of each RGB color, it is necessary to perform arithmetic processing on the directly obtained data using an external processing circuit. Therefore, in order to achieve low power consumption or high speed of the imaging device, it is preferable to adopt a structure that can omit the arithmetic processing and the like. Summary of the invention

[0008] Therefore, one of the objects of one embodiment of the present invention is to provide an imaging device that does not require the use of an external processing circuit to perform calculations in order to obtain imaging data of each color. One of the other objects of one embodiment of the present invention is to provide an imaging device that can capture color images without using a color filter. One of the other objects of one embodiment of the present invention is to provide an imaging device with low power consumption. One of the other objects of one embodiment of the present invention is to provide an imaging device suitable for high-speed operation. One of the other objects of one embodiment of the present invention is to provide a highly sensitive imaging device. One of the other objects of one embodiment of the present invention is to provide an imaging device with a wide dynamic range. One of the other objects of one embodiment of the present invention is to provide a high-resolution imaging device. One of the other objects of one embodiment of the present invention is to provide a low-cost imaging device. One of the other objects of one embodiment of the present invention is to provide a highly reliable imaging device. One of the other objects of one embodiment of the present invention is to provide a novel imaging device, etc. One of the other objects of one embodiment of the present invention is to provide a novel semiconductor device, etc.

[0009] Note that the recording of these purposes does not prevent the existence of other purposes. In addition, one mode of the present invention does not need to achieve all of the above purposes. Purposes other than the above purposes are obvious from the description of the specification, drawings, claims, etc., and can be extracted from the description of the specification, drawings, claims, etc.

[0010] One embodiment of the present invention relates to an imaging device including a spectroscopic element.

[0011] One embodiment of the present invention is an imaging device, comprising: a pixel circuit; and a spectroscopic element, wherein the pixel circuit comprises a first circuit, a second circuit, a third circuit and a first capacitor, the first circuit comprises a first photoelectric conversion element, a first transistor and a second transistor, the second circuit comprises a second photoelectric conversion element, a third transistor and a fourth transistor, the third circuit comprises a fifth transistor, a sixth transistor, a seventh transistor and a second capacitor, the spectroscopic element is arranged on the first photoelectric conversion element or the second photoelectric conversion element, one terminal of the first photoelectric conversion element is electrically connected to one of the source and drain of the first transistor, one of the source and drain of the second transistor is electrically connected to one of the source and drain of the first transistor, and the source of the first transistor The other of the gate and the drain is electrically connected to one terminal of the first capacitor element, one terminal of the second photoelectric conversion element is electrically connected to one of the source and the drain of the third transistor, one of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the third transistor, the other of the source and the drain of the fourth transistor is electrically connected to one terminal of the first capacitor element, one of the source and the drain of the fifth transistor is electrically connected to the other terminal of the first capacitor element, one terminal of the second capacitor element is electrically connected to the other terminal of the first capacitor element, the gate of the sixth transistor is electrically connected to the other terminal of the first capacitor element, and one of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor.

[0012] The first photoelectric conversion element and the second photoelectric conversion element preferably have the same structure.

[0013] The capacitance value of the first capacitance element is preferably greater than the capacitance value of the second capacitance element.

[0014] The capacitance value between one terminal of the first photoelectric conversion element, one of the source and drain of the first transistor, and one terminal of the first capacitor element is preferably equal to the capacitance value between one terminal of the second photoelectric conversion element, one of the source and drain of the third transistor, and one terminal of the first capacitor element.

[0015] The spectroscopic element can be set on the first photoelectric conversion element, and the light of WR, WG or WB, which is obtained by removing any one of the light components of wavelengths corresponding to red (R), green (G) and blue (B) from the light (W) incident to the pixel circuit, can be incident on the first photoelectric conversion element, and the light W+R, W+G or W+B, which is a combination of the light (W) incident to the pixel circuit and the removed light, can be incident on the second photoelectric conversion element.

[0016] In the above configuration, a part of the light removed in the adjacent pixel may also be incident on the second photoelectric conversion element.

[0017] In addition, the spectroscopic element can also be set on the second photoelectric conversion element, and light W-(R / 2)-(B / 2), W-(R / 2)-(G / 2) or W-(B / 2)-(G / 2) obtained by removing any two of the 1 / 2 light components of wavelengths corresponding to red (R), green (G) and blue (B) from the light (W) incident on the pixel circuit can also be incident on the second photoelectric conversion element, and light W+(R / 2)+(B / 2), W+(R / 2)+(G / 2) or W+(B / 2)+(G / 2) obtained by synthesizing the light (W) incident on the pixel circuit and the removed light can also be incident on the first photoelectric conversion element.

[0018] Part or all of the first to seventh transistors preferably include an oxide semiconductor in the active layer, and the oxide semiconductor preferably includes In, Zn and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf).

[0019] According to one embodiment of the present invention, an imaging device capable of obtaining high-quality imaging data can be provided. In addition, one embodiment of the present invention can provide an imaging device capable of compensating for the electrical characteristics of an amplifying transistor included in a pixel circuit. In addition, one embodiment of the present invention can provide an imaging device with low power consumption. In addition, one embodiment of the present invention can provide an imaging device suitable for high-speed operation. In addition, one embodiment of the present invention can provide a highly sensitive imaging device. In addition, one embodiment of the present invention can provide an imaging device with a wide dynamic range. In addition, one embodiment of the present invention can provide a high-resolution imaging device. In addition, one embodiment of the present invention can provide a low-cost imaging device. In addition, one embodiment of the present invention can provide a highly reliable imaging device. In addition, one embodiment of the present invention can provide a novel imaging device, etc. In addition, one embodiment of the present invention can provide a novel semiconductor device, etc.

[0020] Note that the description of these effects does not prevent the existence of other effects. Note that one mode of the present invention does not necessarily have all of the above effects. In addition, effects other than these effects can be clearly seen and extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a circuit diagram of a pixel included in the imaging device;

[0022] Figure 2 is a schematic diagram illustrating the positional relationship between a spectroscopic element and a photoelectric conversion element included in an imaging device;

[0023] Figure 3 is a schematic diagram illustrating the positional relationship between a spectroscopic element and a photoelectric conversion element included in an imaging device;

[0024] Figure 4 is a top view illustrating the way pixels are formed;

[0025] Figure 5 is a diagram illustrating a cross section of a pixel;

[0026] Figure 6 is a timing diagram illustrating the operation of the pixel circuit;

[0027] Figure 7 is a pixel circuit and a timing diagram illustrating the operation of the pixel circuit;

[0028] Figure 8 is a circuit diagram of a pixel included in the imaging device;

[0029] Fig. 9 is a diagram illustrating the arrangement of pixels;

[0030] Fig.10 is a cross-sectional view of an imaging device including a circuit portion;

[0031] Fig.11 is a diagram illustrating a curved imaging device;

[0032] Fig.12 is a timing diagram illustrating the operation of the global shutter mode;

[0033] Fig.13 is a timing diagram illustrating the operation of the rolling shutter mode;

[0034] Fig.14 are a top view and a cross-sectional view illustrating a transistor;

[0035] Fig.15 are a top view and a cross-sectional view illustrating a transistor;

[0036] Fig.16 are a top view and a cross-sectional view illustrating a transistor;

[0037] Fig.17 are a top view and a cross-sectional view illustrating a transistor;

[0038] Fig.18 are a top view and a cross-sectional view illustrating a transistor;

[0039] Fig.19 are a top view and a cross-sectional view illustrating a transistor;

[0040] Fig. 20 is a diagram illustrating a cross section of a transistor in a channel width direction;

[0041] Fig.21 is a diagram illustrating a cross section of a transistor in a channel length direction;

[0042] Fig. 22 are a top view and a cross-sectional view illustrating a semiconductor layer;

[0043] Fig.23 are a top view and a cross-sectional view illustrating a semiconductor layer;

[0044] Fig.24 are a top view and a cross-sectional view illustrating a transistor;

[0045] Fig.25 are a top view and a cross-sectional view illustrating a transistor;

[0046] Fig.26 are a top view and a cross-sectional view illustrating a transistor;

[0047] Fig. 27 are a top view and a cross-sectional view illustrating a transistor;

[0048] Fig.28 are a top view and a cross-sectional view illustrating a transistor;

[0049] Fig.29 are a top view and a cross-sectional view illustrating a transistor;

[0050] Fig.30 is a diagram illustrating a cross section of a transistor in a channel width direction;

[0051] Fig.31 is a diagram illustrating a cross section of a transistor in a channel length direction;

[0052] Fig.32 is a top view illustrating a transistor;

[0053] Fig.33 is a diagram illustrating a method for manufacturing a transistor;

[0054] Fig.34 is a diagram illustrating a method for manufacturing a transistor;

[0055] Fig.35 is a diagram illustrating a method for manufacturing a transistor;

[0056] Fig.36 is a diagram illustrating a method for manufacturing a transistor;

[0057] Fig.37 is a diagram illustrating a method for manufacturing a transistor;

[0058] Fig.38 is a diagram illustrating a method for manufacturing a transistor;

[0059] Fig.39 is a diagram illustrating an electronic device;

[0060] Fig.40is a circuit diagram of a pixel included in the imaging device;

[0061] Fig.41 is a circuit diagram of a pixel included in the imaging device;

[0062] Fig.42 It is a top view for explaining the structure of pixels. DETAILED DESCRIPTION

[0063] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person of ordinary skill in the art can easily understand the fact that the methods and details of the present invention can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. Note that in the structure of the invention described below, the same figure marks are used in different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. Note that the shading of the same constituent elements is sometimes appropriately omitted or changed in different drawings.

[0064] For example, in this specification, when it is clearly stated that "X is connected to Y", it means the following: X is electrically connected to Y; X is functionally connected to Y; X is directly connected to Y. Therefore, it is not limited to the prescribed connection relationship (for example, the connection relationship shown in the drawings or text, etc.), and the connection relationship other than the connection relationship shown in the drawings or text is also included in the drawings or text.

[0065] Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0066] As an example of a case where X and Y are directly connected, there can be cited a case where an element capable of electrically connecting X and Y (such as a switch, transistor, capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.) is not connected between X and Y, and X and Y are not connected via an element capable of electrically connecting X and Y (such as a switch, transistor, capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.).

[0067] As an example of a case where X and Y are electrically connected, one or more elements (such as switches, transistors, capacitors, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) that can electrically connect X and Y can be connected between X and Y. In addition, the switch has a function of controlling conduction or shutdown. In other words, the switch has a function of controlling whether to allow current to flow by turning it into a conducting state (on state) or a non-conducting state (off state). Alternatively, the switch has a function of selecting and switching a current path. In addition, the case where X and Y are electrically connected includes the case where X and Y are directly connected.

[0068] As an example of a case where X and Y are functionally connected, one or more circuits capable of functionally connecting X and Y (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, γ (gamma) correction circuit, etc.), a potential level conversion circuit (power supply circuit (boost circuit, buck circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplifier circuit (a circuit capable of increasing signal amplitude or current, etc., an operational amplifier, a differential amplifier circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a storage circuit, a control circuit, etc.) may be connected between X and Y. Note that, for example, even if another circuit is interposed between X and Y, when a signal output from A is transmitted to B, X and Y can be said to be functionally connected. In addition, the case where X and Y are functionally connected includes a case where X and Y are directly connected and a case where X and Y are electrically connected.

[0069] Furthermore, when it is explicitly stated that “X is electrically connected to Y”, in this specification, etc., it means the following: X is electrically connected to Y (i.e., X and Y are connected with another element or another circuit interposed therebetween); X and Y are functionally connected (i.e., X and Y are functionally connected with another circuit interposed therebetween); X and Y are directly connected (i.e., X and Y are connected without another element or another circuit interposed therebetween). That is, in this specification, etc., when “electrically connected” is explicitly stated, it is the same as when only “connected” is explicitly stated.

[0070] Note that, for example, in the case where the source (or first terminal, etc.) of the transistor is electrically connected to X through Z1 (or not through Z1) and the drain (or second terminal, etc.) of the transistor is electrically connected to Y through Z2 (or not through Z2) and in the case where the source (or first terminal, etc.) of the transistor is directly connected to a part of Z1 and the other part of Z1 is directly connected to X, the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2 and the other part of Z2 is directly connected to Y, it can be expressed as follows.

[0071] For example, it can be expressed as “X, Y, the source (or first terminal, etc.) of the transistor, and the drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y”. Alternatively, it can be expressed as “the source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in sequence”. Alternatively, it can be expressed as “X is electrically connected to Y through the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are arranged to be connected to each other in sequence”. By specifying the connection order in the circuit structure using the same expression method as this example, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be distinguished to determine the technical scope.

[0072] In addition, as another expression method, for example, it can be expressed as "the source (or first terminal, etc.) of the transistor is electrically connected to X through at least a first connection path, the first connection path does not have a second connection path, the second connection path is a path through the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor, the first connection path is a path through Z1, the drain (or second terminal, etc.) of the transistor is electrically connected to Y through at least a third connection path, the third connection path does not have the second connection path, and the third connection path is a path through Z2". Alternatively, it can also be expressed as "the source (or first terminal, etc.) of the transistor is electrically connected to X through Z1 at least on the first connection path, the first connection path does not have a second connection path, the second connection path has a connection path through the transistor, the drain (or second terminal, etc.) of the transistor is electrically connected to Y through Z2 at least on the third connection path, and the third connection path does not have the second connection path". Alternatively, it can be expressed as "the source (or first terminal, etc.) of the transistor is electrically connected to X through Z1 via at least a first electrical path, the first electrical path does not have a second electrical path, the second electrical path is an electrical path from the source (or first terminal, etc.) of the transistor to the drain (or second terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor is electrically connected to Y through Z2 via at least a third electrical path, the third electrical path does not have a fourth electrical path, and the fourth electrical path is an electrical path from the drain (or second terminal, etc.) of the transistor to the source (or first terminal, etc.) of the transistor". By specifying the connection path in the circuit structure using the same expression method as these examples, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be distinguished to determine the technical scope.

[0073] Note that this expression method is an example and is not limited to the above expression method. Here, X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0074] In addition, even if independent components are electrically connected to each other on a circuit diagram, one component may have the functions of multiple components. For example, when a portion of a wiring is used as an electrode, one conductive film has the functions of both wiring and electrode. Therefore, the category of "electrically connected" in this specification also includes the case where one conductive film has the functions of multiple components.

[0075] In addition, depending on the situation or state, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Also, "insulating film" may be replaced with "insulating layer" in some cases.

[0076] Implementation Method 1

[0077] In this embodiment, an imaging device according to one embodiment of the present invention is described with reference to the drawings.

[0078] An imaging device according to one embodiment of the present invention can use a spectroscopic element instead of a color filter. This can suppress the absorption loss caused by the color filter and increase the amount of light incident on the photoelectric conversion element. In other words, the sensitivity of the imaging device can be improved.

[0079] In addition, in order to extract the imaging data of red (R), green (G), and blue (B) from the split light, a method of detecting the difference of the signals obtained from the two photoelectric conversion elements is used. In other words, it is possible to achieve low power consumption and high speed of the imaging device without using external circuit calculations.

[0080] Figure 1 1 is a circuit diagram of a pixel circuit of an imaging device that can be used in one embodiment of the present invention. The pixel circuit is roughly divided into a photoelectric conversion unit and a signal generation unit. For the sake of simplicity, the structure of the photoelectric conversion unit including circuit 31 and circuit 32 is described. In addition, the structure of the signal generation unit including circuit 33 is described. In addition, the structure of the photoelectric conversion unit and the signal generation unit connected via a capacitor element C-1 is described.

[0081] The circuit 31 in the photoelectric conversion unit includes a photodiode 61, a transistor 51, and a transistor 52. In addition, the circuit 32 includes a photodiode 62, a transistor 53, and a transistor 54.

[0082] As photodiodes 61 and 62, diode elements with pn junctions or pin junctions formed in a silicon substrate can be used. Alternatively, pin junction diode elements using amorphous silicon film or microcrystalline silicon film can also be used. Note that although the circuits 31 and 32 are shown to include photodiodes, the circuits 31 and 32 can also include other photoelectric conversion elements. For example, a diode-connected transistor can also be used. In addition, silicon, germanium, selenium, etc. can also be used to form a variable resistor using a photoelectric effect.

[0083] Alternatively, a photoelectric conversion element containing selenium that utilizes a so-called avalanche multiplication phenomenon may be used. In this photoelectric conversion element, a highly sensitive sensor having a large electron amplification amount relative to the amount of incident light can be obtained.

[0084] As the selenium material, amorphous selenium or crystalline selenium can be used. For example, by forming amorphous selenium and then performing a heat treatment, crystalline selenium can be obtained. In addition, by making the crystal grain size of crystalline selenium smaller than the pixel pitch, the characteristic deviation of each pixel can be reduced.

[0085] The circuit 33 included in the signal generation unit includes a transistor 55, a transistor 56, a transistor 57, and a capacitor C-2.

[0086] In the circuit 31, one terminal of the photodiode 61 is electrically connected to one of the source and drain of the transistor 51 and one of the source and drain of the transistor 52. The other of the source and drain of the transistor 52 is electrically connected to one terminal of the capacitor C-1.

[0087] In the circuit 32, one terminal of the photodiode 62 is electrically connected to one of the source and drain of the transistor 53 and one of the source and drain of the transistor 54. The other of the source and drain of the transistor 54 is electrically connected to one terminal of the capacitor C-1.

[0088] Here, a node connecting the other of the source and drain of the transistor 52, the other of the source and drain of the transistor 54, and one terminal of the capacitor C-1 is referred to as a first charge storage unit (FD1).

[0089] In the circuit 33, one of the source and drain of the transistor 55, the gate of the transistor 56, and one terminal of the capacitor C-2 are electrically connected to the other terminal of the capacitor C-1. In addition, one of the source and drain of the transistor 56 is electrically connected to one of the source and drain of the transistor 57.

[0090] Here, a node connecting the other of the source and the drain of the transistor 55, the gate of the transistor 56, one terminal of the capacitor C-2, and the other terminal of the capacitor C-1 is referred to as a second charge storage unit (FD2).

[0091] The capacitance value of capacitor element C-1 is preferably greater than the capacitance value of capacitor element C-2. In addition, the capacitance value between one terminal of photodiode 61, one of the source and drain of transistor 51, and one terminal of capacitor element C-1 is preferably equal to the capacitance value between one terminal of photodiode 62, one of the source and drain of transistor 53, and one terminal of capacitor element C-1.

[0092] The other terminals of the photodiodes 61 and 62 are electrically connected to the wiring VPD. The other of the sources and drains of the transistors 51 and 53 is electrically connected to the wiring VPR. The other of the source and drain of the transistor 55 is electrically connected to the wiring VFR. The other terminal of the capacitor C-2 is electrically connected to the wiring VC. The other of the source and drain of the transistor 56 is electrically connected to the wiring VO. The wiring VPD and the wiring VC can be used as common wiring. Figure 1 In the structure of , the wiring VPR, the wiring VFR, and the wiring VO can be used as common wiring.

[0093] The gates of transistors 51 and 53 are electrically connected to wiring PR. The gate of transistor 52 is electrically connected to wiring TX1, and the gate of transistor 54 is electrically connected to wiring TX2. The gate of transistor 55 is electrically connected to wiring FR. The gate of transistor 57 is electrically connected to wiring SEL, and the other of the source and the drain is electrically connected to wiring OUT (output).

[0094] Note that the wiring VO may be supplied with a potential such as GND, VSS, or VDD. Here, the potential or voltage is relative, and therefore, GND is not limited to 0V.

[0095] Photodiode 61 (PD1) and photodiode 62 (PD2) are light-receiving elements and may have a function of generating a current corresponding to light incident on the pixel circuit. Transistors 52 and 54 may have a function of controlling the accumulation of charges from photodiodes 61 and 62 in the charge accumulation unit (FD1). Transistors 51 and 53 may have a function of resetting the potential of the charge accumulation unit (FD1). Transistor 55 may have a function of resetting the potential of the charge accumulation unit (FD2). Transistor 56 may have a function of outputting a signal corresponding to the potential of the charge accumulation unit (FD2). Transistor 57 has a function of controlling the selection of the pixel circuit during readout.

[0096] The wiring VPR, the wiring VPD, the wiring VC, the wiring VFR, and the wiring VO may function as a power supply line, and the wiring PR, the wiring TX1, the wiring TX2, the wiring FR, the wiring SEL, and the wiring OUT may function as a signal line.

[0097] Figure 2 A to Figure 2 C is a schematic diagram for explaining the positional relationship between the spectroscopic element and the photoelectric conversion element included in the imaging device according to one embodiment of the present invention.

[0098] Figure 2 A shows a state where two pixels (Pixel-R1 and Pixel-R2) for detecting red (R) imaging data are adjacent to each other. Figure 1 The photodiode 61 shown, PD2 is equivalent to the photodiode 62.

[0099] The spectroscopic element 65R is provided on the PD 1. Light (W: equivalent to white light including RGB light components) to be imaged is incident on the spectroscopic element 65R. W incident on the spectroscopic element 65R is split into light (R) centered on the wavelength component of R and light (WR) centered on the wavelength component of R removed from W.

[0100] WR is emitted from the spectroscopic element 65R to PD1 so as to travel substantially in the spectroscopic element 65R. In addition, R is emitted from the spectroscopic element 65R to PD2 at an angle different from that of WR.

[0101] Notice, Figure 2 A shows the case where R / 2 is emitted from the end of the spectroscopic element 65R in two directions. In this case, R is irradiated to PD2 of Pixel-R1 by synthesizing R / 2 emitted from the spectroscopic element 65R of Pixel-R2 which is an adjacent pixel. In addition, W+R which is synthesized by this R and W which does not pass through the spectroscopic element 65R is incident on PD2.

[0102] In addition, although Figure 2 A shows a structure in which R / 2 is emitted from the light splitting element 65R in two directions, but it may also have a structure as follows: Figure 3 The structure shown in A is that R radiates in one direction.

[0103] Figure 2 B shows a state where two pixels (Pixel-B1 and Pixel-B2) for detecting blue (B) data are adjacent to each other. Figure 1 The photodiode 61 shown, PD2 is equivalent to the photodiode 62.

[0104] The spectroscopic element 65B is provided on the PD 1. The incident light (W) to be imaged is incident on the spectroscopic element 65B. The W incident on the spectroscopic element 65B is split into light (B) centered on the wavelength component of B and light (WB) centered on the wavelength component of B removed from W.

[0105] exist Figure 2 In B, the description of WB incident on PD1 and the description of W+B incident on PD2 are the same as the description of the pixel for detecting the imaging data of R described above. Figure 3 Structural substitution of B Figure 2 The structure of B.

[0106] Figure 2 C shows a state where two pixels (Pixel-G1 and Pixel-G2) for detecting imaging data of green (G) are adjacent to each other. Figure 1 The photodiode 61 shown, PD2 is equivalent to the photodiode 62.

[0107] The spectroscopic element 65G is provided on the PD1. The light to be imaged (W: white light equivalent to synthesized RGB) is incident on the spectroscopic element 65G. W incident on the spectroscopic element 65G is split into a portion of light centered on the wavelength component of R (R / 2), a portion of light centered on the wavelength component of B (B / 2), and light obtained by removing R / 2 and B / 2 from W (W-(R / 2)-(B / 2)).

[0108] W-(R / 2)-(B / 2) is emitted from the spectroscopic element 65R to PD2 in a manner that roughly travels in the spectroscopic element 65R. In addition, R / 2 and B / 2 are emitted from the spectroscopic element 65G at different angles from W-(R / 2)-(B / 2). For example, Figure 2 As shown in C, R / 2 emitted from the light-splitting element 65G of Pixel-G1 is incident on PD1 of Pixel-G1, and B / 2 is incident on PD1 of the adjacent Pixel-G2. Or, Figure 3 As shown in C, a structure may be adopted in which R / 2 and B / 2 are emitted from the light-splitting element 65G in the same direction.

[0109] Note that although the method for obtaining R or B imaging data is described as Figure 2 A and Figure 2 B and Figure 3 A and Figure 3 B, but by changing the spectroscopic element, it is also possible to realize a method for obtaining imaging data of G. In addition, although the method for obtaining imaging data of G is described Figure 2 C and Figure 3C, but by changing the spectroscopic element, it is also possible to obtain imaging data of R or B.

[0110] Figure 4 A and Figure 4 B is an example of the top surface of the pixel. Figure 4 A shows Figure 2 A or Figure 3 The pixels shown in A are used to obtain the imaging data of R, but Figure 2 B or Figure 3 The pixels shown in B for obtaining the imaging data of B may also have the same structure.

[0111] Since the difference of the signals output from PD1 and PD2 is used in one embodiment of the present invention, the electrical characteristics of the two are preferably the same. That is, PD1 and PD2 preferably have the same structure. Note that as long as the electrical characteristics of the two are the same, their structures may be different.

[0112] The spectroscopic element 65R is arranged above the center of PD1, and the light centered on the wavelength component R is emitted in the direction where PD2 is set. The pixel is a micro-pixel, and of the external light irradiating the entire pixel, approximately the same amount of light is incident on the upper side of PD1 and the upper side of PD2. The light incident on the upper side of PD1 is introduced by the spectroscopic element 65R and is split into WR and R. Therefore, in Figure 2 In the structure of A, WR is incident on PD1, and R / 2 is incident on PD2 and PD2 of the adjacent pixel. Figure 3 In the structure of A, R is incident on PD2 of the same pixel.

[0113] Figure 4 B is Figure 2 C or Figure 3 C is a pixel for obtaining imaging data of G. The spectroscopic element 65R is arranged above the center of PD2, and the light centered on the wavelength components of R and B is emitted in the direction where PD1 is set. As with the pixel for obtaining imaging data of R, approximately the same amount of light is incident on the upper side of PD1 and the upper side of PD2. The light incident on the upper side of PD2 is Figure 4 The region 66 shown in B is introduced, and half of the light incident on this region is incident on the spectroscopic element 65G. That is, the light emitted from the spectroscopic element 65G, which is centered on the wavelength components of R and B, is R / 2 and B / 2. Figure 2 In the structure of C, W-(R / 2)-(B / 2) is incident on PD2, and R / 2 and B / 2 are incident on PD1 and PD1 of the adjacent pixel respectively. Figure 3In the structure of C, R / 2 and B / 2 are incident on PD1 of the same pixel.

[0114] Note that although Figure 4 A and Figure 4 B shows that the top surface of the pixel, photodiode and spectrometer is rectangular, but it is not limited to this. The top surface of the above components can also be a polygon such as a circle or a hexagon. Figure 4 C Figure 4 As in the modified example of A, the pixel may be a polygon with two adjacent hexagons, the photodiode may be substantially hexagonal, and the spectroscopic element may be substantially circular. In addition, the corners of the above-mentioned rectangular, hexagonal or other polygonal components may have curvature.

[0115] Figure 5 A is an example of a cross section of a pixel for obtaining imaging data of R. PD1 and PD2 are separated by an element separation layer 1500, and a light shielding layer 1510 for preventing color mixing is provided on the element separation layer 1500. An insulating layer 1520 having high light transmittance to visible light is provided on the photodiode (PD1, PD2), and a microlens 1540 is provided on the insulating layer 1520 in a paired manner with the photodiode.

[0116] Furthermore, a spectroscopic element 65R is provided on the optical path of the light passing through the microlens 1540. There is no limitation on the type of the spectroscopic element 65R, and for example, an optical element such as a prism or a diffraction grating can be used. In addition, a plate-like body with a high refractive index that is transparent to visible light can be used as a spectroscopic element. For example, the plate-like body with a high refractive index can be formed using a silicon nitride film or the like. In addition, a spectroscopic element and other components can also be combined. For example, a spectroscopic element such as a prism, a diffraction grating, a plate-like body with a high refractive index and components such as a mirror and a light guide plate can also be combined.

[0117] As an example, Figure 5 B shows a method of combining the spectroscopic element 65R and the mirror 67. By using the mirror 67, the degree of freedom of the optical path of the light emitted from the spectroscopic element 65R can be increased. In addition, the mirror can be formed of a material with high reflectivity such as metal, or can have a structure that causes total reflection by combining materials with different refractive indices. Fig.42 yes Figure 5 An example of a top view of a pixel in B.

[0118] In addition, if Figure 5 As shown in C, a microlens 1541 can also be set on the photodiode.

[0119] Note that although Figure 5 A. Figure 5 B and Figure 5C illustrates the pixel used to obtain the imaging data of R, but the pixel used to obtain the imaging data of B and the pixel used to obtain the imaging data of G may also have the same structure. In addition, there is no limitation on the structure of the above-mentioned pixel, and it may also have an insulating layer other than the above-mentioned, a light shielding layer other than the above-mentioned, a passivation layer film, an adhesive layer, an anti-reflection film, a light absorption layer, etc. In addition, a coloring layer may also be included between the microlens 1540 and the photodiode (PD1, PD2).

[0120] Next, the description includes Figure 1 The circuit shown is used to obtain the operation of the pixel of R imaging data. Figure 6 A is a timing chart for explaining the operation of the pixel. Here, the wiring VPD is at a low potential, the wiring VPR is at a high potential, the wiring VC is at a low potential, the wiring VFR is at a high potential, and the wiring VO is at a high potential.

[0121] From time T1 to time T2, the wiring PR is set to "H" ("High"), the wiring FR is set to "H", the wiring TX1 is set to "H", and the wiring TX2 is set to "H". At this time, the potential of the node FD2 is set to the potential of the wiring VFR, and the potential of the node FD1 is set to the potential of the wiring VPR (reset operation).

[0122] From time T2 to time T3, the wiring PR is set to "L" ("low"), the wiring FR is set to "H", the wiring TX1 is set to "H", and the wiring TX2 is set to "L". At this time, the potential of the node FD1 decreases by ΔV1' (refer to formula 1, α' is a proportionality coefficient) in proportion to the light intensity (I(WR)) of the light irradiating the photodiode 61 (PD1), that is, WR. In addition, the stronger the light irradiating the photodiode 61 (PD1), the faster the potential of the node FD1 decreases (accumulation operation 1).

[0123] [Formula 1]

[0124] ΔV1′=α′·(WR) (1)

[0125] At time T3, wiring FR is set to "L", and wiring TX1 is set to "L". At this time, the potential of node FD2 is maintained at the potential of wiring VPR. In addition, the potential of node FD1 is maintained at a potential that is lowered by ΔV1' from the potential of wiring VPR.

[0126] From time T4 to time T5, the wiring PR is set to "H". At this time, the potential of the cathode of the photodiode 61 (PD1) and the potential of the cathode of the photodiode 62 (PD2) are set to the potential of the wiring VPR (reset operation 2). From time T3 to time T5, because the potential of the cathode of the photodiode 61 (PD1) and the photodiode 62 (PD2) decreases, it is preferred to set the potential of the cathode to the potential of the wiring VPR before time T5 (setting the wiring TX1 and the wiring TX2 to "H"). As a result, the phenomenon of a rapid decrease in the potential of the node FD1 just after time T5, that is, the phenomenon of noise, does not occur, so that imaging data can be acquired with high precision.

[0127] In order to obtain the same effect, it is preferable that the capacitance value of the capacitor C-1 is sufficiently larger than the capacitance value of the cathode of the photodiode 61 (PD1) and the capacitance value of the cathode of the photodiode 62 (PD2).

[0128] From time T5 to time T6, the wiring PR is set to "H", the wiring FR is set to "L", the wiring TX1 is set to "H", and the wiring TX2 is set to "H". At this time, the potential of the node FD1 is set to the potential of the wiring VPR. That is, the potential of the node FD1 is higher by ΔV1' than from time T3 to time T4. Here, the potential of the node FD2 rises by ΔV1 due to the capacitive coupling of the combined capacitance of the capacitance C1 of the capacitance element C-1, the capacitance C2 of the capacitance element C-2, and the gate capacitance Cg of the transistor 56 (refer to Formula 2, α is the proportionality coefficient).

[0129] [Formula 2]

[0130]

[0131] From time T6 to time T7, the wiring PR is set to "L", the wiring FR is set to "L", the wiring TX1 is set to "L", and the wiring TX2 is set to "H". At this time, the potential of the node FD1 decreases by ΔV2' (see equation 3) in proportion to the light intensity (I(W+R)) of the light irradiating the photodiode 62 (PD2), that is, W+R. In addition, the stronger the light irradiating the photodiode 62 (PD2), the lower the potential of the node FD1 (accumulation operation 2).

[0132] [Formula 3]

[0133] ΔV2′=α′·I(W+R) (3)

[0134] In addition, the potential of the node FD2 decreases by ΔV2 (see Formula 4). That is, the potential of the node FD2 is lower than the potential of the wiring VFR by ΔV2-ΔV1. Here, if Formula 5 is satisfied, ΔV2-ΔV1=2αIR is satisfied (see Formula 6), and thus the potential of the node FD2 is a potential that depends on the R component of the incident light W.

[0135] [Formula 4]

[0136]

[0137] [Formula 5]

[0138] I(W+R)-I(WR)=I(2R)=2I(R) (5)

[0139] [Formula 6]

[0140] ΔV2-ΔV1=α·I(W+R)-α·I(WR)=2αI(R) (6)

[0141] From time T8 to time T9, the wiring SEL is set to "H" (selection operation). At this time, a potential corresponding to the potential of the node FD2 is output to the wiring OUT. That is, the stronger the light intensity of the R component of the incident light W, the higher the potential of the wiring OUT.

[0142] Although the above description is given as an operation for obtaining imaging data of R, the operation for obtaining imaging data of B can also be performed in the same manner.

[0143] Next, the operation of the pixel for obtaining the imaging data of G will be described. Figure 6 B is a timing diagram illustrating the operation of the pixel. In the pixel used to obtain imaging data of G, W+(R / 2)+(B / 2) is incident on the photodiode 61 (PD1), and W-(R / 2)-(B / 2) is incident on the photodiode 62 (PD2).

[0144] Figure 6 B's timing diagram and Figure 6 The difference of the timing diagram of A is that the period from time T6 to time T7 is three times that from time T2 to time T3 (A:B=1:3). In other words, Figure 6 ΔV1 and ΔV2 in the description of A can be replaced by equations 7 and 8.

[0145] [Formula 7]

[0146]

[0147] [Formula 8]

[0148]

[0149] Therefore, the potential of the node FD2 is lower than the potential of the wiring VFR by ΔV2-ΔV1. Here, if equation 9 is satisfied, ΔV2-ΔV1=2αIG is satisfied (see equation 10), and thus the potential of the node FD2 is a potential dependent on the G component of the incident light W.

[0150] [Formula 9]

[0151]

[0152] [Formula 10]

[0153]

[0154] Note that although the amount of light received is adjusted by adjusting the period in the above description, the amount of light received can also be adjusted by adjusting the light receiving area of ​​the photodiode. For example, by operating in a manner such that the light receiving area is PD1:PD2=1:3 and A:B=1:1, imaging data of G can be obtained.

[0155] The following structure can be adopted: the data of the wiring OUT is converted into digital data by the A / D conversion circuit in the readout circuit, and then the digital data is output as image data. Note that although a structure in which a differential operation is performed by a readout circuit outside the pixel can also be adopted, it is easy to extend the exposure time by performing the differential operation within the pixel.

[0156] In addition, it is preferred that a transistor including an oxide semiconductor having excellent off-state current is used as part or all of the transistors constituting the pixel. By using this transistor, a pixel with high charge retention characteristics can be formed. In the above structure, it is easy to maintain subtraction data, and thus the above structure is suitable for performing differential operations within the pixel.

[0157] In addition, when a transistor including an oxide semiconductor is used in a pixel circuit, the dynamic range of imaging can be expanded. Figure 1 In the circuit structure shown, when the intensity of light incident on the photodiodes 61 and 62 is high, the potential of the node FD1 is low. Since the off-state current of the transistor using an oxide semiconductor is extremely low, the current corresponding to the gate potential can be accurately output even if the gate potential is extremely low. As a result, the range of detectable illumination, that is, the dynamic range, can be expanded.

[0158] Since the transistor containing the oxide semiconductor has the characteristic of small off-state current, the charge of the node FD1 and the node FD2 can be maintained for a very long time. Therefore, a global shutter method can be applied, in which the circuit structure or working method is not complicated to apply the charge storage work in all pixels at the same time. Therefore, even when the subject is a moving object, an image with less distortion can be easily obtained. In addition, by adopting the global shutter method, the exposure time (the period for the charge storage work) can also be extended, which is suitable for imaging in low-light environments.

[0159] In addition, transistors for controlling the potential of nodes FD1 and FD2 are required to have low noise. The channel of the transistor using the two or three oxide semiconductor layers described later is a buried channel, and the transistor has extremely high noise resistance. Therefore, by using this transistor, an image with low noise can be obtained.

[0160] According to one embodiment of the present invention, imaging data of each component of R, G, and B can be obtained from the incident light W. Note that, although the above description shows a method of obtaining G by differential detection using a spectroscopic element that separates R and B, a method of obtaining B by differential detection using a spectroscopic element that separates R and G may also be adopted. In addition, a method of obtaining R by differential detection using a spectroscopic element that separates B and G may also be adopted.

[0161] In addition, if Fig.40 As shown in A, the pixel circuit of the imaging device which can be used in one embodiment of the present invention may also have an embodiment in which a photoelectric conversion unit is constituted by one circuit 31. In this case, by Figure 1 The circuit operation is described in which the light irradiated to PD1 and the light irradiated to PD2 are alternately irradiated to Fig.40 PD1 shown in A can obtain imaging data of each color.

[0162] In addition, a structure in which the photoelectric conversion unit includes three or more circuits may also be adopted. Fig.40 In the pixel circuit shown in B, the photoelectric conversion unit includes a circuit 31 , a circuit 32 , and a circuit 34 , and the circuit 34 includes a photodiode 63 ( PD3 ), a transistor 58 , and a transistor 59 .

[0163] In addition, if Figure 7 As shown in A, in a pixel circuit of an imaging device that can be used in one embodiment of the present invention, the connection direction of the photodiode can also be different from Figure 1 In this case, the wiring VPD is at a high potential, the wiring VPR is at a low potential, the wiring VC is at a low potential, the wiring VFR is at a high potential, and the wiring VO is at a high potential.

[0164] The operation of the pixels used to obtain R and B imaging data can be compared with Figure 6 The timing diagram shown in A has the same input signal, and the potentials of FD1 and FD2 are as follows Figure 7 At time T7, the potential of node FD2 is higher than the potential of wiring VFR by ΔV2-ΔV1. In order to obtain the imaging data of G, Figure 6 The timing diagram of B is the same. Figure 7 In the timing chart of B, the period from time T6 to time T7 may be set to three times the period from time T2 to time T3. Alternatively, the light receiving area of ​​the photodiode may be set to PD1:PD2=1:3.

[0165] In addition, if Figure 8 As shown, the pixel circuit of the imaging device that can be used in one embodiment of the present invention can also be formed from Figure 1 The circuit shown in the figure is a structure without transistors 51 and 53. In this case, the wiring VC is at a low potential, the wiring VFR is at a high potential, and the wiring VO is at a high potential. In addition, the wiring PR can also be used as a power supply line.

[0166] In this case, by setting the wiring PR to a high potential, the node FD1 can be reset. When the wiring PR is set to a high potential during a predetermined period, PD1 and PD2 are forward biased. During this period, by setting TX1 and TX2 to "H", the node FD1 can be set to the potential of the wiring PR. In addition, when the wiring PR is set to a low potential during a predetermined period, PD1 and PD2 are reverse biased. During this period, the accumulation operation can be performed by setting TX1 and TX2 to "H". In addition, in these operations, Figure 6 A and Figure 6 B shows the timing diagram.

[0167] In addition, if Fig.41 As shown in A, Figure 8 The structure of the pixel circuit shown in FIG. 1 may also use one circuit 31 to constitute the photoelectric conversion unit. Fig.41 As shown in B, three or more circuits may be used to constitute the photoelectric conversion unit.

[0168] In addition, as an arrangement of pixels for obtaining the above-mentioned R, G, and B imaging data, for example, Fig. 9 A and Fig. 9 The method shown in B. Fig. 9 A and Fig. 9B shows an example of a top surface method of 3×3 pixels, and there is no restriction on the order of RGB. In the pixel used to obtain the imaging data of R and B, PD1 is set on the lower side of the symbol of the spectroscopic element. In addition, in the pixel used to obtain the imaging data of G, PD2 is set on the lower side of the symbol of the spectroscopic element.

[0169] Alternatively, a structure may be adopted in which any one of the R, G, and B components is separated using a color filter. Fig. 9 C is an example, which is a method of providing a color filter (R) on a pixel for obtaining imaging data of R. Alternatively, a configuration may be adopted in which any two components of R, G, and B are separated using a color filter. Fig. 9 D is an example of a method of providing a color filter (R) and a color filter (G) respectively on pixels for obtaining imaging data of R and G. By adopting the above structure, it is easy to manufacture the spectroscopic element or the color filter, thereby easily achieving miniaturization and low cost.

[0170] Note that although Fig. 9 A to Fig. 9 D shows a method of arranging RGB in the vertical direction, but it is also possible to adopt a method of arranging RGB in the horizontal direction. Fig. 9 As shown in E, a structure including pixels with half a pitch offset may also be used. Fig. 9 The structure of E can also be applied to a structure including a color filter.

[0171] Fig.10 A shows an example of a cross-sectional view of an imaging device including a circuit unit. The circuit unit 90 is a combination of a transistor 51 having an active region in a silicon substrate and a transistor 52 using an oxide semiconductor as an active layer, and can constitute, for example, an inverter circuit or a memory circuit. The circuit unit 92 is a combination of a photodiode 60 formed using a silicon substrate 40 and a transistor 56 using an oxide semiconductor as an active layer, and can constitute, for example, Figure 1 The circuit 31 or the circuit 32 shown, etc. Note that the wiring and the contact plug indicated by the dotted line indicate that the position in the depth direction is different from other wirings and contact plugs.

[0172] Here, the circuit unit 92 corresponds to Figure 1 The photodiode 60 is a part of the photoelectric conversion unit shown in FIG. Figure 1 The photodiode 61 or the photodiode 62 shown. In addition, the transistor 56 is equivalent to Figure 1 The transistor 51 or the transistor 53 is shown.

[0173] exist Fig.10In A, the photodiode 60 and the transistor 56 can be formed overlapping each other, so the integration of pixels can be improved. In other words, the resolution of the imaging device can be improved. In addition, no transistor is formed in the silicon substrate 40 in the area occupied by the circuit portion 92, so the area of ​​the photodiode can be expanded. Therefore, an image with less noise can be obtained even in a low-light environment.

[0174] Notice, Fig.10 A and Fig.10 B shows a structure in which the photodiode 60 and the transistor 51 are formed using the same silicon substrate 40, but the present invention is not limited thereto. For example, the transistor 51 may be formed using the silicon substrate 40, and a photodiode formed using another substrate may be bonded to the transistor 51. Alternatively, the transistor 51 may be formed without using the silicon substrate 40, and a transistor using an oxide semiconductor as an active layer may be used as the transistor 51, similarly to the transistor 52 and the transistor 56. Fig.10 As shown in FIG. 2B , transistors 51, 52, and 56 (transistor 52 is not shown) can be provided using silicon substrate 40. Elements other than transistor 51 can also be formed using silicon substrate 40. For example, capacitors, diodes, resistors, and the like can be formed using silicon substrate 40.

[0175] In addition, when Fig.10 When the structure shown in A includes the transistor 51 and the photodiode 60 , an insulating layer 80 is provided between the transistor 52 and the transistor 56 .

[0176] The hydrogen in the insulating layer disposed near the active region of the transistor 51 terminates the dangling bonds of silicon. Therefore, the hydrogen has the effect of improving the reliability of the transistor 51. On the other hand, the hydrogen in the insulating layer disposed near the oxide semiconductor layer of the active layer of the transistor 52, the transistor 56, etc. becomes one of the main reasons for the generation of carriers in the oxide semiconductor. Therefore, the hydrogen is likely to cause a decrease in the reliability of the transistor 52, the transistor 56, etc. Therefore, when stacking a layer including a transistor using a silicon-based semiconductor material and another layer including a transistor using an oxide semiconductor, it is preferred to provide an insulating layer 80 having a function of preventing hydrogen diffusion therebetween. By providing the insulating layer 80 to enclose hydrogen in one layer, the reliability of the transistor 51 can be improved. At the same time, since it is possible to suppress the diffusion of hydrogen from one layer to another, the reliability of the transistor 52, the transistor 56, etc. can be improved at the same time.

[0177] The insulating layer 80 can be made of, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like.

[0178] The silicon substrate 40 is not limited to a bulk silicon substrate, and an SOI substrate may be used. In addition, a substrate made of germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used instead of the silicon substrate 40 .

[0179] Note that the transistor 51 is not limited to a planar transistor and various types of transistors may be used, such as a FIN type transistor, a TRI-GATE type transistor, or the like.

[0180] Depending on circumstances, the transistor 56 may include various semiconductors other than an oxide semiconductor, and may include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like.

[0181] like Fig.11 A1 and Fig.11 As shown in B1, the imaging device can be bent. Fig.11 A1 shows a state in which the imaging device is bent in the direction of a two-dot chain line X1 - X2 in the figure. Fig.11 A2 is along Fig.11 This is a cross-sectional view of a portion indicated by a two-dot chain line X1 - X2 in A1. Fig.11 A3 is along Fig.11 This is a cross-sectional view of a portion indicated by a two-dot chain line Y1 - Y2 in A1 .

[0182] Fig.11 B1 shows a state in which the imaging device is bent in the direction of the two-dot chain line X3 - X4 in the figure and in the direction of the two-dot chain line Y3 - Y4 in the figure. Fig.11 B2 is along Fig.11 This is a cross-sectional view of a portion indicated by a two-dot chain line X3 - X4 in B1. Fig.11 B3 is along Fig.11 This is a cross-sectional view of a portion indicated by a two-dot chain line Y3 - Y4 in B1 .

[0183] By bending the imaging device, field curvature or astigmatism can be reduced. Therefore, the optical design of the lens used in combination with the imaging device can be made easier. For example, since the number of lenses used for aberration correction can be reduced, the miniaturization or lightweight of the semiconductor device using the imaging device can be easily achieved. In addition, the quality of the imaged image can be improved.

[0184] Note that in this embodiment, one mode of the present invention is described. Alternatively, in other embodiments, one mode of the present invention will be described. Note that one mode of the present invention is not limited to these. For example, although an example of applying one mode of the present invention to an imaging device is shown, one mode of the present invention is not limited to this. In some cases, or depending on the circumstances, one mode of the present invention may not be applied to an imaging device. For example, one mode of the present invention may be applied to a semiconductor device having other functions.

[0185] This embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0186] Implementation Method 2

[0187] In this embodiment, an example of a method for driving a pixel circuit is described.

[0188] As described in Embodiment 1, the operation of the pixel circuit is to repeat the resetting operation, the accumulation operation, and the selection operation. As an imaging method for controlling the entire pixel matrix, a global shutter method and a rolling shutter method are known.

[0189] Fig.12 This is a timing diagram when using the global shutter method. Fig.12 In the embodiment, a plurality of pixel circuits are provided in a matrix and a plurality of pixel circuits are provided in the pixel circuits. Figure 1 Taking the imaging device of the circuit shown in FIG. 1 as an example, the operation of the pixel circuits in the first row to the nth row (n is a natural number greater than or equal to 3) will be described.

[0190] exist Fig.12 , signals 501, 502, and 503 are signals input to the wiring PR connected to each pixel circuit in the first row, the second row, and the nth row. In addition, signals 504, 506, and 508 are signals input to the wiring TX1 connected to each pixel circuit in the first row, the second row, and the nth row. In addition, signals 505, 507, and 509 are signals input to the wiring TX2 connected to each pixel circuit in the first row, the second row, and the nth row. In addition, signals 510, 511, and 512 are signals input to the wiring SEL connected to each pixel circuit in the first row, the second row, and the nth row.

[0191] In addition, period 515 is the period required for one shooting. Period 516 is the period during which the pixel circuits of each row simultaneously perform the reset operation and the accumulation operation. The pixel circuits of each row perform the selection operation in sequence. As an example, period 517 is the period during which the pixel circuits of the first row perform the selection operation. In this way, in the global shutter method, the reset operation and the accumulation operation are performed in all pixel circuits at approximately the same time, and the readout operation is performed in sequence by row.

[0192] That is, in the global shutter method, since the accumulation operation is performed in all pixel circuits at substantially the same time, the simultaneity of imaging in the pixel circuits of each row is ensured, so that even if the subject is a moving object, an image with less distortion can be obtained.

[0193] on the other hand, Fig.13 This is a timing diagram for the case where the rolling shutter method is used. For signals 501 to 512, refer to Fig.10 A and Fig.10 B. Period 615 is the period required for one shooting. Period 621 is the period during which the pixels of the first row perform reset work and accumulation work. Period 622 is the period during which the pixels of the second row perform reset work and accumulation work. Period 623 is the period during which the pixels of the nth row perform reset work and accumulation work. In addition, period 617 is the period during which the pixel circuits of the first row perform selection work. As described above, in the rolling shutter method, since the accumulation work is not performed simultaneously in all pixel circuits but is performed sequentially row by row, the simultaneity of imaging between the pixel circuits of each row cannot be ensured. Therefore, the timing of imaging in the first row and the final row is different, and thus the distortion of the image becomes larger when a moving object is the shooting object.

[0194] In order to realize the global shutter method, it is necessary to maintain the potential of the charge accumulation section (FD2) for a long time until the readout of the signal from each pixel is completed. By using a transistor whose channel formation region is formed of an oxide semiconductor and whose off-state current is extremely small as the transistor 55, etc., the potential of the charge accumulation section (FD2) can be maintained for a long time. On the other hand, when a transistor whose channel formation region is formed of silicon or the like is used as the transistor 55, etc., the potential of the charge accumulation section (FD2) cannot be maintained for a long time due to the large off-state current, and therefore the global shutter method cannot be used.

[0195] As described above, by using a transistor whose channel formation region is formed of an oxide semiconductor in a pixel circuit, a global shutter method can be easily realized.

[0196] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes as appropriate.

[0197] Implementation 3

[0198] In this embodiment, a transistor including an oxide semiconductor which can be used as one embodiment of the present invention is described with reference to drawings. In the drawings of this embodiment, some components are enlarged, reduced, or omitted for clarity.

[0199] Fig.14 A and Fig.14 B is a top view and a cross-sectional view of the transistor 101 according to one embodiment of the present invention. Fig.14A is the top view, Fig.14 The cross section in the direction of the dotted line B1-B2 shown in A is equivalent to Fig.14 B. In addition, Fig.14 The cross section in the direction of the dotted line B3-B4 shown in A is equivalent to Fig. 20 A. In addition, the direction of the dashed line B1 - B2 is sometimes referred to as the channel length direction, and the direction of the dashed line B3 - B4 is sometimes referred to as the channel width direction.

[0200] The transistor 101 includes an insulating layer 120 in contact with a substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, a conductive layer 140 and a conductive layer 150 electrically connected to the oxide semiconductor layer 130, an insulating layer 160 in contact with the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 in contact with the conductive layer 140, the conductive layer 150, the insulating layer 160, and the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. In addition, the insulating layer 180 may be provided with a function of a planarization film as necessary.

[0201] Here, the conductive layer 140, the conductive layer 150, the insulating layer 160, and the conductive layer 170 can function as a source electrode layer, a drain electrode layer, a gate insulating film, and a gate electrode layer, respectively.

[0202] also, Fig.14 Region 231, region 232, and region 233 shown in B can be used as a source region, a drain region, and a channel formation region, respectively. Region 231 is in contact with conductive layer 140, and region 232 is in contact with conductive layer 150. By using a conductive material that easily bonds with oxygen as conductive layer 140 and conductive layer 150, the resistance of region 231 and region 232 can be reduced.

[0203] Specifically, since the oxide semiconductor layer 130 is in contact with the conductive layers 140 and 150 , oxygen vacancies are generated in the oxide semiconductor layer 130 . The interaction between the oxygen vacancies and hydrogen remaining in the oxide semiconductor layer 130 or diffused from the outside causes the regions 231 and 232 to become low-resistance n-type.

[0204] In addition, the functions of the "source" and "drain" of a transistor are sometimes interchanged when using transistors with different polarities or when the direction of current changes during circuit operation. Therefore, in this specification, "source" and "drain" can be interchanged. In addition, "electrode layer" can also be called "wiring".

[0205] In addition, although the example in which the conductive layer 170 is formed of two layers of the conductive layer 171 and the conductive layer 172 is shown, a stacked layer of one layer or three or more layers may be used. The same can be applied to the other transistors described in this embodiment.

[0206] In addition, although the conductive layer 140 and the conductive layer 150 are examples of single layers, two or more layers may be stacked. The same can be applied to other transistors described in this embodiment.

[0207] Furthermore, a transistor according to one embodiment of the present invention may also be configured as Fig.15 A and Fig.15 The structure shown in B. Fig.15 A is a top view of transistor 102, Fig.15 The cross section in the direction of the dotted line C1-C2 shown in A is equivalent to Fig.15 B. In addition, Fig.15 The cross section in the direction of the dotted line C3-C4 shown in A is equivalent to Fig. 20 B. In addition, the direction of the dashed line C1 - C2 is sometimes referred to as the channel length direction, and the direction of the dashed line C3 - C4 is sometimes referred to as the channel width direction.

[0208] The transistor 102 has the same structure as the transistor 101 except that an end of an insulating layer 160 serving as a gate insulating film is not aligned with an end of a conductive layer 170 serving as a gate electrode layer. In the transistor 102, since wider portions of the conductive layers 140 and 150 are covered with the insulating layer 160, resistance between the conductive layers 140, 150, and 170 is high, and thus the transistor 102 has a feature of small gate leakage current.

[0209] The transistor 101 and the transistor 102 have a top gate structure having a region where the conductive layer 170 overlaps with the conductive layer 140 and the conductive layer 150. In order to reduce parasitic capacitance, the width of the region in the channel length direction is preferably set to be greater than 3 nm and less than 300 nm. On the other hand, since the bias region is not formed in the oxide semiconductor layer 130, it is easy to form a transistor with a large on-state current.

[0210] Furthermore, a transistor according to one embodiment of the present invention may also be configured as Fig.16 A and Fig.16 The structure shown in B. Fig.16 A is a top view of transistor 103, Fig.16 The cross section in the direction of the dotted line D1-D2 shown in A is equivalent to Fig.16 B. In addition, Fig.16 The cross section in the direction of the dotted line D3-D4 shown in A is equivalent to Fig. 20 A. In addition, the direction of the dashed line D1 - D2 is sometimes referred to as the channel length direction, and the direction of the dashed line D3 - D4 is sometimes referred to as the channel width direction.

[0211] The transistor 103 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, an insulating layer 160 in contact with the oxide semiconductor layer 130, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and conductive layers 140 and 150 electrically connected to the oxide semiconductor layer 130 via openings provided in the insulating layers 175 and 180. In addition, an insulating layer (planarization film) in contact with the insulating layer 180, the conductive layer 140, and the conductive layer 150 may be included as necessary.

[0212] Here, the conductive layer 140, the conductive layer 150, the insulating layer 160, and the conductive layer 170 can function as a source electrode layer, a drain electrode layer, a gate insulating film, and a gate electrode layer, respectively.

[0213] also, Fig.16 Region 231, region 232, and region 233 shown in B can be used as a source region, a drain region, and a channel formation region, respectively. Region 231 and region 232 are in contact with insulating layer 175. For example, by using an insulating material containing hydrogen as insulating layer 175, the resistance of region 231 and region 232 can be reduced.

[0214] Specifically, the interaction between oxygen vacancies generated in regions 231 and 232 through the process until the insulating layer 175 is formed and hydrogen diffused from the insulating layer 175 into regions 231 and 232 causes regions 231 and 232 to become low-resistance n-type. In addition, as an insulating material containing hydrogen, for example, a silicon nitride film, an aluminum nitride film, or the like can be used.

[0215] Furthermore, a transistor according to one embodiment of the present invention may also be configured as Fig.17 A and Fig.17 The structure shown in B. Fig.17 A is a top view of transistor 104, Fig.17 The cross section in the direction of the dotted line E1-E2 shown in A is equivalent to Fig.17 B. In addition, Fig.17 The cross section in the direction of the dotted line E3-E4 shown in A is equivalent to Fig. 20 A. In addition, the direction of the dashed line E1-E2 is sometimes referred to as the channel length direction, and the direction of the dashed line E3-E4 is sometimes referred to as the channel width direction.

[0216] The transistor 104 has the same structure as the transistor 103 except that the conductive layer 140 and the conductive layer 150 overlap with and are in contact with the end of the oxide semiconductor layer 130 .

[0217] also, Fig.17Region 331 and region 334 shown in B can be used as source regions, region 332 and region 335 can be used as drain regions, and region 333 can be used as a channel formation region. The resistance of region 331 and region 332 can be reduced in the same manner as region 231 and region 232 in transistor 101. In addition, the resistance of region 334 and region 335 can be reduced in the same manner as region 231 and region 232 in transistor 103. In addition, when the length of region 334 and region 335 in the channel length direction is 100 nm or less, preferably 50 nm or less, the gate electric field helps prevent the on-state current from decreasing significantly, so a structure without the above-mentioned low resistance can also be adopted.

[0218] The transistor 103 and the transistor 104 have a self-aligned structure in which the conductive layer 170 does not overlap with the conductive layer 140 and the conductive layer 150. A transistor having a self-aligned structure has extremely small parasitic capacitance between a gate electrode layer and a source electrode layer and a drain electrode layer, and is therefore suitable for high-speed operation.

[0219] Furthermore, a transistor according to one embodiment of the present invention may also be configured as Fig.18 A and Fig.18 The structure shown in B. Fig.18 A is a top view of transistor 105, Fig.18 The cross section in the direction of the dotted line F1-F2 shown in A is equivalent to Fig.18 B. In addition, Fig.18 The cross section in the direction of the dotted line F3-F4 shown in A is equivalent to Fig. 20 A. In addition, the direction of the dashed line F1 - F2 is sometimes referred to as the channel length direction, and the direction of the dashed line F3 - F4 is sometimes referred to as the channel width direction.

[0220] The transistor 105 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, a conductive layer 141 and a conductive layer 151 electrically connected to the oxide semiconductor layer 130, an insulating layer 160 in contact with the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 in contact with the oxide semiconductor layer 130, the conductive layer 141, the conductive layer 151, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and conductive layers 142 and 152 electrically connected to the conductive layer 141 and the conductive layer 151, respectively, via openings provided in the insulating layers 175 and 180. Insulating layers in contact with the insulating layer 180, the conductive layer 142, and the conductive layer 152 may be provided as necessary.

[0221] Here, the conductive layer 141 and the conductive layer 151 are in contact with the top surface of the oxide semiconductor layer 130 but are not in contact with the side surface.

[0222] The transistor 105 has the same structure as the transistor 101, except that it includes conductive layers 141 and 151, openings provided in the insulating layers 175 and 180, and conductive layers 142 and 152 electrically connected to the conductive layers 141 and 151, respectively, through the openings. The conductive layer 140 (the conductive layer 141 and the conductive layer 142) can be used as a source electrode layer, and the conductive layer 150 (the conductive layer 151 and the conductive layer 152) can be used as a drain electrode layer.

[0223] Furthermore, a transistor according to one embodiment of the present invention may also be configured as Fig.19 A and Fig.19 The structure shown in B. Fig.19 A is a top view of transistor 106, Fig.19 The cross section in the direction of the dotted line G1-G2 shown in A is equivalent to Fig.19 B. In addition, Fig.19 The cross section in the direction of the dotted line G3-G4 shown in A is equivalent to Fig. 20 A. In addition, the direction of the dashed line G1 - G2 is sometimes referred to as a channel length direction, and the direction of the dashed line G3 - G4 is sometimes referred to as a channel width direction.

[0224] The transistor 106 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, a conductive layer 141 and a conductive layer 151 electrically connected to the oxide semiconductor layer 130, an insulating layer 160 in contact with the oxide semiconductor layer 130, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 in contact with the insulating layer 120, the oxide semiconductor layer 130, the conductive layer 141, the conductive layer 151, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and conductive layers 142 and 152 electrically connected to the conductive layers 141 and 151, respectively, via openings provided in the insulating layers 175 and 180. In addition, an insulating layer (planarization film) or the like in contact with the insulating layer 180, the conductive layer 142, and the conductive layer 152 may be provided as necessary.

[0225] Here, the conductive layer 141 and the conductive layer 151 are in contact with the top surface of the oxide semiconductor layer 130 but are not in contact with the side surface.

[0226] The transistor 106 has the same structure as the transistor 103 except that it includes the conductive layer 141 and the conductive layer 151. The conductive layer 140 (the conductive layer 141 and the conductive layer 142) can be used as a source electrode layer, and the conductive layer 150 (the conductive layer 151 and the conductive layer 152) can be used as a drain electrode layer.

[0227] In the transistor 105 and the transistor 106 , since the conductive layer 140 and the conductive layer 150 are not in contact with the insulating layer 120 , oxygen in the insulating layer 120 is not easily taken away by the conductive layer 140 and the conductive layer 150 , and oxygen can be easily supplied from the insulating layer 120 to the oxide semiconductor layer 130 .

[0228] In addition, impurities for forming oxygen vacancies to improve conductivity may be added to the regions 231 and 232 in the transistor 103 and the regions 334 and 335 in the transistor 104 and the transistor 106. As impurities for forming oxygen vacancies in the oxide semiconductor layer, for example, one or more selected from phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon can be used. As a method for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

[0229] By adding the above-mentioned elements as impurity elements to the oxide semiconductor layer, the bond between the metal element and oxygen in the oxide semiconductor layer is cut off, forming an oxygen vacancy. The conductivity of the oxide semiconductor layer can be improved by the interaction between the oxygen vacancy contained in the oxide semiconductor layer and the hydrogen remaining in the oxide semiconductor layer or added later.

[0230] In addition, when hydrogen is added to an oxide semiconductor having oxygen vacancies formed by adding an impurity element, hydrogen enters the oxygen vacancies and forms a donor level near the conduction band. As a result, an oxide conductor can be formed. In addition, the oxide conductor here refers to an oxide semiconductor that has been made into a conductor.

[0231] The oxide conductor is a degenerate semiconductor, and it can be inferred that the end of its conduction band is consistent or approximately consistent with the Fermi level. Therefore, an ohmic contact is obtained between the oxide conductor layer and the conductive layer used as the source electrode layer and the drain electrode layer, and the contact resistance between the oxide conductor layer and the conductive layer used as the source electrode layer and the drain electrode layer can be reduced.

[0232] In addition, if Fig.21 A to Fig.21 The cross-sectional view of F along the channel length direction and Fig. 20 C and Fig. 20 As shown in the cross-sectional view of the channel width direction of D, the transistor of one embodiment of the present invention may also include a conductive layer 173 between the oxide semiconductor layer 130 and the substrate 115. By using this conductive layer as a second gate electrode layer (back gate), the on-state current can be further increased or the threshold voltage can be controlled. Fig.21 A to Fig.21In the cross-sectional view shown in F, the width of the conductive layer 173 may be smaller than that of the oxide semiconductor layer 130. Furthermore, the width of the conductive layer 173 may be smaller than that of the conductive layer 170.

[0233] When the on-state current is to be increased, for example, the same potential may be supplied to the conductive layer 170 and the conductive layer 173 to realize a dual-gate transistor. In addition, when the threshold voltage is to be controlled, a constant potential different from that of the conductive layer 170 may be supplied to the conductive layer 173. In order to supply the same potential to the conductive layer 170 and the conductive layer 173, for example, Fig. 20 As shown in D, the conductive layer 170 and the conductive layer 173 can be electrically connected through the contact hole.

[0234] In addition, Fig.14 A to Fig.19 In the transistors 101 to 106 of FIG. 1B , the oxide semiconductor layer 130 is an example in which the oxide semiconductor layer 130 is a single layer. However, the oxide semiconductor layer 130 may be a stacked layer. Fig. 22 A to Fig. 22 C or Fig.23 A to Fig.23 The oxide semiconductor layer 130 shown in C is replaced.

[0235] Fig. 22 A to Fig. 22 C is a top view and a cross-sectional view of the oxide semiconductor layer 130 having a two-layer structure. Fig. 22 A is the top view, Fig. 22 The cross section in the direction of the dotted line A1-A2 shown in A is equivalent to Fig. 22 B. In addition, Fig. 22 The cross section in the direction of the dotted line A3-A4 shown in A is equivalent to Fig. 22 C.

[0236] Fig.23 A to Fig.23 C is a top view and a cross-sectional view of the oxide semiconductor layer 130 having a three-layer structure. Fig.23 A is the top view, Fig.23 The cross section in the direction of the dotted line A1-A2 shown in A is equivalent to Fig.23 B. In addition, Fig.23 The cross section in the direction of the dotted line A3-A4 shown in A is equivalent to Fig.23 C.

[0237] As the oxide semiconductor layer 130 a , the oxide semiconductor layer 130 b , and the oxide semiconductor layer 130 c , oxide semiconductor layers having different compositions from each other or the like can be used.

[0238] Furthermore, a transistor according to one embodiment of the present invention may also be configured as Fig.24 A and Fig.24 The structure shown in B. Fig.24 A is a top view of transistor 107, Fig.24 The cross section in the direction of the dotted line H1-H2 shown in A is equivalent to Fig.24 B. In addition, Fig.24 The cross section in the direction of the dotted line H3-H4 shown in A is equivalent to Fig.30 A. In addition, the direction of the dashed line H1 - H2 is sometimes referred to as the channel length direction, and the direction of the dashed line H3 - H4 is sometimes referred to as the channel width direction.

[0239] The transistor 107 includes an insulating layer 120 in contact with a substrate 115, a stack of oxide semiconductor layers 130a and 130b in contact with the insulating layer 120, a conductive layer 140 and a conductive layer 150 electrically connected to the stack, an oxide semiconductor layer 130c in contact with the stack, the conductive layer 140, and the conductive layer 150, an insulating layer 160 in contact with the oxide semiconductor layer 130c, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 in contact with the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. The insulating layer 180 may also function as a planarizing film as necessary.

[0240] The structure of transistor 107 is the same as that of transistor 101 except that the oxide semiconductor layer 130 is composed of two layers (oxide semiconductor layer 130a and oxide semiconductor layer 130b) in regions 231 and 232, the oxide semiconductor layer 130 is composed of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in region 233, and a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is sandwiched between the conductive layer 140 and the conductive layer 150 and the insulating layer 160.

[0241] Furthermore, a transistor according to one embodiment of the present invention may also be configured as Fig.25 A and Fig.25 The structure shown in B. Fig.25 A is a top view of transistor 108, Fig.25 The cross section in the direction of the dotted line I1-I2 shown in A is equivalent to Fig.25 B. In addition, Fig.25 The cross section in the direction of the dotted line I3-I4 shown in A is equivalent to Fig.30 B. In addition, the direction of the dashed line I1 - I2 is sometimes referred to as the channel length direction, and the direction of the dashed line I3 - I4 is sometimes referred to as the channel width direction.

[0242] The transistor 108 is different from the transistor 107 in that the ends of the insulating layer 160 and the oxide semiconductor layer 130 c are not aligned with the end of the conductive layer 170 .

[0243] Furthermore, a transistor according to one embodiment of the present invention may also be configured as Fig.26 A and Fig.26 The structure shown in B. Fig.26 A is a top view of transistor 109, Fig.26 The cross section in the direction of the dotted line J1-J2 shown in A is equivalent to Fig.26 B. In addition, Fig.26 The cross section in the direction of the dotted line J3-J4 shown in A is equivalent to Fig.30 A. In addition, the direction of the dashed line J1 - J2 is sometimes referred to as the channel length direction, and the direction of the dashed line J3 - J4 ​​is sometimes referred to as the channel width direction.

[0244] The transistor 109 includes an insulating layer 120 in contact with the substrate 115, a stack of oxide semiconductor layers 130a and 130b in contact with the insulating layer 120, an oxide semiconductor layer 130c in contact with the stack, an insulating layer 160 in contact with the oxide semiconductor layer 130c, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 covering the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and conductive layers 140 and 150 electrically connected to the stack via openings provided in the insulating layers 175 and 180. In addition, an insulating layer (planarization film) in contact with the insulating layer 180, the conductive layer 140, and the conductive layer 150 may be included as necessary.

[0245] The structure of transistor 109 is the same as that of transistor 103 except that the oxide semiconductor layer 130 is composed of two layers (oxide semiconductor layer 130a and oxide semiconductor layer 130b) in regions 231 and 232 and the oxide semiconductor layer 130 is composed of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c) in region 233.

[0246] Furthermore, a transistor according to one embodiment of the present invention may also be configured as Fig. 27 A and Fig. 27 The structure shown in B. Fig. 27 A is a top view of transistor 110, Fig. 27 The cross section in the direction of the dotted line K1-K2 shown in A is equivalent to Fig. 27 B. In addition, Fig. 27 The cross section in the direction of the dotted line K3-K4 shown in A is equivalent to Fig.30A. In addition, the direction of the dashed line K1 - K2 is sometimes referred to as the channel length direction, and the direction of the dashed line K3 - K4 is sometimes referred to as the channel width direction.

[0247] The structure of the transistor 110 is the same as that of the transistor 104 except that the oxide semiconductor layer 130 is composed of two layers (oxide semiconductor layer 130a and oxide semiconductor layer 130b) in regions 231 and 232 and the oxide semiconductor layer 130 is composed of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c) in region 233.

[0248] Furthermore, a transistor according to one embodiment of the present invention may also be configured as Fig.28 A and Fig.28 The structure shown in B. Fig.28 A is a top view of transistor 111, Fig.28 The cross section in the direction of the dotted line L1-L2 shown in A is equivalent to Fig.28 B. In addition, Fig.28 The cross section in the direction of the dotted line L3-L4 shown in A is equivalent to Fig.30 A. In addition, the direction of the dashed line L1 - L2 is sometimes referred to as the channel length direction, and the direction of the dashed line L3 - L4 is sometimes referred to as the channel width direction.

[0249] The transistor 111 includes an insulating layer 120 in contact with a substrate 115, a stack formed of an oxide semiconductor layer 130a and an oxide semiconductor layer 130b in contact with the insulating layer 120, a conductive layer 141 and a conductive layer 151 electrically connected to the stack, an oxide semiconductor layer 130c in contact with the stack, the conductive layer 141, and the conductive layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130c, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 in contact with the stack, the conductive layer 141, the conductive layer 151, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and a conductive layer 142 and a conductive layer 152 electrically connected to the conductive layer 141 and the conductive layer 151, respectively, through openings provided in the insulating layer 175 and the insulating layer 180. In addition, an insulating layer (planarization film) or the like which is in contact with the insulating layer 180 , the conductive layer 142 , and the conductive layer 152 may be included as necessary.

[0250] The structure of the transistor 111 is the same as that of the transistor 105, except that the oxide semiconductor layer 130 is composed of two layers (oxide semiconductor layer 130a and oxide semiconductor layer 130b) in regions 231 and 232, the oxide semiconductor layer 130 is composed of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in region 233, and a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is sandwiched between the conductive layer 141 and the conductive layer 151 and the insulating layer 160.

[0251] Furthermore, a transistor according to one embodiment of the present invention may also be configured as Fig.29 A and Fig.29 The structure shown in B. Fig.29 A is a top view of transistor 112, Fig.29 The cross section in the direction of the dotted line M1-M2 shown in A is equivalent to Fig.29 B. In addition, Fig.29 The cross section in the direction of the dotted line M3-M4 shown in A is equivalent to Fig.30 A. In addition, the direction of the dashed line M1 - M2 is sometimes referred to as the channel length direction, and the direction of the dashed line M3 - M4 is sometimes referred to as the channel width direction.

[0252] The structure of the transistor 112 is the same as that of the transistor 106 except that the oxide semiconductor layer 130 is composed of two layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in regions 331, 332, 334 and 335, and the oxide semiconductor layer 130 is composed of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in region 333.

[0253] In addition, if Fig.31 A to Fig.31 The cross-sectional view of F along the channel length direction and Fig.30 C and Fig.30 As shown in the cross-sectional view of the channel width direction of D, the transistor of one embodiment of the present invention may also include a conductive layer 173 between the oxide semiconductor layer 130 and the substrate 115. By using this conductive layer as a second gate electrode layer (back gate), the on-state current can be further increased or the threshold voltage can be controlled. Fig.31 A to Fig.31 In the cross-sectional view shown in F, the width of the conductive layer 173 may be smaller than that of the oxide semiconductor layer 130. Furthermore, the width of the conductive layer 173 may be smaller than that of the conductive layer 170.

[0254] In the conductive layer 140 (source electrode layer) and the conductive layer 150 (drain electrode layer) in the transistor of one embodiment of the present invention, Fig.32 A and Fig.32As shown in the top view shown in FIG. 1B (only the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150 are shown), the widths (W SD ) may be greater than the width of the oxide semiconductor layer (W OS ) is large or small. When W is satisfied OS ≥W SD (W SD W OS When the relationship is as follows, the gate electric field is easily applied to the entire oxide semiconductor layer 130, which can improve the electrical characteristics of the transistor.

[0255] In any structure of the transistor (transistor 101 to transistor 109) of one embodiment of the present invention, the conductive layer 170 as a gate electrode layer electrically surrounds the oxide semiconductor layer 130 in the channel width direction via the insulating layer 160 as a gate insulating film, thereby increasing the on-state current. This transistor structure is called a surrounded channel (s-channel) structure.

[0256] In a transistor having an oxide semiconductor layer 130b and an oxide semiconductor layer 130c and a transistor having an oxide semiconductor layer 130a, an oxide semiconductor layer 130b and an oxide semiconductor layer 130c, by appropriately selecting the materials constituting the two or three layers of the oxide semiconductor layer 130, current can flow through the oxide semiconductor layer 130b. Since the current flows through the oxide semiconductor layer 130b, it is not easily affected by interface scattering, so a large on-state current can be obtained. In addition, by increasing the thickness of the oxide semiconductor layer 130b, the on-state current can be increased. For example, the thickness of the oxide semiconductor layer 130b can also be set to 100nm to 200nm.

[0257] By using the transistor having the above structure, a semiconductor device can have good electrical characteristics.

[0258] Note that in this specification, for example, the channel length refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap or the region where the channel is formed in the top view of the transistor. In addition, in a transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of a transistor is sometimes not limited to one value. Therefore, in this specification, the channel length is any value, maximum value, minimum value, or average value in the region where the channel is formed.

[0259] For example, the channel width refers to the length of the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is in the on state) overlaps with the gate electrode or the portion where the source and drain are opposite in the region where the channel is formed. In addition, in a transistor, the channel width does not necessarily have the same value in all regions. In other words, the channel width of a transistor is sometimes not limited to one value. Therefore, in this specification, the channel width is any value, maximum value, minimum value or average value in the region where the channel is formed.

[0260] In addition, in some transistor structures, the channel width in the area where the channel is actually formed (hereinafter referred to as the effective channel width) is sometimes different from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in the case where the gate electrode covers the side of the semiconductor, sometimes the effective channel width is larger than the apparent channel width, so its influence cannot be ignored. For example, in a miniature transistor with a gate electrode covering the side of the semiconductor, sometimes the proportion of the channel area formed on the side of the semiconductor is larger than the proportion of the channel area formed on the top surface of the semiconductor. In this case, the effective channel width is larger than the apparent channel width.

[0261] In the above case, it is sometimes difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width based on the design value, it is necessary to know the shape of the semiconductor in advance as an assumption. Therefore, when the shape of the semiconductor is unclear, it is difficult to accurately measure the effective channel width.

[0262] Therefore, in this specification, the apparent channel width is sometimes referred to as the "surrounded channel width (SCW)". In addition, in this specification, when simply expressing "channel width", it sometimes refers to the surrounded channel width or the apparent channel width. Alternatively, in this specification, when simply expressing "channel width", it sometimes refers to the effective channel width. Note that the values ​​of the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0263] When calculating the field effect mobility of a transistor or the current value per channel width, the calculation may be performed using the actual channel width. In this case, the value may be different from the value calculated using the effective channel width.

[0264] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0265] Implementation 4

[0266] In this embodiment, components of the transistor described in Embodiment 5 are described in detail.

[0267] The substrate 115 includes a silicon substrate on which a transistor and / or a photodiode are formed, and an insulating layer, wiring, and a conductor used as a contact plug formed on the silicon substrate. In addition, when a p-channel transistor is formed using a silicon substrate, it is preferable to use an n-channel transistor. - Alternatively, a silicon substrate having an n - The SOI substrate of the type or i-type silicon layer. In addition, it is preferable that the crystal plane orientation of the surface where the transistor is formed in the silicon substrate is (110) plane. By forming a p-channel transistor on the (110) plane, the mobility can be improved.

[0268] In addition to the function of preventing impurities from diffusing from the constituent elements included in the substrate 115, the insulating layer 120 may also have the function of supplying oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, the insulating layer 120 is a film having an oxygen release amount converted to oxygen atoms of 1.0×10 obtained by a TDS (Thermal Desorption Spectroscopy) method during a heat treatment at a film surface temperature of 100° C. to 700° C., preferably 100° C. to 500° C. 19 atoms / cm 3 The insulating layer 120 also has the function of an interlayer insulating film, and may be planarized by a CMP (Chemical Mechanical Polishing) method or the like to make its surface flat.

[0269] For example, an oxide insulating film such as aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, a nitride insulating film such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride, or a mixed material of these oxides can be used as the insulating layer 120. Alternatively, a stack of the above materials can be used.

[0270] In this embodiment, the detailed description is mainly based on the case where the oxide semiconductor layer 130 included in the transistor has a three-layer structure in which an oxide semiconductor layer 130 a , an oxide semiconductor layer 130 b , and an oxide semiconductor layer 130 c are stacked in this order from the insulating layer 120 side.

[0271] In addition, when the oxide semiconductor layer 130 is a single layer, a layer corresponding to the oxide semiconductor layer 130 b described in this embodiment may be used.

[0272] When the oxide semiconductor layer 130 is a two-layer structure, a layer corresponding to the oxide semiconductor layer 130b and a layer corresponding to the oxide semiconductor layer 130c described in this embodiment may be stacked in this order from the insulating layer 120. When this structure is used, the oxide semiconductor layer 130b and the oxide semiconductor layer 130c may be swapped.

[0273] When the oxide semiconductor layer 130 has four or more layers, for example, a structure in which another oxide semiconductor layer is added to the three-layer structure of the oxide semiconductor layer 130 described in this embodiment mode.

[0274] For example, the oxide semiconductor layer 130b uses an oxide semiconductor having a greater electron affinity (energy difference between the vacuum level and the bottom of the conduction band) than the oxide semiconductor layer 130a and the oxide semiconductor layer 130c. The electron affinity is a value obtained by subtracting the energy difference (energy gap) between the bottom of the conduction band and the top of the valence band from the energy difference (ionization potential) between the vacuum level and the top of the valence band.

[0275] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c preferably contain one or more metal elements constituting the oxide semiconductor layer 130b. For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are preferably formed using an oxide semiconductor whose conduction band bottom energy is closer to the vacuum level by 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV and less than 2 eV, 1 eV, 0.5 eV, or 0.4 eV than the conduction band bottom energy of the oxide semiconductor layer 130b.

[0276] In the above structure, when an electric field is applied to the conductive layer 170 , a channel is formed in the oxide semiconductor layer 130 b having the lowest energy at the bottom of the conduction band among the oxide semiconductor layers 130 .

[0277] In addition, the oxide semiconductor layer 130a contains one or more metal elements constituting the oxide semiconductor layer 130b, so it is not easy to form an interface energy level at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a compared to the interface between the oxide semiconductor layer 130b and the insulating layer 120 when the two are in contact. The above-mentioned interface energy level sometimes forms a channel, and thus sometimes causes a change in the threshold voltage of the transistor. Therefore, by providing the oxide semiconductor layer 130a, the deviation of electrical characteristics such as the threshold voltage of the transistor can be suppressed. In addition, the reliability of the transistor can be improved.

[0278] In addition, the oxide semiconductor layer 130c contains one or more metal elements constituting the oxide semiconductor layer 130b, and therefore, carrier scattering is less likely to occur at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c than at the interface between the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) when the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact. Therefore, by providing the oxide semiconductor layer 130c, the field effect mobility of the transistor can be improved.

[0279] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c can use the following materials: materials containing Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce or Hf and the atomic number ratio of the element is higher than that of the oxide semiconductor layer 130b. Specifically, the atomic number ratio of the above elements is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more of that of the oxide semiconductor layer 130b. The above elements are firmly bonded to oxygen, so they have the function of suppressing the generation of oxygen vacancies in the oxide semiconductor layer. It can be said that compared with the oxide semiconductor layer 130b, it is difficult to generate oxygen vacancies in the oxide semiconductor layer 130a and the oxide semiconductor layer 130c.

[0280] In addition, the oxide semiconductor that can be used for the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c preferably contains at least In or Zn. Alternatively, it is preferred to contain both In and Zn. In addition, in order to reduce the deviation of the electrical characteristics of the transistor using the oxide semiconductor, in addition to the above elements, it is preferred to further contain a stabilizer.

[0281] As the stabilizer, Ga, Sn, Hf, Al or Zr can be mentioned. In addition, as other stabilizers, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu of lanthanide elements can be mentioned.

[0282] For example, as an oxide semiconductor, indium oxide, tin oxide, gallium oxide, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In- Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide.

[0283] Note that, for example, In-Ga-Zn oxide refers to an oxide containing In, Ga, and Zn as main components. In addition, it may also contain metal elements other than In, Ga, and Zn. In addition, in this specification, a film composed of In-Ga-Zn oxide is referred to as an IGZO film.

[0284] Alternatively, you can use InMO 3 (ZnO) m (m>0, and m is not an integer). Note that M represents one or more metal elements selected from Ga, Y, Zr, La, Ce, or Nd. In addition, In 2 SnO 5 (ZnO) n (n>0, and n is an integer) represented material.

[0285] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are In-M-Zn oxides containing at least indium, zinc, and M (M is a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf), and the atomic ratio of the oxide semiconductor layer 130a is In:M:Zn=x. 1 :y 1 :z 1 The atomic ratio of the oxide semiconductor layer 130b is In:M:Zn=x 2 :y2 :z 2 The atomic ratio of the oxide semiconductor layer 130c is In:M:Zn=x 3: y 3: z 3 In the case of 1 / x 1 and 3 / x 3 Preferably greater than y 2 / x 2 .y 1 / x 1 and 3 / x 3 for y 2 / x 2 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. In this case, in the oxide semiconductor layer 130b, 2 For x 2 In the above case, the electrical characteristics of the transistor can be stabilized. 2 For x 2 When the field effect mobility of the transistor decreases, y 2 Preferably less than x 2 3 times.

[0286] The atomic percentages of In and M other than Zn and O in the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are preferably such that the ratio of In is less than 50 atomic % and the ratio of M is greater than 50 atomic %, and more preferably such that the ratio of In is less than 25 atomic % and the ratio of M is greater than 75 atomic %. In addition, the atomic percentages of In and M other than Zn and O in the oxide semiconductor layer 130b are preferably such that the ratio of In is greater than 25 atomic % and the ratio of M is less than 75 atomic %, and more preferably such that the ratio of In is greater than 34 atomic % and the ratio of M is less than 66 atomic %.

[0287] In addition, it is preferred that the indium content of the oxide semiconductor layer 130b is higher than that of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c. In oxide semiconductors, the s orbital of a heavy metal mainly contributes to carrier conduction, and the overlap of the s orbitals is increased by increasing the ratio of In, so that the mobility of an oxide having a ratio of In greater than M is higher than that of an oxide having a ratio of In equal to or less than M. Therefore, by using an oxide having a high indium content for the oxide semiconductor layer 130b, a transistor having a high field effect mobility can be realized.

[0288] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, and more preferably 5 nm or more and 25 nm or less. In addition, the thickness of the oxide semiconductor layer 130b is 3 nm or more and 200 nm or less, preferably 10 nm or more and 150 nm or less, and more preferably 15 nm or more and 100 nm or less. In addition, the thickness of the oxide semiconductor layer 130c is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, and more preferably 3 nm or more and 15 nm or less. In addition, the oxide semiconductor layer 130b is preferably thicker than the oxide semiconductor layer 130a and the oxide semiconductor layer 130c.

[0289] In addition, in order to provide a transistor using an oxide semiconductor layer as a channel with stable electrical characteristics, it is effective to reduce the impurity concentration in the oxide semiconductor layer so that the oxide semiconductor layer becomes intrinsic (i-type) or substantially intrinsic. Here, “substantially intrinsic” means that the carrier density of the oxide semiconductor layer is less than 1×10 17 / cm 3 , less than 1×10 15 / cm 3 , or less than 1×10 13 / cm 3 .

[0290] In addition, for the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main components are impurities. For example, hydrogen and nitrogen cause the formation of donor energy levels, thereby increasing the carrier density. In addition, silicon causes the formation of impurity energy levels in the oxide semiconductor layer. The impurity energy levels become traps, which may degrade the electrical characteristics of the transistor. Therefore, it is preferred to reduce the impurity concentration in the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c or at the interface of each layer.

[0291] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, the silicon concentration estimated by SIMS (Secondary Ion Mass Spectrometry) analysis is controlled to be less than 1×10 19 atoms / cm 3 , preferably less than 5×10 18 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 In addition, the hydrogen concentration is controlled so that it has a value of 2×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 In addition, for example, at a certain depth of the oxide semiconductor layer or in a certain region of the oxide semiconductor layer, the nitrogen concentration is preferably less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0292] If silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer may be reduced. In order to prevent the reduction of the crystallinity of the oxide semiconductor layer, for example, the silicon concentration is controlled to be less than 1×10 19 atoms / cm 3 , preferably less than 5×10 18 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 In addition, the carbon concentration is controlled to have a value lower than 1×10 19 atoms / cm 3 , preferably less than 5×10 18 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 area.

[0293] In addition, the off-state current of a transistor using a highly purified oxide semiconductor film as described above for a channel formation region is extremely small. For example, the off-state current per channel width of the transistor can be reduced to several yA / μm to several zA / μm when the voltage between the source and the drain is about 0.1V, 5V or 10V.

[0294] In addition, as the gate insulating film of the transistor, an insulating film containing silicon is mostly used, so it is preferred that the region of the oxide semiconductor layer used as a channel is not in contact with the gate insulating film as in the transistor of one embodiment of the present invention. In addition, when the channel is formed at the interface between the gate insulating film and the oxide semiconductor layer, carrier scattering occurs at the interface and the field effect mobility of the transistor is reduced. From the above viewpoint, it can be said that it is preferred to separate the region of the oxide semiconductor layer used as a channel from the gate insulating film.

[0295] Therefore, by making the oxide semiconductor layer 130 have a stacked-layer structure of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, a channel can be formed in the oxide semiconductor layer 130b, thereby forming a transistor having high field effect mobility and stable electrical characteristics.

[0296] In the energy band structure of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, the energy of the conduction band bottom changes continuously. This can also be understood from the fact that the compositions of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b and the oxide semiconductor layer 130c are similar to each other, and oxygen easily diffuses among the above three. Therefore, it can be said that although the oxide semiconductor layer 130a, the oxide semiconductor layer 130b and the oxide semiconductor layer 130c are stacked bodies with different compositions, they are continuous in physical properties. Therefore, in the accompanying drawings, the interfaces of the stacked oxide semiconductor layers are represented by dotted lines.

[0297] The stacked oxide semiconductor layers 130 having the same main component are not simply stacked, but are formed in a manner that forms a continuous combination (here, in particular, a U-shaped well structure in which the energy of the conduction band bottom between the layers changes continuously). In other words, the stacked structure is formed in a manner that there are no impurities that form defect energy levels such as capture centers or recombination centers between the interfaces of the layers. If impurities are mixed between the layers of the stacked oxide semiconductor layers, the energy band loses continuity, so that carriers are captured or recombinated at the interface and disappear.

[0298] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c may use In-Ga-Zn oxide with In:Ga:Zn=1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4, or 1:9:6 (atomic ratio), and the oxide semiconductor layer 130b may use In-Ga-Zn oxide with In:Ga:Zn=1:1:1, 2:1:3, 5:5:6, or 3:1:2 (atomic ratio). The atomic ratios of the oxide semiconductor layers 130a, 130b, and 130c include a variation of ±20% of the atomic ratio as an error.

[0299] The oxide semiconductor layer 130b in the oxide semiconductor layer 130 is used as a well, and a channel is formed in the oxide semiconductor layer 130b. In addition, the energy of the conduction band bottom of the oxide semiconductor layer 130 changes continuously, so the oxide semiconductor layer 130 can also be called a U-shaped well. In addition, the channel having the above structure can also be called a buried channel.

[0300] In addition, although trap energy levels caused by impurities or defects may be formed between the oxide semiconductor layer 130a and an insulating layer such as a silicon oxide film and near the interface between the oxide semiconductor layer 130c and an insulating layer such as a silicon oxide film, the oxide semiconductor layer 130b can be separated from the trap energy levels by providing the oxide semiconductor layer 130a and the oxide semiconductor layer 130c.

[0301] Note that when the energy difference between the energy of the conduction band bottom of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c and the energy of the conduction band bottom of the oxide semiconductor layer 130b is small, electrons in the oxide semiconductor layer 130b may exceed the energy difference and reach a trap level. When electrons are captured by the trap level, negative charges are generated at the insulating layer interface, causing the threshold voltage of the transistor to drift in the positive direction.

[0302] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c preferably include a crystal portion. In particular, by using c-axis oriented crystals, stable electrical characteristics can be imparted to the transistor. In addition, c-axis oriented crystals are resistant to bending, thereby improving the reliability of a semiconductor device using a flexible substrate.

[0303] As the conductive layer 140 used as the source electrode layer and the conductive layer 150 used as the drain electrode layer, for example, a single layer or a stack of materials selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and alloys of these metal materials can be used. Typically, it is particularly preferred to use Ti that is easy to bond with oxygen or W with a high melting point that can be processed at a higher temperature later. In addition, a stack of low-resistance Cu or Cu-Mn alloys and the above materials can also be used. In addition, in the transistor 105, the transistor 106, the transistor 111, and the transistor 112, for example, W can be used as the conductive layer 141 and the conductive layer 151, and a stack of Ti and Al can be used as the conductive layer 142 and the conductive layer 152.

[0304] The above-mentioned material has the property of extracting oxygen from the oxide semiconductor layer. As a result, in a region of a portion of the oxide semiconductor layer in contact with the above-mentioned material, oxygen in the oxide semiconductor layer is desorbed, and an oxygen vacancy is formed in the oxide semiconductor layer. A trace amount of hydrogen contained in the layer is bonded to the oxygen vacancy to make the region n-type. Therefore, the n-type region can be used as a source or drain of a transistor.

[0305] As the insulating layer 160 used as a gate insulating film, an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be used. In addition, the insulating layer 160 may also be a stack of the above materials. In addition, the insulating layer 160 may also contain La, nitrogen, Zr, etc. as impurities.

[0306] In addition, an example of a stacked-layer structure of the insulating layer 160 will be described. The insulating layer 160 contains, for example, oxygen, nitrogen, silicon, hafnium, etc. Specifically, it is preferable that the insulating layer 160 contains hafnium oxide and silicon oxide or hafnium oxide and silicon oxynitride.

[0307] The relative dielectric constants of hafnium oxide and aluminum oxide are higher than those of silicon oxide and silicon oxynitride. Therefore, the insulating layer 160 using hafnium oxide or aluminum oxide can have a thickness greater than that of the insulating layer 160 using silicon oxide, thereby reducing the leakage current caused by the tunnel current. That is, a transistor with a small off-state current can be realized. Furthermore, compared with hafnium oxide including an amorphous structure, hafnium oxide including a crystalline structure has a high relative dielectric constant. Therefore, in order to form a transistor with a small off-state current, it is preferred to use hafnium oxide including a crystalline structure. As examples of crystalline structures, monoclinic system or cubic system can be cited. However, one embodiment of the present invention is not limited to this.

[0308] In addition, the insulating layer 120 and the insulating layer 160 that are in contact with the oxide semiconductor layer 130 may also have a region with a low energy level density of nitride oxide. As the oxide insulating layer with a low energy level density of nitride oxide, a silicon oxynitride film with a small amount of nitride oxide released or an aluminum oxynitride film with a small amount of nitride oxide released can be used.

[0309] The silicon oxynitride film with low nitrogen oxide release is a film that releases more ammonia than nitrogen oxide in thermal desorption spectroscopy (TDS). Typically, the ammonia release is 1×10 18 Pieces / cm 3 Above and 5×10 19 Pieces / cm 3 The ammonia release amount is a release amount obtained by heat treatment at a membrane surface temperature of 50° C. to 650° C., preferably 50° C. to 550° C.

[0310] By using the above-described oxide insulating layer as the insulating layer 120 and the insulating layer 160 , a drift in the threshold voltage of the transistor can be reduced, thereby reducing variations in the electrical characteristics of the transistor.

[0311] As the conductive layer 170 used as the gate electrode layer, for example, a conductive film of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, and W can be used. In addition, an alloy of the above materials or a conductive nitride of the above materials can also be used. In addition, a stack of multiple materials selected from the above materials, the alloy of the above materials, and the conductive nitride of the above materials can also be used. Typically, tungsten, a stack of tungsten and titanium nitride, a stack of tungsten and tantalum nitride, etc. can be used. In addition, low-resistance alloys such as Cu or Cu-Mn, or a stack of the above materials and alloys such as Cu or Cu-Mn can also be used. In this embodiment, tantalum nitride is used as the conductive layer 171, and tungsten is used as the conductive layer 172 to form the conductive layer 170.

[0312] A silicon nitride film or an aluminum nitride film containing hydrogen can be used as the insulating layer 175. In the transistor 103, the transistor 104, the transistor 106, the transistor 109, the transistor 110, and the transistor 112 described in Embodiment 2, a portion of the oxide semiconductor layer can be made n-type by using an insulating film containing hydrogen as the insulating layer 175. In addition, the nitride insulating film also functions as a film that blocks moisture and the like, and can improve the reliability of the transistor.

[0313] An aluminum oxide film can also be used as the insulating layer 175. In particular, it is preferable to use an aluminum oxide film as the insulating layer 175 in the transistor 101, the transistor 102, the transistor 105, the transistor 107, the transistor 108, and the transistor 111 shown in Embodiment 2. The aluminum oxide film has a high barrier effect of preventing impurities such as hydrogen and water and oxygen from passing through. Therefore, the aluminum oxide film is suitable for use as a protective film having the following effects: preventing impurities such as hydrogen and water from mixing into the oxide semiconductor layer 130 during the manufacturing process of the transistor and after the manufacturing of the transistor; preventing the release of oxygen from the oxide semiconductor layer; and preventing the unnecessary release of oxygen from the insulating layer 120. In addition, the oxygen contained in the aluminum oxide film can also be diffused into the oxide semiconductor layer.

[0314] An insulating layer 180 is preferably formed on the insulating layer 175. As the insulating layer, an insulating film containing one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be used. In addition, the insulating layer can also be a stacked layer of the above materials.

[0315] Here, the insulating layer 180 preferably contains more oxygen than the stoichiometric composition, similarly to the insulating layer 120. Oxygen released from the insulating layer 180 can diffuse into the channel formation region of the oxide semiconductor layer 130 through the insulating layer 160, and thus oxygen vacancies formed in the channel formation region can be filled with oxygen. Thus, stable transistor electrical characteristics can be obtained.

[0316] In order to realize high integration of semiconductor devices, miniaturization of transistors is necessary. On the other hand, it is known that the electrical characteristics of transistors deteriorate with miniaturization of transistors. In particular, shortening of channel width leads to reduction of on-state current.

[0317] In the transistors 107 to 112 of one embodiment of the present invention, the oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b in which the channel is formed, and the channel forming layer is not in contact with the gate insulating film. Therefore, carrier scattering generated at the interface between the channel forming layer and the gate insulating film can be suppressed, and the on-state current of the transistor can be increased.

[0318] In the transistor of one embodiment of the present invention, as described above, the gate electrode layer (conductive layer 170) is formed so as to electrically surround the oxide semiconductor layer 130 in the channel width direction, so that the gate electric field is applied to the oxide semiconductor layer 130 in a direction perpendicular to the side surface in addition to the direction perpendicular to the top surface. In other words, the gate electric field is applied to the entire channel formation layer to increase the effective channel width, thereby further increasing the on-state current.

[0319] In a transistor having a two-layer or three-layer structure in an embodiment of the present invention, the oxide semiconductor layer 130b in which a channel is formed is formed on the oxide semiconductor layer 130a to efficiently suppress the generation of interface energy levels. In addition, in a transistor having a three-layer structure in an embodiment of the present invention, the oxide semiconductor layer 130b is located in the middle of the three-layer structure to simultaneously eliminate the effects of impurities mixed from above and below. Therefore, in addition to increasing the on-state current of the above-mentioned transistor, the stabilization of the threshold voltage and the decrease of the S value (subthreshold) can also be achieved. Therefore, Icut (the current when the gate voltage VG is 0V) can be reduced, and power consumption can be reduced. In addition, since the threshold voltage of the transistor is stable, the long-term reliability of the semiconductor device can be improved. In addition, the transistor in one embodiment of the present invention can suppress the degradation of electrical characteristics caused by miniaturization, so it can be said that it is suitable for semiconductor devices with high integration.

[0320] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0321] Implementation method 5

[0322] In this embodiment, a method for manufacturing the transistor 101 and the transistor 107 described in Embodiment 3 is described.

[0323] First, a method for manufacturing a silicon transistor included in the substrate 115 is described. Here, a method for manufacturing a p-channel transistor is described as an example. - A single crystal silicon substrate is formed on the surface of which a device formation region is separated by an insulating layer (also called a field oxide film). The device isolation region can be formed using a LOCOS method (Local Oxidation of Silicon) or an STI method (Shallow Trench Isolation).

[0324] Here, the substrate is not limited to a single crystal silicon substrate, and an SOI (Silicon on Insulator) substrate or the like may be used.

[0325] Next, a gate insulating film is formed to cover the element formation region. For example, a silicon oxide film can be formed by oxidizing the surface of the element formation region by heat treatment. Alternatively, a nitridation treatment can be performed after the silicon oxide film is formed to nitride the surface of the silicon oxide film.

[0326] Next, a conductive film is formed in a manner covering the gate insulating film. As the conductive film, an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, Nb, etc., or an alloy material or compound material containing the above elements as a main component can be used. In addition, a metal nitride film obtained by nitriding the above elements can be used. In addition, a semiconductor material represented by polycrystalline silicon doped with impurity elements such as phosphorus can be used.

[0327] Next, the conductive film is selectively etched to form a gate electrode layer on the gate insulating film.

[0328] Next, an insulating film such as a silicon oxide film or a silicon nitride film is formed so as to cover the gate electrode layer, and etch-back is performed to form side walls on the side surfaces of the gate electrode layer.

[0329] Next, a resist mask is selectively formed to cover regions other than the element formation region, and an impurity element is introduced using the resist mask and the gate electrode layer as a mask to form a p-type gate electrode. + Here, in order to form a p-channel transistor, an impurity element imparting p-type conductivity, such as B or Ga, can be used as the impurity element.

[0330] Through the above steps, a p-channel transistor having an active region in a silicon substrate is completed. Note that it is preferable to form a passivation film such as a silicon nitride film or an aluminum oxide film on the transistor.

[0331] Next, an interlayer insulating film is formed on the silicon substrate on which the transistors are formed, and various contact plugs and various wirings are formed.

[0332] Next, use Fig.33 A to Fig.34 C describes a method for manufacturing the transistor 102. Note that the left side of the drawing shows a cross section of the transistor in the channel length direction, and the right side shows a cross section in the channel width direction. In addition, since the drawing in the channel width direction is an enlarged view, the apparent film thickness of each component is different between the drawing on the left and the drawing on the right.

[0333] The following is an example in which the oxide semiconductor layer 130 has a three-layer structure of an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c. When the oxide semiconductor layer 130 has a two-layer structure, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are used, and when the oxide semiconductor layer 130 has a single-layer structure, the oxide semiconductor layer 130b is used.

[0334] First, the insulating layer 120 is formed over the substrate 115. For the type of the substrate 115 and the material of the insulating layer 120, refer to the description of Embodiment 4. The insulating layer 120 can be formed by sputtering, CVD, MBE (Molecular Beam Epitaxy), or the like.

[0335] Alternatively, oxygen may be added to the insulating layer 120 by ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like. By adding oxygen, oxygen can be more easily supplied from the insulating layer 120 to the oxide semiconductor layer 130 .

[0336] In addition, when the surface of the substrate 115 is formed of an insulator and impurities do not diffuse into the oxide semiconductor layer 130 to be formed later, the insulating layer 120 may not be provided.

[0337] Next, an oxide semiconductor film 130A to be an oxide semiconductor layer 130a, an oxide semiconductor film 130B to be an oxide semiconductor layer 130b, and an oxide semiconductor film 130C to be an oxide semiconductor layer 130c are formed on the insulating layer 120 by a sputtering method, a CVD method, an MBE method, or the like (see Fig.33 A).

[0338] When the oxide semiconductor layer 130 has a stacked structure, it is preferred to use a multi-chamber film forming apparatus (e.g., a sputtering apparatus) equipped with a load lock chamber to continuously stack the layers without exposing them to the atmosphere. Preferably, each chamber in the sputtering apparatus can be evacuated to a high vacuum (evacuated to 5×10 -7 Pa to 1×10 -4Pa) and the substrate is heated to above 100°C, preferably above 500°C, to remove water, etc., which are impurities for the oxide semiconductor as much as possible. In addition, it is preferred to combine a turbomolecular pump and a cold trap to prevent the gas containing carbon components or water, etc. from flowing back into the chamber from the exhaust system. In addition, an exhaust system combining a turbomolecular pump and a cryopump may also be used.

[0339] In order to obtain a high-purity intrinsic oxide semiconductor, it is necessary not only to evacuate the chamber to a high vacuum, but also to purify the sputtering gas. By purifying the oxygen gas or argon gas used as the sputtering gas until the dew point is below -40°C, preferably below -80°C, and more preferably below -100°C, it is possible to prevent moisture and the like from mixing into the oxide semiconductor film as much as possible.

[0340] The oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C can be made of the materials described in Embodiment 4. When sputtering is used as a film formation method, the film can be formed using the materials described in Embodiment 4 as a target.

[0341] Note that as described in detail in Embodiment 4, a material having a higher electron affinity than those of the oxide semiconductor film 130A and the oxide semiconductor film 130C is selected as the oxide semiconductor film 130B.

[0342] When the oxide semiconductor film is formed, sputtering is preferably used. As the sputtering method, RF sputtering, DC sputtering, AC sputtering, or the like can be used.

[0343] The first heat treatment may also be performed after the oxide semiconductor film 130C is formed. The first heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. As a first heat treatment, a heat treatment in an inert gas atmosphere may be performed, and then a heat treatment in an atmosphere containing 10 ppm or more of an oxidizing gas may be performed to replenish the oxygen that has been separated. Through the first heat treatment, the crystallinity of the oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C may be improved, and impurities such as hydrogen or water may be removed from the insulating layer 120, the oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C. In addition, the first heat treatment may also be performed after the etching for forming the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c described later.

[0344] Next, a first conductive layer is formed over the oxide semiconductor film 130A. The first conductive layer can be formed using the following method, for example.

[0345] First, a first conductive film is formed over the oxide semiconductor film 130A. The first conductive film can be formed using a single layer or a stacked layer of a material selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and alloys thereof.

[0346] Next, a negative resist film is formed on the first conductive film, and the resist film is exposed by electron beam exposure, immersion exposure, EUV exposure or the like, and developed to form a first resist mask. In addition, an organic coating film is preferably formed between the first conductive film and the resist film as a sealant. Alternatively, the first resist mask may be formed by nanoimprinting.

[0347] Next, the first conductive film is selectively etched using the first resist mask, and the first resist mask is ashed, thereby forming a conductive layer.

[0348] Next, the oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C are selectively etched using the conductive layer as a hard mask to remove the conductive layer, thereby forming an oxide semiconductor layer 130 including a stack of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c (see Fig.33 B) Alternatively, the oxide semiconductor layer 130 may be formed using the first resist mask without forming the above-mentioned conductive layer. Here, oxygen ions may be implanted into the oxide semiconductor layer 130 .

[0349] Next, a second conductive film is formed to cover the oxide semiconductor layer 130. The second conductive film may be formed using a material that can be used for the conductive layer 140 and the conductive layer 150 described in Embodiment 6. The second conductive film can be formed by sputtering, CVD, MBE, or the like.

[0350] Next, a second resist mask is formed on the portions to be the source region and the drain region. A portion of the second conductive film is etched to form conductive layers 140 and 150 (see Fig.33 C).

[0351] Next, an insulating film 160A is formed over the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150. The insulating film 160A may be formed using a material that can be used for the insulating layer 160 described in Embodiment 4. The insulating film 160A can be formed by sputtering, CVD, MBE, or the like.

[0352] Next, a second heat treatment may be performed. The second heat treatment may be performed under the same conditions as the first heat treatment. The second heat treatment may diffuse the oxygen injected into the oxide semiconductor layer 130 to the entire oxide semiconductor layer 130. In addition, a third heat treatment may be performed to obtain the above-mentioned effect without performing the second heat treatment.

[0353] Next, a third conductive film 171A and a fourth conductive film 172A, which are to be the conductive layer 170, are formed over the insulating film 160A. The third conductive film 171A and the fourth conductive film 172A may be formed using a material that can be used for the conductive layer 171 and the conductive layer 172 described in Embodiment 4. The third conductive film 171A and the fourth conductive film 172A can be formed by a sputtering method, a CVD method, an MBE method, or the like.

[0354] Next, a third resist mask 156 is formed on the fourth conductive film 172A (see Fig.34 A). Then, the third conductive film 171A, the fourth conductive film 172A, and the insulating film 160A are selectively etched using the third resist mask 156 to form a conductive layer 170 and an insulating layer 160 including a conductive layer 171 and a conductive layer 172 (see FIG. Fig.34 B) In addition, when a structure is employed in which the insulating film 160A is not etched, the transistor 102 can be manufactured.

[0355] Next, an insulating layer 175 is formed over the oxide semiconductor layer 130, the conductive layer 140, the conductive layer 150, the insulating layer 160, and the conductive layer 170. The material of the insulating layer 175 can be referred to the description of Embodiment 3. An aluminum oxide film is preferably used in the transistor 101. The insulating layer 175 can be formed by a sputtering method, a CVD method, an MBE method, or the like.

[0356] Next, an insulating layer 180 is formed on the insulating layer 175 (see Fig.34 C) The material of the insulating layer 180 can be referred to Embodiment 4. In addition, the insulating layer 180 can be formed by a sputtering method, a CVD method, an MBE method, or the like.

[0357] Alternatively, oxygen may be added to the insulating layer 175 and / or the insulating layer 180 by ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like. By adding oxygen, oxygen can be more easily supplied from the insulating layer 175 and / or the insulating layer 180 to the oxide semiconductor layer 130.

[0358] Next, a third heat treatment may be performed. The third heat treatment may be performed under the same conditions as the first heat treatment. The third heat treatment facilitates the release of excess oxygen from the insulating layer 120 , the insulating layer 175 , and the insulating layer 180 , thereby reducing oxygen vacancies in the oxide semiconductor layer 130 .

[0359] Next, a description is given of a method for manufacturing the transistor 107. Note that a detailed description of the same steps as those of the method for manufacturing the transistor 101 described above will be omitted.

[0360] An insulating layer 120 is formed over the substrate 115, and an oxide semiconductor film 130A to be an oxide semiconductor layer 130a and an oxide semiconductor film 130B to be an oxide semiconductor layer 130b are formed over the insulating layer by sputtering, CVD, MBE, or the like (see Fig.35 A).

[0361] Next, a first conductive film is formed on the oxide semiconductor film 130B, and a conductive layer is formed using a first resist mask in the same manner as in the above method. Then, the oxide semiconductor film 130A and the oxide semiconductor film 130B are selectively etched using the conductive layer as a hard mask, and the conductive layer is removed to form a stacked layer consisting of the oxide semiconductor layer 130a and the oxide semiconductor layer 130b (see Fig.35 B) Alternatively, the stacked layers may be formed using a first resist mask without forming a hard mask. Here, oxygen ions may be implanted into the oxide semiconductor layer 130a and the oxide semiconductor layer 130b.

[0362] Next, a second conductive film is formed to cover the stacked layers. A second resist mask is formed on the portions to be the source region and the drain region, and a portion of the second conductive film is etched using the second resist mask to form conductive layers 140 and 150 (see Fig.35 C).

[0363] Next, an oxide semiconductor film 130C serving as the oxide semiconductor layer 130c is formed on the stack of the oxide semiconductor layers 130a and 130b and on the conductive layers 140 and 150. Furthermore, the insulating film 160A, the third conductive film 171A, and the fourth conductive film 172A are formed over the oxide semiconductor film 130C.

[0364] Next, a third resist mask 156 is formed on the fourth conductive film 172A (see Fig.36 A). The third conductive film 171A, the fourth conductive film 172A, the insulating film 160A, and the oxide semiconductor film 130C are selectively etched using the resist mask to form a conductive layer 170 including the conductive layer 171 and the conductive layer 172, the insulating layer 160, and the oxide semiconductor layer 130c (see Fig.36 B) At this time, if the insulating film 160A and the oxide semiconductor film 130C are etched using the fourth resist mask, the transistor 108 can be manufactured.

[0365] Next, insulating layers 175 and 180 are formed over the insulating layer 120, the oxide semiconductor layer 130 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c), the conductive layer 140, the conductive layer 150, the insulating layer 160, and the conductive layer 170 (see Fig.36 C).

[0366] Through the above steps, the transistor 107 can be manufactured.

[0367] Next, a description is given of a method for manufacturing the transistor 111. Note that a detailed description of the same steps as those of the method for manufacturing the transistor 102 described above will be omitted.

[0368] An insulating layer 120 is formed on the substrate 115, and an oxide semiconductor film 130A to be an oxide semiconductor layer 130a and an oxide semiconductor film 130B to be an oxide semiconductor layer 130b are formed on the insulating layer by sputtering, CVD, MBE, or the like. A first conductive film is formed on the oxide semiconductor film 130B, and a conductive layer 141a is formed using a first resist mask (see Fig.37 A).

[0369] Then, the oxide semiconductor film 130A and the oxide semiconductor film 130B are selectively etched using the conductive layer 141a as a hard mask to form a stacked layer including the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the conductive layer 141a (see Fig.37 B) Here, oxygen ions may be implanted into the oxide semiconductor layer 130a and the oxide semiconductor layer 130b.

[0370] Next, a second resist mask is formed on the portions to be the source region and the drain region, and a portion of the conductive layer 141a is etched using the second resist mask to form the conductive layer 141 and the conductive layer 151 (see Fig.37 C).

[0371] Next, an oxide semiconductor film 130C serving as the oxide semiconductor layer 130c is formed over the stack of the oxide semiconductor layers 130a and 130b and over the conductive layers 141 and 151. Furthermore, the insulating film 160A, the third conductive film 171A, and the fourth conductive film 172A are formed over the oxide semiconductor film 130C.

[0372] Next, a third resist mask 156 is formed on the fourth conductive film 172A (see Fig.38A). The third conductive film 171A, the fourth conductive film 172A, the insulating film 160A, and the oxide semiconductor film 130C are selectively etched using the resist mask to form a conductive layer 170 including the conductive layer 171 and the conductive layer 172, the insulating layer 160, and the oxide semiconductor layer 130c (see Fig.38 B).

[0373] Next, the insulating layer 175 and the insulating layer 180 are formed over the insulating layer 120 , the oxide semiconductor layer 130 (the oxide semiconductor layer 130 a , the oxide semiconductor layer 130 b , and the oxide semiconductor layer 130 c ), the conductive layer 140 , the conductive layer 150 , the insulating layer 160 , and the conductive layer 170 .

[0374] Next, openings reaching the conductive layers 141 and 151 are provided in the insulating layers 175 and 180, and a fifth conductive film is formed so as to cover the openings. A fourth resist mask is provided over the fifth conductive film, and the fifth conductive film is selectively etched using the resist mask to form the conductive layers 142 and 152 (see FIG. 1 ). Fig.38 C).

[0375] Through the above steps, the transistor 107 can be manufactured.

[0376] Note that, although various films such as the metal film, semiconductor film, and inorganic insulating film described in this embodiment can be typically formed by a sputtering method or a plasma CVD method, they can also be formed by other methods such as a thermal CVD method. Examples of thermal CVD methods include MOCVD (Metal Organic Chemical Vapor Deposition) method and ALD (Atomic Layer Deposition) method.

[0377] Since the thermal CVD method is a film forming method that does not use plasma, it has an advantage that defects due to plasma damage do not occur.

[0378] Film formation using the thermal CVD method can be performed by supplying a source gas and an oxidant simultaneously into a chamber, setting the pressure in the chamber to atmospheric pressure or reduced pressure, and causing a reaction near or on a substrate.

[0379] In addition, film formation using the ALD method can be performed in the following method: the pressure in the chamber is set to atmospheric pressure or reduced pressure, the source gas for the reaction is introduced into the chamber and reacted, and the gas is repeatedly introduced in this order. In addition, the source gas can also be introduced together with an inert gas (argon or nitrogen, etc.) as a carrier gas. For example, two or more source gases can also be supplied to the chamber in sequence. At this time, an inert gas is introduced after the first source gas reacts, and then a second source gas is introduced to prevent multiple source gases from mixing. Alternatively, the first source gas can be discharged by vacuum pumping without introducing an inert gas, and then the second source gas is introduced. The first source gas adheres to the surface of the substrate and reacts to form a first layer, and the second source gas introduced thereafter adheres and reacts, thereby stacking the second layer on the first layer to form a thin film. By repeatedly introducing the gas in this order until the desired thickness is obtained, a thin film with good step coverage can be formed. Since the thickness of the film can be adjusted according to the number of times the gas is repeatedly introduced, the ALD method can accurately adjust the thickness and is suitable for manufacturing micro FETs.

[0380] Various films such as metal films, semiconductor films, and inorganic insulating films disclosed in the above embodiments can be formed by thermal CVD methods such as MOCVD and ALD. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH 3 ) 3 ), trimethylgallium (Ga(CH 3 ) 3 ) and dimethyl zinc (Zn(CH 3 ) 2 ). Not limited to the above combination, triethylgallium (Ga(C 2 H 5 ) 3 ) instead of trimethylgallium and diethylzinc (Zn(C 2 H 5 ) 2 ) instead of dimethyl zinc.

[0381] For example, when a hafnium oxide film is formed using a film forming apparatus using the ALD method, the following two gases are used: a liquid containing a solvent and a hafnium precursor (hafnium alkoxide, tetrakis dimethylamide hafnium (TDMAH, Hf[N(CH 3 ) 2 ] 4 ) or hafnium amide such as tetra(ethylmethylamide) hafnium) gasified; and ozone (O 3 ).

[0382] For example, when an aluminum oxide film is formed using a film forming apparatus using the ALD method, the following two gases are used: a liquid containing a solvent and an aluminum precursor (trimethylaluminum (TMA, Al(CH 3 ) 3 ) etc.) gasified; and H used as an oxidant 2 O. Other materials include tris(dimethylamide)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione), and the like.

[0383] For example, when a silicon oxide film is formed using an ALD method, hexachlorodisilane is attached to the film-forming surface and an oxidizing gas (O 2 , nitrous oxide) to react with the attached substances.

[0384] For example, when a tungsten film is formed using an ALD film forming apparatus, WF 6 Gas and B 2 H 6 The gas forms the initial tungsten film, and then sequentially introduces WF 6 Gas and H 2 Gas to form a tungsten film. Note that SiH 4 Gas Replacement B 2 H 6 gas.

[0385] For example, when an oxide semiconductor film such as an In—Ga—Zn—O film is formed using a film forming apparatus using the ALD method, In(CH 3 ) 3 Gas and O 3 The gas forms an In-O layer, and then Ga(CH 3 ) 3 Gas and O 3 The gas forms a GaO layer, followed by the introduction of Zn(CH 3 ) 2 and O 3 The ZnO layer is formed by using the gases. Note that the order of these layers is not limited to the above example. In addition, these gases can also be used to form mixed compound layers such as In-Ga-O layers, In-Zn-O layers, Ga-Zn-O layers, etc. Note that although H obtained by bubbling with an inert gas such as Ar can also be used, 2 O gas replaces O 3 gas, but preferably O containing no H 3 gas.

[0386] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0387] Implementation 6

[0388] Next, the structure of an oxide semiconductor film that can be used in one embodiment of the present invention is described.

[0389] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included.

[0390] In this specification, the hexagonal crystal system includes the trigonal crystal system and the rhombohedral crystal system.

[0391] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Non-single-crystal oxide semiconductor films include CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) films, polycrystalline oxide semiconductor films, microcrystalline oxide semiconductor films, and amorphous oxide semiconductor films.

[0392] First, the CAAC-OS film is described.

[0393] The CAAC-OS film is one of oxide semiconductor films including a plurality of c-axis-aligned crystal parts.

[0394] In the composite analysis image (also called high-resolution TEM image) of the bright field image and diffraction pattern of the CAAC-OS film observed using a transmission electron microscope (TEM), multiple crystal parts are observed. However, even in the high-resolution TEM image, the boundary between the crystal parts, i.e., the grain boundary, is not observed. Therefore, it can be said that the reduction of electron mobility due to the grain boundary is not likely to occur in the CAAC-OS film.

[0395] When a high-resolution TEM image of a cross section of the CAAC-OS film is observed from a direction roughly parallel to the sample surface, it is observed that metal atoms are arranged in layers in the crystal part. Each metal atom layer has a shape that reflects the convex and concave shape of the surface forming the CAAC-OS film (also referred to as the formed surface) or the top surface of the CAAC-OS film and is arranged in a manner parallel to the formed surface or the top surface of the CAAC-OS film.

[0396] On the other hand, high-resolution TEM images of the plane of the CAAC-OS film observed from a direction substantially perpendicular to the sample surface show that metal atoms are arranged in a triangular or hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0397] The CAAC-OS film is structurally analyzed using an X-ray diffraction (XRD) device. For example, when the out-of-plane method is used to analyze the structure of InGaZnO 4 When the CAAC-OS film is made of a crystal, a peak appears when the diffraction angle (2θ) is around 31°. This peak originates from the InGaZnO 4 From the (009) plane of the crystal, it can be seen that the crystal in the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the top surface of the CAAC-OS film.

[0398] Note that when using the out-of-plane method to analyze the InGaZnO 4 In the case of a crystallized CAAC-OS film, in addition to a peak at 2θ of 31°, a peak at 2θ of 36° is sometimes observed. A peak at 2θ of 36° means that a portion of the CAAC-OS film contains crystals that do not have a c-axis orientation. Preferably, in the CAAC-OS film, a peak appears at 2θ of 31° and no peak appears at 2θ of 36°.

[0399] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities refer to elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements such as silicon have a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film, and thus become the main factor that disrupts the atomic arrangement of the oxide semiconductor film and reduces the crystallinity by taking oxygen from the oxide semiconductor film. In addition, heavy metals such as iron or nickel, argon, carbon dioxide, etc., because of their large atomic radius (molecular radius), become the main factor that disrupts the atomic arrangement of the oxide semiconductor film and reduces the crystallinity when contained in the oxide semiconductor film. Note that impurities contained in the oxide semiconductor film sometimes become carrier traps or carrier generation sources.

[0400] In addition, the CAAC-OS film is an oxide semiconductor film with a low defect state density. For example, oxygen vacancies in the oxide semiconductor film may become carrier traps or may become carrier generation sources by capturing hydrogen.

[0401] The state of low impurity concentration and low defect state density (small number of oxygen vacancies) is called "high-purity intrinsic" or "substantially high-purity intrinsic". The high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has fewer carrier generation sources and therefore can have a lower carrier density. Therefore, transistors using the oxide semiconductor film rarely have electrical characteristics of negative threshold voltage (also called normally-on characteristics). In addition, the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has fewer carrier traps. Therefore, the electrical characteristics of the transistor using the oxide semiconductor film vary little, making it a high-reliability transistor. In addition, it takes a long time for the charges captured by the carrier traps of the oxide semiconductor film to be released, and sometimes behaves like fixed charges. Therefore, the electrical characteristics of transistors using oxide semiconductor films with high impurity concentrations and high defect state density are sometimes unstable.

[0402] Furthermore, in a transistor using the CAAC-OS film, variation in electric characteristics due to irradiation with visible light or ultraviolet light is small.

[0403] Next, a microcrystalline oxide semiconductor film is described.

[0404] In the high-resolution TEM image of the microcrystalline oxide semiconductor film, there are areas where crystal parts are observed and areas where no clear crystal parts are observed. The size of the crystal parts contained in the microcrystalline oxide semiconductor film is mostly greater than 1 nm and less than 100 nm, or greater than 1 nm and less than 10 nm. In particular, the oxide semiconductor film of nanocrystalline (nc: nanocrystal) having microcrystals with a size of greater than 1 nm and less than 10 nm or greater than 1 nm and less than 3 nm is called nc-OS (nanocrystalline Oxide Semiconductor: nanocrystalline oxide semiconductor) film. In addition, for example, in the high-resolution TEM image of the nc-OS film, clear grain boundaries are not often observed.

[0405] The atomic arrangement of the nc-OS film is periodic in a tiny region (for example, a region between 1 nm and 10 nm, in particular, a region between 1 nm and 3 nm). In addition, the regularity of the crystal orientation is not observed between different crystalline parts of the nc-OS film. Therefore, no orientation is observed in the film as a whole. Therefore, sometimes the nc-OS film is no different from the amorphous oxide semiconductor film in some analysis methods. For example, when the nc-OS film is structurally analyzed by the out-of-plane method of an XRD device using an X-ray whose beam diameter is larger than the crystalline part, no peak representing the crystalline surface is detected. In addition, when the nc-OS film is subjected to electron diffraction (selected area electron diffraction) using an electron beam whose beam diameter is larger than the crystalline part (for example, more than 50 nm), a diffraction pattern similar to a halo pattern is observed. On the other hand, when the nc-OS film is subjected to nanobeam electron diffraction using an electron beam whose beam diameter is close to or smaller than the crystalline part, spots are observed. In addition, in the nanobeam electron diffraction pattern of the nc-OS film, spots distributed in a circular shape are sometimes observed. Furthermore, in the nanobeam electron diffraction pattern of the nc-OS film, a plurality of spots are sometimes observed in a ring-shaped region.

[0406] The nc-OS film is an oxide semiconductor film with higher regularity than the amorphous oxide semiconductor film. Therefore, the defect state density of the nc-OS film is lower than that of the amorphous oxide semiconductor film. However, the regularity of the crystal orientation is not observed between different crystal parts of the nc-OS film. Therefore, the defect state density of the nc-OS film is higher than that of the CAAC-OS film.

[0407] Next, the amorphous oxide semiconductor film is described.

[0408] An amorphous oxide semiconductor film is an oxide semiconductor film having a disordered atomic arrangement and having no crystalline part. An example thereof is an oxide semiconductor film in an amorphous state such as quartz.

[0409] In a high-resolution TEM image of an amorphous oxide semiconductor film, no crystal portion is observed.

[0410] The amorphous oxide semiconductor film was structurally analyzed using an XRD device. When analyzed using the out-of-plane method, no peak indicating the crystal plane was detected. In addition, a halo pattern was observed in the electron diffraction pattern of the amorphous oxide semiconductor film. In addition, in the nanobeam electron diffraction pattern of the amorphous oxide semiconductor film, no spots were observed, but a halo pattern was observed.

[0411] In addition, an oxide semiconductor film may have a structure showing physical properties between an nc-OS film and an amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly called an amorphous-like oxide semiconductor (amorphous-like OS: amorphous-like Oxide Semiconductor, amorphous oxide semiconductor) film.

[0412] In high-resolution TEM images of amorphous-like OS films, cavities (also called voids) are sometimes observed. In addition, in high-resolution TEM images, there are areas where crystals are clearly confirmed and areas where crystals are not confirmed. Amorphous-like OS films sometimes crystallize due to trace amounts of electron irradiation during TEM observation, and the growth of crystals is observed. On the other hand, in high-quality nc-OS films, crystallization due to trace amounts of electron irradiation during TEM observation is almost not observed.

[0413] In addition, the size of the crystal part of the amorphous-like OS film and the nc-OS film can be measured using high-resolution TEM images. 4 The crystal has a layered structure with two Ga-Zn-O layers between the In-O layers. 4 The unit lattice of the crystal has a total of nine layers, three In-O layers and six Ga-Zn-O layers, overlapping in the c-axis direction. Therefore, the spacing between these adjacent layers is roughly equal to the lattice surface spacing of the (009) plane (also called d value), which is 0.29nm as determined from the crystal structure analysis. Therefore, focusing on the lattice fringes of the high-resolution TEM image, in the region where the lattice fringes are spaced from 0.28nm to 0.30nm, each lattice fringe is considered to be the same as InGaZnO. 4 The ab plane of the crystal corresponds to the ab plane of the crystal.

[0414] Note that the oxide semiconductor film may be a stacked-layer film including two or more of an amorphous oxide semiconductor film, an amorphous-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

[0415] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0416] Implementation 7

[0417] An imaging device according to one embodiment of the present invention and a semiconductor device including the imaging device can be used in a display device, a personal computer, or an image reproduction device having a recording medium (typically, a device that can play a recording medium such as a digital versatile disk (DVD) and has a display that can display the image). In addition, as electronic devices that can use the imaging device according to one embodiment of the present invention and the semiconductor device including the imaging device, there can be cited mobile phones, portable game consoles, portable data terminals, e-book readers, camera devices such as video imagers or digital cameras, goggle-type displays (head-mounted displays), navigation systems, audio reproduction devices (car audio systems, digital audio players, etc.), copiers, fax machines, printers, multifunction printers, automatic teller machines (ATMs), and vending machines. Fig.39 A to Fig.39 F shows specific examples of these electronic devices.

[0418] Fig.39 A is a portable game machine, which includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, an operation key 907, a stylus pen 908, and a camera 909. Fig.39 The portable game machine shown in A includes two display portions 903 and 904 , but the number of display portions included in the portable game machine is not limited thereto. The imaging device of one embodiment of the present invention can be used for the camera 909 .

[0419] Fig.39 B is a portable data terminal including a first housing 911, a display portion 912, a camera 919, etc. Information can be input and output by a touch function of the display portion 912. The imaging device of one embodiment of the present invention can be used for the camera 909.

[0420] Fig.39 C denotes a digital camera including a housing 921 , a shutter button 922 , a microphone 923 , a light emitting unit 927 , a lens 925 , and the like. The imaging device of one embodiment of the present invention may be provided at the focal point of the lens 925 .

[0421] Fig.39 D is a wristwatch type information terminal, which includes a housing 931, a display portion 932, a wristband 933, a camera 939, and the like. The display portion 932 may be a touch screen. The imaging device of one embodiment of the present invention can be used for the camera 909.

[0422] Fig.39E is a video camera, which includes a first frame 941, a second frame 942, a display unit 943, an operation key 944, a lens 945, a connection unit 946, and the like. The operation key 944 and the lens 945 are provided in the first frame 941, and the display unit 943 is provided in the second frame 942. Furthermore, the first frame 941 and the second frame 942 are connected by a connection unit 946, and the angle between the first frame 941 and the second frame 942 can be changed by the connection unit 946. The image displayed by the display unit 943 can also be switched according to the angle between the first frame 941 and the second frame 942 formed by the connection unit 946. The imaging device of one embodiment of the present invention can be provided at the position of the focus of the lens 945.

[0423] Fig.39 F denotes a mobile phone, and a display portion 952, a microphone 957, a speaker 954, a camera 959, an input / output terminal 956, an operation button 955, and the like are provided in a housing 951. The imaging device of one embodiment of the present invention can be used for the camera 959.

[0424] This embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0425] Explanation of symbols

[0426] 31 Circuit

[0427] 32 Circuit

[0428] 33 Circuit

[0429] 34 Circuit

[0430] 40 Silicon substrate

[0431] 51 Transistor

[0432] 52 Transistors

[0433] 53 Transistor

[0434] 54 Transistors

[0435] 55 Transistor

[0436] 56 Transistors

[0437] 57 Transistor

[0438] 58 Transistors

[0439] 59 Transistor

[0440] 60 Photodiode

[0441] 61 Photodiode

[0442] 62 Photodiode

[0443] 63 Photodiode

[0444] 65B Spectral Element

[0445] 65G Splitter

[0446] 65R Spectral Element

[0447] 66 Area

[0448] 67 Mirror

[0449] 80 Insulation layer

[0450] 90 Circuit Department

[0451] 92 Circuit Department

[0452] 101 Transistor

[0453] 102 Transistors

[0454] 103 Transistor

[0455] 104 Transistors

[0456] 105 Transistor

[0457] 106 Transistors

[0458] 107 Transistor

[0459] 108 Transistors

[0460] 109 Transistor

[0461] 110 Transistors

[0462] 111 Transistor

[0463] 112 Transistors

[0464] 115 Substrate

[0465] 120 Insulation layer

[0466] 130 Oxide semiconductor layer

[0467] 130a Oxide semiconductor layer

[0468] 130A Oxide semiconductor film

[0469] 130b Oxide semiconductor layer

[0470] 130B Oxide semiconductor film

[0471] 130c Oxide semiconductor layer

[0472] 130C Oxide semiconductor film

[0473] 140 Conductive layer

[0474] 141 Conductive layer

[0475] 141a Conductive layer

[0476] 142 Conductive layer

[0477] 150 Conductive layer

[0478] 151 Conductive layer

[0479] 152 Conductive layer

[0480] 156 Resist Mask

[0481] 160 Insulation layer

[0482] 160A Insulation film

[0483] 170 Conductive layer

[0484] 171 Conductive layer

[0485] 171A Conductive film

[0486] 172 Conductive layer

[0487] 172A Conductive film

[0488] 173 Conductive layer

[0489] 175 Insulation layer

[0490] 180 Insulation layer

[0491] 231 Area

[0492] 232 Area

[0493] 233 Area

[0494] 331 Area

[0495] 332 Area

[0496] 333 Area

[0497] 334 Area

[0498] 335 Area

[0499] 501 signal

[0500] 502 signal

[0501] 503 signal

[0502] 504 signal

[0503] 505 signal

[0504] 506 signal

[0505] 507 Signal

[0506] 508 signal

[0507] 509 signal

[0508] 510 signal

[0509] 511 signal

[0510] 512 Signal

[0511] 515 Period

[0512] 516 Period

[0513] 517 Period

[0514] 615 Period

[0515] 617 Period

[0516] 621 Period

[0517] 622 Period

[0518] 623 Period

[0519] 901 Frame

[0520] 902 Frame

[0521] 903 Display

[0522] 904 Display

[0523] 905 Microphone

[0524] 906 Speakers

[0525] 907 Operation keys

[0526] 908 Touch Pen

[0527] 909 Camera

[0528] 911 Frame

[0529] 912 Display

[0530] 919 Camera

[0531] 921 Frame

[0532] 922 Shutter button

[0533] 923 Microphone

[0534] 925 Lens

[0535] 927 Luminous Department

[0536] 931 Frame

[0537] 932 Display

[0538] 933 Wristband

[0539] 939 Camera

[0540] 941 Frame

[0541] 942 Frame

[0542] 943 Display

[0543] 944 Operation keys

[0544] 945 Lens

[0545] 946 Connection

[0546] 951 Frame

[0547] 952 Display

[0548] 954 Speakers

[0549] 955 Button

[0550] 956 Input and output terminals

[0551] 957 Microphone

[0552] 959 Camera

[0553] 1500 Component separation layer

[0554] 1510 Shading layer

[0555] 1520 Insulation layer

[0556] 1540 Microlens

[0557] 1541 Microlens.

Claims

1. An imaging device, comprising a pixel, wherein the pixel comprises: a first photoelectric conversion element; a second photoelectric conversion element adjacent to the first photoelectric conversion element; as well as The light splitting element on the first photoelectric conversion element, In which, the spectroscopic element is arranged on the second photoelectric conversion element, and the light WR / 2-B / 2, WR / 2-G / 2 or WB / 2-G / 2 obtained by removing any two of the 1 / 2 light components corresponding to the wavelengths of red R, green G and blue B from the light W incident on the pixel is incident on the second photoelectric conversion element, and the light W+R / 2+B / 2, W+R / 2+G / 2 or W+B / 2+G / 2 obtained by synthesizing the light W incident on the pixel and the removed light is incident on the first photoelectric conversion element.

2. An imaging device, comprising a pixel, wherein the pixel comprises: a first photoelectric conversion element; a second photoelectric conversion element adjacent to the first photoelectric conversion element, wherein the element separation layer is located between the first photoelectric conversion element and the second photoelectric conversion element; A light shielding layer disposed on the element separation layer; a light splitting element on the first photoelectric conversion element; a first microlens on the light splitting element; as well as a second microlens on the second photoelectric conversion element, In which, the spectroscopic element is arranged on the second photoelectric conversion element, and the light WR / 2-B / 2, WR / 2-G / 2 or WB / 2-G / 2 obtained by removing any two of the 1 / 2 light components corresponding to the wavelengths of red R, green G and blue B from the light W incident on the pixel is incident on the second photoelectric conversion element, and the light W+R / 2+B / 2, W+R / 2+G / 2 or W+B / 2+G / 2 obtained by synthesizing the light W incident on the pixel and the removed light is incident on the first photoelectric conversion element. 3 . The imaging device according to claim 2 , further comprising a mirror provided between the first photoelectric conversion element and the light splitting element.

4. The imaging device according to claim 1 or 2, in, Each of the first photoelectric conversion element and the second photoelectric conversion element contains selenium.

5. An imaging device comprising a plurality of pixels, each pixel comprising: Pixel circuit; as well as Spectral element, The pixel circuit includes a photoelectric conversion unit, a signal generation unit and a first capacitor element, wherein the photoelectric conversion unit and the signal generation unit are connected via the first capacitor element. The signal generating unit includes a first transistor, a second transistor, a third transistor and a second capacitor. The photoelectric conversion unit includes a first photoelectric conversion element, a second photoelectric conversion element, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The light splitting element overlaps with one of the first photoelectric conversion element and the second photoelectric conversion element, The first terminal of the first photoelectric conversion element is electrically connected to one of the source and the drain of the fourth transistor and one of the source and the drain of the fifth transistor. The first terminal of the second photoelectric conversion element is electrically connected to one of the source and the drain of the sixth transistor and one of the source and the drain of the seventh transistor. The first terminal of the first capacitive element is electrically connected to the other of the source and the drain of the fourth transistor and the other of the source and the drain of the sixth transistor, The second terminal of the first capacitor is electrically connected to the first terminal of the second capacitor, the gate of the second transistor, and one of the source and the drain of the first transistor. Furthermore, one of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor.

6. The imaging device according to claim 5, in, The capacitance value between the first terminal of the first photoelectric conversion element, the one of the source and the drain of the fifth transistor, and the first terminal of the first capacitor element is equal to the capacitance value between the first terminal of the second photoelectric conversion element, the one of the source and the drain of the seventh transistor, and the first terminal of the first capacitor element.

7. The imaging device according to claim 5, in, A channel formation region of each of the first to seventh transistors includes an oxide semiconductor.

8. An imaging device comprising a plurality of pixels, each pixel comprising: Pixel circuit; as well as Spectral element, The pixel circuit includes a photoelectric conversion unit, a signal generation unit and a first capacitor element, wherein the photoelectric conversion unit and the signal generation unit are connected via the first capacitor element. The signal generating unit includes a first transistor, a second transistor, a third transistor and a second capacitor. The photoelectric conversion unit includes a first photoelectric conversion element, a second photoelectric conversion element, a fourth transistor, and a fifth transistor, and the light splitting element overlaps with one of the first photoelectric conversion element and the second photoelectric conversion element. The first terminal of the first photoelectric conversion element is electrically connected to one of the source and the drain of the fourth transistor. The first terminal of the second photoelectric conversion element is electrically connected to one of the source and the drain of the fifth transistor. The first terminal of the first capacitive element is electrically connected to the other of the source and the drain of the fourth transistor and the other of the source and the drain of the fifth transistor, The second terminal of the first capacitor is electrically connected to the first terminal of the second capacitor, the gate of the second transistor, and one of the source and the drain of the first transistor. Furthermore, one of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor.

9. The imaging device according to claim 8, in, A capacitance value between the first terminal of the first photoelectric conversion element and the first terminal of the first capacitor element is equal to a capacitance value between the first terminal of the second photoelectric conversion element and the first terminal of the first capacitor element.

10. The imaging device according to claim 8, in, A channel formation region of each of the first to fifth transistors includes an oxide semiconductor.

11. The imaging device according to claim 7 or 10, in, The oxide semiconductor contains In, Zn, and Ga.

12. The imaging device according to claim 5 or 8, in, The other of the source and the drain of the third transistor is electrically connected to a first wiring.

13. The imaging device according to claim 5 or 8, in, The capacitance value of the first capacitance element is greater than the capacitance value of the second capacitance element.

14. The imaging device according to claim 5 or 8, in, The first pixel and the second pixel for detecting imaging data of red R are adjacent to each other, The third pixel and the fourth pixel of the imaging data for detecting blue B are adjacent to each other, The fifth pixel and the sixth pixel of the imaging data for detecting green G are adjacent to each other, In each of the first pixel to the fourth pixel, the light splitting element overlaps with the first photoelectric conversion element, Furthermore, in each of the fifth pixel and the sixth pixel, the light splitting element overlaps with the second photoelectric conversion element.

15. The imaging device according to any one of claims 1, 2, 5 and 8, in, The first photoelectric conversion element and the second photoelectric conversion element have the same structure.

16. An electronic device, comprising: The imaging device according to any one of claims 1, 2, 5 and 8; Display device; as well as Operation keys.

Images