Superjunction semiconductor device and method for manufacturing superjunction semiconductor device

Abstract

The present invention provides a superjunction semiconductor device and a method for manufacturing a superjunction semiconductor device that can suppress the reduction of avalanche resistance even when the charge balance is "1". The semiconductor device has an active region (30) for current flow and a terminal structure (40). A first semiconductor layer (2) of a first conductivity type is provided on the front surface of a semiconductor substrate (1) of a first conductivity type. A parallel pn structure (20) is provided on the surface of the first semiconductor layer (2) in which a first column (3) of a first conductivity type and a second column (4) of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface. The second column (4) of the active region (30) includes a first region (41) and a second region (42), and in the first region (41), the distance between the bottom surface of the second column (4) and the front surface of the semiconductor substrate (1) is longer than the distance between the bottom surface of the second column (4) and the front surface of the semiconductor substrate (1) in the second region (42).

Description

Technical Field

[0001] The invention relates to a super junction semiconductor device and a method for manufacturing the super junction semiconductor device. Background Art

[0002] In a conventional n-channel vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor: insulated gate field effect transistor), the n-type drift layer is the semiconductor layer with the highest resistance among the multiple semiconductor layers formed in the semiconductor substrate. The resistance of the n-type drift layer has a significant impact on the on-resistance of the vertical MOSFET as a whole. The reduction of the on-resistance of the vertical MOSFET as a whole can be achieved by reducing the thickness of the n-type drift layer and shortening the current path.

[0003] However, the vertical MOSFET has the function of maintaining the withstand voltage by extending the depletion layer to the high-resistance n-type drift layer in the off state. Therefore, when the n-type drift layer is thinned to reduce the on-resistance, the extension distance of the depletion layer in the off state is short, and the depletion layer immediately reaches the n-type drift layer. + type semiconductor substrate, the depletion layer no longer extends further. Therefore, the maximum electric field strength is reached immediately, and the withstand voltage is reduced. On the other hand, in order to improve the withstand voltage of the vertical MOSFET, the thickness of the n-type drift layer needs to be increased, but the on-resistance increases. Such a relationship between on-resistance and withstand voltage is called a trade-off relationship, and it is usually difficult to improve both parties in the trade-off relationship. It is known that the trade-off relationship between on-resistance and withstand voltage also holds true in semiconductor devices such as IGBT (Insulated Gate Bipolar Transistor: insulated gate bipolar transistor), bipolar transistors, and diodes.

[0004] As a structure of a semiconductor device that solves the above problems, a super junction (SJ) structure is known. For example, a MOSFET having a super junction structure (hereinafter referred to as SJ-MOSFET) is known. Fig.23 It is a cross-sectional view showing the structure of a conventional SJ-MOSFET.

[0005] like Fig.23 As shown, SJ-MOSFET 150 has a high impurity concentration n + The n-type semiconductor substrate 101 is used to grow an n-type layer 102. + A p-type column region 104 is provided at a depth of the n-type semiconductor substrate 101. The bottom surface of the p-type column region 104 reaches the bottom surface of the n-type semiconductor substrate 101. + An n-type buffer layer 102' is formed between the n-type semiconductor substrate 101 and the n-type layer 102. Fig.23 In the process, the p-type column region 104 does not reach the n + type semiconductor substrate 101, but it may also be + The morphology of the semiconductor substrate 101 is shown in FIG.

[0006] In addition, in the n-type layer 102, a p-type region (p-type column region 104) extending in a direction perpendicular to the substrate main surface and having a narrow width in a plane parallel to the substrate main surface and an n-type region (a portion of the n-type layer 102 sandwiched by adjacent p-type column regions 104, hereinafter referred to as n-type column region 103) are alternately and repeatedly arranged in a plane parallel to the substrate main surface (hereinafter referred to as a parallel pn region 120). The p-type column region 104 and the n-type column region 103 constituting the parallel pn region 120 are regions in which the impurity concentration of the n-type layer 102 is increased accordingly. In the parallel pn region 120, by making the impurity concentrations contained in the p-type column region 104 and the n-type column region 103 approximately equal, in the off state, the depletion layer extends from the PN junction of the p-type column region 104 and the n-type column region 103 formed according to the cell pitch to the p-type column region 104 and the n-type column region 103 in the lateral direction (the direction in which the p-type column region 104 and the n-type column region 103 are alternately arranged). The cell pitch represents the interval between adjacent gate electrodes. As a result, the depletion layer is easily connected in the lateral direction and a high withstand voltage can be achieved. Therefore, even if the impurity concentration of the n-type column region 103 is increased, the withstand voltage does not decrease, and the on-state resistance can be reduced.

[0007] A p-type base region 105 is provided on the parallel pn region 120 on the active region 130 side where the element is formed and current flows in the on state of the SJ-MOSFET 150. An n-type base region 105 is provided inside the p-type base region 105. + Type source region 106. + The type source region 106 is disposed in the active region 130 and configured in a trench gate structure to be described later.

[0008] In addition, a layer is provided that penetrates the p-type base region 105 and the n + The trench 118 is formed by connecting the n-type source region 106 to the n-type column region 103. The n-type + Type source region 106.

[0009] The inner wall surface of the trench 118 is covered by a gate insulating film 107 composed of an oxide film or the like, and the trench 118 is filled with a gate electrode 108 formed on the surface of the gate insulating film 107. Thus, a trench gate structure is formed. A portion of the gate electrode 108 may be provided with a gate wiring 115 protruding from the upper side of the trench 118 (the side where the source electrode 10 described later is provided) toward the source electrode 110 side.

[0010] In addition, in the p-type base region 105 and the n +A source electrode 110 is provided on the surface of the p-type source region 106 and the surface of the gate electrode 108 via an interlayer insulating film 109. The source electrode 110 is electrically insulated on the interlayer insulating film 109. The source electrode 110 is connected to the p-type base region 105 and the n-type base region 106 through a contact hole formed in the interlayer insulating film 109. + The gate metal wiring 114 is provided on the periphery of the source electrode 110 so as to surround the source electrode 110. The gate metal wiring 114 is embedded in the opening 116 of the interlayer insulating film 109 provided on the upper part of the gate wiring 115 and is electrically connected to the gate electrode 108 via the gate wiring 115.

[0011] And, in n + The back side of the semiconductor substrate 101 is formed with n + The drain electrode (not shown) is electrically connected to the semiconductor substrate 101. With such a structure, an n-channel enhancement type trench gate structure MOSFET is formed.

[0012] In the edge termination region 140 surrounding the active region 130 of the SJ-MOSFET 150, a parallel pn region 120 is provided in the n-type layer 102 similarly to the active region 130. + A drain electrode (not shown) is provided on the back side of the p-type semiconductor substrate 101. The edge termination region 140 includes a withstand voltage holding region 144 for relaxing the electric field on the front side of the semiconductor substrate of the drift region and maintaining withstand voltage, and a boundary region 143 between the withstand voltage holding region 144 and the active region 130. In addition, in the withstand voltage holding region 144, a thick insulating film 117 such as a LOCOS film may be provided from a portion under the gate wiring 115 to the outside of the withstand voltage holding region 144. In the length direction of the p-type column region 104, a p-type region 125 deeper (longer) than the p-type base region 105 is provided from the boundary region 143 to the withstand voltage holding region 144.

[0013] For example, as a superjunction semiconductor device, it is known that there is a semiconductor device comprising a first semiconductor region in which the bottom is in contact with the main surface of the first semiconductor layer and sandwiches the second semiconductor region, and a third semiconductor region is arranged between adjacent first semiconductor regions and the bottom is pn-junctioned with the second semiconductor region (for example, refer to the following patent document 1).

[0014] Prior art literature

[0015] Patent Literature

[0016] Patent Document 1: Japanese Patent Application Publication No. 2008-210899 Summary of the invention

[0017] Technical issues

[0018] In the parallel pn region 120, when the impurity amount of the n-type column region 103 is substantially equal to the impurity amount of the p-type column region 104 (the state where the charge balance is "1"), the breakdown voltage of the SJ-MOSFET 150 reaches a maximum value. Therefore, in the conventional SJ-MOSFET 150, the impurity amount of the n-type column region 103 is substantially equal to the impurity amount of the p-type column region 104.

[0019] Fig.24 This shows the structure of a conventional SJ-MOSFET. Fig.23 Cross-sectional view of the BB' portion. Fig.25 This shows the structure of a conventional SJ-MOSFET. Fig.23 FIG. 1 is a cross-sectional view of the CC' portion of FIG. In the conventional SJ-MOSFET 150, the n-type column region 103 and the p-type column region 104 are provided with the same length in the depth direction of the trench 118. For example, in the conventional SJ-MOSFET, since the charge balance needs to be in the "1" state, the n-type column region 103 and the p-type column region 104 have the same length at the same impurity concentration.

[0020] However, in the state where the charge balance is "1", the avalanche resistance decreases sharply. At this time, if an avalanche occurs in a region close to the channel, the avalanche current flows into the parasitic bipolar transistor without passing through the drift resistor, and the reduction in avalanche resistance becomes significant. Therefore, in existing semiconductor devices, the design is avoided to avoid the state where the charge balance is "1", and the design becomes a design to reduce characteristics such as on-state resistance.

[0021] In order to solve the above-mentioned problems of the prior art, the present invention aims to provide a super junction semiconductor device and a method for manufacturing the super junction semiconductor device which can suppress the reduction of avalanche withstand capability even in a state where the charge balance is "1".

[0022] Technical Solution

[0023] In order to solve the above-mentioned problems and achieve the purpose of the present invention, the superjunction semiconductor device of the present invention has the following characteristics. The superjunction semiconductor device has an active region for current flow and a terminal structure portion arranged outside the above-mentioned active region and having a voltage-resistant structure surrounding the periphery of the above-mentioned active region. A first semiconductor layer of the first conductivity type having an impurity concentration lower than the impurity concentration of the above-mentioned semiconductor substrate is provided on the front surface of the semiconductor substrate of the first conductivity type. A parallel pn structure in which a first column of the first conductivity type and a second column of the second conductivity type are repeatedly and alternately arranged in a surface parallel to the above-mentioned front surface is provided on the surface of the above-mentioned first semiconductor layer. A first semiconductor region of the second conductivity type is provided on the surface of the above-mentioned parallel pn structure of the above-mentioned active region. A second semiconductor region of the first conductivity type is selectively provided on the surface layer of the above-mentioned first semiconductor region of the above-mentioned active region. A gate insulating film in contact with the above-mentioned first semiconductor region is provided. A gate electrode is provided on the surface of the above-mentioned gate insulating film on the opposite side of the surface in contact with the above-mentioned first semiconductor region. The second column of the active region includes a first region and a second region, wherein a distance between a bottom surface of the second column and a front surface of the semiconductor substrate in the first region is longer than a distance between a bottom surface of the second column and a front surface of the semiconductor substrate in the second region.

[0024] In addition, the superjunction semiconductor device of the present invention is characterized in that, in the above invention, the superjunction semiconductor device has a groove that penetrates the above first semiconductor region and the above second semiconductor region and reaches the above first column, and the above gate electrode is arranged inside the above groove through the above gate insulating film.

[0025] Furthermore, in the superjunction semiconductor device of the present invention, in the above invention, the first region is provided at equal intervals from adjacent first regions.

[0026] In addition, the superjunction semiconductor device of the present invention is characterized in that, in the above invention, the superjunction semiconductor device has a current detection region, the current detection region has the first semiconductor layer, the parallel pn structure, the first semiconductor region, the second semiconductor region, the gate insulating film and the gate electrode, the second column of the current detection region includes a third region and a fourth region, and in the third region, the distance between the bottom surface of the second column and the front surface of the semiconductor substrate is longer than the distance between the bottom surface of the second column and the front surface of the semiconductor substrate in the fourth region.

[0027] Furthermore, in the superjunction semiconductor device of the present invention, in the above invention, the volume of the second pillar of the active region is 90% or more of the volume of the first pillar of the active region.

[0028] In order to solve the above-mentioned problems and achieve the purpose of the present invention, the manufacturing method of the superjunction semiconductor device of the present invention is a manufacturing method of a superjunction semiconductor device having an active region for current flow and a terminal structure portion arranged outside the above-mentioned active region and having a voltage-resistant structure surrounding the periphery of the above-mentioned active region. First, a first step of forming a first semiconductor layer of the first conductivity type having an impurity concentration lower than the impurity concentration of the above-mentioned semiconductor substrate on the front surface of the first conductivity type semiconductor substrate is performed. Next, a second step of forming a parallel pn structure on the surface of the above-mentioned first semiconductor layer is performed, and the above-mentioned parallel pn structure repeatedly and alternately arranges a first column of the first conductivity type and a second column of the second conductivity type in a plane parallel to the above-mentioned front surface. Next, a third step of forming a first semiconductor region of the second conductivity type on the surface of the above-mentioned parallel pn structure of the above-mentioned active region is performed. Next, a fourth step of selectively forming a second semiconductor region of the first conductivity type on the surface layer of the above-mentioned first semiconductor region of the above-mentioned active region is performed. Next, a fifth step of forming a gate insulating film in contact with the above-mentioned first semiconductor region is performed. Next, a sixth step of forming a gate electrode on a surface of the gate insulating film opposite to a surface in contact with the first semiconductor region is performed. The second pillar of the active region includes a first region and a second region, and in the second step, a distance between a bottom surface of the second pillar in the first region and a front surface of the semiconductor substrate is formed to be longer than a distance between a bottom surface of the second pillar in the second region and a front surface of the semiconductor substrate.

[0029] In order to solve the above-mentioned problems and achieve the purpose of the present invention, the manufacturing method of the superjunction semiconductor device of the present invention is a manufacturing method of a superjunction semiconductor device having an active region for current flow and a terminal structure portion arranged outside the active region and having a voltage-resistant structure surrounding the active region. First, a first step of forming a first semiconductor layer of the first conductivity type having an impurity concentration lower than the impurity concentration of the semiconductor substrate on the front surface of the semiconductor substrate of the first conductivity type is performed. Next, a second step of forming a parallel pn structure on the surface of the first semiconductor layer is performed, and the parallel pn structure repeatedly and alternately arranges a first column of the first conductivity type and a second column of the second conductivity type in a plane parallel to the front surface. Next, a third step of selectively forming a groove reaching the first column from the upper surface of the parallel pn structure of the active region to the semiconductor substrate is performed. Next, a fourth step of forming a gate insulating film along the shape of the groove is performed. Next, a fifth step of forming a gate electrode on the surface of the gate insulating film is performed. Next, a sixth step of forming a first semiconductor region of the second conductivity type on the surface of the parallel pn structure of the active region is performed. Next, a seventh step is performed of selectively forming a second semiconductor region of the first conductivity type in a surface layer on the side opposite to the semiconductor substrate side of the first semiconductor region in the active region in contact with the trench. The second pillar in the active region includes a first region and a second region, and in the second step, a distance between a bottom surface of the second pillar in the first region and a front surface of the semiconductor substrate is formed to be longer than a distance between a bottom surface of the second pillar in the second region and a front surface of the semiconductor substrate.

[0030] According to the above invention, a long p-type column region whose length from the upper surface of the p-type column region to the bottom surface of the p-type column region is a predetermined length and a short p-type column region whose length from the upper surface of the p-type column region to the bottom surface of the p-type column region is shorter than the long p-type column region are selectively provided in the parallel pn region of the active region. As a result, in the region where the short p-type column region of the parallel pn region is provided, the charge balance becomes a state where n-type impurities are more, and the position where avalanche occurs can be guided to the bottom of the short p-type column region. Therefore, since the position where avalanche occurs is separated from the channel region, the current is not concentrated in the channel region, so that a sharp decrease in avalanche resistance can be suppressed.

[0031] Effects of the Invention

[0032] According to the superjunction semiconductor device and the method for manufacturing the superjunction semiconductor device of the present invention, it is possible to suppress a decrease in avalanche withstand capability even in a state where the charge balance is “1”. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1It is a cross-sectional view showing the structure of the SJ-MOSFET according to the embodiment.

[0034] Figure 2 1 is a diagram showing the structure of an SJ-MOSFET according to an embodiment. Figure 1 Top view of portion a-a'.

[0035] Figure 3 1 is a diagram showing the structure of an SJ-MOSFET according to an embodiment of the present invention. Figure 1 Top view of part b-b'.

[0036] Figure 4A 1 is a diagram showing the structure of an SJ-MOSFET according to an embodiment. Figure 1 Cross-sectional view of the AA' portion.

[0037] Figure 4B 1 is a diagram showing the structure of an SJ-MOSFET according to an embodiment of the present invention. Figure 1 Cross-sectional view of the BB' portion.

[0038] Figure 4C 1 is a diagram showing the structure of an SJ-MOSFET according to an embodiment. Figure 1 Cross-sectional view of the C-C' portion.

[0039] Figure 5 This is a graph showing the balance of the breakdown voltage and the on-resistance with respect to the charge in the SJ-MOSFET according to the embodiment and the conventional SJ-MOSFET.

[0040] Figure 6 This is a graph showing the balance between the breakdown voltage and the withstand capacity with respect to the charge in the SJ-MOSFET according to the embodiment and the conventional SJ-MOSFET.

[0041] Fig. 7A It is a top view showing the SJ-MOSFET according to the embodiment.

[0042] Figure 7B This is a diagram showing an SJ-MOSFET of an embodiment. Fig. 7A Enlarged view of part D.

[0043] Figure 8 1 is a diagram showing the structure of an SJ-MOSFET according to an embodiment of the present invention. Fig. 7A Cross-sectional view of the AA' portion.

[0044] Fig. 9 1 is a diagram showing the structure of an SJ-MOSFET according to an embodiment of the present invention. Fig. 7A Cross-sectional view of the AA' portion.

[0045] Fig.10 It is a top view showing the structure of the SJ-MOSFET according to the embodiment.

[0046] Fig.11 It is a plan view showing the structure of the SJ-MOSFET according to the embodiment.

[0047] Fig.12 It is a top view showing the structure of the SJ-MOSFET according to the embodiment.

[0048] Fig.13 It is a top view showing the structure of the SJ-MOSFET according to the embodiment.

[0049] Fig.14 It is a cross-sectional view showing a state during the manufacturing process of the SJ-MOSFET according to the embodiment.

[0050] Fig.15A It is a cross-sectional view showing a state during the manufacturing process of the SJ-MOSFET according to the embodiment.

[0051] Fig. 15B It is a cross-sectional view showing a state during the manufacturing process of the SJ-MOSFET according to the embodiment.

[0052] Fig.16 It is a cross-sectional view showing a state during the manufacturing process of the SJ-MOSFET according to the embodiment.

[0053] Fig.17 It is a cross-sectional view showing a state during the manufacturing process of the SJ-MOSFET according to the embodiment.

[0054] Fig.18 It is a cross-sectional view showing a state during the manufacturing process of the SJ-MOSFET according to the embodiment.

[0055] Fig.19 It is a cross-sectional view showing a state during the manufacturing process of the SJ-MOSFET according to the embodiment.

[0056] Fig. 20 It is a cross-sectional view showing a state during the manufacturing process of the SJ-MOSFET according to the embodiment.

[0057] Fig.21 It is a cross-sectional view showing a state during the manufacturing process of the SJ-MOSFET according to the embodiment.

[0058] Fig. 22 It is a cross-sectional view showing a state during the manufacturing process of the SJ-MOSFET according to the embodiment.

[0059] Fig.23 It is a cross-sectional view showing the structure of a conventional SJ-MOSFET.

[0060] Fig.24This shows the structure of a conventional SJ-MOSFET. Fig.23 Cross-sectional view of the BB' portion.

[0061] Fig.25 This shows the structure of a conventional SJ-MOSFET. Fig.23 Cross-sectional view of the C-C' portion.

[0062] Explanation of symbols

[0063] 1.101:n + Semiconductor Substrate

[0064] 2. 102: n-type layer

[0065] 2', 102': n-type buffer layer

[0066] 2a~2e:n-type layer

[0067] 3.103: n-type column area

[0068] 4.104: p-type column area

[0069] 41: Short p-type column area

[0070] 42: Long p-type column area

[0071] 5.105: p-type base region

[0072] 6, 106: n + Type Source Region

[0073] 7.107: Gate insulation film

[0074] 8.108: Gate electrode

[0075] 9, 109: Interlayer insulation film

[0076] 10, 110: Source electrode

[0077] 11: Source pad area

[0078] 12: Current sensing area

[0079] 13: Gate pad area

[0080] 14, 114: Gate metal wiring

[0081] 15, 115: Gate wiring

[0082] 16, 116: Opening

[0083] 17, 117: Thick insulating film

[0084] 18, 118: Groove

[0085] 19: p-type region

[0086] 20, 120: parallel pn area

[0087] 21a, 21b, 21c: Masks for ion implantation

[0088] 22: Ion implantation

[0089] 23: n-type region

[0090] 24: Ion implantation

[0091] 25, 125: p-type region

[0092] 30, 130: Active area

[0093] 40, 140: Edge terminal area

[0094] 43, 143: Border area

[0095] 44, 144: Pressure-resistant holding area

[0096] 50, 150: SJ-MOSFET DETAILED DESCRIPTION

[0097] Hereinafter, preferred embodiments of the superjunction semiconductor device and the method for manufacturing the superjunction semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, in the layers and regions prefixed with n or p, it is indicated that electrons or holes are the majority carriers, respectively. In addition, + and - marked on n or p respectively indicate that the impurity concentration is higher and lower than the impurity concentration of the layer or region not marked with + and -. In the case where the same expression of n or p including + and - indicates a similar concentration, it is not limited to the same concentration. It should be noted that in the following descriptions of the embodiments and the accompanying drawings, the same symbols are marked for the same configurations, and repeated descriptions are omitted.

[0098] (Implementation Method)

[0099] The superjunction semiconductor device of the present invention is described by taking SJ-MOSFET as an example. Figure 1 It is a cross-sectional view showing the structure of the SJ-MOSFET according to the embodiment.

[0100] Figure 1The SJ-MOSFET 50 shown is an SJ-MOSFET 50 having a MOS (Metal Oxide Semiconductor) gate on the front side (the side of the p-type base region 5 described later) of a semiconductor substrate (silicon substrate: semiconductor chip) containing silicon (Si). The SJ-MOSFET 50 includes an active region 30 and an edge termination region 40 surrounding the active region 30. The active region 30 is a region where current flows when in the on state. The edge termination region 40 includes a withstand voltage holding region 44 that relaxes the electric field on the front side of the semiconductor substrate of the drift region and maintains a withstand voltage, and a boundary region 43 between the withstand voltage holding region 44 and the active region 30. It should be noted that the boundary between the active region 30 and the boundary region 43 is provided with an n-type base region 5 described later only on one side. + The center of the trench 18 of the p-type source region 6 is formed. In addition, the boundary between the boundary region 43 and the withstand voltage holding region 44 is the end of the p-type base region 5. Figure 1 Only four unit cells (functional units of the element) are shown in the active region 30, and illustration of other unit cells adjacent to them is omitted.

[0101] n + The first conductivity type semiconductor substrate (first conductivity type semiconductor substrate) 1 is a silicon single crystal substrate doped with, for example, arsenic (As) or phosphorus (P). + type semiconductor substrate 1, with a ratio of n + The n-type semiconductor substrate 1 is provided with an n-type buffer layer (first semiconductor layer of the first conductivity type) 2' having a low impurity concentration. The n-type buffer layer 2' is a low-concentration n-type layer doped with, for example, phosphorus. An n-type layer 2 is provided on the n-type buffer layer 2'. The n-type layer 2 is a low-concentration n-type layer doped with, for example, phosphorus having a lower impurity concentration than the n-type buffer layer 2'. + The n-type semiconductor substrate 1, the n-type buffer layer 2' and the n-type layer 2 are combined to form a semiconductor base. A MOS gate structure (element structure) is formed on the front side of the semiconductor base. In addition, a drain electrode (not shown) is provided on the back side of the semiconductor base.

[0102] The parallel pn region 20 is provided in the active region 30 and the edge termination region 40 of the SJ-MOSFET 50. In the parallel pn region 20, the n-type column region 3 and the p-type column region 4 are alternately and repeatedly arranged. The p-type column region 4 is arranged so as not to reach the n-type layer 2 from the surface. + The n-type column region 3 and the p-type column region 4 in the active region 30 and the edge termination region 40 are arranged in a stripe shape or a rectangular shape. The impurity concentration of the n-type column region 3 is higher than that of the n-type buffer layer 2' and is higher than that of the n-type buffer layer 2'. + The impurity concentration of the semiconductor substrate 1 is low.

[0103] In addition, a p-type base region (first semiconductor region of the second conductivity type) 5 is provided in the surface layer of the n-type layer 2 in contact with the p-type column region 4, and an n-type conductive layer is selectively provided in the surface layer of the p-type base region 5. + Type source region (second semiconductor region of the first conductivity type) 6.

[0104] A trench structure is formed on the first main surface side (the p-type base region 5 side) of the semiconductor substrate. Specifically, the trench 18 extends from the n-type substrate 5 to the p-type base region 5. + The surface on the opposite side of the p-type semiconductor substrate 1 (the first main surface side of the semiconductor substrate) penetrates the p-type base region 5 and the n-type semiconductor substrate 1. + The n-type source region 6 reaches the n-type column region 3. A gate insulating film 7 is formed at the bottom and sidewalls of the trench 18 along the inner wall of the trench 18, and a gate electrode 8 is provided inside the gate insulating film 7 in the trench 18. The gate electrode 8 is insulated from the n-type column region 3 and the p-type base region 5 by the gate insulating film 7. A gate wiring 15 protruding from the upper side of the trench 18 (the side where the source electrode 10 described later is provided) to the source electrode 10 side can be provided as a part of the gate electrode 8. The gate insulating film 7 is provided at the lower part of the gate wiring 15. An interlayer insulating film 9 is provided at the upper part of the gate wiring 15.

[0105] The interlayer insulating film 9 is provided on the entire surface of the first main surface side of the semiconductor substrate so as to cover the gate electrode 8 embedded in the trench 18. The source electrode 10 is connected to the n + The p-type source region 6 is in contact with the p-type base region 5. The source electrode 10 is electrically insulated from the gate electrode 8 by the interlayer insulating film 9. A gate metal wiring 14 is provided on the outside of the source electrode 10 in a manner surrounding the source electrode 10. The gate metal wiring 14 is buried in an opening 16 of the interlayer insulating film 9 provided on the upper part of the gate wiring 15. Thus, the gate metal wiring 14 is electrically connected to the gate electrode 8 via the gate wiring 15. A barrier metal (not shown) that prevents metal atoms from diffusing from, for example, the source electrode 10 to the gate electrode 8 side may be provided between the source electrode 10 and the interlayer insulating film 9. A protective film (not shown) such as a passivation film including, for example, polyimide is selectively provided on the source electrode 10. In the opening provided by the protective film such as the passivation film provided on the source electrode 10, the area where the source electrode 10 is exposed becomes the source pad area 11.

[0106] In the conventional SJ-MOSFET 150, since the charge balance needs to be in the "1" state, the n-type column region 103 and the p-type column region 104 have the same length at the same impurity concentration. Figure 1As shown, in the p-type column region 4 of the active region 30, a short p-type column region 41 and a long p-type column region 42 are provided, and the length Ls of the p-type column region 4 in the short p-type column region 41 is shorter than the length Ll of the p-type column region 4 in the long p-type column region 42 (Ls<Ll). Figure 1 As shown, in the short p-type column region 41, the p-type column region 4 does not reach the n-type buffer layer 2', but in the long p-type column region 42, the p-type column region 4 reaches the n-type buffer layer 2'. In addition, in the short p-type column region 41 and the long p-type column region 42, the p-type column region 4 does not reach the n-type buffer layer 2'. + The p-type column region 4 is connected to the n-type semiconductor substrate 1. + The n-type semiconductor substrate 1 is in contact with the n-type buffer layer 2 ′ between the n-type column regions 3 , thereby being able to suppress a decrease in withstand voltage and an increase in on-resistance.

[0107] For example, the length L1 of the p-type column region 4 in the long p-type column region 42 is about 6 μm, and the length Ls of the p-type column region 4 in the short p-type column region 41 is shorter than the length L1 by about 1.2 to 1.8 μm. Here, the length indicates the depth (length) from the upper surface of the p-type column region 4, i.e., the interface between the p-type column region 4 and the p-type base region 5, toward the bottom surface of the p-type column region 4. That is, it is the length to the interface between the p-type column region 4 and the n-type region (n-type buffer layer 2' or n-type layer 2).

[0108] In addition, due to the presence of the short p-type column region 41, the volume of the p-type column region 4 is smaller than the volume of the n-type column region 3 in the active region 30. From the viewpoint of charge balance in the parallel pn region 20, it is preferred that the volume of the p-type column region 4 in the active region 30 is 90% or more of the volume of the n-type column region 3 in the active region.

[0109] In addition, in the short p-type column region 41, a part of the bottom of the p-type column region 4 is not formed. That is, in the short p-type column region 41, the bottom surface of the p-type column region 4 is not in contact with the n-type column region 4. + The distance between the front surface of the p-type semiconductor substrate 1 is longer than the distance between the bottom surface of the p-type column region 42 and the n-type semiconductor substrate 1. + The length of the p-type column region 4 in the edge termination region 40 having the withstand voltage holding region 44 and the boundary region 43 between the withstand voltage holding region 44 and the active region 30 reaches the n-type buffer layer 2', but does not reach the n-type buffer layer 2'. + type semiconductor substrate 1. Therefore, a p-type column region 4 having the same length as the long p-type column region 42 provided in the active region 30 is provided.

[0110] In addition, in the withstand voltage holding region 44, a thick insulating film 17 such as a LOCOS film may be provided from a portion under the gate wiring 15 to the outside of the withstand voltage holding region 44. In the length direction of the p-type column region 4, a p-type region 25 deeper (longer) than the p-type base region 5 is provided from the boundary region 43 to the withstand voltage holding region 44. In addition, the impurity concentration of the p-type region 25 is lower than that of the p-type base region.

[0111] The impurity concentrations of the p-type column region 4 and the n-type column region 3 vary depending on the withstand voltage level. For example, in a high withstand voltage level (a semiconductor device having a withstand voltage level of about 600 V), the impurity concentrations of the p-type column region 4 and the n-type column region 3 are preferably 1.0×10 15 / cm 3 Above and 5.0×10 16 / cm 3 In the case of a low withstand voltage class (a semiconductor device having a withstand voltage of about 100 V), the preferred value is 1.0×10 16 / cm 3 Above and 1.0×10 17 / cm 3 the following.

[0112] Figure 2 1 is a diagram showing the structure of an SJ-MOSFET according to an embodiment of the present invention. Figure 1 Top view of portion a-a'. Figure 3 1 is a diagram showing the structure of an SJ-MOSFET according to an embodiment of the present invention. Figure 1 Top view of part b-b'. Figure 2 is a top view of the p-type column region 4 in the short p-type column region 41 , which is closer to the trench 18 than the bottom surface thereof. Figure 3 is closer to the bottom surface of the p-type column region 4 in the short p-type column region 41 than the bottom surface of the p-type column region 4 in the short p-type column region 41. + A top view of the semiconductor substrate 1 side.

[0113] Figure 4A 1 is a diagram showing the structure of an SJ-MOSFET according to an embodiment of the present invention. Figure 1 Cross-sectional view of the AA' portion. Figure 4B 1 is a diagram showing the structure of an SJ-MOSFET according to an embodiment of the present invention. Figure 1 In addition, Figure 4C 1 is a diagram showing the structure of an SJ-MOSFET according to an embodiment of the present invention. Figure 1 Cross-sectional view of the C-C' portion.

[0114] like Figure 2 and Figure 3As shown, the n-type column region 3 and the p-type column region 4 in the active region 30 may be, for example, a stripe structure parallel to the depth direction (z-axis direction) of the trench 18. In addition, in the shorter p-type column region 41, where the bottom surface of the p-type column region 4 is closer to the trench 18 side, the width w1 of the n-type column region 3 and the width w2 of the p-type column region 4 are preferably equal to each other in order to make the charge balance in the "1" state. In addition, the width of the n-type column region 3 refers to the length of the n-type column region 3 in the direction (x-axis direction) perpendicular to the direction in which the trench 18 extends. The same is true for the width w2 of the p-type column region 4. It should be noted that the width w1 of the n-type column region 3 and the width w2 of the p-type column region 4 differ according to the withstand voltage level of the SJ-MOSFET.

[0115] The bottom surface of the p-type column region 4 in the shorter p-type column region 41 is closer to the n + Type semiconductor substrate 1 side, such as Figure 3 , Figure 4A and Figure 4B As shown, the short p-type column regions 41 and the long p-type column regions 42 are alternately arranged in the depth direction of the groove 18. In addition, the short p-type column regions 41 are preferably arranged at equal intervals with the adjacent short p-type column regions 41 at intervals w4 and at the same width w3. The interval w4 and the width of the long p-type column region 42 have the same meaning, and the width of the short p-type column region 41 and the long p-type column region 42 are the lengths in the depth direction (Z-axis direction) of the groove 18. In addition, in order to reduce the reduction in withstand voltage, it is preferred that the width w3 of the short p-type column region 41 is less than the interval P1 of the p-type column region 4. The interval P1 of the p-type column region 4 is the distance between the center of the p-type column region 4 and the center of the adjacent p-type column region 4. In addition, the interval P1 of the p-type column regions 4 is the same as the sum of the width w1 of the n-type column regions 3 of the active region 30 and the width w2 of the p-type column regions 4 of the active region 30 (P1=w1+w2), which is the repetition pitch of the n-type column regions 3 and the p-type column regions 4 of the active region 30.

[0116] Figure 5 Graph showing the breakdown voltage and on-resistance relative to charge balance in the SJ-MOSFET of the embodiment and the conventional SJ-MOSFET. Figure 5 In the figure, the left vertical axis represents the withstand voltage (BVdss) of the SJ-MOSFET, in V. In addition, the right vertical axis represents the on-resistance (Ron) of the SJ-MOSFET, in Ω. In addition, the horizontal axis represents the charge balance (p / n ratio), and 1 on the horizontal axis represents the state of charge balance "1", the side closer to the origin than 1 ((n surplus) in the figure) represents the state with more n-type impurities, and the side farther from the origin than 1 ((p surplus) in the figure) represents the state with more p-type impurities. In addition, the solid line represents the withstand voltage, and the dotted line represents the on-resistance.

[0117] like Figure 5As shown, the SJ-MOSFET of the embodiment has a slightly lower withstand voltage and a lower on-resistance than the conventional SJ-MOSFET. This is because the charge balance of the n-type impurities is achieved in the portion where the short p-type column region 41 is provided. However, since the short p-type column region 41 is only partially provided, the withstand voltage is not significantly reduced. For example, in the low withstand voltage level, the withstand voltage is reduced by several V, and in the high withstand voltage level, the withstand voltage is reduced by tens of V. In addition, since the edge termination region 40 has the same structure as in the past, the withstand voltage of the edge termination region 40 of the SJ-MOSFET50 of the embodiment is equivalent to the withstand voltage of the edge termination region 140 of the conventional SJ-MOSFET150.

[0118] Furthermore, even in a state where the charge balance is deviated (a state where the amount of either n-type or p-type impurities is greater), the SJ-MOSFET 50 of the embodiment suffers less reduction in breakdown voltage than the conventional SJ-MOSFET.

[0119] Figure 6 Graph showing the breakdown voltage and withstand capacity relative to charge balance in the SJ-MOSFET of the embodiment and the conventional SJ-MOSFET. Figure 6 In the figure, the left vertical axis represents the withstand voltage (BVdss) of the SJ-MOSFET, and the unit is V. In addition, the right vertical axis represents the avalanche withstand voltage of the SJ-MOSFET, and the unit is A. In addition, the horizontal axis represents the charge balance (p / n ratio), and 1 on the horizontal axis represents the state of charge balance "1", and the side closer to the origin than 1 ((n surplus) in the figure) represents the state with more n-type impurities, and the side farther from the origin than 1 ((p surplus) in the figure) represents the state with more p-type impurities. In addition, the solid line represents the withstand voltage, and the dotted line represents the avalanche withstand voltage.

[0120] like Figure 6 As shown, the SJ-MOSFET 50 of the embodiment has a higher avalanche resistance than the conventional SJ-MOSFET 150. The lowest avalanche resistance is the state where the charge balance is "1", and in this state, the avalanche resistance is higher than that of the conventional SJ-MOSFET 150.

[0121] In the SJ-MOSFET 50 of the embodiment, by adopting a shape in which a short p-type column region 41 is provided and a part of the bottom of the p-type column region 4 is not provided, it is possible to suppress the JFET (Junction Field Effect Transistor) effect and the increase in on-state resistance due to the spreading resistance of carriers, thereby reducing the on-state resistance. The JFET effect refers to the situation in which the depletion layer extends from the adjacent channel formation region (the region in contact with the trench 18 and the p-type base region 5) due to the source-drain electric field during MOSFET operation, thereby narrowing the current path.

[0122] In addition, in a region where a portion of the bottom of the p-type column region 4 is not provided, since the charge balance is in a state where the n-type impurities are more, the location where the avalanche occurs can be guided to the bottom of the p-type column region 4 in the short p-type column region 41. Therefore, since the location where the avalanche occurs is separated from the channel region, the current is not concentrated in the channel region, so that a sharp decrease in avalanche resistance can be suppressed.

[0123] Fig. 7A It is a top view showing the SJ-MOSFET according to the embodiment. Figure 7B express Fig. 7A An enlarged view of the D portion of the semiconductor device. In order to improve the reliability of the semiconductor device, a device having a high-function structure is proposed in which high-function parts such as a current sensing part, a temperature sensing part, and an overvoltage protection part are arranged on the same semiconductor substrate as a vertical MOSFET as a main semiconductor element. In the case of adopting a high-function structure, in order to stably form the high-function part, an area in which only the high-function part is arranged is provided in the active area in a manner separated from the unit cell of the main semiconductor element and adjacent to the edge terminal area.

[0124] Fig. 7A denoted by SJ-MOSFET provided with a current sensing region 12. Fig. 7A In the embodiment, the current sensing region 12 is provided in the gate pad region 13 separated from the source pad region 11 provided with the active region 30. The source pad region 11 is an opening provided in a protective film such as a passivation film provided on the source electrode 10, and is a region where the source electrode 10 is exposed. Figure 7B As shown, the gate pad region 13 is in contact with the gate metal wiring 14 and is electrically connected to the gate electrode 8. An external terminal electrode (not shown) for current detection is provided in the current sensing region 12. In current detection, an external resistor can be connected between the external terminal electrode for current detection and the source electrode 10 of the active region, and the potential difference between the external resistors can be detected to obtain the current value.

[0125] The current sensing region 12 is formed with Figure 1 The active region 30 shown has the same MOS structure, and the parallel pn region 20 is provided in the same manner as the active region 30. In the parallel pn region 20 of the current sensing region 12, a short p-type column region 41 and a long p-type column region 42 are also provided in the p-type column region 4, and the length Ls of the short p-type column region 41 is shorter than the length Ll of the long p-type column region 42.

[0126] Figure 8 and Fig. 9 1 is a diagram showing the structure of an SJ-MOSFET according to an embodiment. Fig. 7AA cross-sectional view of the A-A' portion. The short p-type column region 41 is arranged at equal intervals with an interval w4 and with the same width w3 as the adjacent short p-type column region 41. The interval w4 and the width w3 of the short p-type column region 41 are different according to the withstand voltage level of the SJ-MOSFET. For example, in the high withstand voltage level, high withstand voltage can be achieved by increasing the interval w4. Specifically, in the high withstand voltage level, it is preferred to set the interval w4 to be greater than 5μm and less than 15μm, and in the low withstand voltage level, it is preferred to set the interval w4 to be greater than 0.8μm and less than 4μm. The width w3 of the short p-type column region 41 in the bottom of the p-type column of the active area 30 and the interval w4 of the adjacent short p-type column region 41 are w3 / (w3+w4). The larger the value, the lower the withstand voltage and the higher the tolerance.

[0127] In addition, if Fig. 9 As shown, only certain columns in the active region 30 may be used as short p-type column regions 41. Figure 1 In the cross section of the AA′ portion, only the short p-type column region 41 may be present, and in the BB′ portion adjacent to the AA′ portion, only the long p-type column region 42 may be present.

[0128] Figure 10 to Figure 13 1 is a top view showing the structure of an SJ-MOSFET according to an embodiment. Figure 10 to Figure 13 , which is a top view of a portion where an n-type column region 3 and a p-type column region 4 are provided. Fig.10 and Fig.11 As shown, in the SJ-MOSFET of the embodiment, the n-type column region 3 and the p-type column region 4 can be formed in stripe shapes in both the active region 30 and the edge termination region 40 .

[0129] At this time, if Fig.10 As shown, the width w1 of the n-type column region 3 in the active region 30 can be made wider than the width w5 of the n-type column region 3 in the edge termination region 40, and the width w2 of the p-type column region 4 in the active region 30 can be made wider than the width w6 of the p-type column region 4 in the edge termination region 40. Thus, the interval P2 of the p-type column regions 4 in the edge termination region 40 is narrowed compared to the interval P1 of the p-type column regions 4 in the active region 30. It should be noted that the interval P2 of the p-type column regions 4 in the edge termination region 40 is the same as the sum of the width w5 of the n-type column regions 3 in the edge termination region 40 and the width w6 of the p-type column regions 4 in the edge termination region 40 (P2=w5+w6), and is the repetition pitch of the n-type column regions 3 and the p-type column regions 4 in the edge termination region 40. Therefore, the repetition pitch P2 of the n-type column region 3 and the p-type column region 4 of the edge termination region 40 is narrowed compared to the repetition pitch P1 (P1=w1+w2) of the n-type column region 3 and the p-type column region 4 of the active region 30. In addition, the n-type column region 3 and the p-type column region 4 at the boundary between the active region 30 and the edge termination region 40 may not be in contact.

[0130] In addition, if Fig.11 As shown, the width w2 of the p-type column region 4 in the active region 30 can be made wider than the width w6 of the p-type column region 4 in the edge termination region 40. In the edge termination region 40, the interval P2 of the p-type column region 4 (the sum of the width w5 of the n-type column region 3 and the width w6 of the p-type column region 4) is the same as the interval P1 of the p-type column region 4 in the active region 30 (the sum of the width w1 of the n-type column region 3 and the width w2 of the p-type column region 4). For the durability of the semiconductor device, the withstand voltage of the edge termination region 40 needs to be higher than the withstand voltage of the active region 30. Therefore, it is preferable to reduce the impurity concentration of the p-type column region 4 and the n-type column region 3 in the edge termination region 40, and to narrow the width of the n-type column region 3 and the width of the p-type column region 4 so that the edge termination region 40 is easily depleted. In addition, it is preferable to provide a field limiting ring (FLR) structure, a guard chain structure, a surface field reduction structure, etc. for relaxing the electric field based on the shape in the edge termination region 40.

[0131] In addition, if Fig.12 As shown, in the SJ-MOSFET of the embodiment, in the active region 30 , the n-type column region 3 and the p-type column region 4 may be formed in a stripe shape, and in the edge termination region 40 , the p-type column region 4 may be formed in a rectangular shape, such as a square.

[0132] At this time, if Fig.12 As shown, the width w2 of the p-type column region 4 in the active region 30 can be made smaller than the vertical and horizontal lengths (widths) w8 of the rectangle of the p-type column region 4 in the edge termination region 40, and the interval P1 of the p-type column region 4 in the active region 30 (the sum of the width w1 of the n-type column region 3 and the width w2 of the p-type column region 4) can be set to a length greater than the interval P2 of the p-type column region 4 in the edge termination region 40. The interval P2 of the rectangular p-type column region 4 refers to the distance obtained by summing the width w8 of the p-type column region 4 and the width w7 of the n-type column region 3 adjacent to the p-type column region 4 in the direction orthogonal to the stripe shape. That is, the repetition pitch P1 of the n-type column region 3 and the p-type column region 4 of the active region 30 (the sum of the width w1 of the n-type column region 3 and the width w2 of the p-type column region 4) becomes greater than the repetition pitch P2 of the n-type column region 3 and the p-type column region 4 of the edge termination region 40 (the sum of the width w7 of the n-type column region 3 and the width w8 of the p-type column region 4).

[0133] In addition, if Fig.13 As shown, in the SJ-MOSFET of the embodiment, the p-type column region 4 can be formed into a rectangular shape in both the active region 30 and the edge termination region 40 .

[0134] At this time, if Fig.13As shown, the vertical and horizontal lengths (widths) w2 of the rectangle of the p-type column region 4 in the active region 30 can be made larger than the vertical and horizontal lengths (widths) w8 of the rectangle of the p-type column region 4 in the edge termination region 40, and the interval P1 of the p-type column region 4 in the active region 30 can be set to a length larger than the interval P2 of the p-type column region 4 in the edge termination region 40. That is, the repetition pitch P1 of the n-type column region 3 and the p-type column region 4 in the active region 30 (the sum of the width w1 of the n-type column region 3 and the width w2 of the p-type column region 4 in the active region 30) becomes a length larger than the repetition pitch P2 of the n-type column region 3 and the p-type column region 4 in the edge termination region 40 (the sum of the width w7 of the n-type column region 3 and the width w8 of the p-type column region 4 in the edge termination region 40).

[0135] (Method for Manufacturing Superjunction Semiconductor Device According to Embodiment)

[0136] Next, a method for manufacturing a super junction semiconductor device according to an embodiment will be described. Figures 14 to 19 The SJ-MOSFET 50 of the embodiment is shown in a cross-sectional view during the manufacturing process. First, a silicon-containing n-type semiconductor device is prepared. + n-type drain layer + Next, on n + On the front surface of the semiconductor substrate 1, the impurity concentration is made higher than n + The n-type buffer layer 2' is epitaxially grown on the low n-type semiconductor substrate 1. The state up to this point is described in Fig.14 .

[0137] Next, an n-type layer 2a having a higher impurity concentration than the n-type layer 2' is epitaxially grown on the front side of the n-type buffer layer 2'. At this time, for example, the impurity concentration of the n-type buffer layer 2' can be 1.0×10 15 / cm 3 Above and 1.0×10 17 / cm 3 Next, the impurity concentration of the n-type layer 2a is set to 2.0×10 15 / cm 3 Above and 5.0×10 15 / cm 3 The n-type impurities are doped and epitaxially grown in the following manner. It should be noted that the film thickness of the n-type layer 2a can be 0.5 μm or more and 40 μm or less. For example, in a low withstand voltage level (a semiconductor device with a withstand voltage level of about 100V), it is 1 μm or more and 4 μm or less, and in a high withstand voltage level (a semiconductor device with a withstand voltage level of about 600V), it is 6 μm or more and 20 μm or less.

[0138] Next, a mask 21a for ion implantation having a predetermined opening width is formed on the surface of the n-type layer 2a by photolithography technology, for example, using a photoresist. At this time, the mask 21a for ion implantation is formed in such a way that an opening is provided in the p-type column region 4, and impurity ions are not implanted into the short p-type column region 41. Using the mask 21a for ion implantation as a mask, ion implantation 22 of a p-type impurity such as boron (B) is performed to form a p-type region 19 in the surface layer of the n-type layer 2a. The state so far is recorded in Fig.15A Next, the ion implantation mask is removed.

[0139] Next, an ion implantation mask 21b having a predetermined opening width is formed on the surface of the n-type layer 2a by using, for example, a photoresist through photolithography. At this time, an ion implantation mask 21b having an opening is formed in the n-type column region 3. Using the ion implantation mask 21b as a mask, ion implantation 24 of n-type impurities, such as phosphorus (P) or arsenic (As), is performed to form an n-type region 23 in the surface layer of the n-type layer 2a. The state so far is recorded in Fig. 15B Next, the ion implantation mask 21b is removed.

[0140] Next, an n-type layer 2b having the same impurity concentration as that of the n-type layer 2a is epitaxially grown on the front side of the n-type layer 2a. Next, an ion implantation mask 21c having a predetermined opening width is formed on the surface of the n-type layer 2b by photolithography technology, for example, using a photoresist. At this time, an ion implantation mask 21c having an opening is formed in the p-type column region 4. Using the ion implantation mask 21c as a mask, ion implantation 22 of a p-type impurity such as boron (B) is performed to form a p-type region 19 in the surface layer of the n-type layer 2b. Next, the ion implantation mask 21c is removed.

[0141] Next, an ion implantation mask (not shown) having a predetermined opening width is formed on the surface of the n-type layer 2b by photolithography technology, for example, using a photoresist. At this time, an ion implantation mask having an opening is formed in the n-type column region 3. Using the ion implantation mask as a mask, ion implantation of n-type impurities is performed to form an n-type region 23 in the surface layer of the n-type layer 2b. Next, the ion implantation mask is removed.

[0142] Next, an n-type layer 2c having the same impurity concentration as that of the n-type layer 2a is epitaxially grown on the front side of the n-type layer 2b. Next, an ion implantation mask 21 having a predetermined opening width is formed on the surface of the n-type layer 2c by using, for example, a photoresist through a photolithography technique. At this time, an ion implantation mask 21 having an opening is formed in the p-type column region 4. Using the ion implantation mask 21 as a mask, ion implantation 22 of a p-type impurity, such as boron (B), is performed to form a p-type region 19 in the surface layer of the n-type layer 2c. Next, the ion implantation mask 21 is removed.

[0143] Next, an ion implantation mask (not shown) having a predetermined opening width is formed on the surface of the n-type layer 2c by photolithography technology, for example, using a photoresist. At this time, an ion implantation mask having an opening is formed in the n-type column region 3. Using this ion implantation mask as a mask, ion implantation of n-type impurities is performed to form an n-type region 23 in the surface layer of the n-type layer 2c. The state so far is recorded in Fig.16 Next, the ion implantation mask is removed.

[0144] Here, in Fig.16 In the example, in the short p-type column region 41, the length is shorter than that of the long p-type column region 42 by the n-type layer 2a, which is a part of the epitaxial growth. However, this is not limiting and can be appropriately changed according to target characteristics such as withstand voltage.

[0145] Next, the n-type layer 2d and the n-type layer 2e are similarly epitaxially grown, and the p-type region 19 and the n-type region 23 are formed on the surface layers of the n-type layer 2d and the n-type layer 2e. Thus, a parallel pn region including the n-type region 23 and the p-type region 19 is formed. The state up to this point is described in Fig.17 .

[0146] exist Fig.17 In the example of , an example of repeating ion implantation and epitaxial growth five times is shown, but it is not limited to this. The number of ion implantation and epitaxial growth can be appropriately changed according to the target characteristics such as withstand voltage. In addition, the n-type layer 2f (not shown) can be epitaxially grown on the n-type layer 2e. It should be noted that ion implantation is not performed in the active region 30 of the uppermost n-type layer 2f. Through the steps so far, the region that becomes a parallel pn structure is formed by the heat treatment described later. In the edge termination region 40 of the uppermost n-type layer 2f, ion implantation can be performed to form a p-type region 25 on the p-type column region 4 formed on the n-type layer 2e. The p-type region 25 can have a function of reducing the surface field region, is deeper than the p-type base region, and has a lower impurity concentration than the p-type base region. In addition, ion implantation to form the n-type region 23 and the p-type region 19 for forming the n-type column region 3 and the p-type column region 4 can be performed on the edge termination region 40 of the uppermost n-type layer 2f.

[0147] Next, a heat treatment is performed to activate the n-type region 23 and the p-type region 19. This heat treatment diffuses the implanted impurities, and the diffused impurities are connected vertically, thereby forming the n-type column region 3 and the p-type column region 4. It should be noted that in the high withstand voltage stage, it is preferable to perform the heat treatment every time the ion implantation and epitaxial growth are repeated 2 to 3 times. In addition, in the low withstand voltage stage, it is possible to perform the heat treatment in conjunction with the step of activating the p-type base region 5 and the n-type column region 4. + The heat treatment for activating the n-type source region 6 is shared. It should be noted that in the method for manufacturing the superjunction semiconductor device of this embodiment, although the ions for forming the n-type column region 3 and the p-type column region 4 are implanted into the n-type layer 2a, the ions for forming the n-type column region 3 and the p-type column region 4 may be implanted into the buffer layer 2'. In addition, in the method for manufacturing the superjunction semiconductor device of this embodiment, although the ions for forming the p-type column region 4 are implanted first, it is not limited to this, and the ions for forming the n-type column region 3 may be implanted first.

[0148] Next, a mask having a desired opening is formed on the surface of the n-type layer on the active region 30 side using, for example, a resist by photolithography. Then, p-type impurities are ion-implanted by ion implantation using the resist mask as a mask. Thus, a p-type base region 5 is formed in the surface region of the n-type layer. Next, the mask used in the ion implantation for forming the p-type base region 5 is removed.

[0149] Next, a mask having a desired opening is formed on the surface of the p-type base region 5 using, for example, a resist by photolithography. Then, the n-type impurity is ion-implanted by ion implantation using the resist mask as a mask. Thus, an n-type impurity is formed in a portion of the surface area of ​​the p-type base region 5. + Next, remove the + The mask used for ion implantation of the type source region 6. The state so far is recorded in Fig.18 .

[0150] Next, the process for making the p-type base region 5 and the n-type base region 5 + In addition, the p-type base region 5 and the n-type source region 6 are formed. + The order of the type source regions 6 can be changed in various ways.

[0151] Next, by photolithography, an oxide film is formed on the p-type base region 5 and the n-type base region 5 using, for example, an oxide film. + A trench formation mask having a predetermined opening is formed on the surface of the n-type source region 6. Next, a through-hole trench is formed by dry etching. + The trench 18 is formed by forming the n-type source region 6 and reaching the n-type column region 3. Next, the trench forming mask is removed. The state thus far is shown in FIG. Fig.19 It should be noted that the n +Type source region 6.

[0152] Next, along n + A gate insulating film 7 is formed on the surface of the source region 6 and the bottom and sidewall of the trench 18. The gate insulating film 7 can be formed by thermal oxidation at a temperature of about 1000° C. in an oxygen atmosphere. Alternatively, the gate insulating film 7 can be formed by a deposition method using a chemical reaction such as high temperature oxidation (High Temperature Oxide: HTO).

[0153] Next, a polycrystalline silicon layer doped with phosphorus atoms is provided on the gate insulating film 7. The polycrystalline silicon layer can be formed so as to be buried in the trench 18. The polycrystalline silicon layer is patterned by photolithography and remains in the trench 18, thereby forming the gate electrode 8.

[0154] Next, phosphorus glass, for example, is deposited in a thickness of about 1 μm to cover the gate insulating film 7 and the gate electrode 8 to form an interlayer insulating film 9. Next, the interlayer insulating film 9 and the gate insulating film 7 are patterned by photolithography to form a layer that makes the gate insulating film 7 and the gate electrode 8 have a thickness of about 1 μm. + A contact hole is formed to expose the p-type source region 6 and the p-type base region 5. Thereafter, a heat treatment (reflow) is performed to planarize the interlayer insulating film 9.

[0155] Next, the source electrode 10 is formed into a film by sputtering, and the source electrode 10 is patterned by photolithography and etching. It should be noted that before the source electrode 10 is formed into a film, a barrier metal (not shown) including a titanium film (Ti), a titanium nitride film (TiN), or a stacked film of these (for example, Ti / TiN, etc.) may be formed by sputtering. Thereafter, the source electrode 10 is formed into a film on the barrier metal by sputtering, and the source electrode 10 and the barrier metal (not shown) are patterned by photolithography and etching. Next, the source electrode 10 is embedded in the contact hole, so that n + The type source region 6 is electrically connected to the source electrode 10. It should be noted that a tungsten plug or the like may be buried in the contact hole via a barrier metal.

[0156] Next, in n + A metal film such as nickel (Ni), titanium (Ti), gold (Au), aluminum (Al), an alloy with aluminum as the main component, or a laminated film thereof (such as Ti / Ni / Au, Al / Ti / Ni / Au, etc.) is formed on the surface of the semiconductor substrate 1 (the back side of the semiconductor substrate) as a drain electrode (not shown). Then, a heat treatment is performed to form an n + The ohmic junction between the semiconductor substrate 1 and the drain electrode is completed. Figure 1 The SJ-MOSFET 50 is shown.

[0157] Figure 20 to Figure 22 It means Figure 18-19The manufacturing method shown is a cross-sectional view of a state during the manufacturing process of an SJ-MOSFET 50 according to a different embodiment.

[0158] It should be noted that Figure 14 to Figure 17 In the same manufacturing method, an n-type layer 2f (not shown) is epitaxially grown on the n-type layer 2e. It should be noted that ion implantation is not performed in the active region 30 of the uppermost n-type layer 2f. In the edge termination region 40 of the uppermost n-type layer 2f, ion implantation for forming a p-type region 25 which also serves as a resurf region may be performed on the p-type column region 4 formed on the n-type layer 2e. In addition, ion implantation for forming an n-type region 23 and a p-type region 19 for forming an n-type column region 3 and a p-type column region 4 may be performed in the edge termination region 40 of the uppermost n-type layer 2f. A heat treatment is performed to activate the n region 23 and the p-type region 19. By this heat treatment, the implanted impurities are diffused, and the diffused impurities are connected in the vertical direction, thereby forming the n-type column region 3 and the p-type column region 4.

[0159] Next, a trench forming mask having a predetermined opening is formed on the uppermost n-type layer 2f using, for example, an oxide film by photolithography. Next, a trench 18 reaching the n-type column region 3 is formed by dry etching. Next, the trench forming mask is removed.

[0160] Next, a gate insulating film 7 is formed along the surface of the uppermost n-type layer 2f and the bottom and sidewall of the trench 18. The gate insulating film 7 can be formed by thermal oxidation at a temperature of about 1000° C. in an oxygen atmosphere. Alternatively, the gate insulating film 7 can be formed by a deposition method such as a chemical reaction such as high temperature oxidation (High Temperature Oxide: HTO).

[0161] Next, a polycrystalline silicon layer doped with phosphorus atoms is provided on the gate insulating film 7. The polycrystalline silicon layer can be formed so as to be buried in the trench 18. The polycrystalline silicon layer is patterned by photolithography and remains in the trench 18, thereby forming the gate electrode 8. The state so far is described in Fig. 20 .

[0162] Next, a mask having a desired opening is formed on the surface of the active region 30 side of the uppermost n-type layer 2f by using, for example, a resist. Then, the resist mask is used as a mask to ion-implant p-type impurities by ion implantation. Thus, a p-type base region 5 is formed in the surface region of the n-type layer. Next, the mask used for ion implantation to form the p-type base region 5 is removed. Next, a heat treatment is performed to activate the p-type base region 5. The state up to this point is recorded in Fig.21 .

[0163] Next, a mask having a desired opening is formed on the surface of the p-type base region 5 using, for example, a resist by photolithography. Then, the n-type impurity is ion-implanted by ion implantation using the resist mask as a mask. Thus, an n-type impurity is formed in a portion of the surface area of ​​the p-type base region 5. + Next, remove the + Next, a mask is used to implant ions into the n-type source region 6. + The state up to this point is recorded in Fig. 22 .

[0164] Next, phosphorus glass, for example, is deposited in a thickness of about 1 μm to cover the gate insulating film 7 and the gate electrode 8 to form an interlayer insulating film 9. Next, the interlayer insulating film 9 and the gate insulating film 7 are patterned by photolithography to form a layer that makes the gate insulating film 7 and the gate electrode 8 have a thickness of about 1 μm. + A contact hole is formed to expose the p-type source region 6 and the p-type base region 5. Thereafter, a heat treatment (reflow) is performed to planarize the interlayer insulating film 9.

[0165] Next, the source electrode 10 is formed into a film by sputtering, and the source electrode 10 is patterned by photolithography and etching. It should be noted that before the source electrode 10 is formed into a film, a barrier metal (not shown) including a titanium film (Ti), a titanium nitride film (TiN), or a laminated film thereof (for example, Ti / TiN, etc.) may be formed by sputtering. Thereafter, the source electrode 10 is formed into a film on the barrier metal by sputtering, and the source electrode 10 and the barrier metal (not shown) are patterned by photolithography and etching. Next, the source electrode 10 is embedded in the contact hole, so that n + The type source region 6 is electrically connected to the source electrode 10. It should be noted that a tungsten plug or the like may be buried in the contact hole via a barrier metal.

[0166] Next, in n + On the surface of the semiconductor substrate 1 (the back of the semiconductor substrate), a metal film such as nickel (Ni), titanium (Ti), gold (Au), aluminum (Al), an alloy with aluminum as the main component, or a laminated film thereof (such as Ti / Ni / Au, Al / Ti / Ni / Au, etc.) is formed as a drain electrode (not shown). Then, a heat treatment is performed to form an n + The ohmic junction between the semiconductor substrate 1 and the drain electrode is completed. Figure 1 The SJ-MOSFET 50 is shown.

[0167] As described above, according to the embodiment, in the parallel pn region of the active region, a short p-type column region having a short length from the upper surface of the p-type column region to the bottom surface of the p-type column region is selectively provided. As a result, in the region where the short p-type column region of the parallel pn region is provided, the charge balance becomes a state where n-type impurities are more, and the location where avalanche occurs can be guided to the bottom of the p-type column region other than the long p-type column region. Therefore, since the location where avalanche occurs is separated from the channel region, the current is not concentrated in the channel region, so that a sharp decrease in avalanche resistance can be suppressed.

[0168] In the above, in the present invention, the case where a MOS gate structure is formed on the first main surface of a silicon substrate is used as an example for explanation, but it is not limited to this, and various changes can be made to the type of semiconductor (for example, silicon carbide (SiC)), the surface orientation of the main surface of the substrate, etc. In addition, in the embodiment of the present invention, the trench MOSFET is used as an example for explanation, but it is not limited to this, and it can be applied to various semiconductor devices of various structures such as MOS semiconductor devices such as planar MOSFET and IGBT. In addition, in the present invention, in each embodiment, the first conductivity type is used as n-type and the second conductivity type is used as p-type, but the present invention also holds true when the first conductivity type is used as p-type and the second conductivity type is used as n-type.

[0169] Industrial Applicability

[0170] As described above, the superjunction semiconductor device and the method for manufacturing the superjunction semiconductor device of the present invention are useful for high withstand voltage semiconductor devices used in power conversion devices, power supply devices for various industrial machines, and the like.

Claims

1. A superjunction semiconductor device, characterized in that: The superjunction semiconductor device has an active region for current flow and a terminal structure portion disposed outside the active region and having a voltage-resistant structure surrounding the active region, wherein: a semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type, which is disposed on the front surface of the semiconductor substrate and has an impurity concentration lower than that of the semiconductor substrate; A parallel pn structure provided on the surface of the first semiconductor layer, wherein first pillars of the first conductivity type and second pillars of the second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface; a first semiconductor region of a second conductivity type, which is disposed on a surface of the parallel pn structure of the active region; a second semiconductor region of the first conductivity type, which is selectively disposed on a surface layer of the first semiconductor region of the active region; a gate insulating film in contact with the first semiconductor region; a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the first semiconductor region; as well as a trench penetrating the first semiconductor region and the second semiconductor region and reaching the first pillar, The gate electrode is disposed inside the trench via the gate insulating film. The first column and the second column are arranged in a stripe shape, The second column of the active area includes a first region and a second region, the length of the second column in the first region from the upper surface toward the bottom surface of the second column is shorter than the length of the second column in the second region from the upper surface toward the bottom surface of the second column, the first region and the second region are repeatedly and alternately arranged in the second column along the depth direction of the second column, the width w3 of the second column in the first region in the depth direction is smaller than the width w4 of the second column in the second region in the depth direction, and in the second column adjacent to the first column, the second regions are staggeredly arranged.

2. The superjunction semiconductor device according to claim 1, characterized in that: The first regions are provided at equal intervals from adjacent first regions.

3. The superjunction semiconductor device according to claim 1, characterized in that: The super junction semiconductor device includes a current detection region, wherein the current detection region includes the first semiconductor layer, the parallel pn structure, the first semiconductor region, the second semiconductor region, the gate insulating film, and the gate electrode. The second column of the current detection area includes a third region and a fourth region, wherein in the third region, a distance between a bottom surface of the second column and a front surface of the semiconductor substrate is longer than a distance between a bottom surface of the second column and a front surface of the semiconductor substrate in the fourth region.

4. The superjunction semiconductor device according to claim 1, characterized in that: The volume of the second pillar of the active region is greater than 90% of the volume of the first pillar of the active region.

5. A method for manufacturing a superjunction semiconductor device, characterized in that: The super junction semiconductor device has an active region for current flow and a terminal structure portion disposed outside the active region and having a voltage-resistant structure surrounding the active region. The method for manufacturing the super junction semiconductor device includes: In a first step, a first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate is formed on a front surface of a semiconductor substrate of a first conductivity type; A second step of forming a parallel pn structure on the surface of the first semiconductor layer, wherein the parallel pn structure has first columns of the first conductivity type and second columns of the second conductivity type repeatedly and alternately arranged in a plane parallel to the front surface; A third step of selectively forming a trench reaching the first pillar from the upper surface of the parallel pn structure in the active region toward the semiconductor substrate; A fourth step is to form a gate insulating film along the shape of the trench; A fifth step of forming a gate electrode on the surface of the gate insulating film; A sixth step is to form a first semiconductor region of a second conductivity type on a surface of the parallel pn structure in the active region; and In a seventh step, a second semiconductor region of the first conductivity type is selectively formed in a surface layer of the first semiconductor region in the active region on the side opposite to the semiconductor substrate side so as to be in contact with the trench. The second column of the active area includes a first region and a second region. In the second process, the first column and the second column are arranged in a stripe shape. The length of the second column in the first region from the upper surface toward the bottom surface of the second column is shorter than the length of the second column in the second region from the upper surface toward the bottom surface of the second column. The first region and the second region are repeatedly and alternately arranged in the second column along the depth direction of the second column. The width w3 of the second column in the first region in the depth direction is smaller than the width w4 of the second column in the second region in the depth direction. In the second column adjacent to the first column, the second regions are arranged in an alternating manner.

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