Method for forming a semiconductor device

Abstract

A method of forming a semiconductor device. The fin field effect transistor device and method of forming the same described herein have reduced resistance / capacitance power loss of the source / drain contacts and increased process margins between the source / drain contacts and the gate via. A metal bump can be formed in a first recess of a first material of the source / drain contact. The metal bump and a contact via can be formed of a second material and the contact via can be formed on the metal bump to provide a hybrid source / drain contact of the fin field effect transistor and the interface between the source / drain contact and the metal bump has a large surface contact area. A dielectric fill material and / or a compliant contact etch stop layer can be used to form an isolation region in a second recess of the source / drain contact to increase the process margin between the gate contact and the isolation region of the fin field effect transistor.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for reducing interface resistance / capacitance between source / drain vias and source / drain contacts and increasing process tolerance between source / drain vias and source / drain contacts, and a semiconductor device formed therefrom. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor device fabrication typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers onto a semiconductor substrate. The various material layers are then patterned using lithography to form circuit components and units on the semiconductor substrate.

[0003] The semiconductor industry continues to reduce minimum feature sizes to continuously improve the integration density of various electronic components such as transistors, diodes, resistors, capacitors, and the like, thereby integrating more components into a given area. However, as minimum feature sizes decrease, additional problems arise that need to be solved. Summary of the Invention

[0004] In one embodiment, a method for forming a semiconductor device includes: recessing a first portion of a source / drain contact to form a recess in a first dielectric layer of a fin field effect transistor device, wherein the source / drain contact is formed of a first metal material; depositing a second metal material in the recess to form a metal bump, wherein the metal bump physically contacts the source / drain contact, the second metal material being different from the first metal material, and a first width of an interface between the metal bump and the source / drain contact being less than a width of the source / drain contact; depositing a second dielectric layer over the metal bump; etching an opening through the second dielectric layer to expose the metal bump from the second dielectric layer; and depositing a third metal material in the opening through the second dielectric layer, wherein the third metal material physically contacts the metal bump to form a source / drain contact via, and wherein a second width of an interface between the source / drain contact via and the metal bump is less than the first width.

[0005] In another embodiment, a method for forming a semiconductor device includes: forming a first source / drain region and a second source / drain region in a fin of the semiconductor device; depositing a first dielectric layer on the fin; forming a gate stack after depositing the first dielectric layer; depositing a hard mask layer on the gate stack; forming a first source / drain contact to the first source / drain region and forming a second source / drain contact to the second source / drain region; recessing a portion of the first source / drain contact to form a first recess; filling the first recess with a first dielectric material, wherein the first dielectric material and the hard mask layer are in contact with each other; The material composition is different; a gate contact through hole is formed to the gate stack, a first dielectric material is separated from the gate contact through hole by a first distance, a surface of the first source / drain contact along the top of the recess is separated from the gate contact through hole by a second distance, the second distance is greater than the first distance, and the direction of the first distance is parallel to the direction of the second distance; and a source / drain contact through hole is formed on a portion of the second source / drain contact on the fin and electrically coupled to a portion of the second source / drain contact on the fin, wherein the source / drain contact through hole and the second source / drain contact are made of different materials.

[0006] In another embodiment, a semiconductor device includes: a source / drain contact located on a source / drain region of a fin of a semiconductor substrate and electrically coupled to the source / drain region, and the source / drain contact includes a first metal; a metal bump located on and physically contacting the source / drain contact, the metal bump including a second metal, and the second metal is different from the first metal; and a source / drain via located on and physically contacting the metal bump, the source / drain via including the second metal, wherein an interface between the metal bump and the source / drain contact is larger than an interface between the source / drain via and the metal bump. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A FIG. 1 is a perspective view of an intermediate structure when forming a semiconductor fin, a series of dummy gate stacks, and an interlayer dielectric layer in a semiconductor device in some embodiments.

[0008] Figure 1B and Figures 2 to 11 In some embodiments, the Figure 1A A cross-sectional view of a semiconductor device in a subsequent process of an intermediate structure.

[0009] Figure 12 、 Figure 13A 、 Figure 13B 、 Figure 14 、 Figure 15A 、 Figure 15B 、 Figure 16A ,and Figure 16B 1 and 2 are top views and cross-sectional views of a semiconductor device in some embodiments.

[0010] Description of reference numerals:

[0011] θ1: first angle

[0012] θ2: second angle

[0013] AA,BB,CC,3-3': Tangent

[0014] D1: First distance

[0015] D2: Second distance

[0016] D3: The third distance

[0017] D4: The fourth distance

[0018] H1: First height

[0019] H2: Second height

[0020] H3: third height

[0021] T1, Th1: first thickness

[0022] T2, Th2: second thickness

[0023] Th3: third thickness

[0024] Th4: fourth thickness

[0025] W B : bottom width

[0026] W1: first width

[0027] W2: first width

[0028] W3: third width

[0029] W4: fourth width

[0030] W5: fifth width

[0031] W6: Sixth width

[0032] W7: seventh width

[0033] W8: eighth width

[0034] W9: ninth width

[0035] 100, 1400, 1600: Semiconductor devices

[0036] 101: Substrate

[0037] 103: First groove

[0038] 105: First Isolation Area

[0039] 107: Fins

[0040] 109: Virtual gate dielectric layer

[0041] 111: Virtual gate

[0042] 113: Spacer

[0043] 115: Virtual stack

[0044] 201: Source / drain region

[0045] 201A: First source / drain region

[0046] 201B: Second source / drain region

[0047] 201C: Third source / drain region

[0048] 203: First interlayer dielectric layer

[0049] 205: Back etching process

[0050] 301: First metal layer

[0051] 303: First hard mask layer

[0052] 401: Etching process

[0053] 403: Source / drain via opening

[0054] 501: Silicide contact

[0055] 503: Source / drain contact

[0056] 503A: First source / drain contact

[0057] 503B: Second source / drain contact

[0058] 503C: Third source / drain contact

[0059] 601: Photoresist mask

[0060] 603: Gate Stack

[0061] 603A: First gate stack

[0062] 603B: Second gate stack

[0063] 701,901: Etching process

[0064] 703: First Depression

[0065] 803: Quarantine

[0066] 903: Second Depression

[0067] 1001: Source / drain contact stack

[0068] 1001A: First source / drain contact stack

[0069] 1001B: Second source / drain contact stack

[0070] 1001C: Third source / drain contact stack

[0071] 1003: Source / drain metal bumps

[0072] 1003A: First source / drain metal bump

[0073] 1003B: Second source / drain metal bump

[0074] 1003C: Third source / drain metal bump

[0075] 1101: Contact etch stop layer

[0076] 1103: Second interlayer dielectric layer

[0077] 1105: Gate via contact

[0078] 1107: Source / drain via contacts

[0079] 1501: Equal height source / drain contact stack

[0080] 1501A: First equal height source / drain contact stack

[0081] 1501B: Second highest source / drain contact stack

[0082] 1501C: Third-highest source / drain contact stack DETAILED DESCRIPTION

[0083] The following provides different embodiments or examples for implementing different structures of the embodiments of the present invention. The embodiments of specific components and arrangements are intended to simplify the present disclosure and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes the two being in direct contact, or the two being separated by additional components rather than in direct contact. In addition, the same reference numerals may be repeatedly used in various embodiments of the present invention for simplicity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same corresponding relationship.

[0084] Additionally, spatially relative terms such as "below," "beneath," "lower side," "above," "upper side," or similar terms may be used to simplify descriptions of an element's relative relationship to another element in a diagram. Spatially relative terms extend to elements used in other orientations and are not limited to the orientation shown. Elements may also be rotated 90° or other angles, so directional terms are used only to describe the orientation shown in the diagram.

[0085] The following description uses a FinFET device with reduced interface resistance / capacitance between source / drain vias and source / drain contacts, and increased process tolerance between the source / drain vias and source / drain contacts as an example. However, the embodiments are not limited to the examples provided herein, and the concept can be implemented in a variety of embodiments.

[0086] Figure 1A The figure is a perspective view of a semiconductor device 100, such as a fin field-effect transistor (FFET) device. In one embodiment, the semiconductor device 100 includes a substrate 101 and a first trench 103. The substrate 101 may be a silicon substrate, but other substrates such as a semiconductor-on-insulator (SIO) substrate, a strained SIO substrate, or a silicon-germanium-on-insulator (SiGe-OS) substrate may also be used. The substrate 101 may be a p-type semiconductor, but in other embodiments, the substrate 101 may be an n-type semiconductor.

[0087] In other embodiments, the material of substrate 101 can specifically enhance the performance of devices formed from substrate 101 (e.g., enhance carrier mobility). For example, in some embodiments, the material of substrate 101 is selected to be an epitaxially grown semiconductor material layer, such as epitaxially grown silicon germanium, which can help enhance certain performance characteristics of devices formed from epitaxially grown silicon germanium. While the use of these materials can enhance some device performance characteristics, they may also affect other device performance characteristics. For example, the use of epitaxially grown silicon germanium may degrade interface defects in the device (compared to silicon).

[0088] The step of forming the first trench 103 may be an initial step for eventually forming the first isolation region 105. The first trench 103 may be formed by using a mask layer (not shown in the figure). Figure 1A ) and a suitable etching process. For example, the mask layer can be a hard mask comprising silicon nitride (which can be formed by chemical vapor deposition), but can also be other materials such as oxides, oxynitrides, silicon carbide, combinations thereof, or the like, and can be formed by other processes such as plasma-assisted chemical vapor deposition, low-pressure chemical vapor deposition, or forming silicon oxide followed by a nitridation process. Once the mask layer is formed, it can be patterned by a suitable photolithography process to expose the portion of the substrate 101 that will be removed to form the first trench 103.

[0089] However, those skilled in the art will appreciate that the above-described process and materials for forming the mask layer are not the only methods for protecting portions of the substrate 101 and exposing other portions of the substrate 101 for forming the first trench 103. Any suitable process, such as patterning and developing a photoresist, may be used to expose the portion of the substrate 101 to be removed to form the first trench 103. All such methods are intended to be within the scope of these embodiments.

[0090] Once the mask layer is formed and patterned, a first trench 103 may be formed in the substrate 101. The exposed substrate 101 may be removed by a suitable process such as reactive ion etching to form the first trench 103 in the substrate 101, but any suitable process may be used to remove the exposed substrate 101. In one embodiment, the first trench 103 has a first depth from the surface of the substrate 101 of less than about For example,

[0091] However, those skilled in the art will appreciate that the above process for forming the first trench 103 is only one possible process and not the only embodiment. Rather, any suitable process may be used to form the first trench 103, including any number of masking and removal steps.

[0092] In addition to forming the first trench 103, the masking and etching process can further form fins 107 from the remaining portion of the substrate 101 that is not removed. To facilitate the illustration of the fins 107, the fins 107 and the substrate 101 in the accompanying drawings are separated by a dotted line, but there may or may not be a physical separation between the two. These fins 107 can be used to form the channel region of a multi-gate fin field effect transistor. Although Figure 1A Only three fins 107 formed from substrate 101 are shown, but any number of fins 107 may be employed.

[0093] The fins 107 may have a width on the surface of the substrate 101 of between about 5 nm and about 80 nm, such as about 30 nm. Furthermore, the fins 107 may be spaced apart by a distance of between about 10 nm and about 100 nm, such as about 50 nm. Separating the fins 107 in this manner allows each to form a separate channel region while still being close enough to share a common gate (as described below).

[0094] In addition, the fin 107 can be patterned by any suitable method. For example, the patterning method of the fin 107 can use one or more photolithography processes, including double patterning or multiple patterning processes. Generally speaking, the double patterning or multiple patterning process combines photolithography with a self-alignment process, and the pattern spacing produced is smaller than the pattern spacing obtained by using a single direct photolithography process. For example, one embodiment forms a sacrificial layer on a substrate and uses a photolithography process to pattern the sacrificial layer. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the retained spacers are used to pattern the fin 107.

[0095] Once the first trench 103 and the fin 107 are formed, a dielectric material may be filled into the first trench 103 and recessed to form the first isolation region 105. The dielectric material may be an oxide material, a high-density plasma oxide, or the like. After optionally cleaning and lining the first trench 103, the dielectric material may be formed using chemical vapor deposition (e.g., a high aspect ratio process), high-density plasma chemical vapor deposition, or other suitable methods known in the art.

[0096] The dielectric material may be overfilled between the first trench 103 and the substrate 101, and then the excess material outside the first trench 103 and the fin 107 may be removed to fill the first trench 103. The excess material may be removed by a suitable process such as chemical mechanical polishing, etching, a combination thereof, or the like. In one embodiment, the removal process may remove any dielectric material located on the fin 107, exposing the surface of the fin 107 for subsequent processing steps.

[0097] Once the dielectric material has filled the first trench 103, the dielectric material may then be recessed from the surface of the fin 107. The recessing step may expose at least a portion of the sidewalls of the fin 107 adjacent the upper surface of the fin 107. The dielectric material may be recessed by wet etching, such as immersing the upper surface of the fin 107 in an etchant such as hydrofluoric acid, although other etchants (such as hydrogen) or other methods (such as reactive ion etching, dry etching using ammonia / nitrogen trifluoride as an etchant, chemical oxide removal, or dry chemical cleaning) may also be used. The dielectric material may be recessed from the surface of the fin 107 by a distance between about to about For example, Additionally, the recessing step removes any remaining dielectric material on the fin 107 , ensuring that the fin 107 is exposed for subsequent processing.

[0098] However, those skilled in the art will appreciate that the above steps are only part of the overall process flow for filling the recess with a dielectric material. For example, a lining step, an annealing step, a gap filling step, a combination of the above, or similar steps may be used to form the first trench 103 and fill the first trench 103 with a dielectric material. All possible process steps are included within the scope of this embodiment.

[0099] After forming the first isolation region 105, a dummy gate dielectric layer 109, a dummy gate 111 on the dummy gate dielectric layer 109, and spacers 113 may be formed on each fin 107. In one embodiment, the dummy gate dielectric layer 109 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other known method for forming a gate dielectric layer in the art. The thickness of the dummy gate dielectric layer 109 on the top of the fin 107 may be different from the thickness of the dummy gate dielectric layer 109 on the sidewalls of the fin 107, depending on the gate dielectric layer formation technique.

[0100] The material of the dummy gate dielectric layer 109 may include silicon oxide or silicon oxynitride, and the thickness thereof may be about to about For example, The dummy gate dielectric layer 109 may be formed of a high dielectric constant material (e.g., a material with a dielectric constant greater than about 5), such as lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, or a combination thereof, with an equivalent oxide thickness between about 100 nm and about 200 nm. to about For example, less than or equal to approximately In addition, any combination of silicon oxide, silicon oxynitride, and / or high-k dielectric materials may be used as the dummy gate dielectric layer 109 .

[0101] The dummy gate 111 may comprise a conductive or non-conductive material, such as polysilicon, tungsten, aluminum, copper, aluminum copper, titanium, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, a combination thereof, or the like. The dummy gate 111 may be deposited by chemical vapor deposition, sputtering deposition, or other methods known in the art for depositing conductive materials. The thickness of the dummy gate 111 may be approximately to about The dummy gate 111 may have an uneven upper surface, and the upper surface of the dummy gate 111 may be flattened before patterning the dummy gate 111 or gate etching. Ions may or may not be introduced into the dummy gate 111. For example, ions may be introduced by ion implantation.

[0102] Once the dummy gate dielectric layer 109 and the dummy gate 111 are formed, they can be patterned to form a series of dummy stacks 115 on the fin 107. The dummy stacks 115 define a plurality of channel regions on each side of the fin 107 below the dummy gate dielectric layer 109. The dummy stacks 115 can be formed by depositing and patterning a gate mask (not shown) on the dummy gate 111. Figure 1A ), such as by deposition and photolithography techniques known in the art. The gate mask can be a combination of commonly used masks and sacrificial materials (such as but not limited to silicon oxide, silicon oxynitride, silicon oxycarbonitride, silicon carbide, silicon oxycarbide, and / or silicon nitride), and its deposition thickness can be between about to about A dry etching process may be used to etch the dummy gate 111 and the dummy gate dielectric layer 109 to form a patterned dummy stack 115 .

[0103] Once the dummy stack 115 is patterned, the spacers 113 may be formed. The spacers 113 may be formed on both sides of the dummy stack 115. The spacers 113 may be formed by blanket depositing a (eg, Figure 1A as shown) or multiple (as shown Figure 1B ) spacer layer on the previously formed structure. One or more spacer layers may include silicon nitride, oxynitride, silicon carbide, silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, or the like, and may be formed by chemical vapor deposition, plasma-assisted chemical vapor deposition, sputtering, or other methods known in the art. In embodiments with more than one spacer layer, one or more spacer layers of similar but different materials may be formed in a similar manner, such as materials with different composition percentages and different curing temperatures and porosities. In addition, one or more spacer layers may include the same material as the dielectric material in the first isolation region 105, or a different material with different etching characteristics than the dielectric material in the first isolation region 105, and then the one or more spacer layers may be patterned, such as by removing one or more spacer layers from the horizontal surface of the structure in one or more etching steps. In this way, the one or more spacer layers formed along the sidewalls of the dummy stack 115 are collectively referred to as spacers 113.

[0104] In one embodiment, the thickness of the spacer 113 is about to about Furthermore, once the spacers 113 are formed, the distance between the spacers 113 of adjacent stacks of the dummy stack 115 is between about 5 nm and about 200 nm, such as about 20 nm. However, any suitable thickness and distance may be used.

[0105] Figure 1A Also shown is the removal of the fin 107 from those areas not protected by the dummy stack 115 and spacer 113 (but Figure 1A The fin 107 is still shown in the original position, as well as the structure after the source / drain regions 201 are regrown. The fin 107 is removed from the unprotected areas of the dummy stack 115 and spacers 113 by reactive ion etching using the dummy stack 115 and spacers 113 as a hard mask, or by any other suitable removal process. The removal process can continue until the fin 107 is coplanar with the surface of the first isolation region 105 (as shown) or below the surface of the first isolation region 105.

[0106] Once these portions of the fins 107 are removed, a hard mask (not shown) may be formed and patterned to cover the dummy gates 111 to prevent growth, and source / drain regions 201 may be regrown to contact each fin 107. In one embodiment, the source / drain regions 201 may be regrown to form a stressor that applies stress to the channel region of the fin 107 beneath the dummy stack 115. In one embodiment, the fin 107 comprises silicon and the FinFET is a p-type device, and the source / drain regions 201 may be regrown using a selective epitaxial growth process. The regrown material may be silicon or a material having a different lattice constant than the channel region, such as silicon germanium. The epitaxial growth process may utilize precursors such as silane, dichlorosilane, germane, or the like, and may take from about 5 minutes to about 120 minutes (e.g., about 30 minutes).

[0107] In one embodiment, the thickness of the source / drain region 201 may be between about to about and its height above the first isolation region 105 may be between about to about Between (for example, about In this embodiment, the source / drain region 201 may be higher than the upper surface of the first isolation region 105 by a height between about 5 nm and about 250 nm, such as about 100 nm. However, any suitable height may be used.

[0108] Once the source / drain regions 201 are formed, appropriate dopants may be implanted into the source / drain regions 201 to supplement the dopants in the fins 107. For example, p-type dopants such as boron, gallium, indium, or the like may be implanted to form a p-type metal oxide semiconductor device. In other embodiments, n-type dopants such as phosphorus, arsenic, antimony, or the like may be implanted to form an n-type metal oxide semiconductor device. The implantation of these dopants may utilize the dummy stack 115 and the spacer 113 as a mask. It should be noted that those skilled in the art will appreciate that many other processes, steps, or similar methods may be employed to implant dopants. For example, those skilled in the art will appreciate that various combinations of spacers and liner layers may be employed for various implantations that form source / drain regions of specific shapes or characteristics suitable for specific purposes. Any of these processes may be used to implant dopants, and the foregoing is not intended to limit this embodiment to the foregoing steps.

[0109] Furthermore, the hard mask covering the dummy gate 111 during the formation of the source / drain regions 201 can be removed at this time. In one embodiment, the hard mask can be removed using a wet or dry etching process that is selective to the material of the hard mask. However, any suitable removal process can be used.

[0110] Figure 1A The first interlayer dielectric layer 203 is also shown (in order to clearly show the underlying structure, Figure 1A The first interlayer dielectric layer 203 (indicated by the dotted line in the figure) is formed on the dummy stack 115 and the source / drain region 201. The material of the first interlayer dielectric layer 203 may include borophosphosilicate glass, but any suitable dielectric layer may be used. The formation process of the first interlayer dielectric layer 203 may be plasma-assisted chemical vapor deposition, but other processes such as low-pressure chemical vapor deposition may also be used. The thickness of the first interlayer dielectric layer 203 may be between about to about Once the first interlayer dielectric layer 203 is formed, a planarization process such as a chemical mechanical polishing process may be used to planarize the first interlayer dielectric layer 203 and the spacers 113 . However, any other suitable process may also be used.

[0111] Figure 1B In some embodiments, Figure 1A A cross-sectional view along the cutting line 3 - 3 ′ is provided to facilitate illustrating the formation of the gate contact, gate via, source / drain contacts, and source / drain vias.

[0112] like Figure 2As shown, the dummy gate 111 and the dummy gate dielectric layer 109 are removed. In one embodiment, the dummy gate 111 and the dummy gate dielectric layer 109 may be removed using one or more wet etching or dry etching processes, wherein the etchant used is selective to the materials of the dummy gate 111 and the dummy gate dielectric layer 109. However, any suitable removal process may be used.

[0113] Once the dummy gate 111 and the dummy gate dielectric layer 109 are removed, the multiple layers of the gate stack may be deposited (at Figure 2 The first dielectric material is collectively referred to as the gate stack 603, and includes a first dielectric material, a first conductive layer, a first metal material, a work function layer, and a first barrier layer. In one embodiment, the first dielectric material is a high dielectric constant material such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, lanthanum oxide, zirconium oxide, tantalum oxide, combinations thereof, or the like, and the deposition process may be atomic layer deposition, chemical vapor deposition, or the like. The deposition thickness of the first dielectric material may be between about 1000Å and 1000Å. to about However, any suitable material and thickness may be used.

[0114] Before forming the first dielectric material, an interfacial layer may be formed as appropriate. In one embodiment, the interfacial layer may be made of silicon oxide and formed using an in-situ steam generation process. However, any suitable material or formation process may be used.

[0115] The first conductive layer may be a metal silicide material such as titanium silicon nitride. In one embodiment, the first conductive layer may be formed by a deposition process such as chemical vapor deposition, but any suitable deposition method (such as deposition and subsequent silicidation step) may also be used, and its thickness may be between about to about However, any suitable thickness may be used.

[0116] The first metal material may be adjacent to the first dielectric material to serve as a barrier layer, and the first metal material may be tantalum nitride, titanium, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, ruthenium, molybdenum, tungsten nitride, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or the like. The first metal material may be deposited by atomic layer deposition, chemical vapor deposition, sputtering, or the like, and may have a thickness between about 1000 nm and 1000 nm. to about However, any suitable deposition process or thickness may be used.

[0117] The work function layer is formed on the first metal material, and the material used for the work function layer is selected based on the type of device required. Exemplary p-type work function metals may include aluminum, titanium aluminum carbide, titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals may include titanium, silver, tantalum aluminum, tantalum aluminum carbide, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, other suitable n-type work function materials, or combinations thereof. The work function value is related to the material composition of the work function layer, so the material of the work function layer can be selected to adjust its work function value so that individual regions in the device reach the desired critical voltage. The deposition method of the work function layer can be chemical vapor deposition, physical vapor deposition, and / or other suitable processes, and the deposition thickness of the work function layer can be between about to about between.

[0118] The first barrier layer may be adjacent to the work function layer, and in a specific embodiment, the first barrier layer may be similar to the first metal material. For example, the first barrier layer may be a metal material such as titanium nitride, titanium, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, tantalum nitride, ruthenium, molybdenum, tungsten nitride, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or the like. In addition, the deposition process of the first barrier layer may be atomic layer deposition, chemical vapor deposition, sputtering, or the like, and the thickness thereof may be between about 100 nm and about 200 nm. to about However, any suitable deposition process or thickness may be used.

[0119] The material of the metal layer can be suitable as a seed layer to facilitate the subsequent filling process and help block or reduce the migration of fluorine atoms into the work function layer. In a specific embodiment, the metal layer can be crystalline tungsten, and its formation method can be an atomic layer deposition process that does not contain fluorine atoms, but any suitable deposition process can also be used. The thickness of the metal layer can be between about to about between, for example, between to about between.

[0120] Once the metal layer is formed, a fill material may be deposited to fill the remainder of the opening. In one embodiment, the fill material may be aluminum, copper, aluminum copper, tungsten, titanium, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, combinations thereof, or the like, and may have a thickness between about 1000 Å and about 2000 Å. to about Between, such as However, any suitable material may be used.

[0121] After depositing the fill material to fill or overfill the opening, the first dielectric material, the first conductive layer, the first metal material, the work function layer, the first barrier layer, the metal layer, and the fill material may be planarized to form the gate stack 603. In one embodiment, a chemical mechanical polishing process or the like may be used to planarize the material and the first interlayer dielectric layer 203, but any suitable process such as polishing or etching may also be used. In addition, the bottom width W of the gate stack 603 after planarization is B It may be between about 10 nm and about 13 nm (such as about 11 nm), but any suitable size may be used.

[0122] like Figure 2 As shown, the gate stack 603 is recessed. After the gate stack 603 material is formed and patterned, an etch back process 205 (in Figure 2 The material of gate stack 603 is recessed (indicated by an arrow in the figure), and the etchant used in etch-back process 205 is selective to the material of gate stack 603. Etch-back process 205 can be a wet etch or a dry etch process, and the etchant used is selective to the material of gate stack 603. In some embodiments, the first distance D1 by which the material of gate stack 603 is recessed can be between about 5 nm and about 150 nm, such as about 120 nm. However, any suitable etching process, any suitable etchant, and any suitable distance can be used.

[0123] When recessing the gate stack 603, the spacer 113 may also be recessed, but the recessed depth of the spacer 113 is less than that of the gate stack 603. Thus, in one embodiment, the spacer 113 is recessed by a second distance D2 between about 1 nm and about 10 nm, such as about 5 nm. However, any suitable distance may be used.

[0124] like Figure 3 As shown, a first metal layer 301 is deposited, and a first hard mask layer 303 is deposited on the first metal layer 301. Once the material of the gate stack 603 is recessed, the first metal layer 301 (e.g., a capping layer) is deposited to serve as an etch stop layer for subsequent processes (as described below). In one embodiment, the first metal layer 301 is a metal material such as tungsten, cobalt, aluminum, zirconium, gold, platinum, copper, ruthenium, alloys of the above metal materials, or the like, and its formation method can use an atomic layer deposition process to selectively grow on the material of the gate stack 603 without forming on other exposed surfaces. The thickness of the first metal layer 301 can be between about 1 nm and about 10 nm, such as 3 nm. However, any suitable material, formation process, and thickness can also be used.

[0125] In one embodiment, the material of the first hard mask layer 303 has a high etch selectivity to other materials used to form the gate stack 603, the first metal layer 301, the first interlayer dielectric layer 203, and the spacer 113, such as an oxide such as silicon oxide or a nitride such as silicon nitride. The first hard mask layer 303 has a high etch selectivity to the material of the second metal layer used to form the plurality of source / drain contacts 503, and the second hard mask material of the isolation region 803 (not shown). Figure 3 , but paired with Figure 5 and Figure 8 Detailed description) also has high etch selectivity. Thus, when etching any material with high etch selectivity to the first hard mask layer 303, the first hard mask layer 303 can serve as an etch mask with little residual material, without the need for another etch stop layer.

[0126] Furthermore, in some embodiments, the dielectric material of the first hard mask layer 303 exhibits excellent chemical mechanical polishing properties, which helps increase integration flexibility in advanced technology nodes. In one embodiment, the material of the first hard mask layer 303 may be silicon nitride, but other suitable materials such as silicon oxide, aluminum oxide, silicon oxycarbide, silicon carbide, zirconium nitride, zirconium oxide, combinations thereof, or the like may also be used. The deposition process of the first hard mask layer 303 may be plasma-assisted atomic layer deposition, thermal atomic layer deposition, or plasma-assisted chemical vapor deposition, and the process temperature may be maintained between approximately 250°C and approximately 400°C. However, any suitable deposition process and process conditions may be used.

[0127] These materials protect gate height and help reduce or avoid etching loss or damage during subsequent etching processes, as described below. Furthermore, these materials can achieve high oxide etch selectivity when etching oxides with small critical dimensions and high aspect ratios. Furthermore, these materials can provide high etch selectivity when etching the second hard mask material of the isolation region 803, and offer a wide etch process tolerance.

[0128] Once the first hard mask layer 303 is deposited, it can be planarized to remove excess material. In one embodiment, the first hard mask layer 303 can be planarized using a process such as chemical mechanical polishing, where an etchant and an abrasive, combined with a rotating plate, react to remove excess material from the first hard mask layer 303. However, any suitable planarization process can be used to planarize the first hard mask layer 303 and the first interlayer dielectric layer 203.

[0129] By planarizing the first hard mask layer 303 and the first interlayer dielectric layer 203, the first hard mask layer 303 can have two portions: a first portion located within the spacers 113, and a second portion located outside the spacers 113 and within the first interlayer dielectric layer 203. In one embodiment, the first portion has a first width W1 between approximately 12 nm and approximately 15 nm (e.g., approximately 12 nm), and a first thickness T1 between approximately 20 nm and approximately 30 nm (e.g., approximately 22 nm). Furthermore, the second portion has a second width W2 between approximately 20 nm and approximately 28 nm (e.g., approximately 22 nm), and a second thickness T2 between approximately 14 nm and approximately 26 nm (e.g., approximately 16 nm). However, any suitable dimensions may be employed.

[0130] like Figure 4 As shown, the etching process 401 is performed (in Figure 4 1 ) to form source / drain via openings 403 through the first interlayer dielectric layer 203, exposing the source / drain regions 201. In some embodiments, the first hard mask layer 303 and the spacers 113 may serve as masks, and the etching process 401 may include one or more reactive ion etching processes using an etchant that is selective to the material of the first interlayer dielectric layer 203. However, any suitable etchant may be used.

[0131] In addition, other masks may be used for the etching process 401 without departing from the concepts of the embodiments disclosed herein. For example, one or more other hard mask layers may be deposited on the first hard mask layer 303 and then patterned using photolithographic masking and etching processes to form the other masks. For example, a single or triple layer of photoresist may be applied to the one or more hard mask layers and the photoresist may be exposed and developed to form the desired pattern. Once the desired pattern is formed in the photoresist, one or more etching processes may be used to transfer the photoresist pattern to the one or more other hard mask layers below, and the patterned one or more other hard mask layers may serve as a mask for the etching process 401. However, any suitable process may be used to form the source / drain via openings 403 through the first interlayer dielectric layer 203 and expose the source / drain regions 201.

[0132] like Figure 5As shown, once the source / drain region 201 is exposed, a silicide contact 501 may be formed on the source / drain region 201 as appropriate. The silicide contact 501 formed as appropriate may include titanium, such as titanium silicide, to reduce the Schottky barrier of the contact. However, other metals such as nickel, cobalt, erbium, platinum, palladium, or the like may also be used. A suitable metal layer may be conformally deposited, and then an annealing step may be performed to allow the metal to react with the silicon exposed in the underlying source / drain region 201 to perform a silicidation step. The unreacted metal is then removed, and the removal method may be a selective etching process. The thickness of the silicide contact formed as appropriate may be between about 5 nm and about 50 nm.

[0133] like Figure 5 As shown, a second metal layer is formed for the source / drain contacts 503 to physically contact the optional silicide contacts (if present) or the source / drain regions 201. In one embodiment, the second metal layer used for the source / drain contacts 503 may be a conductive material such as tungsten, aluminum, copper, aluminum-copper, cobalt, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum, tantalum tantalide, nickel, titanium, titanium aluminum nitride, ruthenium, molybdenum, or tungsten nitride. However, any suitable material such as aluminum, copper, alloys thereof, combinations thereof, or the like may be used, and the second metal layer may be deposited by sputtering, chemical vapor deposition, electroplating, electroless plating, or the like to fill and / or overfill the opening in the first hard mask layer 303.

[0134] Once the second metal layer is deposited, the second metal layer and the first hard mask layer 303 for the source / drain contacts 503 may be planarized to remove excess material and separate the second metal layer into a plurality of individual source / drain contacts 503 corresponding to the respective regions of the source / drain regions 201. In one embodiment, the second metal layer for the source / drain contacts 503 may be planarized using a chemical mechanical polishing process, wherein an etchant and an abrasive, in conjunction with a rotating plate, react and remove excess material from the second metal layer for the source / drain contacts 503 and / or the material of the first hard mask layer 303. However, any suitable planarization process may be used to planarize the second metal layer and the first hard mask layer 303 for the source / drain contacts 503 and separate the second metal layer into a plurality of individual source / drain contacts 503. In this way, the contact regions of the second metal layer corresponding to the individual contacts of the source / drain contacts 503 and the first hard mask layer 303 can be planarized, and the contact regions of the second metal layer are exposed in the first hard mask layer 303 .

[0135] like Figure 6As shown, a photoresist mask 601 is deposited and patterned on the planar surfaces of the second metal layer and the first hard mask layer 303 for the source / drain contacts 503 in preparation for subsequent processing. In some embodiments, a single or triple layer of photoresist is applied to the planar surfaces of the second metal layer and the first hard mask layer 303 for the source / drain contacts 503. Once the photoresist is applied, it can be exposed and developed to form a desired pattern in the photoresist mask 601. In some embodiments, the pattern of the photoresist mask 601 exposes some surface area of ​​the second metal layer for the source / drain contacts 503, while the photoresist mask 601 remains covered.

[0136] exist Figure 7 In some embodiments shown, the second metal layer of the source / drain contacts 503 exposed from the photoresist mask 601 is recessed. In some embodiments, the photoresist mask 601 and the first hard mask layer 303 serve as masks, and an etching process 701 (e.g., wet etching, dry etching, or the like) is used to recess the second metal layer of the source / drain contacts 503 to below the planar surface of the first hard mask layer 303. In one embodiment, the method of recessing the second metal layer for the source / drain contacts 503 employs one or more etchants that are selective to the material of the second metal layer (e.g., cobalt) and do not significantly remove the material of the first hard mask layer 303. As a result, the first recess 703 is formed into the exposed source / drain contacts 503 in the second metal layer, while the source / drain contacts 503 and the first hard mask layer 303 protected by the photoresist mask 601 remain planar. In one embodiment, the depth of the first recess 703 , such as the third distance D3 , is between about 1 nm and about 20 nm, such as about 10 nm. However, any suitable depth may be used.

[0137] like Figure 8 As shown, the photoresist mask 601 is removed (e.g., by ashing) and a second hard mask material for the isolation region 803 is deposited into the first recess 703. In one embodiment, the second hard mask material for the isolation region 803 has a high etch selectivity relative to the first hard mask layer 303 and the spacer 113. For example, the etch selectivity of the second hard mask material for the isolation region 803 relative to the first hard mask layer 303 and the spacer 113 is greater than about 12, such as between about 12 and about 40.

[0138] In some embodiments, the second hard mask material of the isolation region 803 may be a single layer or a stack of multiple dielectric layers, and its material may include a high-k dielectric material (e.g., a dielectric constant greater than 4), a low-k dielectric material (e.g., a dielectric constant less than 4), and / or a metal oxide material. The second hard mask material of the isolation region 803 may be a high-k dielectric material (e.g., a dielectric constant greater than 4), such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, a silicon compound, a nitride compound, an oxide compound, a combination thereof, or the like. The second hard mask material of the isolation region 803 may also be a low-k dielectric material (e.g., a dielectric constant less than 4), such as SiLK, Black Diamond, a combination thereof, or the like. In addition, the second hard mask material of the isolation region 803 may also be composed of a metal oxide material such as zirconium oxide, aluminum oxide, a combination thereof, or the like. However, any other suitable material may be used. The second hard mask material of the isolation region 803 may be deposited by plasma-assisted atomic layer deposition, thermal atomic layer deposition, or plasma-assisted chemical vapor deposition, wherein the process temperature is maintained between about 250° C. and about 400° C. However, any suitable deposition and process conditions may be used.

[0139] A second hard mask material for the isolation region 803 can be formed to fill and overfill the first recess 703 in the recessed source / drain contact 503 of the second metal layer. Once the second hard mask material for the isolation region 803 is deposited, a planarization process, such as a chemical mechanical polishing process, can be used to planarize the second hard mask material for the isolation region 803 and the first hard mask layer 303, although any suitable process may be used. In some embodiments, the first thickness Th1 of the second hard mask material for the isolation region 803 is between approximately 0.5 nm and approximately 20 nm. Thus, the second hard mask material for the isolation region 803 serves as an isolation region for the recessed source / drain contact 503 of the second metal layer, as described in detail below.

[0140] like Figure 9As shown, when recessing the exposed one or more source / drain contacts 503 of the second metal layer, a photoresist mask 601 is used to protect the one or more source / drain contacts 503 of the remaining second metal layer, and a second recess 903 is formed in the one or more source / drain contacts 503 of the remaining second metal layer. In some embodiments, the first hard mask layer 303 and the second hard mask material of the isolation region 803 serve as masks, and an etching process 901 (such as a wet etching, dry etching, or the like) is used to recess the one or more source / drain contacts 503 of the remaining second metal layer to below the planar surface of the first hard mask layer 303. In one embodiment, the one or more etchants used in the method of recessing the second metal layer of the source / drain contacts 503 are selective to the second metal layer (such as cobalt) used for the source / drain contacts 503 and do not significantly remove the material of the first hard mask layer 303 and the second hard mask material of the isolation region 803. Thus, the second recess 903 is formed to a depth, such as a fourth distance D4, in the exposed surface of the one or more source / drain contacts 503 of the remaining second metal layer, ranging from about 10 nm to about 40 nm (eg, about 28 nm). However, any suitable depth may be used.

[0141] like Figure 10 As shown, a third metal layer is formed for forming source / drain metal bumps 1003 to physically connect to one or more source / drain contacts 503 of the remaining second metal layer. In the embodiment described herein, the third metal layer used for source / drain metal bumps 1003 is a conductive material that is different from the material of the second metal layer used for source / drain contacts 503. The material of source / drain metal bumps 1003 can be tungsten, aluminum, copper, aluminum-copper, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum, tantalum nitride, nickel, titanium, titanium aluminum nitride, ruthenium, molybdenum, nitride, or cobalt, but any suitable material such as aluminum, copper, alloys thereof, combinations thereof, or the like can also be used. The deposition process of the third metal layer used for the source / drain metal bumps 1003 may be sputtering, chemical vapor deposition, atomic layer deposition, electroplating, electroless plating, or the like, so as to fill and / or overfill the second recess 903 in the one or more source / drain contacts 503 of the remaining second metal layer with the third metal layer. However, any suitable material and any suitable deposition process may be used.

[0142] Once the third metal layer for the source / drain metal protrusions 1003 is deposited, the third metal layer for the source / drain metal protrusions 1003 and the first hard mask layer 303 can be planarized to remove excess material, and the third metal layer can be separated into a plurality of independent metal protrusions to form source / drain metal protrusions 1003 (such as 1003A, 1003B, and 1003C) corresponding to the individual contacts (such as 503A, 503B, and 503C) of the source / drain contacts 503. Figure 10 It passes through Figure 1A The cross-sectional view taken along line 3-3' of FIG. 1 shows that the third source / drain metal bump 1003C is formed on and physically contacts the third source / drain contact 503C. Figure 10 Although not shown, it should be understood that in other cross-sectional views, the first source / drain metal bump 1003A and the second source / drain metal bump 1003B may be formed on and in physical contact with the first source / drain contact 503A and the second source / drain contact 503B, respectively, as will be described in detail below with reference to the following figures. In one embodiment, the third metal layer used for the source / drain metal bump 1003 may be planarized using a process such as chemical mechanical polishing (CMP). An etchant and an abrasive, combined with a rotating plate, react to remove excess material from the third metal layer used for the source / drain metal bump 1003, the material of the first hard mask layer 303, and / or the second hard mask material of the isolation region 803. As a result, the second thickness Th2 of the third metal layer used for the source / drain metal bump 1003 may be between approximately 0.5 nm and approximately 20 nm. However, any suitable planarization process and any suitable dimensions can be used to planarize the third metal layer, the first hard mask layer 303, and the second hard mask material of the isolation region 803 used for the source / drain metal protrusions 1003, and separate the third metal layer into individual metal protrusions to form the source / drain metal protrusions 1003 (such as 1003A, 1003B, and 1003C).

[0143] In some embodiments, the third source / drain metal bump 1003C, the third source / drain contact 503C, and the optional silicide contact 501 (if present) together form a third source / drain contact stack 1001C of the third source / drain region 201C. In some embodiments, the material of the third source / drain metal bump 1003C is different from the material of the third source / drain contact 503C. As such, the third source / drain contact stack 1001C may be referred to herein as a mixed source / drain contact stack. Figure 10In the cross-sectional view of FIG, the first source / drain metal bump 1003A and the first source / drain contact 503A form a first source / drain contact stack 1001A for the first source / drain region 201A, and the second source / drain metal bump 1003B and the second source / drain contact 503B form a second source / drain contact stack 1001B for the second source / drain region 201B. The first source / drain contact stack 1001A, the second source / drain contact stack 1001B, and the third source / drain contact stack 1001C are collectively referred to herein as source / drain contact stacks 1001. In addition, portions of the second hard mask material serve as isolation regions 803 on the corresponding contact stacks of the source / drain contact stacks 1001 (e.g., 1001A, 1001B, and 1001C). Although Figure 10 Although not shown, it should be understood that in other cross-sectional views along other cut lines, the isolation region 803 is located on the third source / drain contact stack 1001C, which will be described in detail below with subsequent figures. In some embodiments, the height of the isolation region 803 (e.g. Figure 8 The first thickness Th1 of the isolation region 803 may be respectively the same as the height of the first source / drain metal protrusion 1003A, the second source / drain metal protrusion 1003B, and the third source / drain metal protrusion 1003C (e.g. Figure 10 The thickness Th2 of the third source / drain metal protrusion 1003C is directly related to the thickness Th2 of the third source / drain metal protrusion 1003C, as described in detail below.

[0144] like Figure 11 In some embodiments shown, a contact etch stop layer 1101 and a second interlayer dielectric layer 1103 are formed on the planar surface of the third metal layer used for the source / drain metal bumps 1003, the first hard mask layer 303, and the second hard mask material of the isolation region 803. In some embodiments, Figure 11 Also shown are gate via contacts 1105 and source / drain via contacts 1107 penetrating the second interlayer dielectric layer 1103 and the contact etch stop layer 1101. The gate via contact 1105 is formed on and electrically coupled to the first gate stack 603A of the gate stack 603, while the source / drain via contacts 1107 are formed on and electrically coupled to the third source / drain region 201C of the source / drain region 201.

[0145] After depositing the third metal layer for the source / drain metal bumps 1003, the third metal layer, the first hard mask layer 303, and the second hard mask material for the isolation region 803 are planarized, and then a contact etch stop layer 1101 is deposited on the third metal layer for the source / drain metal bumps 1003. In some embodiments, the contact etch stop layer 1101 can be formed as a single layer or multiple etch stop layers, and the material used can be silicon nitride, silicon oxycarbide, aluminum oxide, combinations thereof, or the like, and can be blanket and / or conformally deposited on any exposed surfaces of the source / drain contacts 503, the third metal layer for the source / drain metal bumps 1003, the first hard mask layer 303, and / or the second hard mask material for the isolation region 803. The contact etch stop layer 1101 can be deposited using one or more low-temperature deposition processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In one embodiment, the contact etch stop layer 1101 may be a multi-layer etch stop layer, which may be formed by depositing a first etch stop material such as aluminum oxide on the third metal layer (serving as the source / drain metal bumps 1003), the first hard mask layer 303, and the flat surface of the second hard mask material of the isolation region 803, and then depositing a second etch stop material (such as silicon nitride) on the first etch stop layer. In some embodiments, the total deposition thickness of the contact etch stop layer 1101, such as the third thickness Th3, may be between about 100 and 200 nm. to about Between, such as However, any suitable etch stop material, any suitable number of etch stop layers, or any suitable combination thereof may be deposited to form the contact etch stop layer 1101 .

[0146] Once the contact etch stop layer 1101 is formed, a second interlayer dielectric layer 1103 is deposited on the contact etch stop layer 1101. The second interlayer dielectric layer 1103 may be composed of a dielectric material such as an oxide (e.g., silicon oxide) and may be formed by an acceptable process such as chemical vapor deposition, plasma-assisted atomic layer deposition, thermal atomic layer deposition, plasma-assisted chemical vapor deposition, or the like. However, other suitable insulating materials (e.g., phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like) deposited by any suitable method (e.g., chemical vapor deposition, plasma-assisted chemical vapor deposition, flowable chemical vapor deposition, or the like) may also be used. After the second interlayer dielectric layer 1103 is formed, it may be cured and then planarized using a planarization process such as a chemical mechanical polishing process. The curing method may be an ultraviolet curing process, but any suitable process may also be used. Thus, the fourth thickness Th4 of the second interlayer dielectric layer 1103 is between about 5 nm and about 20 nm, such as about 13 nm. However, any suitable thickness may be used.

[0147] Once the second interlayer dielectric layer 1103 is formed and planarized, contact via openings for the gate via contact 1105 and the source / drain via contact 1107 are formed through the second interlayer dielectric layer 1103. The openings may be formed using one or more etching processes. In some embodiments, the openings for the gate via contact 1105 are formed through the second interlayer dielectric layer 1103, the contact etch stop layer 1101, and the first hard mask layer 303. The first hard mask layer 303 and the openings for the source / drain via contact 1107 are formed through the second interlayer dielectric layer 1103 and the contact etch stop layer 1101. The openings may be formed using any combination of acceptable photolithography and suitable etching techniques, such as dry etching processes (e.g., plasma etching, reactive ion etching, or physical etching such as ion beam etching), wet etching, combinations thereof, or the like. However, any suitable etching process may be used to form the contact via openings.

[0148] Once the openings are formed, one or more conductive materials may be filled or overfilled into the openings to form gate via contacts 1105 and source / drain via contacts 1107. In one embodiment, a liner layer, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material may be formed in the openings. The liner layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, may be performed to remove excess material from the surface of the second interlayer dielectric layer 1103. The remaining liner layer and conductive material form gate via contacts 1105 and source / drain via contacts 1107 in the openings. In one embodiment, the gate via contact 1105 is physically coupled to the first metal layer 301 and electrically coupled to the first gate stack 603A of the gate stack 603 via the first metal layer 301. The source / drain via contact 1107 is physically coupled to the third source / drain metal bump 1003C and electrically coupled to the third source / drain region 201C via the third source / drain contact stack 1001C. Furthermore, the gate via contact 1105 and the source / drain via contact 1107 can be formed using different processes or the same process.

[0149] In some embodiments, the entire first height H1 of the gate via contact 1105 may be between about 5 nm and about 45 nm (e.g., about 30 nm), and the first angle θ1 of its sidewall with the first metal layer 301 may be between about 80° and about 150° (e.g., about 97°). The third width W3 of the top of the gate via contact 1105 may be between about 10 nm and about 20 nm (e.g., about 12 nm), and the fourth width W4 of the bottom may be between about 8 nm and about 20 nm (e.g., about 10 nm). However, the gate via contact 1105 may have any suitable height, any suitable angle, and any suitable width.

[0150] In some embodiments, Figure 11 The gate via contact 1105 in the cross-sectional view along the cut line 3-3' has a sloped sidewall between the isolation regions 803 of the corresponding source / drain regions 201 (eg, 201A and 201C). In addition, the height of the isolation regions 803 (eg, Figure 8 The first thickness Th1 of the isolation region 803 may be proportional to the height of the corresponding source / drain metal protrusion 1003. Thus, the step height of the first source / drain metal protrusion 1003A associated with the isolation region 803 (e.g., Figure 8 The first thickness Th1 of the middle isolation region 803 and the process tolerance range of the distances from the first and second gate vias to the source / drain contacts can increase the process tolerance range of the first gate via to the source / drain contacts.

[0151] For example, for the first source / drain contact 503A, when the isolation region 803 is not present, the first source / drain contact 503A extends to the contact etch stop layer 1101. Consequently, the first source / drain contact 503A is separated from the gate via contact 1105 by a third distance D3, which may be between about 1 nm and about 10 nm, such as about 5 nm. However, by recessing the first source / drain contact 503A and forming the isolation region 803, the first source / drain contact 503A is separated from the gate via contact 1105 by a fourth distance D4 between about 1 nm and about 10 nm, such as about 6 nm. By extending the distance between the first source / drain contact 503A and the gate via contact 1105, the overall process tolerance can be improved.

[0152] Furthermore, in some embodiments, the overall second height H2 of the source / drain via contact 1107 is between about 10 nm and about 30 nm (e.g., about 20 nm), and the second angle θ2 formed between the sloped sidewalls and the third metal layer used for the source / drain metal bump 1003 is between about 80° and about 150°, such as about 107°. A fifth width W5 at the top of the source / drain via contact 1107 is between about 8 nm and about 20 nm (e.g., about 14 nm), and a sixth width W6 at the bottom is between about 8 nm and about 20 nm (e.g., about 12 nm). However, the source / drain via contact 1107 may have any suitable height, angle, and width.

[0153] Figure 12 In some embodiments, a top view of the semiconductor device 100 is shown, which has multiple cut lines (such as Figure 1A and Figure 11 The relevant tangent line 3-3') will be described below with reference to the subsequent figures. Figure 12The top view also shows a plurality of gate via contacts 1105 and a plurality of source / drain via contacts 1107 exposed from the planar surface of the second interlayer dielectric layer 1103 of the semiconductor device 100. For clarity of illustration and further reference to subsequent figures, the structure below the mixed source / drain contact stack 1001, source / drain metal bumps 1003, and gate stack 603 and their relative positions are also shown in FIG. Figure 12 in the top view.

[0154] Specifically, Figure 12 The cut line 3-3' shown intersects the first source / drain contact stack 1001A, the gate via contact 1105, the first gate stack 603A, the second source / drain contact stack 1001B, the second gate stack 603B, the third source / drain contact stack 1001C, the third source / drain metal bump 1003C, and the source / drain via contact 1107 from left to right. These structures are also shown in FIG. Figure 11 In the middle (from left to right), the X-sections (such as the cut lines AA, BB, and CC) and the Y-sections intersect various structures of the semiconductor device 100 , which will be described in detail below with reference to the following figures.

[0155] Figure 13A In some embodiments, Figure 12 FIG10 is a diagram illustrating a plurality of cross-sectional views of the X-section taken along lines AA, BB, and CC of FIG10. In the cross-sectional view taken along line AA of the X-section, the gate via contact 1105 passes through the second interlayer dielectric layer 1103 and the contact etch stop layer 1101, and is physically and electrically coupled to the gate stack 603 in the fin 107 via the first metal layer 301. The gate stack 603 and the spacer 113 separate a portion of the first source / drain contact stack 1001A from a portion of the second source / drain contact stack 1001B. As shown in the figure taken along line AA, a portion of the first source / drain contact stack 1001A is located between the fin 107 (and the associated source / drain region 201) and the isolation region 803, while a portion of the second source / drain contact stack 1001B is located between the fin 107 (and the associated source / drain region 201) and the isolation region 803.

[0156] In the cross-sectional view taken along line BB in the X-section, source / drain via contacts 1107 penetrate the second interlayer dielectric layer 1103 and the contact etch stop layer 1101 and are physically and electrically coupled to the source / drain region 201 in the fin 107 via the first source / drain contact stack 1001A. The first source / drain contact stack 1001A includes a first source / drain metal bump 1003A, a first source / drain contact 503A, and an optional silicide contact 501 (if present). The first portion of the first hard mask layer 303 and the gate stack 603 are separated from the second portion of the first hard mask layer 303 and the other gate stack 603 by the first source / drain contact stack 1001A. The gate stack 603 and the first source / drain contact stack 1001A are separated by spacers 113. As shown in the figure along the cut line BB, the gate stack 603 and the first metal layer for the source / drain metal bumps 1003 thereover are located between the fin 107 and the first portion of the first hard mask layer 303. As shown in the figure along the cut line BB, the gate stack 603 and the first metal layer for the source / drain metal bumps 1003 thereover are located between the fin 107 and the second portion of the first hard mask layer 303 below the contact etch stop layer 1101 and the second interlayer dielectric layer 1103.

[0157] In the cross-section taken along line CC of the X-section, a second source / drain contact stack 1001B is located beneath the contact etch stop layer 1101 and the second interlayer dielectric layer 1103. The second source / drain contact stack 1001B includes a second source / drain metal bump 1003B, a second source / drain contact 503B, and, if present, an optional silicide contact 501. The first portion of the first hard mask layer 303 and the gate stack 603 are separated from the second portion of the first hard mask layer 303 and the other gate stack 603 by the second source / drain contact stack 1001B. The first gate stack 603A and the second gate stack 603B are separated from the second source / drain contact stack 1001B by spacers 113. As shown in the drawing taken along line CC, the gate stack 603 and the first metal layer for the source / drain metal bumps 1003 above are located between the fin 107, the contact etch stop layer 1101, and the first portion of the first hard mask layer 303 below the second interlayer dielectric layer 1103. As shown in the drawing taken along line CC, the first metal layer for the source / drain metal bumps 1003 and the gate stack 603 are located between the fin 107, the contact etch stop layer 1101, and the second portion of the first hard mask layer 303 below the second interlayer dielectric layer 1103. As a result, in the cross-sectional view taken along line CC, the second source / drain contact stack 1001B and the gate stack 603 are separated from the planar surface of the second interlayer dielectric layer 1103 by the dielectric material of the second interlayer dielectric layer 1103.

[0158] Figure 13B In some embodiments, Figure 12 , which is related to some structures of the X-section through the cut line BB. In the Y-section cross-sectional view, the source / drain via contact 1107 passes through the second interlayer dielectric layer 1103 and the contact etch stop layer 1101 and is physically and electrically coupled to the source / drain region 201 in the fin 107 via the hybrid source / drain contact stack 1001. The hybrid source / drain contact stack 1001 includes the source / drain metal bump 1003, the source / drain contact 503, and the optional silicide contact 501 (if present). The isolation region 803 isolates a portion of the source / drain contact 503 from the contact etch stop layer 1101. In some embodiments, the total width of the source / drain contact 503, such as the sixth width W6, may be between about 10 nm and about 300 nm (e.g., about 25 nm), and the total height, such as the third height H3, may be between about 5 nm and about 40 nm (e.g., about 20 nm).

[0159] Figure 13A Also shown are some dimensions of some interfaces between the source / drain via contact 1107, the source / drain metal bump 1003, and the source / drain contact 503. In some embodiments, a seventh width W7 of the source / drain via contact 1107 at the interface between the source / drain via contact 1107 and the source / drain metal bump 1003 may be between about 8 nm and about 20 nm, such as about 12 nm. In some embodiments, an eighth width W8 of the source / drain metal bump 1003 at the interface between the source / drain metal bump 1003 and the contact etch stop layer 1101 may be between about 10 nm and about 300 nm, such as about 15 nm. A ninth width W9 of the source / drain metal bump 1003 at the interface between the source / drain metal bump 1003 and the source / drain contact 503 may be between about 10 nm and about 300 nm, such as about 17 nm. As a result, the interface between the source / drain metal bumps 1003 and the source / drain contacts 503 can provide a larger contact surface area than the contact surface area provided by the source / drain contacts 503 alone.

[0160] In some embodiments, the source / drain via contact 1107 can be made of the same material as the source / drain metal bump 1003 to provide a low-resistance interface between the source / drain via contact 1107 and the source / drain metal bump 1003. Consequently, the source / drain metal bump 1003 can provide lower resistive / capacitive power loss between the source / drain via contact 1107 and the source / drain contact 503. As described above, the isolation region 803 can increase the process tolerance between the source / drain contact 503 and the gate via contact 1105. Therefore, the hybrid source / drain contact stack 1001 can increase performance and yield, as the isolation region 803 increases process tolerances, and the source / drain metal bump 1003 provides a large surface area contact and a low-resistance conductive interface with the source / drain contact 503.

[0161] A semiconductor device 1400 according to another embodiment is Figure 14 As shown in the top view of FIG. 1 , it includes multiple source / drain contact stacks (such as 1501A, 1501B, and 1501C) of equal height. Figure 14 The semiconductor device 1400 includes a gate via contact 1105 and a source / drain via contact 1107 exposed from a flat surface of the second interlayer dielectric layer 1103. Figure 14 The source / drain contact stack 1501, the raised metal portion of the first source / drain contact 503A (described in detail below), and the underlying structure of the gate stack 603 are shown with their relative positions. Figure 12 and Figure 14 , to illustrate the structure of the semiconductor device 1400. In addition, Figure 14 References Figure 12 The X-sections (such as the tangent lines AA, BB, and CC) and the Y-sections are shown for comparison and are described in detail below with reference to the subsequent figures. Figure 14 The same reference numerals as those used in the above contents of the semiconductor device 100 are used in the subsequent figures. Figures 1A to 12 The structure is the same or similar, so it will not be repeated later. Figures 1A to 12 Related descriptions of structures that are identical or similar to the structures in .

[0162] Figure 15A and Figure 15B show Figure 14 The X-section (such as the tangent lines AA, BB, and CC) and the Y-section are cross-sectional views. Figure 12 In some embodiments, the contact etch stop layer 1101 and the second interlayer dielectric layer 1103 may be deposited on the substrate. Figure 8 In the structure shown, the second recess 903 is not formed in one or more source / drain contacts 503 of the remaining second metal layer (eg, Figure 9 ), and no source / drain metal protrusions 1003 such as 1003A, 1003B, and 1003C are formed in the second recess 903 (as shown). Figure 10 As shown in FIG), a source / drain contact 503 having a raised metal portion is formed. In this way, the source / drain via contact 1107 can pass through the second interlayer dielectric layer 1103 and the contact etch stop layer 1101 (such as with FIG). Figure 11 ), and may be formed on and in physical contact with the source / drain contacts 503 (without the source / drain metal bumps 1003 formed therebetween).

[0163] exist Figure 15A In the cross-sectional view of the X-section taken along line AA, there is a gate via contact 1105, a gate stack 603, and a spacer 113 separating a first equal-height source / drain contact stack 1501A (see line BB) and a second equal-height source / drain contact stack 1051B (see line CC). As shown in the figure taken along line AA, the first equal-height source / drain contact stack 1501A is located between the fin 107 (and the associated source / drain region 201) and the isolation region 803, and the second equal-height source / drain contact stack 1501B is located between the fin 107 (and the associated source / drain region 201) and the isolation region 803. Figure 15A In the cross-sectional view taken along line BB of the X-section of FIG, the source / drain via contact 1107 passes through the second interlayer dielectric layer 1103 and the contact etch stop layer 1101 and is physically and electrically coupled to the source / drain region 201 in the fin 107 via the first contoured source / drain contact stack 1501A. The first contoured source / drain contact stack 1501A includes a first source / drain contact 503A having a raised metal portion and, if present, a first portion of the silicide contact 501. The first contoured source / drain contact stack 1501A separates the first and second portions of the first hard mask layer 303 and separates the gate stack 603, while the spacer 113 isolates the gate stack 603 from the first contoured source / drain contact stack 1501A.

[0164] exist Figure 15AIn the cross-sectional view taken along line CC of the X-section of FIG, a second contoured source / drain contact stack 1501B is located below the contact etch stop layer 1101 and the second interlayer dielectric layer 1103. The second contoured source / drain contact stack 1501B includes a second source / drain contact 503B having a raised metal portion and includes a second portion of the optional silicide contact 501 (if present). The second contoured source / drain contact stack 1501B separates the first and second portions of the first hard mask layer 303 from each other and separates the gate stack 603 from each other. Spacers 113 isolate the gate stack 603 from the second contoured source / drain contact stack 1501B.

[0165] Figure 15B In some embodiments Figure 14 The cross-sectional view of the Y section, and the cross-sectional view of the Figure 14 In the cross-sectional view of the Y-section, the source / drain via contacts 1107 pass through the second interlayer dielectric layer 1103 and the contact etch stop layer 1101, and are physically and electrically coupled to the source / drain regions 201 in the fin 107 via the contoured source / drain contact stack 1501. The contoured source / drain contact stack 1501 includes the source / drain contacts 503 having a raised metal portion and, if present, the silicide contacts 501. Figure 15B Also shown are source / drain via contacts 1107 physically contacting and electrically coupling to the raised metal portion of source / drain contacts 503, without the source / drain metal bump 1003 in between. Thus, source / drain via contacts 1107 alone can provide a surface area contact interface to the source / drain contact stack 1501 at the same level.

[0166] Figure 15B Also shown are the isolation regions 803 that isolate the contact etch stop layer 1101 from portions of the source / drain contacts 503, and the raised metal portions of the source / drain contacts 503 that have interfaces with the contact etch stop layer 1101 and the sidewalls of the isolation regions 803. In some embodiments, the raised metal portions of the source / drain contacts 503 of the contoured source / drain contact stack 1501 can have similar dimensions to the source / drain metal bumps 1003 of the aforementioned hybrid source / drain contact stack 1001. The remaining portions of the source / drain contacts 503 of the contoured source / drain contact stack 1501 can be substantially the same as those of the source / drain metal bumps 1003 of the aforementioned hybrid source / drain contact stack 1001. Figure 13BThe source / drain contacts 503 of the hybrid source / drain contact stack 1001 are shown as having the same or similar dimensions. However, other suitable dimensions may be used. Thus, the uniform height of the source / drain contact stack 1501 provides a full profile for the source / drain contacts 503 and increases yield, while the isolation region 803 increases the process tolerance between the source / drain contacts 503 and the gate via contact 1105.

[0167] In some embodiments, the material of the source / drain via contact 1107 can be the same as that of the source / drain contact 503 to provide a low-resistance interface between the source / drain via contact 1107 and the source / drain contact 503. Thus, the resistance / capacitance power loss between the source / drain via contact 1107 and the source / drain contact 503 made of the same material is smaller than the resistance / capacitance power loss between the source / drain via contact 1107 and the source / drain contact 503 made of different materials. As described above, the isolation region 803 can increase the process tolerance between the source / drain contact 503 and the gate via contact 1105. Therefore, the equal-height source / drain contact stack 1501 can increase performance and yield, the isolation region 803 can increase the process tolerance between the source / drain contact 503 and the gate via contact 1105, and the source / drain via contact 1107 and the source / drain contact 503 can have a low-resistance conductive interface.

[0168] Figure 16A and Figure 16B Some other embodiments of the semiconductor device 1600 are shown, which include a hybrid source / drain contact stack 1001 without the isolation region 803 shown in the above figures. Figure 16A and Figure 16B The X-section (such as tangent lines AA, BB, and CC) and Y-section cross-section views will be matched with Figure 12 The top view and Figure 13A and Figure 13B In contrast, Figure 16A and Figure 16B The X and Y sections are omitted. Figure 13A and Figure 13B Furthermore, the contact etch stop layer 1101 is conformal to the first hard mask layer 303 , the hybrid source / drain contact stack 1001 , and the surface of the source / drain contact 503 .

[0169] In some embodiments, the contact etch stop layer 1101 and the second interlayer dielectric layer 1103 are deposited on Figure 10 In the structure shown, the second hard mask material of the isolation region 803 is not deposited in the first recess 703 used to form the isolation region 803 (eg, Figure 7As shown), the contact etch stop layer 1101 can be conformal to the above surface, as shown Figure 10 and Figure 11 As shown. Figure 11 In contrast, the contact etching stop layer 1101 and the second interlayer dielectric layer 1103 are formed in the first recess 703 (see FIG. Figure 8 ) and conforms to the flat surface of the first hard mask layer 303, the sidewalls of the first hard mask layer 303, and the recessed surfaces of the first source / drain contact 503A and the second source / drain contact 503B in the first recess 703, rather than being formed on the flat surface of the isolation region 803. In this way, the contact etch stop layer 1101 and the compliant layer of the second interlayer dielectric layer 1103 can maintain an increased process tolerance between the first source / drain contact 503A and the gate via contact 1105 (e.g., with the use of a compliant contact etch stop layer 1101). Figure 11 The above contents of the description) do not require the existence of the isolation area 803.

[0170] exist Figure 16A In the cross-sectional view of the X-section of FIG, there is a gate via contact 1105, a gate stack 603, and a spacer 113 separating the first source / drain contact stack 1001A at cut line BB and the second source / drain contact stack 1001B at cut line CC. As shown in the figure of cut line AA, the first source / drain contact stack 1001A is located between the fin 107 and the contact etch stop layer 1101, and the second source / drain contact stack 1001B is located between the fin 107 and the contact etch stop layer 1101. Figure 16A In the cross-sectional view taken along line BB of the X-section of FIG, source / drain via contacts 1107 penetrate the second interlayer dielectric layer 1103 and the contact etch stop layer 1101 and are physically and electrically coupled to the source / drain region 201 of the fin 107 via the first source / drain contact stack 1001A. The first source / drain contact stack 1001A includes a first source / drain metal bump 1003A, a first source / drain contact 503A, and a first portion of an optionally formed silicide contact 501 (if present). The first source / drain contact stack 1001A separates portions of the first hard mask layer 303 and the gate stack 603. Spacers 113 isolate the gate stack 603 from the first source / drain contact stack 1001A.

[0171] exist Figure 16AIn the cross-sectional view taken along line CC of the X-section of FIG, a second source / drain contact stack 1001B is located below the contact etch stop layer 1101 and the second interlayer dielectric layer 1103. The second source / drain contact stack 1001B includes a second source / drain metal bump 1003B, a second source / drain contact 503B, and a second portion of the optional silicide contact 501 (if present). The second source / drain contact stack 1001B separates the first and second portions of the first hard mask layer 303 and the gate stack 603 from each other, while the spacer 113 separates the gate stack 603 from the second source / drain contact stack 1001B.

[0172] Figure 16B FIG1 is a cross-sectional view of a semiconductor device 1600 in some embodiments, which includes a hybrid source / drain contact stack 1001 without the isolation region 803 shown in the above figures. In the Y-section cross-sectional view, the source / drain via contact 1107 passes through the second interlayer dielectric layer 1103 and the contact etch stop layer 1101 and is physically and electrically coupled to the source / drain region 201 in the fin 107 via the hybrid source / drain contact stack 1001. The hybrid source / drain contact stack 1001 includes a source / drain metal bump 1003, a source / drain contact 503, and, if present, an optional silicide contact 501. Figure 16B The source / drain metal bumps 1003 can be connected to Figure 13B The source / drain metal bumps 1003 have the same or similar dimensions and can be made of the same material (e.g., tungsten) as the source / drain via contacts 1107 to provide a contact interface with less resistance / capacitance power loss. However, any suitable dimensions and materials can be used. Figure 16B The source / drain metal bumps 1003 shown can provide a low resistance conductive interface with a large surface area contact to the source / drain contacts 503, as described above. In addition, the compliant contact etch stop layer 1101 and the second interlayer dielectric layer 1103 can maintain an increased process margin between the source / drain contacts 503 and the gate via contact 1105, even without the isolation region 803. In this way, Figure 16B The mixed source / drain contact stack 1001 can increase process tolerance to improve performance and yield.

[0173] Embodiments described herein relate to a FinFET device having reduced interface resistance / capacitance between source / drain vias and source / drain contacts, and increased process tolerance between a gate via and source / drain contacts. In some embodiments, a metal bump formed on the source / drain contacts provides a larger surface contact area (compared to the interface surface area between the source / drain contact vias and the metal bumps). In some embodiments, the source / drain contact vias and the metal bumps are composed of the same material. Thus, the FinFET device can reduce resistance / capacitance power losses at the interface between the metal bumps and one or more source / drain contact vias and the source / drain contacts. In some embodiments, a recess formed in a portion of the source / drain contacts of the FinFET device can increase the process tolerance between the recess and the gate contact of the FinFET. In some embodiments, an isolation material is filled into the recess on the source / drain contacts. In some embodiments, a compliant contact etch stop layer of a FinFET is formed on the source / drain contacts and along the sidewalls of the recess, thereby providing an improved process margin between the gate via and the source / drain contacts of the FinFET device.

[0174] In one embodiment, a method for forming a semiconductor device includes: recessing a first portion of a source / drain contact to form a recess in a first dielectric layer of a fin field effect transistor device, wherein the source / drain contact is formed of a first metal material; depositing a second metal material in the recess to form a metal bump, the metal bump physically contacting the source / drain contact, the second metal material being different from the first metal material, and a first width of an interface between the metal bump and the source / drain contact being less than a width of the source / drain contact; depositing a second dielectric layer over the metal bump; etching an opening through the second dielectric layer to expose the metal bump from the second dielectric layer; and depositing a third metal material in the opening through the second dielectric layer, the third metal material physically contacting the metal bump to form a source / drain contact via, wherein a second width of an interface between the source / drain contact via and the metal bump is less than the first width. In one embodiment, the method further includes recessing a second portion of the source / drain contact of the fin field effect transistor device before depositing the second dielectric layer. In one embodiment, the method further comprises depositing an etch stop layer in the recess of the second portion of the source / drain contact to physically contact the source / drain contact. In one embodiment, the step of depositing the etch stop layer comprises forming an interface between the sidewalls of the etch stop layer and the sidewalls of the metal bump. In one embodiment, the method further comprises depositing a compliant contact etch stop layer over the metal bump and the source / drain contact to physically contact the metal bump and the source / drain contact. In one embodiment, the step of depositing the second metal material to form the metal bump comprises using a conductive fill material, and the step of depositing the third metal material to form the source / drain contact via comprises using a conductive fill material. In one embodiment, the conductive fill material comprises a tungsten fill material.

[0175] In another embodiment, a method for forming a semiconductor device includes: forming a first source / drain region and a second source / drain region in a fin of the semiconductor device; depositing a first dielectric layer on the fin; forming a gate stack after depositing the first dielectric layer; depositing a hard mask layer on the gate stack; forming a first source / drain contact to the first source / drain region and forming a second source / drain contact to the second source / drain region; recessing a portion of the first source / drain contact to form a first recess; filling the first recess with a first dielectric material, wherein the first dielectric material and the hard mask layer are in contact with each other; The method further comprises forming a gate contact via to the gate stack, wherein the first dielectric material is separated from the gate contact via by a first distance, and a surface of the first source / drain contact along the top of the recess is separated from the gate contact via by a second distance, the second distance being greater than the first distance, and the direction of the first distance being parallel to the direction of the second distance; and forming a source / drain contact via on a portion of a second source / drain contact on the fin and electrically coupling to a portion of the second source / drain contact on the fin, wherein the source / drain contact via and the second source / drain contact are formed of different materials. In one embodiment, the method further comprises planarizing the first dielectric material and the hard mask layer. In one embodiment, filling the first recess with the first dielectric material further comprises: conformally depositing a contact etch stop layer on the planar surface of the hard mask layer, the sidewalls of the first recess, and the exposed portion of the first source / drain contact, with an interface between the contact etch stop layer deposited on the sidewalls of the first recess and the hard mask layer opposite the sidewalls of the gate contact via; and depositing a second dielectric layer on the contact etch stop layer. In one embodiment, the method further comprises: etching a portion of the second source / drain contact to form a second recess before forming the source / drain contact via; and forming a metal bump on the second source / drain contact and physically contacting the second source / drain contact. In one embodiment, a first width of the interface between the metal bump and the second source / drain contact is less than a width of the source / drain contact. In one embodiment, a second width of the interface between the source / drain contact via and the metal bump is less than the first width. In one embodiment, the source / drain contact via comprises tungsten. In one embodiment, the second source / drain contact comprises cobalt.

[0176] In yet another embodiment, a semiconductor device includes: source / drain contacts located on and electrically coupled to source / drain regions of a fin of a semiconductor substrate, the source / drain contacts comprising a first metal; a metal bump located on and physically contacting the source / drain contacts, the metal bump comprising a second metal different from the first metal; and a source / drain via located on and physically contacting the metal bump, the source / drain via comprising the second metal, wherein an interface between the metal bump and the source / drain contact is larger than an interface between the source / drain via and the metal bump. In one embodiment, the semiconductor device further includes an etch stop layer located on the source / drain contact, wherein sidewalls of the etch stop layer have interfaces with sidewalls of the metal bump. In one embodiment, the second metal comprises tungsten. In one embodiment, the first metal comprises cobalt. In one embodiment, the semiconductor device further includes: an isolation region comprising a first dielectric material located on the source / drain contacts, wherein a sidewall of the isolation region has an interface with a sidewall of the metal protrusion; a gate stack located on the channel region of the fin; a gate via located on the gate stack and electrically coupled to the gate stack; and a hard mask layer comprising a second dielectric material and separating the gate via from the isolation region and separating the gate via from the metal protrusion, wherein the second dielectric material is different from the first dielectric material.

[0177] The features of the above-described embodiments will facilitate understanding of the embodiments of the present invention by those skilled in the art. Those skilled in the art will appreciate that the present invention may be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present invention and that changes, substitutions, or modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: Recessing a first portion of a first source / drain contact and a second portion of a second source / drain contact to form a first recess and a second recess, respectively, in a first dielectric layer of a fin field effect transistor device, wherein the first source / drain contact and the second source / drain contact are formed of a first metal material; forming a first dielectric material in the first recess on the first source / drain contact, the first dielectric material being different from the material of the first dielectric layer; Depositing a second metal material to form a metal bump in the second recess, the metal bump physically contacting the second source / drain contact, the second metal material being different from the first metal material, and a first width of an interface between the metal bump and the second source / drain contact being smaller than a width of the source / drain contact; depositing an etch stop layer on the metal protrusion, the etch stop layer physically contacting the metal protrusion and the first dielectric material; depositing a second dielectric layer on the etch stop layer; etching an opening through the second dielectric layer and the etch stop layer to expose the metal bump from the second dielectric layer; as well as A third metal material is deposited in the opening through the second dielectric layer. The third metal material physically contacts the metal bump to form a source / drain contact via. A second width of an interface between the source / drain contact via and the metal bump is smaller than the first width.

2. The method for forming a semiconductor device according to claim 1 , further comprising: Prior to depositing the second dielectric layer, a third portion of a third source / drain contact of the FinFET device is recessed. 3 . The method for forming a semiconductor device according to claim 2 , further comprising depositing the etch stop layer in a third recess of the third portion of the third source / drain contact to physically contact the third source / drain contact.

4. The method for forming a semiconductor device according to claim 1, wherein the step of depositing the second metal material to form the metal protrusion comprises using a conductive filling material, and the step of depositing the third metal material to form the source / drain contact via comprises using the conductive filling material. 5 . The method for forming a semiconductor device according to claim 4 , wherein the conductive filling material comprises a tungsten filling material.

6. A method for forming a semiconductor device, comprising: forming a first source / drain region and a second source / drain region in a fin of a semiconductor device; depositing a first dielectric layer on the fin; forming a gate stack after depositing the first dielectric layer; depositing a hard mask layer on the gate stack; forming a first source / drain contact to the first source / drain region, and forming a second source / drain contact to the second source / drain region; Recessing a portion of the first source / drain contact to form a first recess; Filling the first recess with a first dielectric material, wherein the first dielectric material has a different material composition from that of the hard mask layer; forming a metal bump on the second source / drain contact; depositing an etch stop layer on the metal protrusion, wherein the etch stop layer physically contacts the metal protrusion and the first dielectric material; forming a gate contact via to the gate stack, wherein the first dielectric material is separated from the gate contact via by a first distance, wherein a surface of the first source / drain contact along a top portion of the first recess is separated from the gate contact via by a second distance, the second distance being greater than the first distance, and a direction of the first distance being parallel to a direction of the second distance; and A source / drain contact via is formed on a portion of the second source / drain contact on the fin and electrically coupled to a portion of the second source / drain contact on the fin, wherein the source / drain contact via is made of a different material than the second source / drain contact. 7 . The method for forming a semiconductor device according to claim 6 , further comprising planarizing the first dielectric material and the hard mask layer.

8. The method for forming a semiconductor device according to claim 6 , wherein the step of filling the first recess with the first dielectric material further comprises: A second dielectric layer is deposited on the etch stop layer. 9 . The method for forming a semiconductor device according to claim 6 , wherein the metal bump physically contacts the second source / drain contact. 10 . The method for forming a semiconductor device according to claim 9 , wherein a first width of an interface between the metal bump and the second source / drain contact is smaller than a width of the source / drain contact. 11 . The method for forming a semiconductor device according to claim 10 , wherein a second width of an interface between the source / drain contact via and the metal bump is smaller than the first width.

12. The method for forming a semiconductor device according to claim 11, wherein the source / drain contact via comprises tungsten.

13. The method for forming a semiconductor device according to claim 12, wherein the second source / drain contact comprises cobalt.

14. A method for forming a semiconductor device, comprising: forming a source / drain contact in a hard mask layer, the source / drain contact being located on and electrically coupled to a source / drain region of a fin of a semiconductor substrate, and the source / drain contact comprising a first metal; forming an isolation region on the source / drain contact, wherein the isolation region is made of a material different from that of the hard mask layer; forming a metal bump on and in physical contact with the source / drain contact, the metal bump comprising a second metal different from the first metal; forming an etch stop layer on the source / drain contact, the etch stop layer physically contacting the metal bump and the isolation region; as well as A source / drain via is formed on and physically contacts the metal bump, the source / drain via comprising the second metal, wherein an interface between the metal bump and the source / drain contact is larger than an interface between the source / drain via and the metal bump.

15. The method for forming a semiconductor device according to claim 14, wherein the second metal comprises tungsten.

16. The method for forming a semiconductor device according to claim 15, wherein the first metal comprises cobalt.

17. The method for forming a semiconductor device according to claim 16, further comprising: wherein an interface is formed between the sidewall of the isolation region and the sidewall of the metal protrusion; forming a gate stack on a channel region of the fin; forming a gate through hole on the gate stack and electrically coupled to the gate stack; and The hard mask layer separates the gate through hole and the isolation region and separates the gate through hole and the metal protrusion.

18. Semiconductor device comprising: a source / drain contact located on a source / drain region of a fin of a semiconductor substrate and electrically coupled to the source / drain region, wherein the source / drain contact comprises a first metal; a metal bump located on the source / drain contact and in a hard mask layer and physically contacting the source / drain contact, the metal bump comprising a second metal different from the first metal; a source / drain via located on and physically contacting the metal bump, the source / drain via comprising the second metal, wherein an interface between the metal bump and the source / drain contact is larger than an interface between the source / drain via and the metal bump; an isolation region located on the source / drain contact, wherein the isolation region is made of a different material than the hard mask layer; and An etch stop layer physically contacts the metal bump and the isolation region. The semiconductor device of claim 18 , wherein the second metal comprises tungsten.

20. The semiconductor device of claim 19, wherein the first metal comprises cobalt.

21. The semiconductor device according to claim 20, further comprising: wherein an interface is formed between the sidewall of the isolation region and the sidewall of the metal protrusion; a gate stack located on a channel region of the fin; a gate through hole located on the gate stack and electrically coupled to the gate stack; and The hard mask layer separates the gate through hole and the isolation region and separates the gate through hole and the metal protrusion.

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