Pipelined architecture for bit-serial multiplier-accumulator (MAC)

Abstract

A unit for accumulating a plurality of N multiplications of M-bit values, comprising a receiving unit, a bit-wise multiplier and a bit-wise accumulator. The receiving unit receives a pipeline of multipliers A and B such that a new set of multipliers is received at each cycle. The bit-wise multiplier multiplies the bits of the current multiplier A with the bits of the current multiplier B bit-wise and sums and carries between the bit-wise multipliers. The bit-wise accumulator accumulates the output of the bit-wise multiplier, thereby accumulating the multipliers during the pipelining process.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application 62 / 850,033, filed May 20, 2019, which is incorporated herein by reference. Technical Field

[0003] This invention generally relates to multiply-accumulate units. Background Technology

[0004] Multiplier-accumulator (MAC) is known in the art and is a common operation used to handle the summation of large numbers of multiplications. This operation is common in dot product multiplication and matrix multiplication in image processing, as well as in convolution used in neural networks.

[0005] In mathematics, the multiplication-addition operation is:

[0006] ∑ i A i k i Formula 1

[0007] Where A i and k i It can be an 8-bit, 16-bit, or 32-bit word.

[0008] In the code, the MAC operation is:

[0009] q i =q i +(A i *k i ) Formula 2

[0010] Where q i Variable cumulative value A i k i .

[0011] Because MAC operations are so common, they are typically implemented in hardware as separate units within a Central Processing Unit (CPU) or Digital Signal Processor (DSP). A typical MAC has a multiplier, adder, and accumulator register implemented using combinational logic. The output of the multiplier is fed into the adder, and the output of the adder is fed into the accumulator register. The output of the accumulator register is fed back to one input of the adder, thus generating an accumulation operation between the previous result and the new multiplication result. At the end of each clock cycle, the output of the multiplier is added to the register.

[0012] The multiplier section of a MAC is typically implemented using combinational logic, while the adder section is typically implemented as an accumulator register that stores the result. Summary of the Invention

[0013] According to a preferred embodiment of the present application, there is provided a method for accumulating a plurality of N multiplied M-bit values. The method comprises pipelining multipliers A and B to a multiply-accumulator such that a new set of multipliers is received at each cycle; multiplying at each cycle a bit of the current multiplier A with a bit of the current multiplier B and summing and carrying between the bit multipliers; and accumulating at each cycle the output of the bit multiplication, thereby accumulating the multipliers during the pipelining process.

[0014] According to a preferred embodiment of the present application, there is also provided a method for accumulating a plurality of N multiplied M-bit values. The method comprises performing the following steps for each pair of multipliers A and B, each having M bits. In M rows of M multiplication units, each bit of the multiplier A is individually multiplied with each bit of the multiplier B, and the results from a previous row of multiplication units are individually summed. In M rows of summing units following the multiplication units of the M rows, the results from a previous row of summing units or multiplication units are individually summed. The rows sum the output to an accumulator formed as a column. In accumulator units of the accumulator, each bit of the results from the bit output of each row is individually accumulated, and a carry value is passed along the bits of the results from the LSB (Least Significant Bit) to the MSB (Most Significant Bit).

[0015] Furthermore, according to a preferred embodiment of the present application, the multiplication units, the summing units and the accumulator units are bit-line processors.

[0016] Furthermore, according to a preferred embodiment of the present application, the method further comprises providing a new pair of multipliers A and B to an upper row of multiplication units at each cycle of operation.

[0017] Still further, according to a preferred embodiment of the present application, the individually summing comprises at least generating a sum value and a carry value of at least one of the multiplication units and the summing units, and passing the carry value down one row and the sum value right and down one row at each cycle.

[0018] Additionally, according to a preferred embodiment of the present application, the method comprises passing the bits of the multiplier A down one row at each cycle, and passing the bits of the multiplier B right and down one row at each cycle.

[0019] Furthermore, according to a preferred embodiment of the present application, M is a power of two.

[0020] Still further, according to a preferred embodiment of the present application, the method comprises storing a bit of the results individually at each cycle after the provision of the stop, the storing starting at the LSB and moving towards the MSB.

[0021] Furthermore, according to a preferred embodiment of the present application, when N is one, the output of the accumulator is a multiplication of the multipliers A and B.

[0022] According to a preferred embodiment of the present application, there is also provided a unit for accumulating a plurality of N multiplications of M-bit values. The unit comprises a receiving unit, a bit-wise multiplier and a bit-wise accumulator. The receiving unit receives a pipeline of multipliers A and B such that a new set of multipliers is received at each cycle. The bit-wise multiplier multiplies a bit of a current multiplier A with a bit of a current multiplier B bit-wise and sums and carries between the bit-wise multipliers. The bit-wise accumulator accumulates the output of the bit-wise multiplier, thereby accumulating the multipliers during the pipelining process.

[0023] Furthermore, according to a preferred embodiment of the present application, the bit-wise multiplier comprises M rows each having M multiplication units, and M rows of summation units following the multiplication units of the M rows, wherein each row comprises M summation units. Each multiplication unit individually multiplies each bit of the multiplier A with each bit of the multiplier B and individually sums the results from the previous row of multiplication units. Each summation unit individually sums the results from the summation units or the previous row of multiplication units, wherein the rows sum the output towards the bit-wise accumulator.

[0024] Furthermore, according to a preferred embodiment of the present application, the bit-wise accumulator comprises accumulator units formed as columns of accumulators. Each accumulator unit individually accumulates the bits of the results of the bit output from its associated row and passes a carry value along the bits of the results from the LSB (Least Significant Bit) to the MSB (Most Significant Bit) of the results.

[0025] Still further, according to a preferred embodiment of the present application, the multiplication units, the summation units and the accumulator units are bit-line processors.

[0026] Furthermore, according to a preferred embodiment of the present application, the upper row of multiplication units receives a new pair of multipliers A and B at each cycle of operation.

[0027] Furthermore, according to a preferred embodiment of the present application, the summation units communicate with the summation units in the lower row to pass a carry value down one row and a sum value right and down one row at each cycle.

[0028] Still further, according to a preferred embodiment of the present application, the multiplication units communicate with the multiplication units in the lower row to pass a bit of the multiplier A down one row at each cycle.

[0029] Furthermore, according to a preferred embodiment of the present application, the unit further comprises a bit passing unit for passing each bit of the multiplier B to its associated row in the multiplication units.

[0030] Furthermore, according to a preferred embodiment of the present application, when N is 1, the output of the bit-wise accumulator is the multiplication of the multipliers A and B. BRIEF DESCRIPTION OF DRAWINGS

[0031] The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, can best be understood by reference to the following detailed description when read with the accompanying drawings in which:

[0032] Figure 1 is a schematic illustration of a pipelined multiplier-accumulator constructed and operable in accordance with a preferred embodiment of the present invention;

[0033] Figure 2A , Figure 2B and Figure 2C are schematic illustrations of a multiplication processor, a summation processor, and an accumulation processor, respectively, useful in the multiplier-accumulator of Figure 1

[0034] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H and Figure 3I are schematic illustrations showing how data moves through the bit- wise multiplier-accumulator 100 over nine cycles, which help to understand the pipelined multiplier-accumulator of Figure 1 ; and

[0035] Figure 4 is a schematic illustration of three adjacent multiplication bit-line processors 110M.

[0036] It is to be understood that the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some of the elements can be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements. DETAILED DESCRIPTION

[0037] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention can be practiced without these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to obscure the present invention.

[0038] Applicants have realized that the result can be accumulated during the multiplication operation. This is significantly faster and more efficient than accumulating only once a pair of values has been multiplied. Furthermore, since the multiplier and accumulator are part of a single unit, rather than two separate units, it reduces chip real estate.​

[0039] The Applicant has further realized that when the multiplier and accumulator are part of a single unit, the unit should individually accumulate each bit when processing the carry value. Moreover, once each bit is individually processed, the operation can be pipelined. The Applicant has realized that when only one multiplication operation is provided to the pipelined multiplier-accumulator unit, the pipelined multiplier-accumulator unit can also perform only multiplication. Then the accumulation is a single result.

[0040] Reference is now made to Figure 1 , Figure 1 A bit-wise multiplier-accumulator 100 constructed and operable in accordance with a preferred embodiment of the present application is shown. The bit-wise multiplier-accumulator 100 can be implemented in an in-memory associated processor, for example, those discussed in U.S. Patents 8,238,173, 9,418,719 and 9,558,812, currently owned by the Applicant of the present application and incorporated herein by reference. The in-memory processor processes data in a memory array having a plurality of memory cells in a matrix form of rows and columns, and these columns are organized into the processor. When multiple rows are activated together, a Boolean calculation operation takes place in the processor, with the result being read in the column decoders of the processor.

[0041] The bit-wise multiplier-accumulator 100 includes separate input units 102A and 102B for each of the multiplicands A and B, a bit-wise multiplier unit 104 and a bit-wise accumulator unit 106, where each of the units 102, 104 and 106 can be made of a plurality of processors 110 that can operate on one bit or on a pair of bits (one bit from each of the multiplicands A and B) during each operation cycle. The processors 110 can be any suitable processor and can be implemented as bit-line processors 110 as described in the examples herein, described in more detail hereinafter.

[0042] In the bit-wise multiplier-accumulator 100, the processors 110 can be formed in rows and columns, where the input unit 102A can be formed of a single row of processors 110 above the multiplier 104, the accumulator 106 can be located to the right of the bit-wise multiplier 104, and the input unit 102B can be located to the left of the upper part of the bit-wise multiplier 104.

[0043] The bit-wise multiplier-accumulator 100 can operate on multiplicands A and B that can have 4, 8, 16, 32, 64 or more bits, as required. In the example of Figure 1 The bit-wise multiplier-accumulator operates on 4-bit multiplicands A and B only.

[0044] The input unit 102A may include a row of M receiver processors 110A, where M is the number of bits in the multiplicand A, and where... Figure 1 In this case, M is 4. In each operation cycle, each processor 110A can receive one bit of the current multiplicand A, where the least significant bit A0 of the multiplicand A can be located at the rightmost end of the row, and the most significant bit A3 can be located at the leftmost end of the row. In the next operation cycle, processor 110A can pass the value stored therein from the previous cycle to the first row of processor 110M of multiplier 104, and can receive bits from the next multiplicand A. Therefore, for input unit 102A, all bits can be shifted down (i.e., vertically) one row in each cycle. As can be seen, for M cycles, the bits of the multiplicand A are passed down to the next row. Therefore, Figure 1 The first four rows of the multiplier 104 in the diagram show bits A3–A0 from left to right.

[0045] Input unit 102A can provide the bits of multiplicand A to the next row in each cycle; however, according to a preferred embodiment of the invention, as described in more detail below, most of the processors 110 in the multiplier-accumulator 100 can pass their data down and to the right (towards accumulator 106) in each cycle.

[0046] Input unit 102B may include three types of processors 110: 1) a line receive processor 110A, which is typically aligned in the same line as processor 110A of input unit 102A; 2) a data transfer processor 110B, which can transfer the value stored therein from the previous cycle down and right in each cycle (as shown by slanted arrow 111); and 3) a signaling processor 110C, which can provide the value stored therein to the signaling line 112 that provides input to the line processor 110 in multiplier 104.

[0047] It should be understood that the signaling processor 110C can provide the associated bits of the multiplicand B to each of the first M rows of the bitwise multiplier 104. Furthermore, the data transfer processor 110B can be configured in a triangular shape to provide different bit values ​​to each of the first M rows of the multiplier 104. Therefore, the input unit 102B can provide the least significant bit B0 of the multiplicand B to the first row of the multiplier 104, the next significant bit of the multiplicand B to the second row of the multiplier 104, and so on. Figure 1 Four rows are shown, each receiving different bits of the multiplicand B along its signaling line 112. Figure 1 It also shows four columns, each receiving different bits of the multiplicand A, with the least significant bit on the right, the next significant bit on the left, and so on.

[0048] The bit-wise multiplier unit 104 can include MxM matrices of multiplication processors 110M and M rows of summation processors 110S. Each multiplication processor 110M in the first row of the multiplier 104 can receive a one-bit multiplicand A and a one-bit multiplier B as input, can multiply them together, and can generate their two-bit result (recall that in binary, 1+1=10). The two bits are referred to as the "sum" bit and the "carry" bit, where the sum is the right-most bit of the result and the carry is the left-most bit of the result (e.g., for 1+1=10, the sum bit is 0 and the carry bit is 1).

[0049] The remaining multiplication processors 110M can receive the sum bit (from the processor above and to the left of it), the carry bit, and a bit from the multiplicand A (from the processor above it), as well as a bit from the multiplier B from its signaling line 112. These processors 110M can perform a multiplication operation between their multiplicand bits (to which they can add the sum and carry values), generating a new sum bit and carry bit as output. In Figure 1 In the middle, the multiplication processors 110M are labeled by the multiplicand bits they are multiplying.

[0050] For example, multiplication processor 110M-E can receive the value of bit Al from the multiplication processor performing multiplication of Al*Bl directly above it, and can receive the value of bit B2 from its associated signaling line 112. Multiplication processor 110M-E can perform multiplication of Al*B2, and can add to it the sum S21 from the multiplication of A2*Bl in the row above and to the left, as well as the carry Cll from the multiplication of Al*Bl directly above it. Multiplication processor 110M-E can provide its summation result S12 to the multiplication processor to perform operation A0*B3 (e.g., the sum bit S12 is shifted down and to the right) and its carry result C12 and the value of Al to the multiplication processor to perform operation Al*B3 (e.g., the carry bit C12 and the A bit are shifted down).

[0051] As can be seen in Figure 1 As can be seen in

[0052] It should be understood that the MSB (most significant bit) bit (A0) is shifted down and to the right (i.e., to the multiplication processor in the next row and to the right of it) and the carry bit (B0) is shifted down (i.e., to the multiplication processor in the next row and in the same column as it). Figure 1The multiplication processor 110M of the A3 operation in the example receives only the multiplicand (A3) and the multiplier (B3) as inputs. Figure 1 The multiplication processor 110M of the A3 and Bj operations in the example receives only the sum bits and the carry-in bits as inputs, and as a result generates only the sum bits. The rest of the unit 110M can receive the sum bits and the carry-in bits. It will further be understood that the LSB (least significant bit) bits (A3 and B3) of the sum bits are the result of the A3*B3 operation. Figure 1 The multiplication processor 110M of the A0 operation in the example can pass its sum bits to the bit-wise accumulator unit 106.

[0053] Each summation processor 110S in the second part of the multiplier 104 can be an addition processor 110SA that performs only an addition operation on its inputs, or a data pass processor 110SB that can pass down and to the right the carry-in value stored in it from the previous cycle. Neither type of summation processor 110S receives any multiplicand bits as input.

[0054] Each summation processor 110SA can add together the sum bits (from the processor above and to the left of it) and the carry-in bits (from the processor above it), and can provide the sum bits of the result to the processor below and to the right of it, and the carry-in bits to the processor below it. There are fewer summation processors 110S in each row because there is no new input multiplicand. Figure 2A It is shown that there are 3 summation processors in the first two rows, 2 summation processors in the third row, and 1 summation processor in the fourth and last row. Similar arrangements can be made for multiplicands with more bits.

[0055] For example, the summation processor 110S-E can receive the sum bits S33 from the multiplication processor that performed the multiplication of A3*B3 in the row above and to the left, and can receive the carry-in bits C23 from the multiplication processor that performed the multiplication of A2*B3 directly above it. The summation processor 110S-E can add the sum bits S33 and the carry-in bits C23, and can provide its summation result S24 down and to the right to the summation processor, and its carry-in bits C24 to the summation processor directly below it.

[0056] It should be understood that each multiplication processor 110M performs a bit-wise multiplication. Rather than multiplying two multi-bit input numbers A and B together and then adding them together, each multiplication processor 110M not only multiplies its associated multiplicand bits together, but also adds summation information and carry-in information received from adjacent multiplication processors to its result. The multiplication processor then provides its summation information and carry-in information to its adjacent multiplication processors. Thus, the multiplier 104 is a “bit-wise” multiplier.

[0057] It will be further appreciated that each row of the multiplier 104 can sum the outputs of that row towards the bit-wise accumulator 106.

[0058] The bit-wise accumulator unit 106 can include a row of accumulation processors 110U and a tail processor 110T, generating its respective result bit Pk. The applicants have realized that each bit of the accumulated result is accumulated from LSB to MSB, and the LSB is always the accumulated value of the LSB bit multiplication. Therefore, the LSB sum bit can be provided to the first accumulation processor 110U in the bit-wise accumulator unit 106 from the multiplication processor 110M that multiplies A0*B0. Note that the first accumulation processor 110U starts in the second row of processors 110.

[0059] Furthermore, the applicants have realized that each accumulation processor 110U can receive a sum bit from its adjacent multiplication processor 110M or sum processor 110S to add to its previously accumulated value, due to the sum and carry operations performed in the bit-wise multiplier 104.

[0060] Therefore, each processor 110U and 110T of the accumulator unit 106 can generate a sum bit and a carry bit, can return its sum bit to itself (as indicated by the return arrow 114, and as input for the next cycle), and can provide its carry bit to the next processor in the row (as indicated by the arrow 115). As mentioned above, the accumulation processors 110U can also receive sum bits from adjacent multiplication processors 110M and sum processors 110S. However, the tail processor 110T can only operate on its fed-back sum bit and on the carry bit from its predecessor processor 110S or 110T in the row.

[0061] Note that there can be M rows of multiplication processors 110M and M rows of sum processors 110S, such that there can be 2M accumulation processors 110U. There can be Q tail processors 110T, where Q is at least log2(N) and N is the number of values to be multiplied and accumulated.

[0062] It should be appreciated that the operations in the multiplier-accumulator 100 can be performed in parallel, where each column can operate simultaneously with the other columns. Therefore, increasing the precision from 4 bits to 8 bits does not significantly affect the timing of the multiplier-accumulator 100, although it does increase its size.

[0063] Furthermore, it should be appreciated that the multiplier-accumulator 100 can only operate for integer operations, as it does not handle exponents.

[0064] Reference is now briefly made to Figure 2B , Figure 2C and Figure 2BThese figures show the processor 110M, 110S, and 110U, respectively. The multiplication processor 110M includes an exclusive OR operator 120 and a full adder 122M.

[0065] The exclusive OR operator 120 can receive the multiplicand bits Ai and Bj and can produce their product Ai*Bj. The exclusive OR operator 120 can be any suitable exclusive OR operator. For example, the exclusive OR operator 120 can be implemented on a bit line and can provide its output to one of the inputs of the full adder 122 labeled In.

[0066] The full adder 122M can add an input sum bit S in and an input carry bit C in to a current input value (i.e., the exclusive OR output). The full adder 122M can generate a new sum bit S out and a carry bit C out , respectively, and can pass through the value of Ai received.

[0067] The full adder 122M can be any suitable full adder. For example, the full adder 122M can be similar to the full adder described in U.S. Patent Application 15 / 708,181, published as US 2018 / 0157621, assigned to the assignee of the present application, and incorporated by reference herein. US 2018 / 0157621 discusses how to implement multiple parallel full adders 122 within a memory array such that all the addition operations occur in parallel. The addition of the exclusive OR 120 adds a minimum number of operations and can also be performed in parallel. Thus, each row of bit line processors 110 can operate in parallel with each other, multiplying Ai by Bj, and then adding the result to the sum bit and carry bit provided to them.

[0068] As shown in Figure 2C , the summation processor 110SA can be similar to the multiplication bit line processor 110M, but without the exclusive OR operator 120. Instead, the summation processor 110SA includes only the full adder 122S and can add an input sum bit S in and an input carry bit C in received from a previous calculation. The full adder 122S can generate a new sum bit S out and a carry bit C out , respectively.

[0069] As shown in Figure 3A , the accumulation processor 110U can be similar to the summation bit line processor 110SA, but with a feedback loop of S out . The full adder 122U can add an input sum bit S in and an input carry bit Cin Add to the output sum bit S from previous calculation out The full adder 122U can generate a new sum bit S out and a carry bit C out , respectively.

[0070] The remaining discussion will present an exemplary embodiment with the processor 110 as a bit line processor; however, it should be understood that the present application can also be implemented with a non-bit line processor.

[0071] The applicants have realized that the structure of the bit-wise multiplier-accumulator 100 can implement pipelined operations, which are very efficient operations. Once the first row of operations is complete (i.e., Ai is multiplied by B0 in the first cycle), Ai is moved down one row and Bj is moved down and to the right, which brings B1 - B3 to the second row.

[0072] A new set of Ai and Bj is introduced in the next cycle and provided to the first row, so the second row can operate on data from the first cycle while the first row can operate on data from the second cycle. In each cycle, the old data is moved down one row and the new data is moved to the now vacated previous row.

[0073] In the second cycle, the LSB bit is provided to the first accumulation bit line processor 110U to start accumulating the result bit P0. As mentioned above, each accumulation bit line processor 110U can output its carry bit, but its sum is returned to it to be added to the value generated in the next cycle. This is the accumulation operation - sum in place and carry to the next higher significant bit.

[0074] Reference is now made to Figure 3A - 3I, which shows how the data moves through the bit-wise multiplier-accumulator 100 in 9 cycles for a simple addition of 3 multiplications, where each multiplicand is 4 bits. Since all values have multiple versions, Figure 3A - 3F labels each value according to the cycle to which it belongs. Thus, A01 comes from the first cycle, A02 comes from the second cycle, and so on.

[0075] In the preparation cycle shown in Figure 3B , the first set of multiplicand bits Ai1 and Bi1 are received into the receiving bit line processors 110A and 110B of the input units 102A and 102B, respectively. In the first cycle after the preparation cycle, B01 can be passed to its signaling bit line processor 110C, which in turn can provide the value of B01 to its signaling line 112 for the first row of multiplication bit line processors 110M.

[0076] The first row of the multiplication bitline processor 110M can multiply its Ai1 by B01 (e.g., Ai1*B01), and can pass its carry (labeled Ci0) and its Ai down to the next row, as well as its sum (labeled Si0) down and to the right in the next row. It should be understood that only the sum S001 from the rightmost multiplication bitline processor 110M can be passed to its associated accumulation bitline processor 110U (labeled P0 here) to begin calculation for P0 in the next cycle.

[0077] exist Figure 3C In the second cycle shown, B01 can be received in the signaling bitline processor 110C of the second row, and the signaling bitline processor 110C can then provide its value to the signaling line 112 of the second row. Simultaneously, the second set of multipliers Ai2 and Bj2 received by the receiving bitline processor 110A from the input units 102A and 102B respectively can be passed to the first row of the bitline processor of the multiplier-accumulator 100. Therefore, B02 can be passed to its signaling bitline processor 110C to provide its value to the first row of the multiplication bitline processor 110M. Thus, the first row of the multiplication bitline processor 110M can multiply Ai2 by B02, while the second row of the multiplication bitline processor 110M can multiply Ai1 by B01 (Ai1*B11), and the result can be added to the sum passed from the previous row along with the carry. For example, A11*B11 can be added to S201 and C101 to generate S111 and C111. At the end of the second cycle, as discussed above, the sum of Ai from the two rows of the multiplication bit line processor 110M, the carry sum, and the value can be passed down one row.

[0078] In the second cycle, accumulation begins when the accumulation bitline processor P0 receives the value passed to it from cycle 1 (i.e., P01 = S001). Accumulation bitline processor P0 can feed the value of P01 back to itself and can pass its carry output CP01 to the next accumulation bitline processor 110U, denoted here as P1, which can calculate P1. Furthermore, at the end of this cycle, the rightmost multiplication bitline processors 110M of the first and second rows can pass the sum bits S002 and S011 to accumulation bitline processors P0 and P1, respectively.

[0079] Figure 3D The operation in the third cycle is shown. The multiplication operation is very similar to that in the second cycle. In this cycle, the third row of the bitwise multiplier 104 can operate on data from the first cycle, the second row can operate on data from the second cycle, and the first row can operate on data from the third cycle.

[0080] In this cycle, the accumulate bit line processor P0 adds the value of S002 passed to it from the second cycle to the previous value P01 to generate an accumulated bit P02. The accumulate bit line processor P0 can feed back the value of P02 and can pass its carry bit CP02 to the accumulate bit line processor P1. Meanwhile, the accumulate bit line processor P1 can add the sum bit S011 passed to it from the rightmost multiplication bit line processor 110M of the second row (which processes data of the first cycle) to the carry bit CP01 received from the accumulate bit line processor P0 in the previous cycle.

[0081] It will be appreciated that each accumulate bit line processor (e.g., P0 and P1) first receives data from cycle 1, then from cycle 2, and so on. Thus, in cycle 3, P1 in the third row processes cycle 1 data, while P0 in the second row accumulates cycle 2 data on top of the cycle 1 data it received in the previous cycle.

[0082] Figure 3D A fourth cycle is shown. Since this example illustrates the accumulation of only three multiplications, there are no more inputs in this fourth cycle. Typically, the bit- wise multiplication-accumulator 100 can accumulate thousands of values, but at some point in time, the accumulation ends.

[0083] In Figure 3A , the accumulate bit line processor P0 accumulates the LSB data of the third cycle and finishes. The value stored therein is the LSB of the three multiplied values (i.e., P03), and thus, the accumulate bit line processor P0 can move the value stored therein to an external register (not shown).

[0084] Although not shown in Figure 3E -3I for ease of understanding, the bit-wise multiplication-accumulator 100 can start on the next MAC operation in the next cycle and can bring a new set of multiplicands A and B to be operated on by the now-empty first row of multiplication bit line processors 110M.

[0085] The accumulate bit line processors P1 and P2 can operate as discussed above, adding the received LSB sum bits to the values previously stored therein, where the accumulate bit line processor P1 can operate on data from cycle 2 (sum from the rightmost multiplication bit line processor and carry from the accumulate bit line processor P0), and the accumulate bit line processor P2 can operate on data from cycle 1.

[0086] In the fifth cycle shown in Figure 3E , the first row (not shown in the figure) and the second row Figure 3FThe top of the array (shown) is empty, and the accumulator bitline processor P0 no longer accumulates. The data from the first cycle is now in the first row of the summator bitline processor 110S. As mentioned above, since the multiplication bitline processor 110M, which operates on the MSB (most significant bit), only generates a sum bit, there are only three summator bitline processors 110SA in the first row of the second part of the multiplier 104. The summator bitline processors 110SA in this row simply add the sum and carry received from the previous row and provide their result sum and carry to the next row. The LSB bit SO41 of this row is provided to the accumulator bitline processor P4. The accumulator bitline processors P2 and P3 can operate as discussed above, and the accumulator bitline processor P1 accumulates the LSB data of the third cycle and completes the operation.

[0087] exist Figure 3F In the sixth cycle shown, the first three rows of multiplier 104 are empty (therefore, Figure 3G (The first two rows are not shown in the image), and the accumulating bitline processors P0 and P1 no longer accumulate. The data from the first cycle is now in the second row of the summing bitline processor 110S. In this second row, there are three bitline processors 110S, of which the leftmost processor is the data transfer processor 110SB, and the remaining processors are the summing bitline processors 110SA.

[0088] The data transfer processor 110SB can receive carry C24, which can be generated from the sum S33 of the multiplication from A3*B3 and the carry C23 from its neighbor. C24 will continue to be transferred until it is transferred to P7—the MSB of any of the individual multiplications.

[0089] The two summation bitline processors 110SA in this row add the sums and carry received from the three summation bitline processors 110SA in the previous row, and provide their result sum and carry to the next row. The LSB bit SO51 of this row is provided to the accumulation bitline processor P5. Accumulation bitline processors P3 and P4 can operate as discussed above, and accumulation bitline processor P2 accumulates the data of the third cycle and completes the operation.

[0090] exist Figure 3H In the seventh cycle shown, the multiplier has completed its operation. The data from the first cycle is now in the third row of the summing bitline processor 110S, which has two bitline processors 110S, both of which are data transfer processors 110SB.

[0091] The data transfer processor 110SB can receive the carry C24 and the sum S15 (generated in the previous row) for data in cycle 1. The carry C24 can be passed to the next row, while the sum S15 can be passed to P6.

[0092] The accumulate bit line processors P4 and P5 can operate as discussed above, and the accumulate bit line processor P3 accumulates the data of the third cycle and completes.

[0093] The multiplication processing is completed in the eighth cycle shown in Figure 3I The eighth row of the multiplier 104 includes a single data pass processor 110SB that receives the data of the carry C24 and passes it to the accumulate bit line processor P7. The accumulate bit line processors P5 and P6 can operate as discussed above, and the accumulate bit line processor P4 accumulates the data of the third cycle and completes.

[0094] In the next three cycles (the first of which is shown in Figure 1 ), the accumulate bit line processors P5, P6, and P7 accumulate the data of the third cycle, the second and third cycles, and the first through third cycles, respectively, to complete their calculations.

[0095] If there are more than three multiplications to be accumulated, the outputs of the accumulate bit line processors 110U (i.e., processors P0 - P7) can be passed to the tail processor 110T Figure 4 ) to continue the accumulation.

[0096] It should be appreciated that the bit-wise multiplier-accumulator 100 has a very efficient structure for a MAC unit. It can be particularly efficient when implemented with bit line processors, since the various bit line processors 110 have a very similar structure, and all of these bit line processors 110 can be implemented in a memory array, as discussed in more detail below. Moreover, the bit-wise multiplier-accumulator 100 performs part of the accumulation operation during the multiplication operation by operating on each bit, rather than on the full bit values of the multiplicands A and B.

[0097] Furthermore, as mentioned above, when the multiplication operation has been completed, part of the accumulation operation has already been completed, so that the multiplier-accumulator 100 can start the next multiplication-accumulation operation at the same time as it completes the previous multiplication-accumulation operation.

[0098] Moreover, as mentioned above, when only one pair of multiplicands is provided to the bit-wise multiplier-accumulator 100, the bit-wise multiplier-accumulator 100 can also be used as a multiplier.

[0099] Reference is now made to Figure 4 , Figure 4Three adjacent multiplication bit line processors 110M are shown, with multiplication bit line processor 110M-i-j in the jth row and ith column of the multiplier-accumulator 100 and operating on the ith bit of multiplicand A and the jth bit of multiplicand B, multiplication bit line processor 110M-i-(j+1) is also in the ith column but in the (j+1)th row, and multiplication bit line processor 110M-(i-1)-(j+1) is in the (i-1)th column and in the (j+1)th row.

[0100] Each bit line processor 110M can be formed from at least seven memory cells 202 in a single column, all of which are attached to a single bit line 200. The bit line 200 and memory cells 202 can form part of a memory array in which the multiplier-accumulator 100 is implemented. As shown in Figure 4 Each cell holds a different value, with, in the embodiment of Figure 4 the first cell storing a multiplicand bit Ai, the second cell storing a multiplicand bit Bj, the third cell storing a carry bit Ci(j-1)i from the previous row, and the fourth cell storing a sum bit S(i+1)(j-1) from the previous row and the next column. These are inputs to the bit line processor 110M, most of which are received from the previous cycle, but the multiplicand bit Bj can be received in the current cycle before the operations described below take place.

[0101] Other cells in the bit line processor 110M can store intermediate and final results of the operations on the four inputs.

[0102] The operations of the multiplication bit line processor 110M can take place in four main steps. In the first step, the multiplication bit line processor 110M-i-j can perform an exclusive OR operation on the cells storing Ai and Bj, and can store the result in an Ai XOR Bj cell, which is shown as the fifth cell in Figure 4 The exclusive OR operation is discussed in U.S. Patent 8,238,173 and can involve activating both rows storing Ai and Bj at the same time, so that the Boolean function result is received in the bit line 202.

[0103] In the second step, the multiplication bit line processor 110M-i-j can implement a full adder 122M as discussed above to add together Ci-(j-1), S(i+1)(j-1), and (Ai XOR Bj) to generate a carry bit Ci-j and a sum bit Si-j.

[0104] In a third step, the multiplication bit line processor 110M-i-j can read and write the bits Ai and C-i-j to the multiplication bit line processor 110M-i-(j+1); and in a fourth step, the multiplication bit line processor 110M-i-j can read and write the Si-j to the multiplication bit line processor 110M-(i-1)-(j+1). Alternatively, the full adder 122M can write the carry bit Ci-j and the sum bit Si-j directly.

[0105] It should be appreciated that the bit-wise multiplier-accumulator 100 can activate each bit line processor 110 together, such that each cycle is a fully parallel operation. As can be seen in the bottom row of Figure 4 ​ As can be seen in the bottom row of ​ , adjacent bit line processors 110M store the same type of bit value in the same row. Thus, in ​ , the rows storing all Ai and Bj can be activated simultaneously, and the XOR result can be written to the (Ai XOR Bj) cells of all bit line processors 110 simultaneously. The same is true for the full adder operation.

[0106] The parallel copying from one bit line processor to the next can be achieved via the multiplexers described in the aforementioned U.S. Patent 9,418,719.

[0107] Thus, all of the operations of one cycle can be performed together, further improving the pipelining efficiency of the bit-wise multiplier-accumulator 100.

[0108] While certain features of the application have been illustrated and described, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the application.

Claims

1. A method for accumulating multiple M-bit values ​​multiplied by N, the method comprising: For each pair of multiplicands A and B, each having M bits: In each of the M rows, which each has M multiplication units, each bit of the multiplicand A is multiplied by each bit of the multiplicand B individually, and the results from the previous row of the multiplication unit are summed individually. In the summation units of the M rows following the multiplication units of the M rows, the results from the previous row of the summation unit or the multiplication unit are summed individually, and the rows sum to the output of the accumulators formed as columns; In the accumulator unit of the accumulator, each bit of the result from the bit output of each row is accumulated individually, and the carry value is passed along the bits of the result from the least significant bit (LSB) to the most significant bit (MSB).

2. The method according to claim 1, wherein the multiplication unit, the summing unit, and the accumulator unit are bitline processors.

3. The method of claim 1, further comprising: In each operation cycle, a new pair of multiplicands A and B are provided to the row above the multiplication unit.

4. The method of claim 3, wherein the individual summation comprises at least: Generate a sum and carry value for at least one of the multiplication unit and the summation unit, and in each cycle, pass the carry value down one row and pass the sum value to the right and down one row.

5. The method of claim 4, further comprising: In each cycle, the bits of the multiplicand A are passed down one row, and in each cycle, the bits of the multiplicand B are passed right and down one row.

6. The method of claim 1, wherein M is a power of 2.

7. The method of claim 3, further comprising: After the provision stops, one bit of the result is stored separately for each cycle, the storage starting at the LSB and moving toward the MSB.

8. The method of claim 1, wherein N is 1, and the output of the accumulator is the multiplication of multiplicands A and B.

9. A method for accumulating multiple M-bit values ​​multiplied by N, the method comprising: The multiplicands A and B are pipelined into a multiplier-accumulator so that a new set of multiplicands is received in each cycle; In each cycle, the bits of the current multiplicand A are multiplied bitwise by the bits of the current multiplicand B, and the summation and carry are performed between the bit multipliers; as well as In each cycle, the output of the bitwise multiplication is accumulated bitwise, and the multiplicand is accumulated during the pipeline process.

10. The method of claim 9, wherein the bitwise multiplication, the summation, and the bitwise accumulation are implemented in a bitline processor.

11. The method of claim 9, further comprising: In each cycle, the bits of the multiplicand A are passed down one row, and in each cycle, the bits of the multiplicand B are passed right and down one row.

12. The method of claim 9, wherein M is a power of 2.

13. The method of claim 9, further comprising: After the pipeline stops, one bit of the result of the bitwise accumulation is stored separately for each cycle, starting at the least significant bit (LSB) of the result and moving toward the most significant bit (MSB) of the result.

14. The method of claim 9, wherein N is 1, and the output of the accumulator is the multiplication of multiplicands A and B.

15. A unit for accumulating multiple M-bit values ​​multiplied by N, the unit comprising: A receiving unit, which is a pipeline for receiving multiplicands A and B, such that a new set of multiplicands is received in each cycle; A bitwise multiplier is used to multiply the bits of the current multiplicand A by the bits of the current multiplicand B, and to sum and carry between bitwise multipliers; and A bitwise accumulator is used to accumulate the output of the bitwise multiplier, thereby accumulating the multiplicand during the pipelined process.

16. The unit of claim 15, wherein the bitwise multiplier comprises: M rows, each with M multiplication units, each multiplication unit is used to individually multiply each bit of the multiplicand A by each bit of the multiplicand B, and to individually sum the results from the previous row of the multiplication unit; as well as The M rows following the multiplication units, each row comprising M summation units, each summation unit being used to sum the result from the previous row of the summation unit or the multiplication unit individually, the rows summing the output towards the bitwise accumulator.

17. The unit of claim 16, wherein the bitwise accumulator comprises: The accumulator units of the accumulator are arranged in columns, each accumulator unit is used to individually accumulate the bits of the result from the bit output of its associated row, and to pass the carry value along the bits of the result from the least significant bit (LSB) to the most significant bit (MSB) of the result.

18. The unit of claim 17, wherein the multiplication unit, the summing unit, and the accumulator unit are bitline processors.

19. The unit of claim 16, wherein the upper row of the multiplication unit is used to receive a new pair of multiplicands A and B in each operation cycle.

20. The unit of claim 16, wherein the summing unit communicates with the summing unit in the next row to pass the carry value down one row in each cycle, and to pass the sum value to the right and down one row.

21. The unit of claim 16, wherein the multiplication unit communicates with the multiplication unit in the next row to pass the bits of the multiplier A down a row in each cycle.

22. The unit of claim 16, further comprising a bit-transfer unit for transferring each bit of the multiplier B to its associated row in the multiplication unit.

23. The unit according to claim 15, wherein M is a power of 2.

24. The unit of claim 15, wherein N is 1, and the output of the bitwise accumulator is the multiplication of multiplicands A and B.

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