Integrated circuit device and circuit system including the integrated circuit device

Abstract

An integrated circuit device and a circuit system including the integrated circuit device are provided. An integrated circuit device having a layered structure, the layered structure including a plurality of wiring layers, a via layer sandwiched between adjacent wiring layers, a capacitor having a first terminal and a second terminal formed by a conductive structure implemented in at least the first wiring layer and the second wiring layer, the conductive structure including an arrangement of conductive strips; the strips formed in the first wiring layer are organized into at least: a first terminal comb arrangement conductively connected to the first terminal and a second terminal comb arrangement conductively connected to the second terminal, each of the comb arrangements having a base strip and a plurality of finger strips extending from the base strip; the strips formed in the second wiring layer include a plurality of individual strips constituting a finger strip of a cross-layer comb arrangement, the base strip of the cross-layer comb arrangement being a finger strip of the first terminal comb arrangement of the first wiring layer conductively connected to the individual strips through vias.

Description

Technical Field

[0001] The present invention relates to integrated circuit devices or components having a layered structure typically formed on a substrate, and in particular to capacitors implemented as such integrated circuit devices. Background Art

[0002] The layered structure may include a plurality of wiring layers and a via layer sandwiched between adjacent wiring layers. A semiconductor integrated circuit may have such a layered structure and include such a device.

[0003] It has been considered that capacitor can be set to a part of integrated circuit device or integrated circuit device.Such device can be arranged on-chip individually or together with other circuit systems, for example, is implemented as MOM (metal oxide metal) capacitor.Usually, such capacitor can be realized by arranging a plurality of unit MOM units (unit capacitors) connected or connectable together to provide a multi-unit capacitor with required capacitance.Such MOM capacitor can be regarded as a plurality of wiring (metal) layers in the hierarchical structure of the wiring layer of the semiconductor integrated circuit system (i.e. IC chip) that is appropriately connected together by utilizing the via (inter-wiring layer dielectric) in the via layer arranged between the wiring layers involved and formed by the interdigitated multi-finger capacitor (inter-digitatedmulti-finger capacitors).

[0004] In view of this, the integrated circuit device herein may be referred to as a semiconductor integrated circuit device or a semiconductor integrated circuit system.

[0005] It has been found that previously considered MOM capacitors (and their unit MOM cells) do not provide sufficient capacitance per unit area of ​​the layered structure.

[0006] It is desired to solve the above-mentioned problems. Summary of the invention

[0007] According to an embodiment of the first aspect of the present invention, there is provided an integrated circuit device having a layered structure, the layered structure comprising a plurality of wiring layers, wherein a via layer is sandwiched between adjacent wiring layers, wherein: a capacitor having a first terminal and a second terminal is formed by a conductive structure implemented in at least the first and second wiring layers, the conductive structure comprising an arrangement of conductive strips; the strips formed in the first wiring layer are organized into at least: a first terminal comb arrangement conductively connected to the first terminal and a second terminal comb arrangement conductively connected to the second terminal, each of these comb arrangements having a base strip and a plurality of finger strips extending from the base strip; and the strips formed in the second wiring layer include a plurality of individual strips constituting a finger strip of a cross-layer comb arrangement, the base strip of the cross-layer comb arrangement being a finger strip of the first terminal comb arrangement of the first wiring layer conductively connected to these individual strips through vias.

[0008] For example, the wiring layer can be considered as a metal layer of a semiconductor IC layered structure. An integrated circuit device (or component) can be referred to as a semiconductor integrated circuit device (or component), or as a capacitor, or as an integrated circuit system or a semiconductor integrated circuit system. A capacitor can be referred to as a capacitor structure, such as a MOM capacitor structure. A comb-like arrangement can be referred to as a comb-like structure or a comb-like electrode.

[0009] It will be appreciated that the arrangement of conductive (eg metal) structures results in a particularly compact capacitor having a high capacitance per unit area of ​​the layered structure.

[0010] Related optional features and related aspects are defined in a group of statements at the end of the description.

[0011] According to an embodiment of the second aspect of the present invention, there is provided a semiconductor device including a (for example, MOM) capacitor structure, the capacitor structure including: a pair of first comb electrodes arranged opposite to each other in a first layer, each of the first comb electrodes including a plurality of first finger wirings extending in a first direction and a first base wiring connecting the plurality of first finger wirings; a pair of unit electrodes arranged in a second layer above the first layer, each of the unit electrodes including a plurality of parallel wirings extending in a second direction perpendicular to the first direction, the parallel wirings of one unit electrode being arranged between adjacent parallel wirings of another unit electrode; and a pair of second comb electrodes arranged opposite to each other in a third layer above the second layer, each of the second comb electrodes including a plurality of second finger wirings extending in the first direction and a second base wiring connecting the plurality of second finger wirings, wherein each parallel wiring of the unit electrode is electrically connected to both the corresponding first finger wiring of the first comb electrode and the corresponding second finger wiring of the second comb electrode through a via in an edge portion of the parallel wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Reference will now be made, by way of example only, to the accompanying drawings in which:

[0013] Figure 1A is a schematic diagram of an example hierarchical structure that may be employed in implementing an integrated circuit device and a semiconductor integrated circuit system;

[0014] Figure 1B is a schematic diagram of a semiconductor integrated circuit system embodying the present invention;

[0015] Figures 2 to 11 is a schematic diagram presenting representative portions of a first comparative example integrated circuit device and a second comparative example integrated circuit device side by side with corresponding representative portions of an integrated circuit device embodying the present invention for ease of comparison; and

[0016] Fig.12 is a schematic diagram of an oscillator circuit embodying the present invention. DETAILED DESCRIPTION

[0017] Figure 1A is a schematic diagram of an exemplary layered structure that may be employed when implementing an integrated circuit device and corresponding circuit system (integrated circuit system or semiconductor integrated circuit system) embodying the present invention. The specific number and labeling of the layers are of course only examples.

[0018] As indicated, a substrate layer is provided at the bottom, followed by a contact layer (VIA0), and then alternating wiring (e.g., M1) layers and via (e.g., VIA1) layers. The wiring layers will be referred to herein as metal layers. For example, wiring layer M1 will be referred to as metal layer M1. As shown, the upward direction is defined as passing through the layers and away from the substrate.

[0019] The indications "AP" (for metal 11) and "RV" (for via 10) are just simple markings corresponding to the example implementation. The marking AP indicates that the top metal layer can be an aluminum layer (and the lower layer can be a copper layer) and is used to connect the pads (hence AP) and the connections to them. The via layer (VIA10) adjacent to this "redistribution layer" (metal 11) is marked as RV. The AP or metal 11 layer will be referred to as the wiring layer in this article, and the connections made in this layer will be referred to as wiring. Such a wiring layer typically includes traces / wiring that interconnects the integrated circuit bonding pads to the under-bump metal layer (not shown) formed on top of the wiring layer, each for connecting to a corresponding solder bump of the completed IC chip.

[0020] Signal lines (routing) may be implemented in metal layers (eg, in layers M8 and M9 ), wherein connections between layers are formed by vias implemented in intermediate via layers or inter-metal dielectric layers (eg, in layer VIA8 ).

[0021] Metal layers M1 to M5 may be considered lower layers, metal layers M6 to M8 may be considered middle layers, and metal layers M9 to AP may be considered upper layers, but this is only an example. The metal layers may become thinner in a downward direction, with the density and resistivity of the structures / traces also increasing in that direction.

[0022] Figure 1B is a schematic diagram of a semiconductor integrated circuit system 2 embodying the present invention and is useful for understanding the wide range of applications of embodiments of the present invention.

[0023] As indicated, circuit 4 is implemented in semiconductor integrated circuit system 2, and capacitor 6 forms part of circuit 4. In this regard, capacitor 6 may be an integrated circuit device implemented in semiconductor integrated circuit system 2 or a part of an integrated circuit device implemented in semiconductor integrated circuit system 2. Circuit 4 may of course be part of a larger circuit that is only partially implemented in semiconductor integrated circuit system 2. In some instances, circuit 4 may be capacitor 6, in which case semiconductor integrated circuit system 2 itself may be referred to as an integrated circuit device or an integrated circuit capacitor.

[0024] In general, Figures 2 to 11 A schematic diagram presenting a representative portion 100 of a first comparative example integrated circuit device (capacitor) and a representative portion 200 of a second comparative example integrated circuit device (capacitor) side by side with a corresponding representative portion 300 of an integrated circuit device (capacitor) embodying the present invention for ease of comparison. These devices may be referred to as circuit system components such as passive components.

[0025] Representative portions 100, 200, 300 can of course be considered capacitors themselves, such as unit capacitors, multiple instances of which can, for example, be dynamically combined to form larger "multi-unit" capacitors. Therefore, representative portions and combinations of those representative portions will be referred to herein as capacitors. Capacitor 300 is a detailed implementation of capacitor 6 or a portion of capacitor 6.

[0026] Now Figures 2 to 11 Consider them together. Figures 2 to 11 In each of the figures, part (a) is related to Comparative Example 1 (capacitor 100), part (b) is related to Comparative Example 2 (capacitor 200), and part (c) is related to the present embodiment (capacitor 300). As an example, the present embodiment is shown as distributed across metal layers M3 to M7 and intermediate via layers VIA3 to VIA6, and for ease of comparison, Comparative Example 1 and Comparative Example 2 are shown as distributed across the same layers.

[0027] Figures 2 to 11Each of shows a plan view (looking through the layers down towards the substrate, ie, looking in a downward direction perpendicular to the layers), with one or more particular layers presented, as indicated. Figure 2 The purpose is to give an overview of all layers of the stack according to FIG. 1 , layers M3 to M7 (and intermediate via layers VIA3 to VIA6 ), however some details are obscure given the number of layers involved and are not described by reference to FIG. Figures 3 to 11 To best understand.

[0028] Figures 3 to 7 Conductive structures (including conductive strips) formed in various layers M3 to M7 are shown respectively. These conductive structures can be considered as metal structures formed by metal strips, and in fact the entire capacitor 300 can be considered as a MOM capacitor.

[0029] Figure 8 Conductive structures formed in layers M3 and M4 and vias formed in the intermediate via layer VIA3 to create connections from layer M3 to M4 are shown. Fig. 9 1 shows conductive structures formed in layers M4 and M5 and vias formed in intermediate via layer VIA4 (making connections from layer M4 to M5), Fig.10 shows conductive structures formed in layers M5 and M6 and vias formed in intermediate via layer VIA5 (making connections from layer M5 to M6), and Fig.11 Conductive structures formed in layers M6 and M7 are shown, as well as vias formed in intermediate via layer VIA6 (making a connection from layer M6 to M7).

[0030] Before comparing with Comparative Examples 1 and 2 (capacitors 100 and 200), the following will first be described. Figures 2 to 11 Implementation method (capacitor 300) (see part (c) of these figures).

[0031] First consider Figures 3 to 7 As can be seen, the conductive (metal) structures are implemented in the wiring (metal) layer, and these structures consist of an arrangement of conductive (metal) strips. These arrangements and the interconnections between them are used to form a capacitor 300 (integrated circuit device), which has a Figure 2 (Part (c)) The first terminal and the second terminal are labeled as "positive" and "negative" respectively.

[0032] First consider Figure 3 (Part (c)), the strips formed in the layer M3 (first wiring layer) are organized into at least: a first terminal comb arrangement 310 conductively connected to the first terminals and a second terminal comb arrangement 320 conductively connected to the second terminals.

[0033] The first terminal comb arrangement 310 includes a base strip 312 and a plurality of finger strips 314, 316, and 318 extending from the base strip 312. The finger strips 314 and 318 can be considered as edge finger strips of the first terminal comb arrangement 310 because they are the outermost finger strips of the comb arrangement. The second terminal comb arrangement 320 includes a base strip 322 and a plurality of finger strips 324, 326, and 328 extending from the base strip 322. The finger strips 324 and 328 can be considered as edge finger strips of the second terminal comb arrangement 320 because they are the outermost finger strips of the comb arrangement. Considering the combination of the first terminal comb arrangement 310 and the second terminal comb arrangement 320, the finger strips 318 and 328 can be referred to as edge finger strips of the combination because they are the outermost finger strips of the combination.

[0034] The finger strips 314, 316, 318, 324, 326, 328 generally have (in Figure 3 the same length as those measured in the left-right direction and (in Figure 3 Finger strip 318 is shown as having a slightly wider width than finger strips 314 and 316, and finger strip 328 is shown as having a wider width than finger strips 324 and 326 over a portion of its length, however these are implementation details and the widths of the finger strips may be uniform in other arrangements. Base strips 312 and 322 have (in Figure 3 The width of the finger-shaped strip (measured in the left-right direction) is greater than the width of the finger-shaped strip. The width and length of the strip and the corresponding area are measured parallel to the layer.

[0035] The first terminal comb arrangement 310 and the second terminal comb arrangement 320 are opposite to each other in that their finger strips extend from their base strips toward each other. In this regard, the first terminal comb arrangement 310 and the second terminal comb arrangement 320 are interlaced with each other so that their finger strips extend side by side with each other in an alternating arrangement. To facilitate this, the first terminal comb arrangement 310 and the second terminal comb arrangement 320 have substantially the same structure as each other, wherein their finger strips are arranged at regular intervals.

[0036] Of course, although the first terminal comb arrangement 310 and the second terminal comb arrangement 320 are shown as each having three finger strips, this is only an example, and generally the comb arrangements can each have two, three or more finger strips. The first terminal comb arrangement 310 and the second terminal comb arrangement 320 do not need to have the same number of finger strips as each other.

[0037] Go to Figure 4(Part (c)), the strip formed in layer M4 (second wiring layer) includes a plurality of individual strips 330 and 340 (only some of these strips are marked). The individual strips 330 and the individual strips 340 are arranged alternately. Figure 4 (For example, by Figure 4 As can be clearly seen from the comparison of the structures of Comparative Example 1 and Comparative Example 2 in FIG. 3 , strips 330 and 340 can be referred to as “separate” strips.

[0038] Strips 330 and 340 are, for example, conductively isolated from one another within layer M4, i.e., considering only conductive connections formed in layer M4 alone, strips 330 and 340 are conductively isolated from one another. In other words, considering only conductive connections formed in layer M4 alone, strips 330 and 340 are each defined by a continuous or closed boundary and are each conductively separated from other finger-like strips formed in layer M4. Strips 330 and strips 340 are each non-adjacent to other finger-like strips formed in layer M4, and (as will become apparent) are each conductively connected to another strip only by vias. Thus, the individual strips may be referred to as isolated, islanded, individual, independent, free-standing, unbonded, or separated strips.

[0039] consider Figure 8 , the individual strips formed in layer M4 include strips 330, which constitute finger strips of a cross-layer comb arrangement, the base strips of which are the finger strips of the first terminal comb arrangement 310 of layer M3 that are conductively connected to these individual strips 330 through vias (in this case, finger strips 318). Therefore, (compared to comparative examples 1 and 2) the individual strips 330 can form part of a comb arrangement (extending across layers) without the need to form a base strip in layer M4, thereby avoiding the associated area loss as considered in more detail later. Similarly, the individual strips formed in layer M4 include strips 340, which constitute finger strips of a cross-layer comb arrangement, the base strips of which are the finger strips of the second terminal comb arrangement 320 of layer M3 that are conductively connected to these individual strips 340 through vias (in this case, finger strips 328). Thus, the individual strips 340 may also form part of a comb arrangement without forming the base strips in layer M4 (ie in the same layer as the strips 340 ).

[0040] Although the finger strips 314, 316, 318, 324, 326, 328 are arranged in a first direction ( Figure 3 The finger strips 330 and 340 extend substantially parallel to each other in the second direction ( Figure 4The first direction and the second direction (in the upper and lower directions) extend substantially parallel to each other, but the first direction and the second direction are different (substantially perpendicular to each other in the present embodiment).

[0041] As previously described, the finger strips of the first terminal comb arrangement 310 and the second terminal comb arrangement 320 extend in opposite directions. Similarly, the finger strip 330 can be considered to extend in the opposite direction to the finger strip 340 relative to its base strip of the cross-layer comb arrangement.

[0042] Similar to the first terminal comb arrangement 310 and the second terminal comb arrangement 320, the two cross-layer comb arrangements including finger strips 330 and 340, respectively, are interlaced so that their finger strips extend side by side with each other in an alternating arrangement. To facilitate this, these cross-layer comb arrangements have substantially the same structure as each other, wherein the finger strips 330 and 340 are arranged at regular intervals. Of course, Figure 4 The number of finger strips 330 and 340 shown is only an example. Generally, two, three or more finger strips 330 and two, three or more finger strips 340 may be provided. The number of finger strips 330 does not have to be the same as the number of finger strips 340.

[0043] from Figure 4 It can be seen that the finger strips 330 and 340 have approximately ( Figure 4 The same length in the upper and lower directions) and ( Figure 4 The width and length of the strips and the corresponding area are measured parallel to the layer. Note that the finger strips 330 are connected to the edge finger strips 318 and 328 respectively by vias. Figure 4 The middle portion is slightly offset downward relative to the finger strip 340 (see Figure 8 As mentioned previously, the finger strips 318 and 328 may be referred to as edge finger strips of the combination of the first terminal comb arrangement 310 and the second terminal comb arrangement 320 .

[0044] Accordingly, the finger strips 318 and 328 serve as both finger strips of the first terminal comb arrangement 310 and the second terminal comb arrangement 320 and as base strips of two cross-layer comb arrangements including the finger strips 330 and 340 , respectively.

[0045] Go to Figure 5(Part (c)), the strips formed in layer M5 (third wiring layer) are organized into at least: a first terminal comb arrangement 410 conductively connected to the first terminal and a second terminal comb arrangement 420 conductively connected to the second terminal. The first terminal comb arrangement 410 (similar to the first terminal comb arrangement 310) includes a base strip and a plurality of finger strips extending from the base strip. The second terminal comb arrangement 420 (similar to the second terminal comb arrangement 320) includes a base strip and a plurality of finger strips extending from the base strip.

[0046] Go to Figure 6 (Part (c)), the strip formed in the layer M6 (fourth wiring layer) includes a plurality of individual strips 430 and 440 (only some of these strips are marked). The individual strips 430 and the individual strips 440 are arranged alternately.

[0047] Go to Figure 7 (Part (c)), the strips formed in layer M7 (fifth wiring layer) are organized into at least: a first terminal comb arrangement 510 conductively connected to the first terminal and a second terminal comb arrangement 520 conductively connected to the second terminal. The first terminal comb arrangement 510 (similar to the first terminal comb arrangement 310) includes a base strip and a plurality of finger strips extending from the base strip. The second terminal comb arrangement 520 (similar to the second terminal comb arrangement 320) includes a base strip and a plurality of finger strips extending from the base strip.

[0048] about Figure 3 The same considerations apply to the first terminal comb arrangement 310 and the second terminal comb arrangement 320 (layer M3) Figure 5 The first terminal comb arrangement 410 and the second terminal comb arrangement 420 (layer M5) and Figure 7 The first terminal comb arrangement 510 and the second terminal comb arrangement 520 of (layer M7) are described, and repeated descriptions may be omitted. Figure 4 The same considerations apply to the individual strips 330 and 340 (layer M4) Figure 6 The individual strips 430 and 440 of (layer M6) and repeated descriptions may be omitted.

[0049] For example, in this embodiment, Figure 5 The first terminal comb arrangement 410 and the second terminal comb arrangement 420 (layer M5) have the same Figure 3The first terminal comb arrangement 310 and the second terminal comb arrangement 320 (layer M3) have the same number of finger strips and the same length and width. In fact, the finger strips in layer M5 overlap with the corresponding finger strips in layer M3. Similarly, the finger strips in layer M7 overlap with the corresponding finger strips in layers M3 and M5. As another example, the individual strips 430 and 440 are the same in number and arrangement as the individual strips 330 and 340, wherein the strips 430 and 440 of layer M6 overlap with the corresponding strips 330 and 340 of layer M4.

[0050] exist Figures 3 to 11 It can be seen that and Figure 4 and Figure 5 It can be clearly seen that in this embodiment, the width of the finger strips is within a lower width range (LW), and the width of the base strips (e.g., strips 312 and 322) of the comb arrangement other than the cross-layer comb arrangement is within a higher width range (HW), and the higher width range (HW) includes a larger width than the width within the lower width range (LW). Therefore, although the various finger strip widths are shown to be uniform, this is an example, and the widths may be different within an appropriate range.

[0051] Through Figure 3 , Figure 5 and Figure 7 As can be seen from the comparison, the base strips (e.g., strips 312 and 322) of the first terminal comb arrangement and the second terminal comb arrangement are generally configured in the same manner as each other, for example, to have similar lengths and widths between layers. The first terminal (positive) of M7 is provided with a significant additional conductive area, however, this is only an implementation detail.

[0052] exist Figure 4 , additional strips 350 and 360 are shown corresponding to base strips 312 and 322, respectively. Figure 6 The corresponding additional strips are also shown in Figures 8 to 11 It will be apparent that these facilitate connecting various first terminal comb arrangements together (forming first terminals of capacitor 300) and connecting various second terminal comb arrangements together (forming second terminals of capacitor 300). Each comb arrangement conductively connected to a first terminal (positive) forms part of a distributed first terminal plate of capacitor 300, and each comb arrangement conductively connected to a second terminal (negative) forms part of a distributed second terminal plate of capacitor 300.

[0053] Those skilled in the art will appreciate that the number of fingers and comb arrangements and their interconnection may vary from implementation to implementation.

[0054] For example, strips 330 of layer M4 are shown as connected to finger strips in layer M3 through vias (downward) and to finger strips in layer M5 through vias (upward), however, they may be connected to only layer M3 or only layer M5 (or some are connected to only layer M3 and some are connected to only layer M5). Similarly, strips 340 of layer M4 are shown as connected to finger strips in layer M3 through vias (downward) and to finger strips in layer M5 through vias (upward), however, they may be connected to only layer M3 or only layer M5 (or some are connected to only layer M3 and some are connected to only layer M5). Each of these strips may be connected to only layer M3 or only layer M5 or to both layers M3 and M5, where the connections may be omitted. Figure 8 or Fig. 9 Any such connection is made to only one of layers M3 and M5 by the associated via or vias of layer M6. Similar considerations apply to strips 430 and 440 of layer M6.

[0055] As another example, the strips 330 and 340 of layer M4 are shown as being connected by vias at their ends (e.g., edge portions, or only at their ends) to connect to edge finger strips in layers M3 and M5. However, they can be connected to other finger strips in the M3 and M5 layers.

[0056] As another example, the inter-interlacing (inter-meshing) is shown as being based on a regular finger-by-finger (alternating with each other) manner, however, the inter-interlacing may be based on a pair of fingers by a pair of fingers manner, for example, or may be irregular.

[0057] As another example, capacitor 300 is shown as including three odd layers (M3, M5, M7 or the first, third and fifth layers) and two even layers (M4, M6 or the second and fourth layers). However, layers M5 to M7 or M6 and M7 may be omitted. As another example, strip 330 or strip 340 of layer M4 may be omitted, and similar considerations apply to layer M6. As another example, additional even layers and / or odd layers (e.g., M8 and / or M9) may be employed, wherein any additional odd layers have a comb structure corresponding to the comb structure in M3, M5 and M7 and any additional even layers have separate strips corresponding to the separate strips in M4 and M6. Incidentally, in the present embodiment, layers M3 to M7 are continuous wiring layers of a layered structure, but this is not necessary.

[0058] consider Figures 3 to 7In an embodiment of the present invention, the finger strips of each wiring layer extend generally parallel to each other. The finger strips of (odd) layers M3, M5 and M7 extend generally parallel to each other, and the finger strips of (even) layers M4 and M6 extend generally parallel to each other. In practice, the finger strips are generally straight, have parallel sides, and define a rectangle. Furthermore, for example according to Figure 8 (combining layers M3 and M4) or in fact according to Figures 9 to 11 It is apparent to any one of the embodiments that, when viewed in a direction perpendicular to the layers, the finger-like strips of the odd and even layers overlap or cross each other to define a grid.

[0059] consider Figures 8 to 11 It is obvious that such a grid structure in which the base strips of the cross-layer comb arrangement are finger strips of the first terminal comb arrangement or the second terminal comb arrangement (of the odd-numbered layers) produces a very compact capacitor structure and thereby produces a high capacitance per unit area. For example, the individual strips of the even-numbered wiring layers (e.g., M4) extend substantially only in a direction parallel to the layers between the edge finger strips of the combination of the pair of the first terminal comb arrangement and the second terminal comb arrangement, for example, formed in the odd-numbered wiring layers (e.g., M3). That is, the individual strips of the even-numbered wiring layers (e.g., M4) are effectively located below or above the area already occupied by the finger strips in the odd-numbered wiring layers (e.g., M3). For example, at least 80 percent or 90 percent of the length of the individual strips of the even-numbered wiring layers extends between the edge finger strips of the combination of the pair of the first terminal comb arrangement and the second terminal comb arrangement formed in at least one odd-numbered wiring layer. This is based on Figure 2 It is also obvious.

[0060] As previously described, capacitor 300 can be considered a unit capacitor, and in this regard can be considered to be part of a larger multi-unit capacitor composed of multiple instances of capacitor 300. These instances of capacitor 300 can, for example, occupy the same layer of a layered structure and be located side by side with each other when viewed down through the layers (e.g., in an array). The number of such instances that are conductively connected together can be dynamically controlled to implement a variable capacitor (multi-unit capacitor) using a group of switched capacitors 300. As the number of such unit capacitors 300 that make up the multi-unit capacitor increases, the benefit of the area gain provided by the compact structure of the unit capacitor 300 also increases.

[0061] Now Figures 3 to 11 The embodiment of part (c) of FIG. 3 is compared with the comparative example of parts (a) and (b) of these drawings. That is, capacitor 300 is now compared with capacitors 100 and 200.

[0062] As indicated, the MOM structure of comparative example 1 (capacitor 100) all uses a comb structure per layer, wherein the fingers extend parallel to each other on the layer. This structure does not utilize the overlapping capacitance (realized by the grid structure in the present embodiment), but only relies on the sidewall capacitance. In addition, for some technologies, the fingers in some layers extend in a "non-preferred" direction, in which case they cannot utilize the minimum width and minimum spacing. Therefore, the capacitance per unit area of ​​comparative example 1 (capacitor 100) is not as high as the capacitance per unit area of ​​the present embodiment.

[0063] As indicated, the MOM structure of comparative example 2 (capacitor 200) still all uses each layer of comb structure, but wherein, fingers extend parallel to each other on the spaced layer and extend perpendicularly to each other on the adjacent layer. This produces (for the present embodiment) a grid structure with useful additional overlapping capacitance. In addition, for some technologies, the fingers in all layers extend in a "preferred" direction, in which case (for the present embodiment) they can utilize minimum width and minimum spacing. Therefore, compared with comparative example 1 (capacitor 100), the capacitance per unit area is improved in these respects. However, as indicated, in order to increase Q, the MOM fingers are connected to an L-shaped base strip, which occupies a large amount of layout area and reduces the capacitance that can be realized in the available area.

[0064] The MOM structure of this embodiment (capacitor 300) has a grid structure of finger-shaped strips across the layers to take advantage of the additional overlap capacitance, and for certain technologies takes advantage of the "preferred" orientation of each layer as described above (allowing for minimum width and minimum spacing). However, the finger-shaped strips are only on two of the four sides of the capacitor ( Figures 3 to 11 The left and right sides of the Figures 3 to 11 The top and bottom sides of the PCB do not require wide base strips, which saves area. Figures 3 to 11 In the present embodiment (capacitor 300) shown in part (c), an area such as a rectangular area parallel to the layers and sized to just include a combination of a pair of first terminal comb arrangements and second terminal comb arrangements formed in at least one odd wiring layer at least substantially includes a separate strip of at least one even wiring layer when viewed in a direction perpendicular to the layers.

[0065] The structure used in this embodiment (capacitor 300) has similar parasitic capacitance as Comparative Example 1 (capacitor 100), while having higher useful capacitance and lower parasitic capacitance than Comparative Example 2 (capacitor 200) since no L-shaped pin is required. Therefore, the structure used in this embodiment (capacitor 300) has a higher ratio of useful capacitance to parasitic capacitance than both Comparative Example 1 (capacitor 100) and Comparative Example 2 (capacitor 200).

[0066] Although the L-shaped pins in Comparative Example 2 result in an increase in Q, the effect of removing the L-shaped pins in the structure used in the present embodiment is relatively small. In short, the structure used in the present embodiment rotates the fingers 90 degrees from wiring layer to wiring layer but does not require the L-shaped structure of Comparative Example 2. This structure maximizes (increases) the capacitance per unit area and also maximizes (increases) the ratio of useful capacitance to parasitic capacitance. For circuits that can tolerate such a small reduction in Q, it is possible to have the higher capacitance per unit area and increased ratio of useful capacitance to parasitic capacitance of the embodiments of the present invention.

[0067] Return to consideration Figure 1B The capacitor (integrated circuit device) 300 as a detailed implementation of the capacitor 6 may form a part of the semiconductor integrated circuit system 2 having a layered structure. A circuit such as the circuit 4 including the capacitor 6, 300 may be implemented at least partially in the semiconductor integrated circuit system 2.

[0068] Fig.12 6 is a schematic diagram of an oscillator circuit 600 embodying the present invention, and in particular a rotary traveling wave (RTW) voltage controlled oscillator (VCO) circuit. Circuit 600 is an example of circuit 4.

[0069] RTW VCO 600 includes a transmission line (TL) 610 forming a loop. An inverter pair 620 connected to the TL compensates for losses in the TL and maintains oscillation. The VCO oscillation frequency is at least partially controlled by a band selection capacitor 630. It will be assumed here that the band selection capacitors 630 are each implemented as a bank of switched capacitors each consisting of (e.g., more than 100) instances of capacitor 300. The capacitance value affects the wavelength of the traveling wave in the VCO and thereby controls the oscillation frequency.

[0070] To achieve a high VCO frequency range, a wide range of capacitance values ​​is required (and therefore a high upper range capacitance value is required). However, the available area is generally limited and becomes smaller as the VCO frequency increases, since a higher frequency VCO requires a smaller length TL.

[0071] By implementing the band select capacitor 630 as a bank of switchable capacitors consisting of capacitors 300, a wider capacitance range (and therefore a wider frequency range) may be achieved for a given usable area.

[0072] It should be understood that RTW VCO 600 is merely an example of circuit 4, and other circuits (e.g., oscillator circuits) may be configured to utilize capacitor 300. It should be understood that capacitor 300 (capacitor 6), circuit 4 (e.g., circuit 600), and semiconductor integrated circuit system 2 each embody the present invention. Circuits such as oscillator circuits including capacitor 300 embody the present invention.

[0073] Such an integrated circuit device 6, 300 and integrated circuit system 2 may be provided in the form of an IC (integrated circuit) chip, and the IC chip may be provided as part of an IC package so that an on-chip circuit (implemented in the IC chip) may be connected to an off-chip circuit (implemented outside the IC chip but connected to the IC chip). In this case, the IC chip may be mounted on a package substrate of the IC package.

[0074] Based on the above disclosure, the present invention can be embodied in many different ways within the spirit and scope of the appended claims.

[0075] The present disclosure extends to the following numbered statements.

[0076] S1. An integrated circuit device having a layered structure, the layered structure comprising a plurality of wiring layers, wherein a via layer is sandwiched between adjacent wiring layers,

[0077] in:

[0078] a capacitor having a first terminal and a second terminal formed by a conductive structure implemented in at least a first said wiring layer and a second said wiring layer, the conductive structure comprising an arrangement of conductive strips;

[0079] The strips formed in the first wiring layer are organized into at least: a first terminal comb arrangement conductively connected to the first terminals and a second terminal comb arrangement conductively connected to the second terminals, each of the comb arrangements having a base strip and a plurality of finger strips extending from the base strip; and

[0080] The strips formed in the second wiring layer include a plurality of individual strips constituting finger strips of a cross-layer comb arrangement, the base strip of which is a finger strip of the first terminal comb arrangement of the first wiring layer conductively connected to the individual strips through vias.

[0081] S2. An integrated circuit device according to statement S1, wherein:

[0082] The strips formed in the second wiring layer include a plurality of individual strips constituting finger strips of a cross-layer comb arrangement, the base strips of which are finger strips of a second terminal comb arrangement of the first wiring layer conductively connected to the individual strips through vias.

[0083] S3. An integrated circuit device according to statement S1 or S2, wherein:

[0084] at least a portion of the conductive structure is implemented in a third wiring layer located on the side of the second wiring layer opposite to the first wiring layer in the layered structure;

[0085] The strips formed in the third wiring layer are organized into at least: a first terminal comb arrangement conductively connected to the first terminals and a second terminal comb arrangement conductively connected to the second terminals, each of the comb arrangements having a base strip and a plurality of finger strips extending from the base strip; and

[0086] The strips formed in the second wiring layer include:

[0087] a plurality of individual strips constituting a cross-layer comb-like arrangement of finger-like strips, the base strip of the cross-layer comb-like arrangement being the finger-like strips of the first terminal comb-like arrangement of the third wiring layer conductively connected to the individual strips through vias; and / or

[0088] A plurality of individual strips constitute the finger strips of the cross-layer comb-like arrangement, the base strip of the cross-layer comb-like arrangement being the finger strips of the second terminal comb-like arrangement of the third wiring layer conductively connected to the individual strips through vias.

[0089] S4. An integrated circuit device according to statement S3, wherein:

[0090] At least a plurality of the finger strips formed in the second wiring layer are finger strips of both the cross-layer comb-like arrangement of finger strips formed in the first wiring layer and the cross-layer comb-like arrangement of finger strips formed in the third wiring layer.

[0091] S5. An integrated circuit device according to statement S3 or S4, wherein:

[0092] At least a portion of the conductive structure is implemented in a fourth wiring layer located on the side of the third wiring layer opposite to the second wiring layer in the layered structure and in a fifth wiring layer located on the side of the fourth wiring layer opposite to the third wiring layer in the layered structure.

[0093] The strips formed in the fifth wiring layer are organized into at least: a first terminal comb arrangement conductively connected to the first terminals and a second terminal comb arrangement conductively connected to the second terminals, each of the comb arrangements having a base strip and a plurality of finger strips extending from the base strip; and

[0094] The strips formed in the fourth wiring layer include a plurality of individual strips constituting a cross-layer comb-like arrangement of finger-shaped strips, the base strip of the cross-layer comb-like arrangement being the finger-shaped strips of the first terminal comb-like arrangement of the third wiring layer conductively connected to these individual strips through vias, and / or the strips formed in the fourth wiring layer include a plurality of individual strips constituting a cross-layer comb-like arrangement of finger-shaped strips, the base strip of the cross-layer comb-like arrangement being the finger-shaped strips of the first terminal comb-like arrangement of the fifth wiring layer conductively connected to these individual strips through vias.

[0095] S6. An integrated circuit device according to statement S5, wherein:

[0096] The strips formed in the fourth wiring layer include a plurality of individual strips constituting a cross-layer comb-like arrangement of finger-shaped strips, the base strip of the cross-layer comb-like arrangement being the finger-shaped strips of the second terminal comb-like arrangement of the third wiring layer conductively connected to these individual strips through vias, and / or the strips formed in the fourth wiring layer include a plurality of individual strips constituting a cross-layer comb-like arrangement of finger-shaped strips, the base strip of the cross-layer comb-like arrangement being the finger-shaped strips of the second terminal comb-like arrangement of the fifth wiring layer conductively connected to these individual strips through vias.

[0097] S7. An integrated circuit device according to any of the preceding statements, wherein, for each of the wiring layers, the finger-shaped strips of the wiring layer extend substantially parallel to each other.

[0098] S8. An integrated circuit device according to any of the preceding statements, wherein:

[0099] The finger-shaped strips of the first wiring layer or the odd-numbered wiring layers extend substantially parallel to each other; and / or

[0100] The finger-shaped strips of the second wiring layer or the even-numbered wiring layer extend substantially parallel to each other; and / or

[0101] The finger-shaped strips of the first wiring layer or the odd-numbered wiring layer extend in a direction different from or substantially perpendicular to a direction in which the finger-shaped strips of the second wiring layer or the even-numbered wiring layer extend.

[0102] S9. An integrated circuit device according to any one of the preceding statements, wherein, for at least one of the wiring layers having a comb-shaped pair of finger strips conductively connected to the first terminal and the second terminal, respectively, the finger strips of the comb-shaped pair are staggered or intermeshed with each other or arranged alternately with each other.

[0103] S10. An integrated circuit device according to any of the preceding statements, wherein, for at least one of the wiring layers having a comb-shaped pair of finger strips conductively connected to the first terminal and the second terminal, respectively, the corresponding comb-shaped finger strips of the comb-shaped pair extend in opposite directions and / or extend from their base strips toward each other.

[0104] S11. An integrated circuit device according to any of the preceding statements, wherein:

[0105] For at least one of the cross-layer comb arrangements, the base strips thereof are edge finger strips of the comb arrangement which are finger strips for a comb arrangement; and / or

[0106] For at least one of the cross-layer comb arrangements, its finger strips are connected to its base strip by corresponding vias at the ends of these finger strips.

[0107] S12. An integrated circuit device according to any of the preceding statements, wherein, when viewed in a direction perpendicular to the layers, at least the finger-like strips of the first wiring layer and the second wiring layer overlap or cross each other to define a grid.

[0108] S13. An integrated circuit device according to any of the preceding statements, wherein:

[0109] The strips have a width and a length parallel to the layer, the width being within a lower width range or within a higher width range, the higher width range including a width greater than a width within the lower width range; and

[0110] The finger strips have a width within the lower width range, and the base strips of the comb arrangements other than the cross-layer comb arrangement have a width within the upper width range.

[0111] S14. An integrated circuit device according to any of the preceding statements, wherein:

[0112] The finger strips have substantially the same width as one another; and / or

[0113] The finger-like strips are substantially rectangular or straight when viewed in a direction perpendicular to the layer; and / or

[0114] The fingers of a given comb arrangement have substantially the same width as one another; and / or

[0115] The fingers of a given comb arrangement have substantially the same width and spacing between them; and / or

[0116] The fingers of a given comb arrangement have substantially the same length as one another; and / or

[0117] The individual strips have substantially the same length as one another; and / or

[0118] The finger strips of the first terminal comb arrangement and the second terminal comb arrangement have substantially the same length as each other; and / or

[0119] The first terminal comb arrangement and the second terminal comb arrangement of a given odd-numbered wiring layer have substantially the same arrangement of finger strips as the corresponding first terminal comb arrangement and second terminal comb arrangement of another odd-numbered wiring layer, and are optionally arranged so that the corresponding finger strips overlap or occupy substantially the same area parallel to the layer when viewed in a direction perpendicular to the layer; and / or

[0120] The first terminal comb arrangement and the second terminal comb arrangement of a given odd-numbered wiring layer have substantially the same arrangement as the corresponding first terminal comb arrangement and the second terminal comb arrangement of another odd-numbered wiring layer, and are optionally arranged to overlap or occupy substantially the same area parallel to the layer when viewed in a direction perpendicular to the layer; and / or

[0121] Individual strips of a given even-numbered wiring layer have substantially the same arrangement as corresponding individual strips of another even-numbered wiring layer, and are optionally arranged so that the corresponding individual strips overlap or occupy substantially the same area parallel to the layers when viewed in a direction perpendicular to the layers.

[0122] S15. An integrated circuit device according to any of the preceding statements, wherein:

[0123] The individual strips of at least one even wiring layer extend substantially only between edge finger strips of a combination of pairs of first and second terminal comb arrangements formed in at least one odd wiring layer in a direction parallel to said layers; and / or

[0124] At least 80 or 90 percent of the length of the individual strips of at least one even wiring layer extends between edge finger strips of a combination of a pair of first and second terminal comb arrangements formed in at least one odd wiring layer in a direction parallel to the layers; and / or

[0125] When viewed in a direction perpendicular to the layers, an area such as a rectangular area parallel to the layers and sized to just include a combination of finger strips of a first terminal comb arrangement and a second terminal comb arrangement formed in at least one odd wiring layer at least substantially includes a single strip of at least one even wiring layer; and / or

[0126] When viewed in a direction perpendicular to the layers, an area such as a rectangular area parallel to the layers and sized to just include a combination of a pair of first terminal comb arrangements and second terminal comb arrangements formed in at least one odd wiring layer at least substantially includes a separate strip of at least one even wiring layer, which area optionally defines an area of ​​the integrated circuit device occupied by the capacitor.

[0127] S16. An integrated circuit device according to any of the preceding statements, wherein, for each of said even-numbered wiring layers having separate strips constituting finger strips, these finger strips:

[0128] are conductively isolated from each other within the layer; and / or

[0129] are electrically conductively isolated from one another taking into account only the electrically conductive connections formed individually in the layer; and / or

[0130] Each is bounded by continuous or closed boundaries; and / or

[0131] Each is conductively separated from other finger-like strips formed in the layer when only the conductive connections formed individually in the layer are considered; and / or

[0132] Each is not adjacent to any other finger strip or other strip formed in the layer; and / or

[0133] Each is conductively connected to another strip only by means of a via; and / or

[0134] Is an isolated, islanded, individual, independent, free-standing unjoined or separated strip.

[0135] S17. The integrated circuit device according to any one of the preceding statements, wherein the even-numbered wiring layers and the odd-numbered wiring layers are consecutive wiring layers among the wiring layers.

[0136] S18. An integrated circuit device according to any one of the preceding statements, comprising a substrate having a layered structure formed thereon, an upward direction being defined as passing through the layer and away from the substrate, wherein the first wiring layer and the second wiring layer are arranged along the upward direction in the layered structure.

[0137] S19. An integrated circuit device according to any of the preceding statements, wherein each comb-like arrangement conductively connected to the first terminal forms a part of a distributed first terminal plate of the capacitor, and each comb-like arrangement conductively connected to the second terminal forms a part of a distributed second terminal plate of the capacitor.

[0138] S20. An integrated circuit device according to any of the preceding statements, wherein the capacitor is a unit capacitor, and wherein the integrated circuit device comprises a plurality of the unit capacitors arranged in different regions of the integrated circuit device when viewed in a direction perpendicular to the layer and connected or capable of being connected together to form a multi-unit capacitor.

[0139] S21. A semiconductor integrated circuit system, comprising an integrated circuit device having the layered structure according to any one of the preceding statements, wherein a circuit is at least partially implemented in the semiconductor integrated circuit system, and wherein the circuit includes at least one of the capacitors.

[0140] S22. A semiconductor integrated circuit system according to statement S21, wherein the circuit is or includes:

[0141] an oscillator circuit; or

[0142] Rotary traveling wave voltage controlled oscillator circuit.

[0143] S23. A circuit, such as an oscillator circuit, comprising an integrated circuit device according to any one of statements S1 to S20 or a semiconductor integrated circuit system according to statement S21 or S22.

[0144] S24. An IC chip comprising an integrated circuit device according to any one of statements S1 to S20 or a semiconductor integrated circuit system according to statement S21 or S22 or a circuit according to statement S23.

Claims

1. An integrated circuit device having a layered structure, the layered structure comprising a plurality of wiring layers, wherein: A via layer is sandwiched between adjacent wiring layers. in: a capacitor having a first terminal and a second terminal formed by a conductive structure implemented in at least a first wiring layer and a second wiring layer of said wiring layers, said conductive structure comprising an arrangement of conductive strips; The strips formed in the first wiring layer are organized into at least a first terminal comb arrangement conductively connected to the first terminals and a second terminal comb arrangement conductively connected to the second terminals, each of the comb arrangements having a base strip and a plurality of finger strips extending from the base strip; and The strips formed in the second wiring layer include a plurality of independent strips constituting a finger-like strip of a cross-layer comb-like arrangement, the base strip of the cross-layer comb-like arrangement being a finger-like strip of the first terminal comb-like arrangement of the first wiring layer conductively connected to the independent strips through vias, in: The finger strips of the first terminal comb-shaped arrangement are interlaced with the finger strips of the second terminal comb-shaped arrangement, the outermost finger strips of the interlaced finger strips are edge finger strips of the interlaced finger strips, and at least one edge finger strip of the edge finger strips of the interlaced finger strips is a finger strip of the first terminal comb-shaped arrangement; The base strip of the cross-layer comb-shaped arrangement is the edge finger strip of the first terminal comb-shaped arrangement of the first wiring layer; a plurality of independent strips constituting the cross-layer comb-like arrangement of finger strips extending in the second wiring layer between edge finger strips of the interdigitated finger strips formed in the first wiring layer such that the vias are located at ends of the independent strips; and Each of the plurality of independent strips formed in the second wiring layer that constitute the finger strips of the cross-layer comb-like arrangement is not adjacent to other finger strips formed in the second wiring layer.

2. The integrated circuit device according to claim 1, wherein: The strips formed in the second wiring layer include a plurality of independent strips constituting finger strips of a cross-layer comb arrangement, the base strips of which are finger strips of the second terminal comb arrangement of the first wiring layer conductively connected to the independent strips through vias.

3. An integrated circuit device according to claim 1 or 2, wherein: at least a portion of the conductive structure is implemented in a third wiring layer located on a side of the second wiring layer opposite to the first wiring layer in the layered structure; the strips formed in the third wiring layer are organized into at least a first terminal comb arrangement conductively connected to the first terminal and a second terminal comb arrangement conductively connected to the second terminal, each of the comb arrangements having a base strip and a plurality of finger strips extending from the base strip; as well as The strips formed in the second wiring layer include: a plurality of independent strips constituting finger strips of a cross-layer comb-like arrangement, the base strips of the cross-layer comb-like arrangement being finger strips of the first terminal comb-like arrangement of the third wiring layer conductively connected to the independent strips through vias; and / or A plurality of independent strips constitute the finger strips of the cross-layer comb-like arrangement, the base strip of the cross-layer comb-like arrangement being the finger strips of the second terminal comb-like arrangement of the third wiring layer conductively connected to the independent strips through vias.

4. The integrated circuit device according to claim 3, wherein: At least a plurality of finger strips formed in the second wiring layer are both finger strips whose base strips are the cross-layer comb-like arrangement of finger strips formed in the first wiring layer and whose base strips are the cross-layer comb-like arrangement of finger strips formed in the third wiring layer.

5. An integrated circuit device according to claim 1 or 2, wherein: The finger strips of the first wiring layer or the odd-numbered wiring layers extend substantially parallel to each other; and / or The finger-shaped strips of the second wiring layer extend substantially parallel to each other; and / or The finger-shaped strips of the first wiring layer or the odd-numbered wiring layer extend in a direction different from or substantially perpendicular to a direction in which the finger-shaped strips of the second wiring layer extend.

6. The integrated circuit device according to claim 1 or 2, wherein: When viewed in a direction perpendicular to the layers, at least the finger-like strips of the first and second wiring layers overlap or cross each other to define a grid.

7. An integrated circuit device according to claim 1 or 2, wherein: The strip has a width and a length parallel to the layer, the width being within a low width range or a high width range, the high width range including a width greater than a width within the low width range; as well as The finger strips have a width within the low width range, and the base strips of the comb arrangements other than the cross-layer comb arrangement have a width within the high width range.

8. An integrated circuit device according to claim 1 or 2, wherein: The finger-like strips are substantially rectangular or straight when viewed in a direction perpendicular to the layer; and / or The finger strips of a given comb arrangement have substantially the same length and / or width as one another; and / or The individual strips have substantially the same length as one another; and / or The first terminal comb arrangement and the second terminal comb arrangement of a given odd-numbered wiring layer have substantially the same arrangement of finger strips as the corresponding first terminal comb arrangement and the second terminal comb arrangement of another odd-numbered wiring layer; and / or The individual strips of the second wiring layer have substantially the same arrangement as corresponding individual strips of another even-numbered wiring layer.

9. The integrated circuit device according to claim 8, wherein: The first terminal comb arrangement and the second terminal comb arrangement of the given odd-numbered wiring layer are arranged so that corresponding finger strips overlap or occupy substantially the same area parallel to the layer when viewed in a direction perpendicular to the layer.

10. The integrated circuit device according to claim 8, wherein: The individual strips of the second wiring layer are arranged such that corresponding individual strips overlap or occupy substantially the same area parallel to the layer when viewed in a direction perpendicular to the layer.

11. The integrated circuit device according to claim 1 or 2, wherein: The capacitor is a unit capacitor and wherein the integrated circuit arrangement comprises a plurality of the unit capacitors which are arranged in different regions of the integrated circuit arrangement when viewed in a direction perpendicular to the layers and which are connected or connectable together to form a multi-unit capacitor.

12. A semiconductor integrated circuit system comprising the integrated circuit device having the layered structure according to any one of the preceding claims, wherein: A circuit is at least partially implemented in the semiconductor integrated circuit system, and wherein the circuit includes at least one of the capacitors.

13. The semiconductor integrated circuit system according to claim 12, wherein: The circuit is an oscillator circuit or a rotary traveling wave voltage controlled oscillator circuit or comprises an oscillator circuit or a rotary traveling wave voltage controlled oscillator circuit.

14. A circuit comprising the integrated circuit device according to any one of claims 1 to 11 or the semiconductor integrated circuit system according to claim 12 or 13.

15. The circuit of claim 14, wherein: The circuit is an oscillator circuit.

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