Electronic device and method of manufacturing the same

Abstract

This technology provides an electronic device and a method for manufacturing the same. An electronic device according to an embodiment of the present document may include: a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed on the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling spaces between adjacent memory cells in the plurality of memory cells; and a second insulating layer disposed over the first insulating layer, wherein the dielectric constant of the first insulating layer is smaller than the dielectric constant of the second insulating layer, or the thermal conductivity of the first insulating layer is smaller than the thermal conductivity of the second insulating layer, or both are satisfied.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0060003, filed on May 22, 2019, entitled “Electronic device and method for manufacturing the same,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The patent document relates to a memory circuit or device and its application in an electronic device or system. Background Art

[0004] Recently, as electronic devices tend toward miniaturization, low power consumption, high performance, and multi-functions, etc., semiconductor devices capable of storing information in various electronic devices such as computers and portable communication devices have been required in the art, and research on the semiconductor devices has been conducted. Such semiconductor devices include semiconductor devices capable of storing data using switching characteristics between different resistance states according to applied voltage or current, for example, RRAM (resistive random access memory), PRAM (phase change random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), electronic fuses, etc. Summary of the invention

[0005] The technology disclosed in this patent document includes storage circuits or devices and their applications in electronic devices or systems, as well as various embodiments of electronic devices and methods for manufacturing the same, wherein the electronic devices include semiconductor memories whose reliability and manufacturing processes can be improved.

[0006] In one embodiment, an electronic device may include a semiconductor memory, wherein the semiconductor memory may include: a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells arranged above the first portion of the substrate; a first insulating layer extending above the second portion of the substrate and at least partially filling a space between adjacent memory cells in the plurality of memory cells; and a second insulating layer arranged above the first insulating layer, and wherein the dielectric constant of the first insulating layer is smaller than the dielectric constant of the second insulating layer, or the thermal conductivity of the first insulating layer is smaller than the thermal conductivity of the second insulating layer, or both are satisfied.

[0007] In another embodiment, a method for manufacturing an electronic device including a semiconductor memory may include: providing a substrate including a first portion in a first region and a second portion in a second region; forming a first insulating layer extending over the second portion of the substrate and at least partially filling a space between adjacent memory cells among the plurality of memory cells; forming a second insulating layer over the first insulating layer; and performing a planarization process until the upper surfaces of the plurality of memory cells are exposed, wherein a dielectric constant of the first insulating layer is smaller than a dielectric constant of the second insulating layer, or a thermal conductivity of the first insulating layer is smaller than a thermal conductivity of the second insulating layer, or both.

[0008] These and other aspects, embodiments and associated advantages are described in more detail in the drawings, the description and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view showing a memory device according to an embodiment of the present disclosure.

[0010] Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 is a cross-sectional view illustrating a memory device and a method of manufacturing the same according to an embodiment of the present disclosure.

[0011] Figure 7 is a cross-sectional view illustrating a memory device and a method of manufacturing the same according to an embodiment of the present disclosure.

[0012] Figure 8 is an example of a configuration diagram of a microprocessor implementing a storage circuit based on the disclosed technology.

[0013] Fig. 9 is an example of a configuration diagram of a processor implementing a storage circuit based on the disclosed technology.

[0014] Fig.10 is an example of a configuration diagram of a system implementing a storage circuit based on the disclosed technology.

[0015] Fig.11 is an example of a configuration diagram of a data storage system implementing a storage circuit based on the disclosed technology.

[0016] Fig.12 is an example of a configuration diagram of a memory system implementing a memory circuit based on the disclosed technology. DETAILED DESCRIPTION

[0017] Various examples and implementations of the disclosed technology are described in detail below with reference to the accompanying drawings.

[0018] The drawings may not necessarily be drawn to scale, and in some cases, the proportions of at least some of the structures in the drawings may have been exaggerated in order to clearly illustrate certain features of the described examples or embodiments. When a specific example having two or more layers in a multilayer structure is shown in the drawings or in the specification, the relative positioning relationship of such layers or the arrangement order of these layers as shown reflects the specific embodiment of the described or shown example, and different relative positioning relationships or arrangement orders of layers are possible. In addition, the described or shown example of a multilayer structure may not reflect all the layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two shown layers). As a specific example, when the first layer in the described or shown multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" a substrate, the first layer may be formed directly on the second layer or substrate, or may represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0019] Figure 1 is a cross-sectional view showing a memory device according to an embodiment of the present disclosure.

[0020] refer to Figure 1 , the memory device may include a plurality of memory cells MC formed over a substrate SUB in which a lower structure (not shown) is formed.

[0021] Each memory cell MC may have a structure in which a bottom electrode BE, a variable resistance layer VR, and a top electrode TE are stacked. The variable resistance layer VR may be a data storage element that switches between different resistance states according to a voltage or current applied through the bottom electrode BE and the top electrode TE, thereby storing data. However, instead of the variable resistance layer VR having a variable resistance characteristic, the memory cell MC may include another data storage element that stores data using a different mechanism.

[0022] An insulating layer ILD may be formed over the substrate SUB to fill spaces between adjacent memory cells MC and to isolate the adjacent memory cells MC from each other.

[0023] However, as the integration of memory devices increases, the space between adjacent memory cells MC decreases, and various problems may occur. For example, leakage of current through the insulating layer ILD may occur between adjacent memory cells MC. When the memory cell MC is a memory cell (e.g., a phase change memory cell) configured to store data using heat generation, heat loss through the insulating layer ILD or heat transfer from the memory cell MC to one or more adjacent memory cells MC, or both may occur. In this case, the operating current may be increased and thermal interference may occur. For example, the operating current flowing through the memory cell MC may be increased to compensate for the heat loss through the insulating layer ILD.

[0024] In the following embodiments, a structure of a cell array region that can substantially solve the above-described various problems will be proposed, and a structure of a peripheral circuit region will also be proposed.

[0025] Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 is a cross-sectional view illustrating a memory device and a method of manufacturing the same according to an embodiment of the present disclosure.

[0026] First, the manufacturing method will be described.

[0027] refer to Figure 2 , a substrate 100 in which a lower structure (not shown) is formed may be provided. The substrate 100 may include a first portion in a first area A1 and a second portion in a second area A2.

[0028] The first region A1 may be a cell array region where a plurality of memory cells 110 are arranged, and the second region A2 may be a peripheral circuit region where a peripheral circuit (not shown) for driving the elements in the cell array region A1 is arranged. In this embodiment, although the first region A1 and the second region A2 are shown as being adjacent to each other, embodiments of the present disclosure are not limited thereto. For example, these regions A1 and A2 may be spaced apart from each other.

[0029] Although not shown, the first portion of the substrate 100 in the first area A1 may include a wiring such as a word line (not shown) that is coupled to a lower end of a corresponding one of the memory cells 110 and supplies a voltage or current to the memory cell 110. In addition, the second portion of the substrate 100 in the second area A2 may include various peripheral circuits such as a switch transistor (not shown) that controls access to a word line or a bit line (not shown) of the cell array region, a metal pad (not shown) coupled to a junction of the switch transistor, or a metal line (not shown).

[0030] The memory cell 110 may be formed on a first portion of the substrate 100 in the first region A1. Each memory cell 110 may include a lower electrode layer 111, a selection element layer 113, an intermediate electrode layer 115, a variable resistance layer 117, and an upper electrode layer 119. The memory cell 110 may be formed by depositing material layers (not shown) corresponding to the lower electrode layer 111, the selection element layer 113, the intermediate electrode layer 115, the variable resistance layer 117, and the upper electrode layer 119, respectively, on the substrate 100, forming a hard mask pattern 120 on the material layer, and etching the material layer using the hard mask pattern 120 as an etching barrier. The memory cell 110 may have a columnar shape, and the memory cell 110 may be formed along a line about Figure 2 The horizontal direction of the orientation of the cross-sectional view and the direction passing through the cross-sectional view are arranged.

[0031] The lower electrode layer 111 may be disposed at the lowermost portion of the memory cell 110 to provide a connection between the memory cell 110 and a portion (e.g., a word line) of the substrate 100. The lower electrode layer 111 may have a single-layer structure or a multi-layer structure and include a low-resistance conductive material such as a metal or a metal nitride.

[0032] The selection element layer 113 may have a threshold switching characteristic to substantially block current when the magnitude of the voltage supplied to the upper and lower ends of the selection element layer 113 is less than a predetermined threshold voltage and allow the current to suddenly increase when the magnitude of the voltage is equal to or greater than the threshold voltage, thereby controlling access to the variable resistance layer 117. The selection element layer 113 may include a diode, an OTS (bidirectional threshold switch) material such as a chalcogenide material, an MIEC (mixed ion electron conduction) material such as a metal containing a chalcogenide material, a MIT (metal insulator transition) material (e.g., NbO2, or VO2, etc.), or a tunneling insulating material having a relatively wide band gap (e.g., SiO2, or Al2O3, etc.).

[0033] The intermediate electrode layer 115 may physically separate the selection element layer 113 from the variable resistance layer 117 but electrically connect them. The intermediate electrode layer 115 may have a single layer structure or a multi-layer structure and may include a low resistance conductive material such as a metal or a metal nitride.

[0034] The variable resistance layer 117 may have a variable resistance characteristic, which switches between different resistance states according to the voltage or current provided to the upper and lower ends of the variable resistance layer 117, thereby storing different data. The variable resistance layer 117 may have a single-layer structure that exhibits variable resistance characteristics alone, or may have a multilayer structure that exhibits variable resistance characteristics by a combination of two or more layers. As an example, the variable resistance layer 117 may include a phase change material that can switch between an amorphous state and a crystalline state by Joule heat generated by a current flowing through the variable resistance layer 117. However, the embodiments of the present disclosure are not limited thereto, and the variable resistance layer 117 may have a single-layer structure or a multilayer structure, and may include at least one of the materials used for RRAM, PRAM, MRAM, or FRAM, that is, metal oxides such as perovskite-based oxides or transition metal oxides, phase change materials such as chalcogenide-based materials, ferromagnetic materials, or ferroelectric materials, etc. In addition, the memory cell 110 may use a data storage element that stores data in a manner different from the variable resistance layer 117. In one embodiment, the variable resistance layer 117 or a data storage element instead of the variable resistance layer 117 may perform an operation, such as a data storage operation, using heat.

[0035] The upper electrode layer 119 may be disposed at the uppermost portion of the memory cell 110 to provide a connection between the memory cell 110 and a conductive element (e.g., a bit line, not shown) above the memory cell 110. The upper electrode layer 119 may include a single-layer structure or a multi-layer structure, and may include a low-resistance conductive material such as a metal or a metal nitride.

[0036] according to Figure 2 The embodiment shown, referring to Figure 2 , the memory cell 110 includes a lower electrode layer 111, a selection element layer 113, an intermediate electrode layer 115, a variable resistance layer 117, and an upper electrode layer 119 stacked in sequence. However, the stacking order of the stacked layers 111, 113, 115, 117, and 119 may vary depending on the implementation. As an example, the positions of the selection element layer 113 and the variable resistance layer 117 may be reversed. Alternatively, as long as the variable resistance layer 117, which is essential for data storage, is retained, one or more of the stacked layers 111, 113, 115, and 119 may be omitted. Alternatively, a layer (not shown) may also be added to the stacked layers 111, 113, 115, 117, and 119.

[0037] refer to Figure 3 , a first insulating layer 130 may be formed over the substrate 100. The first insulating layer 130 may be formed in the first region A1 to fill the space between the memory cells MC. Also, the first insulating layer 130 may extend to the second region A2.

[0038] The first insulating layer 130 may be formed of a material having a low dielectric constant to reduce leakage current between the memory cells 110. When the memory cell 110 utilizes heat generation to store data, for example, when the variable resistance layer 117 includes a phase change material, the first insulating layer 130 may be formed of a material having a low thermal conductivity to reduce heat loss from the memory cell 110 or heat transfer from the memory cell 110 to the adjacent memory cell 110. That is, the first insulating layer 130 may be formed of a Low-k (low dielectric constant) material or a Low-K (low thermal conductivity) material or both. As an example, the first insulating layer 130 may include an insulating material containing silicon and carbon, such as SiOC, SIOCH, SiOCHN, SiC, SiCON or SiCN. The insulating material may be a flowable material that will be cured in a subsequent process. In one embodiment, the first insulating layer 130 may be formed using a flowable chemical vapor deposition (FCVD) process. For example, the first insulating layer 130 may be formed by reacting a dielectric precursor having a Si—C bond with an oxidant to form a dielectric material, and then by curing the dielectric material.

[0039] In order to prevent leakage current and / or heat transfer, the first insulating layer 130 may have a thickness large enough to at least fill the space between adjacent variable resistance layers 117. Hereinafter, the thickness of the first insulating layer 130 in the first area A1, that is, the distance from the upper surface of the substrate 100 to the uppermost surface of the first insulating layer 130 in the first area A1, may be referred to as a first thickness T1. Figure 3 In the illustrated embodiment, in the first region A1, the first insulating layer 130 may completely fill the space between the stacked structures, each of which includes the memory cell MC and the hard mask pattern 120, and the uppermost surface of the first insulating layer 130 may be located above the hard mask pattern 120. However, as described later, it is preferred that the thickness of the first insulating layer 130 in the second region A2 is relatively thin. In view of this, the thickness of the first insulating layer 130 in the first region A1 may be reduced as long as the first insulating layer 130 exists between at least adjacent variable resistance layers 117. For example, as shown by the first dotted line ①, the uppermost surface of the first insulating layer 130 may be lower than the upper surface of the hard mask pattern 120, or as shown by the second dotted line ②, the uppermost surface of the first insulating layer 130 may be lower than the upper surface of the upper electrode layer 119. In these examples indicated by the first dotted line ① and the second dotted line ②, the uppermost surface of the first insulating layer 130 may be higher than the upper surface of the variable resistance layer 117. In addition, a void V may exist in the first insulating layer 130. Since the vacuum in the void V has a relatively low dielectric constant or a relatively low thermal conductivity, or both, the void V together with the first insulating layer 130 may enhance the function of preventing leakage current or heat transfer, or both.

[0040] Here, a memory cell MC having a predetermined height is formed in the first area A1, while no memory cell MC exists in the second area A2. Therefore, the thickness of the first insulating layer 130 in the second area A2 may be less than the thickness of the first insulating layer 130 in the first area A1. Hereinafter, the thickness of the first insulating layer 130 in the second area A2 is referred to as the second thickness T2. Since the first insulating layer 130 is formed together in the first area A1 and the second area A2, the first insulating layer 130 may exist in the second area A2 (unless a separate process is performed to remove a portion of the first insulating layer 130 in the second area A2), but the second thickness T2 may be as thin as desired. This is because the material used for the first insulating layer 130 and having a low dielectric constant or low thermal conductivity or both has a higher shrinkage rate during the curing process, thereby causing stress, compared to the second insulating layer 140, which is to be formed in a subsequent process and includes silicon oxide. In order to make the stress generated by the first insulating layer 130 at or below the level of similar silicon oxide, the second thickness T2 may be adjusted to or less and more than For example, since the first insulating layer 130 shrinks more than the second insulating layer 140 during the curing process, tensile stress may be applied to the first insulating layer 130 during the curing process, thereby causing one or more cracks to appear in the first insulating layer 130. When the second thickness T2 of the first insulating layer 130 is adjusted to be equal to or less than When the insulating layer 130 is subjected to the tensile stress, the tensile stress applied to the insulating layer 130 can be maintained at a sufficiently low level to suppress the occurrence of the cracks.

[0041] In short, Figure 3 In the illustrated embodiment, the first insulating layer 130 may be formed in both the first region A1 and the second region A2, but the first thickness T1 of the first insulating layer 130 in the first region A1 may satisfy the first condition, that is, the first insulating layer 130 fills part or substantially all of the space between the variable resistance layers 117, and under the premise of satisfying the first condition, the second thickness T2 of the first insulating layer 130 in the second region A2 may preferably be as thin as possible. The second thickness T2 may preferably be or smaller, but can be larger To satisfy the first condition.

[0042] Subsequently, a second insulating layer 140 may be formed on the first insulating layer 130. The second insulating layer 140 may include silicon oxide, and may have a higher dielectric constant or a higher thermal conductivity, or both, than the first insulating layer 130. An upper surface of the second insulating layer 140 may be located above an upper surface of the first insulating layer 130 in the first area A1 and the second area A2 to compensate for a step difference between the first area A1 and the second area A2.

[0043] refer to Figure 4 , can be Figure 3 The resulting structure is subjected to a planarization process, such as a chemical mechanical polishing (CMP) process, until the upper surface of the memory cell 110 (e.g., the upper surface of the upper electrode layer 119) is exposed. As a result, in the first area A1, the first insulating layer 130 may exist between the memory cells 110, and may have a third thickness T1' that is substantially the same as the thickness of the memory cell 110. Moreover, in the second area A2, the first insulating layer 130 has a second thickness T2, and the second insulating layer 140 has a thickness corresponding to the difference between the third thickness T1' and the second thickness T2 and is formed on the first insulating layer 130. In the second area A2, the thickness of the second insulating layer 140 may be greater than the second thickness T2 of the first insulating layer 130.

[0044] refer to Figure 5 , the first insulating layer 130 and the second insulating layer 140 in the second region A2 may be selectively etched to form a contact hole 150. The contact hole 150 may expose a portion of the substrate 100, for example, a junction of a switching transistor, a metal pad, or a metal line. The contact hole 150 may be formed by anisotropic etching (such as dry etching).

[0045] Here, the first insulating layer 130 may be a low-k material, or a low-K material, or both, and in an anisotropic etching process (e.g., a dry etching process), these materials may have a higher etching rate than the second insulating layer 140 formed of silicon oxide or the like. Therefore, in the etching process for forming the contact hole 150, the etching rate of the first insulating layer 130 is greater than the etching rate of the second insulating layer 140. Therefore, the width of the lower portion of the contact hole 150 may become greater than the width of the upper portion of the contact hole 150. In other words, the width WB of the second contact hole 150B formed in the first insulating layer 130 may be greater than the width WA of the first contact hole 150A formed in the second insulating layer 140.

[0046] refer to Figure 6 , the contact hole 150 may be filled with a conductive material such as metal or metal nitride to form a contact plug 160 .

[0047] Here, since the lower portion of the contact plug 160 has a relatively wide width according to the shape of the contact hole 150 described above, the contact plug 160 may be easily connected to a portion of the substrate 100 , for example, a junction, a pad, or a wire of a switching transistor.

[0048] Through the above process, it is possible to manufacture Figure 6 The memory device shown in .

[0049] Reference again Figure 6 , a memory device according to an embodiment of the present disclosure may include: a substrate 100, which includes a first portion in a first area A1 and a second portion in a second area A2; memory cells 110, which are formed over the first portion of the substrate 100 in the first area A1 and are spaced apart from each other; a first insulating layer 130, which fills at least a portion of the space between the memory cells 110 and extends over the second portion of the substrate 100 in the second area A2; a second insulating layer 140, which is formed over the first insulating layer 130 in the second area A2; and a contact plug 160, which penetrates the first insulating layer 130 and the second insulating layer 140 in the second area A2 to connect to a portion of the substrate 100.

[0050] Here, the first insulating layer 130 may include a material having a relatively low dielectric constant or a relatively low thermal conductivity, or both. For example, compared to the second insulating layer 140, the first insulating layer 130 may include a material having a lower dielectric constant, or a lower thermal conductivity, or both. The second insulating layer 140 may include silicon oxide. In addition, the first insulating layer 130 may have a higher etching rate than the second insulating layer 140.

[0051] The thickness of the first insulating layer 130 in the first region A1 (eg, Figure 4 The third thickness T1′ in the second region A2 may be greater than the thickness T2 of the first insulating layer 130 in the second region A2. In addition, in the second region A2, the thickness T2 of the first insulating layer 130 may be less than the thickness of the second insulating layer 140.

[0052] The contact plug 160 may have a first portion penetrating the first insulating layer 130 and a second portion penetrating the second insulating layer 140. A width WB of the first portion may be greater than a width WA of the second portion.

[0053] According to the memory device and the method of manufacturing the same as described above, the following advantageous aspects can be obtained.

[0054] First, the first insulating layer 130 having a relatively low dielectric constant or a relatively low thermal conductivity or both exists between the memory cells 110, thereby reducing leakage current or heat transfer / loss through the first insulating layer 130. Therefore, the reliability of the memory device can be increased.

[0055] In addition, since the thickness T2 of the first insulating layer 130 extending over the second portion of the substrate 100 in the second area A2 is less than a given value, an additional process such as reducing the thickness of the first insulating layer 130 in the second area A2 or removing the first insulating layer 130 may not be performed to solve stress-related problems. Therefore, the process difficulty may be reduced and the process may be simplified.

[0056] In addition, since the first insulating layer 130 includes a material having a higher etching rate than the second insulating layer 140, the lower width WB of the contact plug 160 in the second area A2 formed in the first insulating layer 130 over the second portion of the substrate 100 can be easily increased without performing an additional process. As a result, the contact plug 160 can be easily aligned with a component located below and contacting the contact plug 160.

[0057] Meanwhile, according to an embodiment of the present disclosure, two or more memory cells may be stacked in a vertical direction. Figure 7 The description is given by way of example.

[0058] Figure 7 Detailed description of parts substantially the same as those of the above-described embodiment will be omitted.

[0059] refer to Figure 7 , the memory device may include a semiconductor substrate 200 including a first portion in a first area A1 and a second portion in a second area A2 , wherein a plurality of memory cells are arranged in the first area A1 and a peripheral circuit is disposed in the second area A2 .

[0060] A transistor TR may be provided on the second portion of the semiconductor substrate 200 in the second region A2. Specifically, in the second region A2, a gate that is a part of the transistor TR and is insulated from the semiconductor substrate 200 by a gate insulating layer may be formed on the semiconductor substrate 200, and junction regions (not shown) may be formed on both sides of the gate in the semiconductor substrate 200. The junction regions may be formed by doping impurities. Contact plugs CP may be formed on these junction regions, respectively. The contact plugs CP may pass through the first interlayer insulating layer ILD1 that covers the semiconductor substrate 200 on which the transistor TR is formed, and the contact plugs CP may be connected to the two junctions of the transistor TR.

[0061] A first word line WL1 extending in a first direction and a first pad PD1 spaced apart from the first word line WL1 may be provided over the first interlayer insulating layer ILD1. Figure 7 In terms of the orientation of the cross-sectional view, the first direction may be parallel to the horizontal direction. The first word line WL1 may cross the first area A1 and extend to a portion of the second area A2 to be connected to a first one of the contact plugs CP. The first pad PD1 may be formed in the second area A2 to be connected to a second one of the contact plugs CP. The space between the first word line WL1 and the first pad PD1 may be filled with a second interlayer insulating layer ILD2.

[0062] A first stack may be provided over the first word line WL1, the first pad PD1, and the second interlayer insulating layer ILD2, the first stack including: a plurality of memory cells 210-1 connected to the first word line WL1; a first insulating layer 230-1 filling at least a portion of a space between two memory cells 210-1 and extending to the second region A2; a second insulating layer 240-1 formed over the first insulating layer 230-1 in the second region A2; and a contact plug 260-1 penetrating the first insulating layer 230-1 and the second insulating layer 240-1 to be connected to the first pad PD1. The first stack may be provided by the same method as described above with reference to FIG. Figures 2 to 6 The first stack is formed by substantially the same process as described above.

[0063] A common bit line CBL and a second pad PD2 extending in a second direction may be provided on the first stack. The second direction may be perpendicular to Figure 7 2. Although not shown, the common bit line CBL may cross the first area A1 and extend to a portion of the second area A2 to be connected to a specific contact plug. The second pad PD2 may be formed in the second area A2 to be connected to the contact plug 260-1 of the first stack. The space between the common bit line CBL and the second pad PD2 may be filled with a third interlayer insulating layer ILD3.

[0064] A second stack may be formed over the common bit line CBL, the second pad PD2, and the third interlayer insulating layer ILD3, the second stack including: a plurality of memory cells 210-2 connected to the common bit line CBL; a third insulating layer 230-2 filling at least a portion of the space between the memory cells 210-2 and extending to the second region A2; a fourth insulating layer 240-2 formed over the first insulating layer 230-2 in the second region A2; and a contact plug 260-2 penetrating the third insulating layer 230-2 and the fourth insulating layer 240-2 to be connected to the second pad PD2. The second stack may also be formed by the same method as described above with reference to Figures 2 to 6 The above-mentioned process is basically formed by the same process.

[0065] The stacking structure from the first word line WL1 to the second stacking body may be repeated on the second stacking body. For example, the second word line WL2 extending in the same direction as the first word line WL1 to overlap the first word line WL1 and the third pad PD3 coupled to the contact plug 260-2 of the second stacking body may be provided on the second stacking body.

[0066] The above and other memory circuits or semiconductor devices based on the disclosed technology may be used in a range of devices or systems. Figures 8 to 12 Some examples are provided of devices or systems that may implement the memory circuits disclosed herein.

[0067] Figure 8 is an example of a configuration diagram of a microprocessor implementing a storage circuit based on the disclosed technology.

[0068] refer to Figure 8 , the microprocessor 1000 can perform tasks for controlling and adjusting a series of processes, a series of processes for receiving data from various external devices, processing data, and outputting processing results to external devices. The microprocessor 1000 may include a storage unit 1010, a computing unit 1020, and a control unit 1030, etc. The microprocessor 1000 may be various data processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an application processor (AP).

[0069] The storage unit 1010 is a part of the microprocessor 1000 that stores data, such as a processor register or a register. The storage unit 1010 may include a data register, an address register, and a floating point register. In addition, the storage unit 1010 may include various registers. The storage unit 1010 may perform the following functions: temporarily storing data to be operated by the operation unit 1020, the result data of the operation, and the address where the data for the operation is stored.

[0070] The memory unit 1010 may include one or more of the above-described semiconductor devices according to the embodiments. For example, the memory unit 1010 may include: a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed on the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling the space between adjacent memory cells in the plurality of memory cells; and a second insulating layer disposed on the first insulating layer, wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer, or the thermal conductivity of the first insulating layer is less than the thermal conductivity of the second insulating layer, or both are satisfied. In this way, the reliability of the memory unit 1010 can be improved, and the manufacturing process can be improved. As a result, the operating characteristics of the microprocessor 1000 can be improved.

[0071] The operation unit 1020 may perform four arithmetic operations or logic operations according to the result of decoding the command by the control unit 1030. The operation unit 1020 may include at least one arithmetic logic unit (ALU) and the like.

[0072] The control unit 1030 may receive signals from the storage unit 1010 , the operation unit 1020 , and external devices of the microprocessor 1000 , extract and decode commands, control input and output of signals of the microprocessor 1000 , and execute processing indicated by a program.

[0073] The microprocessor 1000 according to the present embodiment may further include a cache unit 1040 that can temporarily store data to be input from or output to an external device different from the storage unit 1010. In this case, the cache unit 1040 can exchange data with the storage unit 1010, the operation unit 1020, and the control unit 1030 through the bus interface 1050.

[0074] Fig. 9 is an example of a configuration diagram of a processor implementing a storage circuit based on the disclosed technology.

[0075] refer to Fig. 9 , the processor 1100 can improve performance and realize multi-functions by including various functions different from a microprocessor that performs tasks for controlling and adjusting a series of processes for receiving data from various external devices, processing data, and outputting processing results to external devices. The processor 1100 may include a core unit 1110 used as a microprocessor, a cache unit 1120 for temporarily storing data, and a bus interface 1130 for transmitting data between internal and external devices. The processor 1100 may include various systems on chip (SoCs), such as a multi-core processor, a graphics processing unit (GPU), and an application processor (AP).

[0076] The core unit 1110 of the present embodiment is a part that performs arithmetic logic operations on data input from an external device, and may include a storage section 1111 , an operation section 1112 , and a control section 1113 .

[0077] The storage unit 1111 is a part that stores data in the processor 1100, as a processor register, or register, etc. The storage unit 1111 may include a data register, an address register, and a floating point register, etc. In addition, the storage unit 1111 may include various registers. The storage unit 1111 may perform the following functions: temporarily storing data to be operated by the operation unit 1112, the result data of the operation, and the address where the data for performing the operation is stored. The operation unit 1112 is a part that performs operations in the processor 1100. The operation unit 1112 may perform four arithmetic operations, logical operations, etc. according to the result of the control unit 1113 decoding the command. The operation unit 1112 may include at least one arithmetic logic unit (ALU), etc. The control unit 1113 may receive signals from the storage unit 1111, the operation unit 1112, and the external device of the processor 1100, perform extraction and decoding of commands, control the input and output of signals of the processor 1100, and run the processing represented by the program.

[0078] The cache unit 1120 is a part that temporarily stores data to compensate for the difference in data processing speed between the kernel unit 1110 operating at a high speed and the external device operating at a low speed. The cache unit 1120 may include a primary storage unit 1121, a secondary storage unit 1122, and a tertiary storage unit 1123. Typically, the cache unit 1120 includes a primary storage unit 1121 and a secondary storage unit 1122, and may include a tertiary storage unit 1123 in the case where a high storage capacity is required. The cache unit 1120 may include an increased number of storage units as required by the situation. That is, the number of storage units included in the cache unit 1120 may be changed according to the design. The speeds at which the primary storage unit 1121, the secondary storage unit 1122, and the tertiary storage unit 1123 store and recognize data may be the same or different. In the case where the speeds of the individual storage units 1121, 1122, and 1123 are different, the speed of the primary storage unit 1121 may be the largest. At least one of the primary storage unit 1121, the secondary storage unit 1122, and the tertiary storage unit 1123 of the cache unit 1120 may include one or more of the above-described semiconductor devices according to the embodiments. For example, the cache unit 1120 may include: a substrate including a first portion in a first region and a second portion in a second region; a plurality of storage cells disposed on the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling a space between adjacent storage cells in the plurality of storage cells; and a second insulating layer disposed on the first insulating layer, and wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer, or the thermal conductivity of the first insulating layer is less than the thermal conductivity of the second insulating layer, or both are satisfied. In this way, the reliability and manufacturing process of the cache unit 1120 can be improved. As a result, the operating characteristics of the processor 1100 can be improved.

[0079] Despite Fig. 91120, it is shown that the primary storage unit 1121, the secondary storage unit 1122, and the tertiary storage unit 1123 are all configured inside the cache unit 1120. It should be noted that the primary storage unit 1121, the secondary storage unit 1122, and the tertiary storage unit 1123 of the cache unit 1120 can all be configured outside the core unit 1110, and the difference in data processing speed between the core unit 1110 and the external device can be compensated. At the same time, it should be noted that the primary storage unit 1121 of the cache unit 1120 can be set inside the core unit 1110, and the secondary storage unit 1122 and the tertiary storage unit 1123 can be configured outside the core unit 1110 to enhance the function of compensating for the difference in data processing speed. In another embodiment, the primary storage unit 1121 and the secondary storage unit 1122 can be set inside the core unit 1110, and the tertiary storage unit 1123 can be set outside the core unit 1110.

[0080] The bus interface 1130 is a portion that connects the core unit 1110 , the cache unit 1120 , and external devices and allows data to be efficiently transferred.

[0081] The processor 1100 according to the present embodiment may include a plurality of core units 1110, and the plurality of core units 1110 may share a cache unit 1120. The plurality of core units 1110 and the cache unit 1120 may be directly connected or may be connected through a bus interface 1130. The plurality of core units 1110 may be configured in the same manner as the configuration of the core unit 1110 described above. In the case where the processor 1100 includes a plurality of core units 1110, a primary storage unit 1121 of the cache unit 1120 may be configured in each core unit 1110 corresponding to the number of the plurality of core units 1110, and a secondary storage unit 1122 and a tertiary storage unit 1123 may be configured outside the plurality of core units 1110 in a manner of being shared through the bus interface 1130. The processing speed of the primary storage unit 1121 may be greater than the processing speeds of the secondary storage unit 1122 and the tertiary storage unit 1123. In another embodiment, the primary storage unit 1121 and the secondary storage unit 1122 can be configured in each core unit 1110 corresponding to the number of multiple core units 1110, and the tertiary storage unit 1123 can be configured outside the multiple core units 1110 in a manner shared through the bus interface 1130.

[0082] The processor 1100 according to the present embodiment may further include: an embedded storage unit 1140 for storing data; a communication module unit 1150, which can send data to an external device and receive data from an external device in a wired or wireless manner; a memory control unit 1160, which drives an external storage device; and a media processing unit 1170, which processes data processed in the processor 1100 or data input from an external input device, and outputs the processed data to an external interface device, etc. In addition, the processor 1100 may include a plurality of various modules and devices. In this case, the added plurality of modules can exchange data with the core unit 1110 and the cache unit 1120 and exchange data with each other through the bus interface 1130.

[0083] The embedded storage unit 1140 may include not only volatile memory but also non-volatile memory. Volatile memory may include DRAM (dynamic random access memory), mobile DRAM, SRAM (static random access memory), and memory having functions similar to the above memory, etc. Non-volatile memory may include ROM (read-only memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), magnetic random access memory (MRAM), and memory having similar functions.

[0084] The communication module unit 1150 may include a module that can be connected to a wired network, a module that can be connected to a wireless network, and may include both. The wired network module may include a local area network (LAN), a universal serial bus (USB), Ethernet, a power line communication (PLC), and various devices such as sending and receiving data through a transmission line. The wireless network module may include an infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), wireless LAN, Zigbee, ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), broadband CDMA (WCDMA), ultra-wideband (UWB), and various devices such as sending and receiving data without a transmission line, etc.

[0085] The memory control unit 1160 is used to manage and process data transmitted between the processor 1100 and an external storage device operating according to different communication standards. The memory control unit 1160 may include various memory controllers, for example, devices that can control IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), SSD (Solid State Disk), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus), Secure Digital (SD) Card, Mini Secure Digital (mSD) Card, Micro Secure Digital (micro SD) Card, Secure Digital High Capacity (SDHC) Card, Memory Stick Card, Smart Media (SM) Card, Multimedia Card (MMC), Embedded MMC (eMMC), and Compact Flash (CF) Card, etc.

[0086] The media processing unit 1170 may process data processed in the processor 1100 or data input from an external input device in the form of an image, voice, or other form, and output the data to an external interface device. The media processing unit 1170 may include a graphics processing unit (GPU), a digital signal processor (DSP), a high-definition audio device (HD audio), a high-definition multimedia interface (HDMI) controller, and the like.

[0087] Fig.10 is an example of a configuration diagram of a system implementing a storage circuit based on the disclosed technology.

[0088] refer to Fig.10 , the system 1200 as a device for processing data can perform input, processing, output, communication, storage, etc. to perform a series of operations on data. The system 1200 may include a processor 1210, a main storage device 1220, an auxiliary storage device 1230, and an interface device 1240, etc. The system 1200 of this embodiment may be various electronic systems that operate using a processor, such as computers, servers, PDAs (personal digital assistants), portable computers, network tablets, wireless phones, mobile phones, smart phones, digital music players, PMPs (portable multimedia players), cameras, global positioning systems (GPS), video cameras, recorders, telematics, audio-visual (AV) systems, and smart TVs, etc.

[0089] The processor 1210 may decode input commands and process operations, comparisons, etc. on data stored in the system 1200, and control these operations. The processor 1210 may include a microprocessor unit (MPU), a central processing unit (CPU), a single-core / multi-core processor, a graphics processing unit (GPU), an application processor (AP), and a digital signal processor (DSP), etc.

[0090] The main memory device 1220 is a storage device that can temporarily store, call and run program codes or data from the auxiliary memory device 1230 when running a program, and can save the stored content even when the power is cut off. The main memory device 1220 may include one or more of the above-mentioned semiconductor devices according to the embodiment. For example, the main memory device 1220 may include: a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells arranged on the first portion of the substrate; a first insulating layer extending on the second portion of the substrate and at least partially filling the space between adjacent memory cells in the plurality of memory cells; and a second insulating layer arranged on the first insulating layer, and wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer, or the thermal conductivity of the first insulating layer is less than the thermal conductivity of the second insulating layer, or both are satisfied at the same time. In this way, the reliability and manufacturing process of the main memory device 1220 can be improved. As a result, the operating characteristics of the system 1200 can be improved.

[0091] In addition, the main memory device 1220 may also include a static random access memory (SRAM), a dynamic random access memory (DRAM), etc., which are volatile memory types, in which all contents are erased when the power is cut off. Different from this, the main memory device 1220 may not include the semiconductor device according to the embodiment, but may include a static random access memory (SRAM), a dynamic random access memory (DRAM), etc., which are volatile memory types, in which all contents are erased when the power is cut off.

[0092] The auxiliary memory device 1230 is a memory device for storing program code or data. Although the auxiliary memory device 1230 is slower than the main memory device 1220, the auxiliary memory device 1230 can store a larger amount of data. The auxiliary memory device 1230 may include one or more of the above-mentioned semiconductor devices according to the embodiments. For example, the auxiliary memory device 1230 may include: a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed on the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling the space between adjacent memory cells in the plurality of memory cells; and a second insulating layer disposed on the first insulating layer, and wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer, or the thermal conductivity of the first insulating layer is less than the thermal conductivity of the second insulating layer, or both are satisfied at the same time. In this way, the reliability and manufacturing process of the auxiliary memory device 1230 can be improved. As a result, the operating characteristics of the system 1200 can be improved.

[0093] In addition, the auxiliary storage device 1230 may also include a data storage system (see Fig.11 The auxiliary memory device 1230 may include a magnetic tape, a magnetic disk, an optical laser disk, a magneto-optical disk, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card. Different from this, the auxiliary memory device 1230 may not include the semiconductor device according to the embodiment, but may include a data storage system (see Fig.11 1300 in the reference numeral 1300), such as a magnetic tape, a magnetic disk, an optical laser disk, a magneto-optical disk using both magnetic and optical properties, a solid-state disk (SSD), a USB memory (Universal Serial Bus memory), a Secure Digital (SD) card, a mini Secure Digital (mSD) card, a micro Secure Digital (micro SD) card, a Secure Digital High Capacity (SDHC) card, a Memory Stick card, a Smart Media (SM) card, a MultiMedia Card (MMC), an embedded MMC (eMMC), and a Compact Flash (CF) card.

[0094] The interface device 1240 can be used to perform the exchange of commands and data between the system 1200 of the present embodiment and the external device. The interface device 1240 can be a keypad, a keyboard, a mouse, a speaker, a microphone, a display, various human-machine interface devices (HIDs), and communication devices, etc. The communication device can include a module that can be connected to a wired network, a module that can be connected to a wireless network, and can include both. The wired network module can include a local area network (LAN), a universal serial bus (USB), Ethernet, a power line communication (PLC), and various devices such as sending and receiving data through a transmission line, etc. The wireless network module can include an infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), wireless LAN, Zigbee, ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), broadband CDMA (WCDMA), ultra-wideband (UWB), and various devices such as sending and receiving data without a transmission line, etc.

[0095] Fig.11 is an example of a configuration diagram of a data storage system implementing a storage circuit based on the disclosed technology.

[0096] refer to Fig.11 , the data storage system 1300 may include: a storage device 1310 having a non-volatile characteristic as a component for storing data, a controller 1320 for controlling the storage device 1310, an interface 1330 for connecting with an external device, and a temporary storage device 1340 for temporarily storing data. The data storage system 1300 may be a disk type such as a hard disk drive (HDD), a compact disk read only memory (CDROM), a digital versatile disk (DVD), and a solid state disk (SSD), and may be a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC)) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card.

[0097] The storage device 1310 may include a nonvolatile memory that semi-permanently stores data. The nonvolatile memory may include ROM (Read Only Memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), etc.

[0098] The controller 1320 may control data exchange between the storage device 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321 for performing operations such as processing a command input from the outside of the data storage system 1300 through the interface 1330, and the like.

[0099] The interface 1330 is used to perform the exchange of commands and data between the data storage system 1300 and the external device. In the case where the data storage system 1300 is a card type, the interface 1330 can be compatible with interfaces used in devices such as USB memory (universal serial bus memory), secure digital (SD) card, mini secure digital (mSD) card, micro secure digital (micro SD) card, secure digital high capacity (SDHC) card, memory stick card, smart media (SM) card, multimedia card (MMC), embedded MMC (eMMC), compact flash memory (CF) card, etc., or with interfaces used in devices similar to the above devices. In the case where the data storage system 1300 is a disk type, the interface 1330 can be compatible with interfaces such as IDE (integrated device electronics), SATA (serial advanced technology attachment), SCSI (small computer system interface), eSATA (external SATA), PCMCIA (personal computer memory card international association), USB (universal serial bus), etc., or with interfaces similar to the above interfaces. The interface 1330 can be compatible with one or more interfaces of different types from each other.

[0100] The temporary storage device 1340 can temporarily store data according to the diversity and high performance of the interface with the external device, the controller and the system, so as to effectively transmit data between the interface 1330 and the storage device 1310. The temporary storage device 1340 for temporarily storing data may include one or more of the above-mentioned semiconductor devices according to the embodiment. The temporary storage device 1340 may include: a substrate including a first portion in a first region and a second portion in a second region; a plurality of storage cells arranged on the first portion of the substrate; a first insulating layer extending on the second portion of the substrate thereof and at least partially filling the space between adjacent storage cells in the plurality of storage cells; and a second insulating layer arranged on the first insulating layer, and wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer, or the thermal conductivity of the first insulating layer is less than the thermal conductivity of the second insulating layer, or both are satisfied at the same time. In this way, the reliability and manufacturing process of the storage device 1310 or the temporary storage device 1340 can be improved. As a result, the operating characteristics and data storage characteristics of the data storage system 1300 can be improved.

[0101] Fig.12is an example of a configuration diagram of a memory system implementing a memory circuit based on the disclosed technology.

[0102] refer to Fig.12 , the storage system 1400 may include a memory 1410 having a nonvolatile characteristic as a component for storing data, a memory controller 1420 for controlling the memory 1410, and an interface 1430 for connecting with an external device, etc. The storage system 1400 may be a card type such as a solid state disk (SSD), a USB memory (Universal Serial Bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card, etc.

[0103] The memory 1410 for storing data may include one or more of the above-described semiconductor devices according to the embodiments. For example, the memory 1410 may include: a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed on the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling the space between adjacent memory cells in the plurality of memory cells; and a second insulating layer disposed on the first insulating layer, wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer, or the thermal conductivity of the first insulating layer is less than the thermal conductivity of the second insulating layer, or both are satisfied. In this way, the reliability and manufacturing process of the memory 1410 can be improved. As a result, the operating characteristics and data storage characteristics of the memory system 1400 can be improved.

[0104] In addition, according to the present embodiment, the memory 1410 may also include ROM (read-only memory) with non-volatile characteristics, NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM) and magnetic random access memory (MRAM), etc.

[0105] The memory controller 1420 may control data exchange between the memory 1410 and the interface 1430. To this end, the memory controller 1420 may include a processor 1421 for performing the following operations: processing a command input from outside the memory system 1400 through the interface 1430.

[0106] The interface 1430 is used to perform command and data exchange between the storage system 1400 and an external device. The interface 1430 may be compatible with interfaces used in devices such as USB memory (Universal Serial Bus Memory), Secure Digital (SD) Card, Mini Secure Digital (mSD) Card, Micro Secure Digital (micro SD) Card, Secure Digital High Capacity (SDHC) Card, Memory Stick Card, Smart Media (SM) Card, Multimedia Card (MMC), Embedded MMC (eMMC), Compact Flash (CF) Card, etc., or with interfaces used in devices similar to the above devices. The interface 1430 may be compatible with one or more interfaces of different types from each other.

[0107] The memory system 1400 according to the present embodiment may further include a buffer memory 1440 for efficiently transmitting data between the interface 1430 and the memory 1410 according to the diversification and high performance of the interface with the external device, the memory controller, and the memory system. For example, the buffer memory 1440 for temporarily storing data may include one or more of the above-mentioned semiconductor devices according to the embodiment. The buffer memory 1440 may include: a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed on the first portion of the substrate; a first insulating layer extending on the second portion of the substrate and at least partially filling the space between adjacent memory cells in the plurality of memory cells; and a second insulating layer disposed on the first insulating layer, and wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer, or the thermal conductivity of the first insulating layer is less than the thermal conductivity of the second insulating layer, or both are satisfied. Thus, the reliability and manufacturing process of the buffer memory 1440 may be improved. As a result, the operating characteristics and data storage characteristics of the memory system 1400 may be improved.

[0108] In addition, the buffer memory 1440 according to the present embodiment may also include SRAM (static random access memory) and DRAM (dynamic random access memory) with volatile characteristics, etc., and phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), and magnetic random access memory (MRAM) with non-volatile characteristics, etc. Different from this, the buffer memory 1440 may not include the semiconductor device according to the embodiment, but may include SRAM (static random access memory) and DRAM (dynamic random access memory) with volatile characteristics, etc., and phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), and magnetic random access memory (MRAM) with non-volatile characteristics, etc.

[0109] Based on the memory device disclosed in this document Figures 8 to 12 The features in the above examples of electronic devices or systems in the present invention can be implemented in various devices, systems or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebooks or laptop computers, game consoles, smart TVs, TV set-top boxes, multimedia servers, digital cameras with or without wireless communication capabilities, watches or other wearable devices with wireless communication capabilities.

[0110] Although this patent document includes many details, these details should not be interpreted as limitations on the scope of any invention or the content that may be claimed, but should be interpreted as descriptions of features that may be specific to a particular embodiment of a particular invention. Certain features described in this patent document in the context of different embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments, respectively, or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, in some cases, one or more features in the combination may be cut out from the claimed combination, and the claimed combination may refer to a sub-combination or a variant of a sub-combination.

[0111] Similarly, although operations are depicted in a particular order in the drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order, or requiring that all of the operations shown be performed, in order to achieve the desired effect. In addition, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0112] Only some embodiments and examples are described. Other embodiments, improvements and variations may be made based on what is described and shown in this patent document.

Claims

1. An electronic device comprising a semiconductor memory, wherein: The semiconductor memory comprises: a substrate including a first portion in a cell array region and a second portion in a peripheral circuit region; a plurality of memory cells disposed on the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and filling spaces between the plurality of memory cells; and a second insulating layer disposed on the first insulating layer in the peripheral circuit region, The dielectric constant of the first insulating layer is smaller than the dielectric constant of the second insulating layer, the thermal conductivity of the first insulating layer is smaller than the thermal conductivity of the second insulating layer, or both of the above are satisfied. wherein the second insulating layer is not disposed in the cell array region, and Wherein, a top surface of the first insulating layer in the cell array region is coplanar with a top surface of the second insulating layer in the peripheral circuit region.

2. The electronic device according to claim 1, wherein: A thickness of the first insulating layer in the peripheral circuit region is smaller than a thickness of the first insulating layer in the cell array region.

3. The electronic device according to claim 1, wherein: The thickness of the first insulating layer is smaller than the thickness of the second insulating layer in the peripheral circuit region.

4. The electronic device according to claim 1, wherein: The semiconductor memory further comprises: A contact plug penetrates the second insulating layer and the first insulating layer in the peripheral circuit region.

5. The electronic device according to claim 4, wherein: A width of a first portion of the contact plug penetrating the first insulating layer is greater than a width of a second portion of the contact plug penetrating the second insulating layer.

6. The electronic device according to claim 1, wherein: The first insulating layer completely fills the space between the plurality of memory cells in the cell array region.

7. The electronic device according to claim 1, wherein: The first insulating layer includes silicon and carbon, and Wherein, the second insulating layer comprises silicon oxide.

8. The electronic device according to claim 7, wherein: The first insulating layer includes SiOC, SIOCH, SiOCHN, SiC, SiCON or SiCN.

9. The electronic device according to claim 1, wherein: Each of the plurality of memory cells includes a phase change material.

10. The electronic device according to claim 1, further comprising: A microprocessor, the microprocessor comprising: a control unit configured to receive a signal including a command from outside the microprocessor, and perform extraction and decoding of the command or control input or output of the signal of the microprocessor; an operation unit configured to perform an operation based on a result of decoding the command by the control unit; and a storage unit configured to store data used to perform the operation, data corresponding to a result of performing the operation, or an address of data on which the operation is performed, The semiconductor memory is part of a storage unit in the microprocessor.

11. The electronic device according to claim 1, further comprising: A processor, the processor comprising: a core unit configured to execute an operation corresponding to a command input from outside the processor by using data based on the command; a cache unit configured to store data used to perform the operation, data corresponding to a result of performing the operation, or an address of data on which the operation is performed; and a bus interface connected between the core unit and the cache unit and configured to transmit data between the core unit and the cache unit; The semiconductor memory is part of a cache unit in the processor.

12. The electronic device according to claim 1, further comprising: A processing system, the processing system comprising: a processor configured to decode a command received by the processor and control an operation on information based on a result of decoding the command; an auxiliary storage device configured to store a program for decoding the command and the information; a main storage device configured to call and store the program and the information from the auxiliary storage device so that the processor uses the program and the information to perform the operation when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device, and the main memory device and an external device, The semiconductor memory is part of an auxiliary memory device or a main memory device in the processing system.

13. The electronic device according to claim 1, further comprising: A data storage system, the data storage system comprising: a storage device configured to store data and retain the stored data regardless of power supply; a controller configured to control data input to and data output from the storage device according to a command input from the outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller, and the temporary storage device and the outside, The semiconductor memory is part of a storage device or a temporary storage device in the data storage system.

14. The electronic device according to claim 1, further comprising: A storage system, the storage system comprising: a memory configured to store data and retain the stored data regardless of power; a memory controller configured to control data input to and data output from the memory according to a command input from the outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to communicate between at least one of the memory, the memory controller, and the buffer memory and the outside, The semiconductor memory is part of a memory or a buffer memory in the storage system.

15. A method for manufacturing an electronic device, the electronic device comprising a semiconductor memory, the method comprising: providing a substrate including a first portion in a cell array region and a second portion in a peripheral circuit region; forming a first insulating layer extending over the second portion of the substrate and filling spaces between a plurality of memory cells disposed over the first portion of the substrate; forming a second insulating layer over the first insulating layer in the peripheral circuit region; as well as performing a planarization process until the upper surfaces of the plurality of memory cells are exposed and are coplanar with the upper surface of the first insulating layer in the cell array region and the upper surface of the second insulating layer in the peripheral circuit region, The dielectric constant of the first insulating layer is smaller than the dielectric constant of the second insulating layer, the thermal conductivity of the first insulating layer is smaller than the thermal conductivity of the second insulating layer, or both of the above are satisfied.

16. The method according to claim 15, wherein: The plurality of memory cells respectively include a plurality of variable resistance layers, and The step of forming the first insulating layer includes: When filling the spaces between the plurality of variable resistance layers, the thickness of the first insulating layer in the peripheral circuit region is adjusted to a given value or less.

17. The method according to claim 15, after performing the planarization process, the method further comprises: forming a contact hole by etching the second insulating layer and the first insulating layer in the peripheral circuit region; as well as forming a contact plug by filling the contact hole with a conductive material, and Wherein, the etching rate of the first insulating layer is higher than the etching rate of the second insulating layer.

18. The method according to claim 17, wherein: A width of a first portion of the first insulating layer penetrating the contact hole is greater than a width of a second portion of the second insulating layer penetrating the contact hole.

19. The method according to claim 15, wherein: The first insulating layer completely fills the space between the plurality of memory cells in the cell array region.

20. The method according to claim 15, wherein: The first insulating layer includes SiOC, SIOCH, SiOCHN, SiC, SiCON or SiCN.

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