Three-dimensional capacitor structure and manufacturing method thereof

Abstract

The present invention provides a three-dimensional capacitor structure and a method for manufacturing the same. The structure includes: a conductive substrate; a laminated structure including alternating conductive layers and cavity layers, the laminated structure having grooves, the grooves isolating the laminated structure into a plurality of fin-shaped laminated units, and a rough conductive structure is formed on the surface of the conductive layer; a conductive support column passing through the fin-shaped laminated unit to connect the conductive layer and the conductive substrate; a capacitor dielectric layer formed on the surface of the conductive layer, the surface of the conductive support column and the bottom of the groove; and a conductive material filled in the cavity layer and the groove. The present invention forms a capacitor dielectric layer on the surface of the three-dimensionally stacked conductive layer, and forms a conductive material on the capacitor dielectric layer as an electrode, thereby forming a three-dimensional capacitor. The three-dimensional capacitor can achieve a very high capacitance density by controlling the number of stacked conductive layers. The rough conductive structure can effectively improve the electrical and mechanical properties of the capacitor.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit manufacturing, and in particular relates to a three-dimensional capacitor structure with high capacitance and low cost and a manufacturing method thereof. Background Art

[0002] At present, the capacitance density of three-dimensional silicon-based capacitors can reach 1.5uf / mm 2 The current development direction of three-dimensional silicon-based capacitors is to increase the effective area of ​​the capacitor by increasing the aspect ratio of the fin-shaped capacitor.

[0003] An existing method for making a three-dimensional silicon-based capacitor is as follows Figure 1 to Figure 6 As shown, the manufacturing method comprises the following steps:

[0004] Step 1), providing a silicon substrate 101 with high conductivity, etching a capacitor hole 102 with a high aspect ratio in the silicon substrate, and the silicon substrate with high conductivity serves as the lower plate of the capacitor, such as Figure 1 shown.

[0005] Step 2), forming a capacitor dielectric layer 103 on the surface of the silicon substrate 101 and the capacitor hole 102, such as Figure 2 shown.

[0006] Step 3), filling the capacitor hole 102 with a conductive material 104 to serve as the upper plate of the capacitor, such as Figure 3 shown.

[0007] Step 4), etching to remove excess conductive material 104, such as Figure 4 shown.

[0008] Step 5), depositing an isolation layer 105, such as Figure 5 shown.

[0009] Step 6), etching a lead-out hole 106 in the isolation layer 105, such as Figure 6 shown.

[0010] The above-mentioned preparation method has the following disadvantages:

[0011] First, the silicon substrate serving as the lower plate of the capacitor must have very high conductivity, which will greatly increase the difficulty and cost of the process.

[0012] Second, in order to increase the capacitance of the capacitor, the capacitor hole 102 needs to have a very high aspect ratio. For example, the existing capacitor hole has an aspect ratio of up to 20, which will greatly increase the requirements and difficulty of the etching process. It will also cause great difficulties for the subsequent filling of the conductive material 104, greatly increase the process cost, and easily reduce the yield. Summary of the invention

[0013] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a three-dimensional capacitor structure and a manufacturing method thereof, so as to solve the problem that the manufacturing method of the high-density capacitor in the prior art has too high process requirements.

[0014] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for manufacturing a three-dimensional capacitor structure, the manufacturing method comprising the following steps: 1) providing a conductive substrate, forming a stacking structure on the conductive substrate, the stacking structure comprising alternating conductive layers and sacrificial layers; 2) forming a conductive support column in the conductive substrate and the stacking structure, the conductive support column connecting the conductive layer and the conductive substrate; 3) etching a groove in the stacking structure, the groove isolating the stacking structure into a plurality of fin-shaped stacking units, each of the fin-shaped stacking units comprising at least one conductive support column; 4) selectively etching to remove the conductive support column; A sacrificial layer in the fin-shaped stacked unit is used to form a cavity layer, wherein the cavity layer exposes the surface of the conductive layer in the fin-shaped stacked unit, and the conductive layer is supported by the conductive support column; 5) The surface of the conductive layer in the fin-shaped stacked unit is processed by a hemispherical granulation process to form a rough conductive structure on the surface of the conductive layer; 6) A capacitor dielectric layer is formed on the surface of the conductive layer and at the bottom of the groove; 7) A conductive material is filled in the cavity layer and the groove to form a first electrode of a three-dimensional capacitor structure, and the conductive layer is electrically led out to the conductive substrate by the conductive support column to form a second electrode of the three-dimensional capacitor.

[0015] Optionally, a thickness ratio of the sacrificial layer to the conductive layer is between 0.5 and 2.

[0016] Optionally, the material of the sacrificial layer includes one of SiOx, SiNx, SiON and amorphous carbon.

[0017] Optionally, the resistivity of the conductive layer is less than 10 ohm*m, and the conductive layer includes one of doped polysilicon, W, Ti, TiN, Ta, TaN and Al.

[0018] Optionally, the fin-shaped stacked units are arranged in a periodic array.

[0019] Optionally, in step 4), the sacrificial layer is removed by isotropic selective etching.

[0020] Optionally, an etching rate ratio of the isotropic selective etching to the sacrificial layer and the conductive layer is not less than 20:1.

[0021] Optionally, in step 6), an atomic layer deposition process is used to form a capacitor dielectric layer on the surface of the conductive layer.

[0022] Optionally, the capacitor dielectric layer includes a stack of one or more of SiOx, HfOx, TaOx, SiNx and AlOx.

[0023] Optionally, after the conductive layer is removed in step 4), the surface of the conductive support column is exposed to the cavity layer, and in step 6), the capacitor dielectric layer is simultaneously formed on the surface of the conductive support column.

[0024] Optionally, the stacking structure further includes a peripheral region, in which a conductive column penetrating the stacking structure is formed to electrically lead the conductive substrate to an upper surface of the stacking structure, wherein an insulating layer is provided between the conductive column and the stacking structure.

[0025] Optionally, the method further includes the steps of: making a first pad on the surface of the conductive material, forming a second pad on the stacked structure in the peripheral area, and connecting the second pad to the conductive column.

[0026] The present invention also provides a three-dimensional capacitor structure, comprising: a conductive substrate; a stacked structure formed on the conductive substrate, the stacked structure comprising alternatingly stacked conductive layers and cavity layers, the stacked structure having grooves therein, the grooves isolating the stacked structure into a plurality of fin-shaped stacked units, a rough conductive structure being formed on the surface of the conductive layer; a conductive support column passing through the fin-shaped stacked units, the conductive support column connecting the conductive layer and the conductive substrate; a capacitor dielectric layer formed on the surface of the conductive layer, the surface of the conductive support column and the bottom of the groove; a conductive material filled in the cavity layer and the groove to form a first electrode of the three-dimensional capacitor structure, the conductive layer being electrically led out to the conductive substrate by the conductive support column to form a second electrode of the three-dimensional capacitor.

[0027] Optionally, a thickness ratio of the cavity layer to the conductive layer is between 0.5 and 2.

[0028] Optionally, the resistivity of the conductive layer is less than 10 ohm*m, and the conductive layer includes one of doped polysilicon, W, Ti, TiN, Ta, TaN and Al.

[0029] Optionally, the fin-shaped stacked units are arranged in a periodic array.

[0030] Optionally, the capacitor dielectric layer includes a stack of one or more of SiOx, HfOx, TaOx, SiNx and AlOx.

[0031] Optionally, the material of the conductive support column includes tungsten.

[0032] Optionally, it also includes a peripheral area located outside the stacked structure, wherein the peripheral area has a conductive column penetrating the peripheral area to electrically lead the conductive substrate to the upper surface of the peripheral area, wherein an insulating layer is provided between the conductive column and the peripheral area.

[0033] Optionally, the surface of the conductive material has a first pad, the peripheral area has a second pad, and the second pad is connected to the conductive column.

[0034] As described above, the three-dimensional capacitor structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0035] The present invention forms a capacitor dielectric layer on the surface of a three-dimensionally stacked conductive layer, and forms a conductive material as an electrode on the capacitor dielectric layer, thereby forming a three-dimensional capacitor. The three-dimensional capacitor can achieve a very high capacitance density by controlling the number of stacked conductive layers.

[0036] The substrate of the three-dimensional capacitor of the present invention does not serve as the main capacitor electrode plate, which can effectively reduce the high conductivity requirement of the substrate.

[0037] The present invention forms a rough conductive structure on the surface of the conductive layer, which can effectively improve the conductivity of the conductive layer surface and increase the surface area of ​​the conductive layer, thereby increasing the capacitance value of the capacitor, and can also increase the bonding strength between the capacitor dielectric layer and the conductive layer, thereby improving the mechanical properties of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 to Figure 6 It shows a schematic structural diagram of each step of a method for manufacturing a three-dimensional silicon-based capacitor in the prior art.

[0039] Figure 7 to Figure 15 Shown are structural schematic diagrams presented at various steps of a method for manufacturing a three-dimensional capacitor structure in an embodiment of the present invention.

[0040] Component number description

[0041] 201 Conductive substrate

[0042] 30 stacking structure

[0043] 301 Conductive layer

[0044] 302 Sacrificial Layer

[0045] 303 Conductive support column

[0046] 304 Groove

[0047] 31 Fin-shaped stacked units

[0048] 305 Cavity Layer

[0049] 306 capacitor dielectric layer

[0050] 307 Conductive material

[0051] 401 First pad

[0052] 402 Second pad

[0053] 403 Isolation Layer

[0054] 501 Conductive Column

[0055] 502 Insulation layer

[0056] 601 Rough Conductive Structure DETAILED DESCRIPTION

[0057] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0058] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0059] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0060] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0061] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0062] like Figure 7 to Figure 13 As shown, this embodiment provides a method for manufacturing a three-dimensional capacitor structure, and the manufacturing method includes the following steps:

[0063] like Figure 7 As shown, step 1) is first performed to provide a conductive substrate 201 , and a stacked structure 30 is formed on the conductive substrate 201 . The stacked structure 30 includes conductive layers 301 and sacrificial layers 302 that are alternately stacked.

[0064] The conductive substrate 201 may be a doped semiconductor material, such as doped polysilicon, etc. A stacked structure 30 may be formed on the conductive substrate 201 by, for example, a chemical vapor deposition process, and the thickness ratio of the sacrificial layer 302 to the conductive layer 301 is between 0.5 and 2, for example, the thickness ratio of the sacrificial layer 302 to the conductive layer 301 may be 1:1, etc.

[0065] The material of the sacrificial layer 302 includes one of SiOx, SiNx, SiON and amorphous carbon. The resistivity of the conductive layer 301 is less than 10 ohm*m, and the conductive layer 301 includes one of doped polysilicon, W, Ti, TiN, Ta, TaN and Al. The sacrificial layer 302 and the conductive layer 301 have a high etching selectivity in the same etching process, such as greater than 10:1, specifically 20:1, etc.

[0066] like Figure 8 As shown, step 2) is then performed to form a conductive support column 303 in the conductive substrate 201 and the stacked structure 30 , wherein the conductive support column 303 connects the conductive layer 301 and the conductive substrate 201 .

[0067] Specifically, a through hole may be formed in the stacked structure 30 by using a photolithography process and an etching process, the through hole is connected to the conductive substrate, and then a metal material is filled in the through hole by a deposition process, and finally a chemical mechanical polishing process is used to remove the metal material on the surface to form the conductive support column 303, the conductive support column 303 connects the conductive layer 301 and the conductive substrate 201, and the conductive support column 303 has the function of supporting the conductive layer 301 after the subsequent removal of the sacrificial layer 302 to avoid the collapse of the conductive layer 301, and the function of the conductive support column 303 is to support the conductive layer 301 after the subsequent removal of the sacrificial layer 302 to avoid the collapse of the conductive layer 301, and to be used for the electrical connection between the conductive layer 301 and the conductive substrate 201. The metal material may preferably be tungsten (W).

[0068] like Fig. 9 and Fig.10 As shown, step 3 is then performed to etch a groove 304 in the stack structure 30 . The groove 304 isolates the stack structure 30 into a plurality of fin-shaped stack units 31 . Each of the fin-shaped stack units 31 includes at least one conductive support column 303 .

[0069] For example, a photolithography process and an etching process can be used to etch a groove 304 in the stack structure 30, and the groove 304 isolates the stack structure 30 into a plurality of fin-shaped stack units 31. Each of the fin-shaped stack units 31 includes at least one conductive support column 303, so as to facilitate the subsequent support of the conductive layer 301 of each fin-shaped stack unit 31. Of course, each of the fin-shaped stack units 31 can also include a plurality of conductive support columns 303, which can be selected according to the size of the fin-shaped stack unit 31, the required electrical requirements, etc. The fin-shaped stack units 31 are arranged in a periodic array, such as a hexagonal array, etc. Fig.10 As shown, the top view shape of the fin-shaped stacking unit 31 can be circular, polygonal, etc.

[0070] like Fig.11 As shown, step 4 is then performed to selectively etch and remove the sacrificial layer 302 in the fin-shaped stack unit 31 to form a cavity layer 305 , wherein the cavity layer 305 exposes the surface of the conductive layer 301 in the fin-shaped stack unit 31 , and the conductive layer 301 is supported by the conductive support column 303 .

[0071] For example, isotropic selective etching may be used to remove the sacrificial layer 302. In this embodiment, the etching rate ratio of the isotropic selective etching to the sacrificial layer 302 and the conductive layer 301 is not less than 20:1, so as to ensure that when the sacrificial layer 302 is completely removed, a relatively complete conductive layer 301 is retained.

[0072] In this embodiment, after the conductive layer 301 is removed, the surface of the conductive support pillar 303 is exposed to the cavity layer 305 .

[0073] like Fig.12 and Fig.13 As shown, Fig.13 The scanning electron microscope image shows a rough conductive structure. Then, step 5) is performed to process the surface of the conductive layer in the fin-shaped stacked unit using a hemispherical granulation process to form a rough conductive structure 601 on the surface of the conductive layer.

[0074] The rough conductive structure 601 can effectively improve the conductivity of the conductive layer surface and the surface area of ​​the conductive layer, thereby increasing the capacitance of the capacitor. On the other hand, it can increase the bonding strength between the capacitor dielectric layer and the conductive layer, thereby improving the mechanical properties of the capacitor.

[0075] like Fig.14 As shown, step 6 is then performed to form a capacitor dielectric layer 306 on the surface of the conductive layer 301 and the bottom of the groove 304. At the same time, the capacitor dielectric layer 306 is also formed on the surface of the conductive support column 303. The capacitor dielectric layer 306 located on the surface of the conductive layer 301, the bottom of the groove 304 and the surface of the support column is continuous.

[0076] For example, an atomic layer deposition process may be used to form a capacitor dielectric layer 306 on the conductive layer 301, the bottom of the groove 304 and the surface of the conductive support column 303. The capacitor dielectric layer 306 includes a stack of one or more of SiOx, HfOx, TaOx, SiNx and AlOx.

[0077] like Fig.15 As shown, step 7 is finally performed to fill the cavity layer 305 and the groove 304 with a conductive material 307 to form a first electrode of the three-dimensional capacitor structure, and the conductive layer 301 is electrically led out to the conductive substrate 201 by the conductive support column 303 to form a second electrode of the three-dimensional capacitor. Finally, an isolation layer 403 is formed on the surface of the conductive material 307 and a pad window is formed, a first pad 401 is made in the pad window on the surface of the conductive material 307, and a second pad 402 is formed in the pad window on the stacked structure 30 in the peripheral area, and the second pad 402 is connected to the conductive column 501.

[0078] like Fig.15As shown, the stacking structure 30 also includes a peripheral area, in which a conductive column 501 is formed that penetrates the stacking structure 30 to electrically lead the conductive substrate 201 to the upper surface of the stacking structure 30, which can be beneficial to the coordinated connection between the three-dimensional capacitor structure and other devices or circuits, wherein an insulating layer 502 is provided between the conductive column 501 and the stacking structure 30 to ensure substantial insulation between the first electrode and the second electrode.

[0079] like Fig.15 As shown, this embodiment also provides a three-dimensional capacitor structure, including: a conductive substrate 201; a stacked structure formed on the conductive substrate 201, the stacked structure including alternately stacked conductive layers 301 and cavity layers 305, the stacked structure having grooves 304, the grooves 304 separating the stacked structure into a plurality of fin-shaped stacked units, the surface of the conductive layer having a rough conductive structure 601; a conductive support column 303 passing through the fin-shaped stacked unit, the conductive support column 303 connecting the conductive layer 301 and the conductive substrate 201; a capacitor dielectric layer 306 formed on the surface of the conductive layer 301, the surface of the conductive support column 303 and the bottom of the groove 304; a conductive material 307 filled in the cavity layer 305 and the groove 304 to form a first electrode of the three-dimensional capacitor structure, the conductive layer 301 is electrically led out to the conductive substrate 201 by the conductive support column 303 to form a second electrode of the three-dimensional capacitor.

[0080] The conductive substrate 201 may be a doped semiconductor material, such as doped polysilicon, etc. The thickness ratio of the cavity layer 305 to the conductive layer 301 is between 0.5 and 2. For example, the thickness ratio of the cavity layer 305 to the conductive layer 301 may be 1:1, etc.

[0081] The resistivity of the conductive layer 301 is less than 10 ohm*m, and the conductive layer 301 includes one of doped polysilicon, W, Ti, TiN, Ta, TaN and Al. The rough conductive structure 601 on the surface of the conductive layer 301 can effectively improve the conductivity of the conductive layer surface and increase the surface area of ​​the conductive layer, thereby increasing the capacitance value of the capacitor, and can also increase the bonding strength between the capacitor dielectric layer and the conductive layer, thereby improving the mechanical properties of the capacitor. The capacitor dielectric layer 306 includes a laminate composed of one or more of SiOx, HfOx, TaOx, SiNx and AlOx.

[0082] Each of the fin-shaped stacked units 31 may also include one or more conductive support pillars 303, which may be selected according to the size of the fin-shaped stacked unit 31, the required electrical requirements, etc. The fin-shaped stacked units 31 are arranged in a periodic array, such as a hexagonal array, etc. Fig.10 As shown, the top view shape of the fin-shaped stacking unit 31 can be circular, polygonal, etc.

[0083] The conductive support column 303 is made of tungsten.

[0084] like Fig.15 As shown, the three-dimensional capacitor structure also includes a peripheral area located outside the stacked structure, and the peripheral area has a conductive column 501 that penetrates the peripheral area to electrically lead the conductive substrate 201 to the upper surface of the peripheral area. The surface of the conductive material 307 has a first pad 401, and the peripheral area has a second pad 402. The second pad 402 is connected to the conductive column 501, which can facilitate the coordinated connection between the three-dimensional capacitor structure and other devices or circuits, wherein an insulating layer 502 is provided between the conductive column 501 and the stacked structure 30 to ensure substantial insulation between the first electrode and the second electrode.

[0085] As described above, the three-dimensional capacitor structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0086] The present invention forms a capacitor dielectric layer on the surface of a three-dimensionally stacked conductive layer, and forms a conductive material as an electrode on the capacitor dielectric layer, thereby forming a three-dimensional capacitor. The three-dimensional capacitor can achieve a very high capacitance density by controlling the number of stacked conductive layers.

[0087] The substrate of the three-dimensional capacitor of the present invention does not serve as the main capacitor electrode plate, which can effectively reduce the high conductivity requirement of the substrate.

[0088] The present invention forms a rough conductive structure on the surface of the conductive layer, which can effectively improve the conductivity of the conductive layer surface and increase the surface area of ​​the conductive layer, thereby increasing the capacitance value of the capacitor, and can also increase the bonding strength between the capacitor dielectric layer and the conductive layer, thereby improving the mechanical properties of the capacitor.

[0089] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0090] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a three-dimensional capacitor structure, characterized in that: The production method comprises the steps of: 1) providing a conductive substrate, and forming a stacked structure on the conductive substrate, wherein the stacked structure includes conductive layers and sacrificial layers alternately stacked; 2) forming a conductive support column in the conductive substrate and the stacked structure, wherein the top surface of the conductive support column is flush with the top surface of the stacked structure, and the conductive support column connects the conductive layer and the conductive substrate; 3) etching a groove in the stack structure, wherein the groove isolates the stack structure into a plurality of fin-shaped stack units, each of which includes at least one conductive support column; 4) selectively etching and removing the sacrificial layer in the fin-shaped stack unit to form a cavity layer, wherein the cavity layer exposes the surface of the conductive layer in the fin-shaped stack unit, and the conductive layer is supported by the conductive support column; 5) using a hemispherical granulation process to process the surface of the conductive layer in the fin-shaped stacked unit to form a rough conductive structure on the surface of the conductive layer; 6) forming a capacitor dielectric layer on the surface of the conductive layer and the bottom of the groove; 7) Filling the cavity layer and the groove with a conductive material to form a first electrode of a three-dimensional capacitor structure, and electrically leading the conductive layer from the conductive support column to the conductive substrate to form a second electrode of the three-dimensional capacitor; The stack structure further includes a peripheral region, in which a conductive column penetrating the stack structure is formed to electrically lead the conductive substrate to an upper surface of the stack structure, wherein an insulating layer is provided between the conductive column and the stack structure; The conductive layer includes doped polysilicon, and the material of the conductive support column includes tungsten; It also includes: making a first pad on the surface of the conductive material, forming a second pad on the stacked structure in the peripheral area, and the second pad is connected to the conductive column; wherein the first electrodes of the seven fin-shaped stacked units arranged in a hexagonal array are electrically connected to each other and are commonly connected to the same first pad.

2. The method for manufacturing a three-dimensional capacitor structure according to claim 1, characterized in that: The thickness ratio of the sacrificial layer to the conductive layer is between 0.5 and 2.

3. The method for manufacturing a three-dimensional capacitor structure according to claim 1, characterized in that: The material of the sacrificial layer includes one of SiOx, SiNx, SiON and amorphous carbon.

4. The method for manufacturing a three-dimensional capacitor structure according to claim 1, characterized in that: The resistivity of the conductive layer is less than 10 ohm*m.

5. The method for manufacturing a three-dimensional capacitor structure according to claim 1, characterized in that: Step 4) removing the sacrificial layer by isotropic selective etching.

6. The method for manufacturing a three-dimensional capacitor structure according to claim 5, characterized in that: The etching rate ratio of the isotropic selective etching to the sacrificial layer and the conductive layer is not less than 20:

1.

7. The method for manufacturing a three-dimensional capacitor structure according to claim 1, characterized in that: Step 6) forming a capacitor dielectric layer on the surface of the conductive layer using an atomic layer deposition process.

8. The method for manufacturing a three-dimensional capacitor structure according to claim 1, wherein: The capacitor dielectric layer includes a stack of one or more of SiOx, HfOx, TaOx, SiNx and AlOx.

9. The method for manufacturing a three-dimensional capacitor structure according to claim 1, characterized in that: Step 4) After removing the conductive layer, the surface of the conductive support column is exposed to the cavity layer. Step 6) The capacitor dielectric layer is simultaneously formed on the surface of the conductive support column.

10. A three-dimensional capacitor structure, characterized in that: include: Conductive substrate; A stacked structure is formed on the conductive substrate, the stacked structure includes alternately stacked conductive layers and cavity layers, the stacked structure has grooves, the grooves isolate the stacked structure into a plurality of fin-shaped stacked units, and a rough conductive structure is formed on the surface of the conductive layer; A conductive support column passing through the fin-shaped stacked unit, the conductive support column connecting the conductive layer and the conductive substrate, and the top surface of the conductive support column is flush with the top surface of the stacked structure; A capacitor dielectric layer is formed on the surface of the conductive layer, the surface of the conductive support column and the bottom of the groove; A conductive material is filled in the cavity layer and the groove to form a first electrode of a three-dimensional capacitor structure, and the conductive layer is electrically led out from the conductive support column to the conductive substrate to form a second electrode of the three-dimensional capacitor; It also includes a peripheral region located at the periphery of the stacked structure, wherein the peripheral region has a conductive column penetrating the peripheral region to electrically lead the conductive substrate to the upper surface of the peripheral region, wherein an insulating layer is provided between the conductive column and the peripheral region; The conductive layer includes doped polysilicon, and the material of the conductive support column includes tungsten; The surface of the conductive material has a first pad, and the peripheral area has a second pad, and the second pad is connected to the conductive column; wherein the first electrodes of the seven fin-shaped stacked units arranged in a hexagonal array are electrically connected to each other and commonly connected to the same first pad.

11. The three-dimensional capacitor structure according to claim 10, characterized in that: The thickness ratio of the cavity layer to the conductive layer is between 0.5 and 2.

12. The three-dimensional capacitor structure according to claim 10, characterized in that: The resistivity of the conductive layer is less than 10 ohm*m.

13. The three-dimensional capacitor structure according to claim 10, characterized in that: The capacitor dielectric layer includes a stack of one or more of SiOx, HfOx, TaOx, SiNx and AlOx.

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