Semiconductor device structure

Abstract

The present invention provides a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure includes a source doping region and a drain doping region disposed on opposite sides of the gate. The semiconductor device structure includes a source protection circuit and a drain protection circuit. When viewed from a side perspective, a first drain conductive element of the drain protection circuit partially overlaps with a first source conductive element of the source protection circuit.

Description

Technical Field

[0001] The invention relates to a semiconductor device structure, and in particular to a semiconductor device structure with an electrostatic protection circuit. Background Art

[0002] In traditional integrated circuits, semiconductor devices are easily damaged by high-voltage electrostatic discharge, mainly because the gate oxide layer structure of the transistor is closer to the drain terminal and farther away from the source / body diffusion region. As a result, when the electrostatic discharge (ESD) current flows from the drain terminal, its energy tends to be distributed toward the gate dielectric layer, rather than flowing toward the source and drain doping regions, causing the gate dielectric layer to be permanently broken down (Zapped).

[0003] In conventional semiconductor devices, additional electrostatic protection components are often used to prevent transistor components from being broken down. However, additional ESD protection components increase the space occupied by the entire integrated circuit and increase the complexity of the process, resulting in high manufacturing costs. In view of this, an improved semiconductor device structure is needed to have good electrostatic discharge protection capabilities. Summary of the invention

[0004] An embodiment of the present invention provides a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate and a gate, which are arranged on the semiconductor substrate; a source doping region, which is arranged in the semiconductor substrate; a drain doping region, which is arranged in the semiconductor substrate, wherein the source doping region and the drain doping region are located on opposite sides of the gate; a source protection circuit, which includes: a plurality of source contact windows, which are arranged on the source doping region; and a plurality of first source conductive elements, which are arranged on the source contact windows, each of which is electrically connected to at least one source contact window; a drain protection circuit, which includes: a plurality of drain contact windows, which are arranged on the drain doping region; and a plurality of first drain conductive elements, which are arranged on the drain contact window, each of which is electrically connected to at least one drain contact window, wherein the first drain conductive element partially overlaps with the first source conductive element when viewed from a side perspective.

[0005] Some embodiments of the present invention provide a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate; a gate disposed on the semiconductor substrate and extending along a first direction; a source doping region disposed in the semiconductor substrate and extending along the first direction; a drain doping region disposed in the semiconductor substrate and extending along the first direction, wherein the source doping region and the drain doping region are located on opposite sides of the gate; a plurality of source contact windows disposed on the source doping region and arranged along the first direction; a plurality of drain contact windows disposed on the drain doping region and arranged along the first direction; and a first source conductive element disposed on the source contact window and electrically connected to at least one source contact window, the first source conductive element extending along the first direction.

[0006] In order to make the features and advantages of the embodiments of the present invention more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments of the present invention;

[0008] Figure 2A A top view of a layout of a semiconductor device structure according to some embodiments of the present invention;

[0009] Figure 2B , Figure 2C , Figure 2D , Figure 2E According to some embodiments of the present invention, Figure 2A A cross-sectional view of a semiconductor device structure shown;

[0010] Figure 3 According to some embodiments of the present invention, Figure 2A A cross-sectional perspective view of a semiconductor device structure shown;

[0011] Figure 4A A top view of a layout of a semiconductor device structure according to some embodiments of the present invention;

[0012] Figure 4B According to some embodiments of the present invention, Figure 4A A cross-sectional view of a semiconductor device structure shown;

[0013] Figure 5A A top view of a layout of a semiconductor device structure according to some embodiments of the present invention;

[0014] Figure 5B According to some embodiments of the present invention, Figure 5A A cross-sectional view of the semiconductor device structure shown.

[0015] Explanation of symbols:

[0016] 100 Semiconductor device structure

[0017] 110 Semiconductor substrate

[0018] 120 Well Area

[0019] 130 Quarantine

[0020] 140 Source doping region

[0021] 150 Drain doping region

[0022] 160 Grid

[0023] 162 gate dielectric layer

[0024] 164 Gate electrode

[0025] 170 Main Area

[0026] 200A semiconductor device structure

[0027] 200B Semiconductor Device Structure

[0028] 200C Semiconductor Device Structure

[0029] 210 Gate

[0030] 212 gate dielectric layer

[0031] 214 Gate electrode

[0032] 220 Source doping region

[0033] 222 Source contact window

[0034] 224 Source via

[0035] 226 first source conductive element

[0036] 228 second source conductive element

[0037] 230 Drain doping region

[0038] 232 Drain contact window

[0039] 234 Drain via

[0040] 236 first drain conductive element

[0041] 238 second drain conductive element

[0042] 240 Semiconductor substrate

[0043] 242 Interlayer dielectric layer

[0044] 244 Interlayer dielectric layer

[0045] 246 Interlayer Dielectric Layer

[0046] 248 interlayer dielectric layer

[0047] 250a, 250b, 250c Source protection circuit

[0048] 260a, 260b, 260c Drain protection circuit

[0049] B, D, S, G Applied voltage DETAILED DESCRIPTION

[0050] A number of embodiments or examples are provided below for implementing different components of the provided semiconductor device. Specific examples of each component and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first component is formed on a second component, it may include an embodiment in which the first and second components are in direct contact, and it may also include an embodiment in which an additional component is formed between the first and second components so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference numbers and / or letters in different examples. Such repetition is for simplicity and clarity, and is not intended to indicate the relationship between the different embodiments discussed.

[0051] Some variations of the embodiments are described below. In the various drawings and illustrated embodiments, similar reference numerals are used to designate similar elements. It is understood that the semiconductor device structure may include additional elements, and some of the described elements may be replaced or deleted for other embodiments of the structure.

[0052] Embodiments of the present invention disclose embodiments of semiconductor device structures, and the above embodiments can be included in integrated circuits (ICs) such as microprocessors, memory devices and / or other devices. The above integrated circuits can also include various passive and active microelectronic components, such as thin-film resistors, other types of capacitors such as metal-insulator-metal capacitors (MIMCAPs), inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors, high-power MOS transistors or other types of transistors. A person having ordinary skill in the art to which the present invention belongs can understand that the semiconductor device can also be used to include other types of semiconductor components in an integrated circuit.

[0053] See also Figure 1 , Figure 1 FIG. 1 is a cross-sectional view of a semiconductor device structure 100 according to some embodiments of the present invention. Figure 1 As shown, the semiconductor device structure 100 includes a semiconductor substrate 110. The semiconductor substrate 110 may be a bulk semiconductor, a semiconductor-on-insulation (SOI) substrate. The semiconductor substrate 110 may be a wafer, such as a silicon wafer. Generally speaking, a semiconductor-on-insulation substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or a similar material. The insulating layer is provided on a substrate, which is generally a silicon or glass substrate. Other substrates may be used, such as a multi-layer or gradient substrate. In some embodiments, the semiconductor substrate 110 may be a semiconductor material, which may include silicon or germanium; the semiconductor substrate 110 may also be a compound semiconductor, which may include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; the semiconductor substrate 110 may also be an alloy semiconductor, which may include SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP or a combination thereof. In some embodiments, the semiconductor substrate 110 has a first conductive form, such as a P-type.

[0054] In addition, the semiconductor device structure 100 may include an epitaxial layer (not shown), which may be formed on the semiconductor substrate 110. The epitaxial layer may include silicon, germanium, silicon and germanium, III-V compounds, or a combination thereof. The epitaxial layer may be formed by an epitaxial growth process, such as metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), plasma-enhanced chemical vapor deposition (PECVD), remote plasma chemical vapor deposition (RPCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), or the like. In some embodiments, the epitaxial layer may have a first conductivity type, such as a P-type.

[0055] like Figure 1 As shown, the semiconductor device structure 100 includes a well region 120 formed in the semiconductor substrate 110. Alternatively, the well region 120 may be formed in the epitaxial layer. In some embodiments, the well region 120 has a first conductivity type, such as a P type. The doping concentration of the well region 120 may be between about 10 12 atoms / cm 3 to about 10 17 atoms / cm 3 range.

[0056] like Figure 1As shown, the semiconductor device structure 100 includes a plurality of isolation regions 130. In some embodiments, the isolation region 130 may be a shallow trench isolation region. The semiconductor substrate 110 may be patterned by a photolithography process and an etching process to form a plurality of openings, and then a dielectric material is filled into the openings by a deposition process to form the isolation region 130. In other embodiments, the isolation region 130 may be a field oxide region formed by silicon oxidation. The above-mentioned photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (e.g., hard baking), other suitable processes or combinations thereof to form. The photolithography process may also be replaced by maskless photolithography, electron beam writing, ion beam writing or molecular imprinting. The above-mentioned etching process includes dry etching, wet etching or other etching methods (e.g., reactive ion etching). The etching process may also be pure chemical etching (plasma etching), pure physical etching (ion milling) or a combination thereof. The above-mentioned deposition process includes chemical vapor deposition, chemical vapor deposition, atomic layer deposition or other deposition methods.

[0057] like Figure 1 As shown, the semiconductor device structure 100 includes a source doping region 140, a drain doping region 150, and a gate 160. The source doping region 140 and the drain doping region 150 are located on opposite sides of the gate 160. In some embodiments, the source doping region 140 and the drain doping region 150 have a second doping type different from the first doping type, such as N-type. The doping concentration of the source doping region 140 and the drain doping region 150 may be between about 10 19 atoms / cm 3 to about 10 21 atoms / cm 3 The source doping region 140 and the drain doping region 150 may be formed by methods such as ion implantation or diffusion, and the implanted dopants may be activated by a rapid thermal annealing (RTA) process.

[0058] like Figure 1As shown, the gate 160 includes a gate dielectric layer 162 and a gate electrode 164. The gate dielectric layer 162 may be silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, or any other suitable dielectric material, or a combination thereof. The material of the high-k dielectric material may be metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, metal aluminate, zirconium silicate, zirconium aluminate. For example, the high-k dielectric material may be LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfO2, HfO3, HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba,Sr)TiO3 (BST), Al2O3, other high-k dielectric materials of other suitable materials, or combinations thereof. The gate dielectric layer 162 may be formed by chemical vapor deposition (CVD) or spin coating. The chemical vapor deposition method may be, for example, low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) of atomic layer chemical vapor deposition, or other commonly used methods.

[0059] In some embodiments, the gate electrode 164 may be polysilicon. In some embodiments, the gate electrode 164 may be one or more metals, metal nitrides, conductive metal oxides, or combinations thereof. The metals may include, but are not limited to, molybdenum, tungsten, titanium, tantalum, platinum, or hafnium. The metal nitrides may include, but are not limited to, molybdenum nitride, tungsten nitride, titanium nitride, and tantalum nitride. The conductive metal oxides may include, but are not limited to, ruthenium oxide and indium tin oxide. The gate electrode 164 may be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method.

[0060] In some embodiments, the semiconductor device structure 100 includes a body region 170. The body region 170 has a first doping type and a doping concentration between about 10 19 atoms / cm 3 to about 10 21 atoms / cm 3 The range of Figure 1 As shown, the source doped region 140 and the body region 170 may be separated by the isolation region 130. In addition, the drain doped region 150, the source doped region 140, the gate 160 and the body region 170 may be connected to an external voltage D, S, G, B respectively, but the invention is not limited thereto.

[0061] See also Figure 2A , Figure 2A FIG. 2 is a top view of the layout of a semiconductor device structure 200A according to some embodiments of the present invention. It is worth noting that Figure 2A In order to clearly illustrate the layout of the conductive elements, doped regions, and vias in the source region and the drain region, some elements are omitted.

[0062] like Figure 2A As shown, the semiconductor device structure 200A includes a gate 210, a source doping region 220, and a drain doping region 230. The gate 210, the source doping region 220, and the drain doping region 230 may correspond to Figure 1The gate 160, the source doping region 140 and the drain doping region 150 are not described again here. The gate 210, the source doping region 220 and the drain doping region 230 extend along the first direction (for example, the Y-axis direction). More specifically, the long sides of the gate 210, the source doping region 220 and the drain doping region 230 are substantially parallel to the first direction. In addition, although Figure 2A Not shown, the semiconductor device structure 200A may include a plurality of gates 210, source doping regions 220, and drain doping regions 230. The plurality of gates 210, source doping regions 220, and drain doping regions 230 may be arranged along a second direction (e.g., an X-axis direction). The semiconductor device structure 200A may also include a body region (not shown). The body region may surround the plurality of gates 210, source doping regions 220, and drain doping regions 230.

[0063] Next, if Figure 2A As shown, the semiconductor device structure 200A includes a source protection circuit 250a and a drain protection circuit 260a. Figure 2B , Figure 2B for Figure 2A The semiconductor device structure 200A is a cross-sectional view along the line CC. The semiconductor device structure 200A includes a semiconductor substrate 240. The semiconductor substrate 240 may be the same as or similar to the semiconductor substrate 110, and will not be described again. Figure 2B As shown, the semiconductor device structure 200A includes interlayer dielectric layers 242, 244, 246, and 248, which are located on a semiconductor substrate 240. In some embodiments, the interlayer dielectric layers 242, 244, 246, and 248 are flowable films formed by flowing chemical vapor deposition. In some embodiments, the interlayer dielectric layers 242, 244, 246, and 248 are formed of a dielectric material, such as phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like, and can be deposited by any suitable method, such as chemical vapor deposition, spin coating, plasma enhanced chemical vapor deposition, or a combination thereof.

[0064] like Figure 2A , Figure 2BAs shown, in some embodiments, the source protection circuit 250a includes a plurality of source contact windows 222, a source via 224, and a first source conductive element 226. In addition, the semiconductor device structure 200 may include a silicide layer (not shown), which is disposed between the source doping region 220 and the source contact window 222. In some embodiments, a metal material may be deposited on the semiconductor substrate 240 and then an annealing process may be performed. Next, the metal material reacts with the surface of the semiconductor substrate 240 to form a silicide layer on the surface of the semiconductor substrate 240. After the silicide layer is formed, the remaining portion of the metal material that has not reacted with the surface of the semiconductor substrate 240 is removed. The remaining portion of the metal material that has not reacted may be removed by an etching process, such as a wet etching process, a dry etching process, one or more other suitable processes, or a combination thereof.

[0065] In some embodiments, the source contact window 222 is disposed on the semiconductor substrate 240. The source contact window 222 is electrically connected to the source doped region 220. The source contact window 222 may include a barrier layer and a conductive layer. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or similar materials. The material of the conductive layer may be copper, copper alloy, silver, gold, tungsten, aluminum, nickel, cobalt, or similar materials.

[0066] like Figure 2B As shown, the first source conductive element 226 is disposed above the source contact window 222 and physically contacts the source contact window 222. The first source conductive element 226 is electrically connected to the source doped region 220. The first source conductive element 226 may include copper, titanium, cobalt, tungsten, nickel, or other suitable metal materials. In addition, the first source conductive element 226 may also include a barrier layer. The first source conductive element 226 may be formed by using a PVD process (e.g., a sputtering process), a CVD process, a spin coating process, other suitable processes, or a combination thereof. Figure 2A and Figure 2B As shown, in some embodiments, the first source conductive element 226 extends along a first direction (eg, the Y-axis direction). More specifically, the long side direction of the first source conductive element 226 is substantially parallel to the first direction. In some embodiments, the first source conductive element 226 may physically contact at least two source contact windows 222.

[0067] like Figure 2B As shown, the source via 224 is disposed on the first source conductive element 226 and physically contacts the source doped region 220. The material of the source via 224 may be the same or similar to that of the source contact window 222, and will not be described again. Figure 2AAs shown, from the top view, the source via hole 224 does not overlap with the source contact window 222. More specifically, the area where the source via hole 224 is projected onto the semiconductor substrate 240 does not overlap with the area where the source contact window 222 is projected onto the semiconductor substrate 240. In this embodiment, each first source conductive element 226 physically contacts two source contact windows 222 and one source via hole 224.

[0068] like Figure 2A , Figure 2B As shown, the source protection circuit 250a further includes a second source conductive element 228. The second source conductive element 228 is disposed above the source conductive hole 224. The material of the second source conductive element 228 may be the same or similar to that of the first source conductive element 226, and will not be repeated here. In some embodiments, the second source conductive element 228 extends along the first direction. In more detail, the long side of the second source conductive element 228 is substantially parallel to the first direction. In some embodiments, the second source conductive element 228 may cover a plurality of first source conductive elements 226.

[0069] See also Figure 2C , Figure 2C for Figure 2A The semiconductor device structure 200A is shown in FIG. Figure 2A , Figure 2C As shown, in some embodiments, the semiconductor device structure 200 includes a plurality of drain contacts 232, drain vias 234, and a first drain conductive element 236. In addition, the semiconductor device structure 200 may include a silicide layer (not shown) disposed between the drain doped region 230 and the drain contact 232.

[0070] In some embodiments, the drain contact window 232 is disposed on the semiconductor substrate 240. The drain contact window 232 is electrically connected to the drain doped region 230. The drain contact window 232 may include a barrier layer and a conductive layer. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or similar materials. The material of the conductive layer may be copper, copper alloy, silver, gold, tungsten, aluminum, nickel, cobalt, or similar materials.

[0071] like Figure 2C As shown, the first drain conductive element 236 is disposed above the drain contact window 232 and physically contacts the drain contact window 232. The first drain conductive element 236 is electrically connected to the drain doping region 230. The first drain conductive element 236 may include copper, titanium, cobalt, tungsten, nickel or other suitable metal materials. In addition, the first drain conductive element 236 may also include a barrier layer. The first drain conductive element 236 may be formed by using a PVD process (such as a sputtering process), a CVD process, a spin coating process, other suitable processes or a combination thereof. Figure 2A and Figure 2C As shown, in some embodiments, the first drain conductive element 236 extends along the first direction. More specifically, the long side direction of the first drain conductive element 236 is substantially parallel to the first direction. In some embodiments, the first drain conductive element 236 may physically contact at least two drain contact windows 232 .

[0072] like Figure 2C As shown, the drain via 234 is disposed on the first drain conductive element 236 and physically contacts the drain doping region 230. The material of the drain via 234 may be the same or similar to that of the drain contact window 232, and will not be described again. Figure 2A As shown, from the top view, the drain via hole 234 does not overlap with the drain contact window 232. More specifically, the area where the drain via hole 234 is projected onto the semiconductor substrate 240 does not overlap with the area where the drain contact window 232 is projected onto the semiconductor substrate 240. In this embodiment, each first drain conductive element 236 physically contacts two drain contact windows 232 and one drain via hole 234.

[0073] like Figure 2A , Figure 2C As shown, the second drain conductive element 238 is disposed above the drain conductive hole 234. The material of the second drain conductive element 238 may be the same or similar to that of the first drain conductive element 236, and will not be repeated here. In some embodiments, the second drain conductive element 238 extends along the first direction. In more detail, the long side direction of the second drain conductive element 238 is substantially parallel to the first direction. In some embodiments, the second drain conductive element 238 may cover a plurality of first drain conductive elements 236.

[0074] In some embodiments, such as Figure 2A As shown, the first source conductive element 226 of the source protection circuit 250a does not extend to the top of the drain doping region 230. That is, the area where the first source conductive element 226 is projected onto the surface of the semiconductor substrate 240 does not overlap with the drain doping region 230. The first drain conductive element 236 of the drain protection circuit 260a does not extend to the top of the source doping region 220. That is, the area where the first drain conductive element 236 is projected onto the surface of the semiconductor substrate 240 does not overlap with the source doping region 220. With such a layout, the difficulty of the process can be reduced, thereby improving the yield of manufacturing the semiconductor device structure 200A.

[0075] like Figure 2AAs shown, in some embodiments, the source contact window 222 of the source protection circuit 250a is not aligned with the drain contact window 232 of the drain protection circuit 260a. In more detail, the arrangement of the source contact window 222 is staggered with the arrangement of the drain contact window 232. If there is an imaginary line along the second direction, the imaginary line will not pass through the source contact window 222 and the drain contact window 232 at the same time.

[0076] In some embodiments, the source via 224 of the source protection circuit 250a is not aligned with the drain via 234 of the drain protection circuit 260a. More specifically, the arrangement of the source via 224 is staggered with the arrangement of the drain via 234. If there is an imaginary line along the second direction, the imaginary line will not pass through the source via 224 and the drain via 234 at the same time.

[0077] In some embodiments, the first source conductive element 226 of the source protection circuit 250a is not aligned with the first drain conductive element 236 of the drain protection circuit 260a. For example, the short side of the first source conductive element 226 has a distance from the short side of the adjacent first drain conductive element 236 along the first direction. That is, the short side of the first source conductive element 226 is not aligned with the short side of the adjacent first drain conductive element 236. In some embodiments, the second source conductive element 228 of the source protection circuit 250a can be aligned with the second drain conductive element 238 of the drain protection circuit 260a. For example, the short side of the second source conductive element 228 is aligned with the short side of the adjacent second drain conductive element 238. In addition, the first source conductive element 226 is separated from the first drain conductive element 236 and is not electrically connected. The second source conductive element 228 is separated from the second drain conductive element 238 and is not electrically connected.

[0078] See also Figure 2D , Figure 2D for Figure 2A The semiconductor device structure 200A is shown as a cross-sectional view along line segment AA. Figure 2D As shown, the source doping region 220 and the drain doping region 230 are located on opposite sides of the gate 210. The gate 210 includes a gate dielectric layer 212 and a gate electrode 214. The gate dielectric layer 212 and the gate electrode 214 may be the same or similar to the gate dielectric layer 162 and the gate electrode 164, respectively, and will not be described again. In some embodiments, on the cross section corresponding to the source contact window 222, the drain contact window 232 is not disposed above the drain doping region 230. In some embodiments, on the cross section corresponding to the drain via hole 234, the source via hole 224 is not disposed above the first source conductive element 226. In some embodiments, the source contact window 222 and the drain via hole 234 may be located on the same cross section.

[0079] In addition, if Figure 2D As shown, the first source conductive element 226 and the first drain conductive element 236 are located at the same horizontal layer. In more detail, the first source conductive element 226 and the first drain conductive element 236 are disposed on the interlayer dielectric layer 242. The second source conductive element 228 and the second drain conductive element 238 are located at the same horizontal layer. In more detail, the second source conductive element 228 and the second drain conductive element 238 are disposed on the interlayer dielectric layer 246.

[0080] See also Figure 2E , Figure 2E for Figure 2A The cross-sectional view of the semiconductor device structure 200A along the line BB is shown. In some embodiments, on the cross-sectional view corresponding to the drain contact window 232, the source contact window 222 is not disposed above the source doping region 220. In some embodiments, on the cross-sectional view corresponding to the source via hole 224, the drain via hole 234 is not disposed above the first drain conductive element 236. In some embodiments, the drain contact window 232 and the source via hole 224 may be located in the same cross-sectional view.

[0081] See also Figure 3 , Figure 3 According to some embodiments of the present invention, Figure 2A FIG. 2 is a cross-sectional perspective view of a semiconductor device structure 200A. More specifically, Figure 3 yes Figure 2B and Figure 2C The diagram after the two sections are overlapped. It is worth noting that the solid line shows Figure 2B The dashed lines are shown as Figure 2C Components. Figure 3 As shown, the source contact window 222 and the drain contact window 232 do not overlap. The source via hole 224 and the drain via hole 234 do not overlap. In some embodiments, the first source conductive element 226 partially overlaps the first drain conductive element 236. In some embodiments, the first source conductive element 226 and the first drain conductive element 236 do not completely overlap. The source via hole 224 and the drain via hole 234 are disposed on the overlapping area.

[0082] Various changes and adjustments can be made to the embodiments of the present invention. In some embodiments, the layout of the protection circuit can have other aspects. Figure 4A and Figure 4B . Figure 4A FIG. 2 is a top view of a layout of a semiconductor device structure 200B according to some embodiments of the present invention. Figure 4B According to some embodiments of the present invention, Figure 4A The cross-sectional view along the EE line is shown in FIG. Figure 4AAs shown, the semiconductor device structure 200B includes a source protection circuit 250b and a drain protection circuit 260b. The source protection circuit 250b includes a source contact window 222, a source via hole 224, a first source conductive element 226, and a second source conductive element 228. The drain protection circuit 260b includes a drain contact window 232, a drain via hole 234, a first drain conductive element 236, and a second drain conductive element 238. In some embodiments, each first source conductive element 226 of the source protection circuit 250b may physically contact one source contact window 222 and two source via holes 224. In some embodiments, each first drain conductive element 236 of the drain protection circuit 260b may contact one drain contact window 232 and two drain via holes 234.

[0083] Various changes and modifications can be made to the embodiments of the present invention. Figure 5A and Figure 5B . Figure 5A FIG. 2 is a top view of a layout of a semiconductor device structure 200C according to some embodiments of the present invention. Figure 5B According to some embodiments of the present invention, Figure 5A The cross-sectional view along the FF line is shown in FIG. Figure 5A As shown, the semiconductor device structure 200C includes a source protection circuit 250c and a drain protection circuit 260c. The source protection circuit 250c includes a source contact window 222, a source via hole 224, a first source conductive element 226, and a second source conductive element 228. The drain protection circuit 260c includes a drain contact window 232, a drain via hole 234, a first drain conductive element 236, and a second drain conductive element 238. In some embodiments, each first source conductive element 226 of the source protection circuit 250c may physically contact three source contact windows 222 and two source via holes 224. In some embodiments, each first drain conductive element 236 of the drain protection circuit 260c may contact three drain contact windows 232 and two drain via holes 234. In some embodiments, the number of source contact windows 222 contacted by the first source conductive element 226 is different from the number of source via holes 224 contacted by the first source conductive element 226. In some embodiments, the number of drain contact windows 232 contacted by the first drain conductive element 236 is different from the number of drain vias 234 contacted by the first drain conductive element 236 .

[0084] It is worth noting that the number of source contact windows or source vias that the source conductive element physically contacts, or the number of drain contact windows or drain vias that the drain conductive element physically contacts shown in the above figures are only examples. In other embodiments, other aspects may be provided. In addition, the first source conductive element 226 and the first drain conductive element 236 may also be referred to as a first metal layer; the second source conductive element 228 and the second drain conductive element 238 may also be referred to as a second metal layer.

[0085] Although the embodiments of the present invention and their advantages have been disclosed as above, it should be understood that any person with ordinary knowledge in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present invention. In addition, the scope of protection of the present invention is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the art can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure of some embodiments of the present invention. As long as the embodiments described herein can implement substantially the same functions or obtain substantially the same results, they can be used according to some embodiments of the present invention. Therefore, the scope of protection of the present invention includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present invention also includes the combination of each claim and embodiment.

Claims

1. A semiconductor device structure, characterized in that: The semiconductor device structure comprises: a semiconductor substrate; A gate, disposed on the semiconductor substrate and extending along a first direction; A source doping region, disposed in the semiconductor substrate and extending along the first direction; a drain doping region, disposed in the semiconductor substrate and extending along the first direction, wherein the source doping region and the drain doping region are located on opposite sides of the gate and arranged along the second direction; A source protection circuit comprising: A plurality of source contact windows are disposed on the source doping region and arranged along the first direction; and a plurality of first source conductive elements, disposed on the source contact window, each of the first source conductive elements being electrically connected to at least one source contact window, and the first source conductive elements extending along the first direction; and A drain protection circuit comprising: A plurality of drain contact windows are disposed on the drain doping region and arranged along the first direction; and A plurality of first drain conductive elements are disposed on the drain contact window, each of the first drain conductive elements is electrically connected to at least one drain contact window, and the first drain conductive elements extend along the first direction; A plurality of source vias, disposed on the first source conductive element; and A plurality of drain conductive holes are disposed on the first drain conductive element, wherein the source conductive holes are staggered with the drain conductive holes, and when viewed from the side perspective in the second direction, the source conductive holes and the drain conductive holes do not overlap; When viewed from the side perspective in the second direction, the first drain conductive element partially overlaps with the first source conductive element.

2. The semiconductor device structure according to claim 1, wherein: The first source conductive element is separated from the first drain conductive element.

3. The semiconductor device structure according to claim 1, wherein: At least one first source conduction element physically contacts the at least two source contacts.

4. The semiconductor device structure according to claim 1, wherein: The source protection circuit further comprises: A plurality of source vias, disposed on the first source conductive element and electrically connected to the source doped region; From the top view, the source through hole and the source contact window do not overlap.

5. The semiconductor device structure according to claim 4, wherein: At least one first source conductive element physically contacts the at least two source vias.

6. The semiconductor device structure according to claim 4, wherein: The number of source contact windows and source via holes contacted by a first source conductive element is different.

7. The semiconductor device structure according to claim 1, wherein: The source protection circuit further comprises: A second source conductive element covers the first source conductive element.

8. The semiconductor device structure according to claim 1, wherein: The source protection circuit does not extend directly above the drain doping region.

9. The semiconductor device structure according to claim 1, wherein: The first source conductive element does not extend above the drain doping region.

10. The semiconductor device structure according to claim 1, wherein: From the side perspective view, the source contact window and the drain contact window do not overlap.

11. A semiconductor device structure, characterized in that: The semiconductor device structure comprises: a semiconductor substrate; A gate, disposed on the semiconductor substrate and extending along a first direction; A source doping region, disposed in the semiconductor substrate and extending along the first direction; a drain doping region, disposed in the semiconductor substrate and extending along the first direction, wherein the source doping region and the drain doping region are located on opposite sides of the gate and arranged along the second direction; A plurality of source contact windows are disposed on the source doping region and arranged along the first direction; A plurality of drain contact windows are disposed on the drain doping region and arranged along the first direction; and a first source conductive element, disposed on the source contact window and electrically connected to the source doped region, the first source conductive element extending along the first direction; a first drain conductive element, disposed on the drain contact window and electrically connected to the drain doping region, the first drain conductive element extending along the first direction; A plurality of source vias, disposed on the first source conductive element; and A plurality of drain vias are arranged on the first drain conductive element, wherein the source vias are staggered with the drain vias, and when viewed from the side perspective in the second direction, the source vias do not overlap with the drain vias.

12. The semiconductor device structure according to claim 11, wherein: When viewed from the side perspective in the second direction, the drain contact window does not overlap with the source contact window.

13. The semiconductor device structure according to claim 11, wherein: When viewed from a top view, the first source conductive element and the first drain conductive element partially overlap in the first direction.

14. The semiconductor device structure according to claim 11, wherein: When viewed from the side perspective in the second direction, the first source conductive element partially overlaps with the first drain conductive element.

15. The semiconductor device structure according to claim 11, wherein: The first source conductive element physically contacts at least two source contact windows.

16. The semiconductor device structure according to claim 11, wherein: When viewed from the side perspective in the second direction, the source through hole and the source contact window do not overlap.

17. The semiconductor device structure according to claim 11, wherein: The first source conductive element physically contacts at least two source vias.

18. The semiconductor device structure according to claim 11, wherein: The semiconductor device structure further comprises: A second source conductive element covers the first source conductive element and extends along the first direction.

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