Semiconductor device

Abstract

A semiconductor device having a ring gate structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a bottom surface and sidewalls of the first trench, a first field insulating layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping end portions of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulating layer.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present disclosure relate to a semiconductor device, and more particularly, to a semiconductor device having a gate-all-around structure. BACKGROUND

[0002] To improve the integration of a semiconductor device, a transistor having a gate-all-around structure including a gate surrounding a nanowire-shaped silicon body formed on a substrate has been proposed.

[0003] Since the transistor having the gate-all-around structure can utilize a three-dimensional channel, it can be scaled down. Also, its current control capability can be improved without increasing its gate length. In the transistor having the gate-all-around structure, a short channel effect (SCE) in which a potential of a channel region is affected by a drain voltage can be effectively reduced and / or suppressed. SUMMARY

[0004] According to example embodiments of the present inventive concept, a semiconductor device can include a first fin pattern and a second fin pattern separated by a first trench, each of the first fin pattern and the second fin pattern extending lengthwise in a first direction; a first nanosheet on the first fin pattern; a second nanosheet on the second fin pattern; a first fin liner extending along at least a portion of a bottom surface and sidewalls of the first trench; a first field insulating layer disposed on the first fin liner and filling a portion of the first trench; and a first gate structure overlapping end portions of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer can be greater than a height from the bottom surface of the first trench to an upper surface of the first field insulating layer.

[0005] According to example embodiments of the present inventive concept, a semiconductor device can include a first fin pattern and a second fin pattern separated by a first trench, each of the first fin pattern and the second fin pattern extending lengthwise in a first direction; a first nanosheet on the first fin pattern; a second nanosheet on the second fin pattern; a first field insulating layer filling at least a portion of the first trench; a first gate structure overlapping end portions of the first fin pattern; a first fin liner disposed between sidewalls of the first fin pattern and the first field insulating layer and extending along at least a portion of a bottom surface and sidewalls of the first trench; and a first insulating liner extending along sidewalls of the first gate structure and an upper surface of the first field insulating layer and contacting the first fin liner.

[0006] According to an example embodiment of the present inventive concept, a semiconductor device can include a first fin pattern and a second fin pattern separated by a trench, each of the first fin pattern and the second fin pattern extending lengthwise in a first direction; a first nanosheet on the first fin pattern; a second nanosheet on the second fin pattern; a fin liner extending along a bottom surface and a portion of sidewalls of the trench and defining a liner trench; a field insulating layer disposed on the fin liner and filling at least a portion of the trench; and a gate structure overlapping end portions of the first fin pattern. Each of the first fin pattern, the second fin pattern, the first nanosheet, and the second nanosheet can include a group IV-IV compound semiconductor or a group III-V compound semiconductor. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a plan view illustrating a semiconductor device according to an example embodiment of the present inventive concept.

[0008] Figure 2 is a cross-sectional view taken along line A-A of Figure 1 .

[0009] Figure 3 is a cross-sectional view taken along line B-B of Figure 1 .

[0010] Figure 4A , Figure 4B , Figure 4C and Figure 4D are cross-sectional views of the nanosheet of Figure 1 taken along line B-B.

[0011] Figure 5A , Figure 5B and Figure 5C are cross-sectional views of the nanosheet of Figure 1 taken along line A-A.

[0012] Figure 6 is a cross-sectional view of the nanosheet of Figure 1 taken along line A-A.

[0013] Figure 7 is a view illustrating a semiconductor device according to an example embodiment of the present inventive concept.

[0014] Figure 8 is a view illustrating a semiconductor device according to an example embodiment of the present inventive concept.

[0015] Figure 9 is a view illustrating a semiconductor device according to an example embodiment of the present inventive concept.

[0016] Figure 10 is a view illustrating a semiconductor device according to an example embodiment of the present inventive concept.

[0017] Figure 11 is a plan view showing a semiconductor device according to an example embodiment of the present inventive concept.

[0018] Figure 12 is a cross-sectional view taken along line C-C of Figure 11

[0019] Figure 13 is a plan view showing a semiconductor device according to an example embodiment of the present inventive concept.

[0020] Figure 14 is a cross-sectional view taken along line D-D of Figure 13

[0021] Figure 15 is a view for comparing a thickness of a first insulating liner in a first region I of Figure 13 with a thickness of a second insulating liner in a second region II of Figure 13

[0022] Figure 16 is a view showing a semiconductor device according to an example embodiment of the present inventive concept.

[0023] Figure 17 is a view showing a semiconductor device according to an example embodiment of the present inventive concept. DETAILED DESCRIPTION

[0024] Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are illustrated. The present inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein.

[0025] In the drawings of the semiconductor device according to example embodiments of the present inventive concept, a ring gate transistor including a nanowire shaped channel or a nanosheet shaped channel is shown, but the present inventive concept is not limited thereto. The semiconductor device according to example embodiments of the present inventive concept can include a tunnel transistor, a three-dimensional transistor, or a transistor having a fin shaped channel. The semiconductor device according to embodiments of the present inventive concept can include a bipolar junction transistor, a lateral double diffused transistor (LDMOS), or the like.

[0026] Figure 1 is a plan view showing a semiconductor device according to an example embodiment of the present inventive concept. Figure 2 is a cross-sectional view taken along line A-A of Figure 1 Figure 3 is a cross-sectional view taken along line B-B of Figure 1 Figure 4A , Figure 4B ,​​​​​Figure 4C and Figure 4D is Figure 1 a cross-sectional view taken along line B-B of the nanosheet of Figure 5A , Figure 5B , Figure 5C and Figure 6 is Figure 1 a cross-sectional view taken along line A-A of the nanosheet of. For ease of illustration, the interlayer insulating layer 190 is not shown in Figure 1

[0027] Referring to Figures 1 to 3 , a semiconductor device according to an example embodiment of the inventive concept can include a substrate 100, a first fin pattern 110, a second fin pattern 210, a first normal nanosheet 115, a first dummy nanosheet 116, a second normal nanosheet 215, a second dummy nanosheet 216, a first gate structure 120 and 120_1, a second gate structure 220 and 220_1, a first fin liner 111, and a first insulating liner 155. The semiconductor device can have a gate-all-around structure.

[0028] The substrate 100 can be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In some embodiments, the substrate 100 can include, for example, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0029] The first fin pattern 110 and the second fin pattern 210 can protrude (e.g., in a third direction Zl perpendicular to a first direction Xl and a second direction Yl) from the substrate 100. The first fin pattern 110 and the second fin pattern 210 can respectively extend lengthwise along the first direction Xl parallel to an upper surface of the substrate 100. As used herein, an article, layer, or portion of an article or layer described as extending "lengthwise" in a particular direction has a length in that particular direction and a width perpendicular to that direction, where the length is greater than the width.

[0030] For example, the first fin pattern 110 can have long sidewalls 110a extending in the first direction Xl and short sidewalls 110b extending in the second direction Yl, and the second fin pattern 210 can have long sidewalls 210a extending in the first direction Xl and short sidewalls 210b extending in the second direction Yl. The second direction Yl can be perpendicular to the first direction Xl and can be parallel to the upper surface of the substrate 100. Each of the first fin pattern 110 and the second fin pattern 210 can be defined by a fin trench 106t. For example, each of the long sidewalls 110a of the first fin pattern 110 and the long sidewalls 210a of the second fin pattern 210 can be defined by the fin trench 106t.

[0031] ​The first fin pattern 110 and the second fin pattern 210 can be aligned in a first direction X1 which is a length direction thereof, and can be spaced apart from each other in the first direction X1. For example, the first fin pattern 110 and the second fin pattern 210 can be arranged in a row in the first direction X1. The upper surfaces of the first fin pattern 110 and the second fin pattern 210 can be coplanar with each other. When referring to orientation, layout, position, shape, size, number, or other metrics, terms such as "same," "identical," "planar," "coplanar," or "uniform" as used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, number, or other metric, but are intended to encompass nearly the same orientation, layout, position, shape, size, number, or other metric within an acceptable variation that can occur, for example, due to a manufacturing process.

[0032] The short sidewall 110b of the first fin pattern 110 and the short sidewall 210b of the second fin pattern 210 can face each other. The first fin pattern 110 and the second fin pattern 210 can be separated from each other by the first fin cut trench 105t. The short sidewall 110b of the first fin pattern 110 and the short sidewall 210b of the second fin pattern 210 can be defined by the first fin cut trench 105t.

[0033] Each of the first fin pattern 110 and the second fin pattern 210 can be formed by etching a portion of the substrate 100, or can include an epitaxial layer grown from the substrate 100. Each of the first fin pattern 110 and the second fin pattern 210 can include a semiconductor material, such as silicon (Si) or germanium (Ge). In some embodiments, each of the first fin pattern 110 and the second fin pattern 210 can include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0034] The group IV-IV compound semiconductor can include a binary compound or a ternary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound doped with a group IV element. The group III-V compound semiconductor can include a binary compound, a ternary compound, or a quaternary compound, each of which is formed by a combination of a group III element (e.g., at least one of aluminum (Al), gallium (Ga), and indium (In)) and a group V element (e.g., at least one of phosphorus (P), arsenic (As), and antimony (Sb)).

[0035] The first fin pattern 110 and the second fin pattern 210 can include the same material. In some embodiments, each of the first fin pattern 110 and the second fin pattern 210 can be a silicon fin pattern including silicon.

[0036] The first fin liner 111 can extend along at least a portion of a bottom surface and sidewalls of the fin trench 106t. The first fin liner 111 can extend along at least a portion of a bottom surface and sidewalls of the first fin cut trench 105t.

[0037] In some embodiments, the first fin liner 111 can be disposed on an entire sidewall of the fin trench 106t and on an entire sidewall of the first fin cut trench 105t.

[0038] The first fin liner 111 can have a lower surface facing the first fin pattern 110 and the second fin pattern 210 and an upper surface opposite the lower surface. For example, the lower surface of the first fin liner 111 can contact the first fin pattern 110 and the second fin pattern 210, and the upper surface of the first fin liner 111 can contact the first field insulating layer 105. As the first fin liner 111 extends along surfaces of the fin trench 106t and the first fin cut trench 105t, a first liner trench 111t can be defined by the upper surface of the first fin liner 111. It will be understood that when a component is referred to as being “connected” or “coupled” to another component, it can be directly connected or coupled to the other component or it can be connected or coupled to the other component via another component. Conversely, when a component is referred to as being “directly connected,” “directly coupled,” to another component, then there is no intervening component. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). The term “contacting” as used herein, unless otherwise indicated, means directly connected (i.e., touching).

[0039] The first fin liner 111 can include, for example, silicon oxynitride, silicon nitride, and / or silicon oxide.

[0040] The first field insulating layer 105 can fill a portion of the first fin cut trench 105t. The first field insulating layer 105 can be disposed on the short sidewall 110b of the first fin pattern 110 and on the short sidewall 210b of the second fin pattern 210. The first field insulating layer 105 can not cover a portion of the sidewall of the first fin pattern 110 and a portion of the sidewall of the second fin pattern 210. In some embodiments, the first fin liner 111 can be disposed between the first field insulating layer 105 and the first fin pattern 110 and between the first field insulating layer 105 and the second fin pattern 210. For example, the first fin liner 111 can contact the short sidewall 110b of the first fin pattern 110, the short sidewall 210b of the second fin pattern 210, and the upper surface of the substrate 100, and the first field insulating layer 105 can contact the first fin liner 111.

[0041] The upper surfaces of the first fin pattern 110 and the second fin pattern 210 can be at a higher vertical level than the upper surface of the first field insulating layer 105 (e.g., in the third direction Z1) with respect to the bottom surface of the first fin cut trench 105t. For example, the upper surface of the first field insulating layer 105 can be at a lower vertical level than the upper surfaces of the first fin pattern 110 and the second fin pattern 210 (e.g., in the third direction Z1).

[0042] The first field insulating layer 105 can fill a portion of the first liner trench 111t. Since the first field insulating layer 105 fills the portion of the first liner trench 111t, the first field insulating layer 105 can not cover a portion of the first fin liner 111 that extends along the sidewall of the first fin cut trench 105t. For example, the first field insulating layer 105 can not cover an upper portion of the first fin liner 111 that is closer to the upper surfaces of the first fin pattern 110 and the second fin pattern 210.

[0043] A portion of the first fin liner 111 can protrude above the upper surface of the first field insulating layer 105 with respect to the bottom surface of the first fin cut trench 105t (e.g., in the third direction Z1).

[0044] The first fin cut trench 105t can include an exposed region 105t_E. The exposed region 105t_E of the first fin cut trench 105t can be a region that is not covered by the first field insulating layer 105. For example, the exposed region 105t_E can be exposed with respect to the first field insulating layer 105. The exposed region 105t_E of the first fin cut trench 105t can be a region that is not covered by the first gate spacer 140 and the second gate spacer 240.

[0045] The first fin liner 111 can be disposed to extend along a portion of the exposed region 105t_E of the first fin cut trench 105t. In some embodiments, the first fin liner 111 can be disposed to extend along the entire exposed region 105t_E of the first fin cut trench 105t.

[0046] The second field insulating layer 106 can fill at least a portion of the fin trench 106t. The second field insulating layer 106 can fill at least a portion of the first liner trench 111t. In some embodiments, the upper surface of the second field insulating layer 106 can be coplanar with the upper surfaces of the first fin pattern 110 and the second fin pattern 210.

[0047] The second field insulating layer 106 can be disposed on the long sidewall 110a of the first fin pattern 110 and the long sidewall 210a of the second fin pattern 210. The second field insulating layer 106 can cover the entire long sidewall 110a of the first fin pattern 110 and the entire long sidewall 210a of the second fin pattern 210, but the inventive concept is not limited thereto.

[0048] The first field insulating layer 105 and the second field insulating layer 106 can include, for example, an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof.

[0049] The first nanosheets 115 and 116 can be disposed on the substrate 100. The first nanosheets 115 and 116 can be disposed on the first fin pattern 110. The first nanosheets 115 and 116 can include a first normal nanosheet 115 and a first dummy nanosheet 116.

[0050] The first nanosheets 115 and 116 spaced apart from each other in the first direction X1 can be arranged on an upper surface of the first fin pattern 110. The first epitaxial pattern 150 can be disposed between the first nanosheets 115 and 116 spaced apart from each other in the first direction X1.

[0051] The first dummy nanosheet 116 can be disposed adjacent to the short sidewall 110b of the first fin pattern 110 (e.g., on an end of the first fin pattern 110). The first dummy nanosheet 116 can be connected to one first epitaxial pattern 150. For example, the first dummy nanosheet 116 can be disposed adjacent to one first epitaxial pattern 150 and can contact the one first epitaxial pattern 150. The first normal nanosheet 115 can be connected to two first epitaxial patterns 150 disposed at opposite sides of the first normal nanosheet 115 in the first direction X1.

[0052] The second nanosheets 215 and 216 can be disposed on the substrate 100. The second nanosheets 215 and 216 can be disposed on the second fin pattern 210. The second nanosheets 215 and 216 can include a second normal nanosheet 215 and a second dummy nanosheet 216.

[0053] The second nanosheets 215 and 216 spaced apart from each other in the first direction X1 can be arranged on an upper surface of the second fin pattern 210. The second epitaxial pattern 250 can be disposed between the second nanosheets 215 and 216 spaced apart from each other in the first direction X1.

[0054] The second dummy nanosheet 216 can be disposed adjacent to the short sidewall 210b of the second fin pattern 210 (e.g., on an end of the second fin pattern 210). The second dummy nanosheet 216 can be connected to one second epitaxial pattern 250. For example, the second dummy nanosheet 216 can be disposed adjacent to one second epitaxial pattern 250 and can contact the one second epitaxial pattern 250. The second normal nanosheet 215 can be connected to two second epitaxial patterns 250 disposed at opposite sides of the second normal nanosheet 215 in the first direction X1. For example, the second normal nanosheet 215 can be disposed between the two second epitaxial patterns 250 and can contact the two second epitaxial patterns 250.

[0055] Each of the first and second nanosheets 115 and 116 and 215 and 216 can include a plurality of nanosheets arranged sequentially in a thickness direction (e.g., the third direction Z1) of the substrate 100. The plurality of first nanosheets 115 and 116 can be arranged sequentially on the first fin pattern 110. For example, each of the plurality of first nanosheets 115 and 116 can be stacked on the first fin pattern 110 in the third direction Z1. The plurality of second nanosheets 215 and 216 can be arranged sequentially on the second fin pattern 210. For example, each of the plurality of second nanosheets 215 and 216 can be stacked on the second fin pattern 210 in the third direction Z1.

[0056] In Figure 2 and Figure 3 , it is shown that each of the first and second nanosheets 115 and 116 and 215 and 216 includes three nanosheets stacked in the thickness direction (e.g., the third direction Z1) of the substrate 100, but the inventive concept is not limited thereto. For example, the first nanosheets 115 and 116 can include one first nanosheet 115 and one first nanosheet 116, and the second nanosheets 215 and 216 can include one second nanosheet 215 and one second nanosheet 216. As another example, the first nanosheets 115 and 116 can include more than three first nanosheets 115 and more than three first nanosheets 116, and the second nanosheets 215 and 216 can include more than three second nanosheets 215 and more than three second nanosheets 216.

[0057] The first fin pattern 110 and the first nanosheets 115 and 116 can be formed by selectively etching a portion of a fin structure including the first fin pattern 110 and the first nanosheets 115 and 116. Accordingly, each of the first nanosheets 115 and 116 can have a width in the second direction Y1 equal to or less than a width of the first fin pattern 110 in the second direction Y1. A sidewall of the first dummy nanosheet 116 can be aligned with the short sidewall 110b of the first fin pattern 110. For example, the sidewall of the first dummy nanosheet 116 can be on the same plane as the short sidewall 110b of the first fin pattern 110 in the third direction Z1.

[0058] Likewise, the second fin pattern 210 and the second nanosheets 215 and 216 can have the same mutual relationship as described above with respect to the first fin pattern 110 and the first nanosheets 115 and 116.

[0059] Each of the first nanosheets 115 and 116 and the second nanosheets 215 and 216 can include a semiconductor material, such as silicon or germanium. In some embodiments, each of the first nanosheets 115 and 116 and the second nanosheets 215 and 216 can include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0060] The first nanosheets 115 and 116 can include the same material as the respective nanosheet at the same height level (e.g., vertical level in the third direction Zl) in the second nanosheets 215 and 216.

[0061] The first normal nanosheet 115 and the second normal nanosheet 215 can function as a channel region of a respective transistor included in the transistor including the first normal nanosheet 115 and the second normal nanosheet 215. The first normal nanosheet 115 included in the plurality of nanosheets stacked in the thickness direction of the substrate 100 and the second normal nanosheet 215 included in the plurality of nanosheets stacked in the thickness direction of the substrate 100 can include the same material or different materials. For example, the lowermost nanosheet among the plurality of nanosheets of the first normal nanosheet 115 adjacent to the first fin pattern 110 and the second lowermost nanosheet among the plurality of nanosheets of the first normal nanosheet 115 adjacent to the first fin pattern 110 can have the same material or different materials.

[0062] The first nanosheets 115 and 116 can include the same material or different materials as the first fin pattern 110.

[0063] Each of the first gate structures 120 and 120_1 can extend lengthwise in the second direction Yl. The first gate structures 120 and 120_1 can cross the first fin pattern 110. The first gate structures 120 and 120_1 can include a first end gate structure 120 and a first normal gate structure 120_1. The first end gate structure 120 can overlap an end of the first fin pattern 110. The first end gate structure 120 can overlap the short sidewall 110b of the first fin pattern 110. For example, the first end gate structure 120 can extend beyond the short sidewall 110b of the first fin pattern 110 in the first direction Xl.

[0064] The first gate structures 120 and 120_1 can respectively straddle the first nanosheets 115 and 116, and can be spaced apart from each other in the first direction Xl. The first normal gate structure 120_1 can surround each first normal nanosheet 115. The first end gate structure 120 can surround each first dummy nanosheet 116.

[0065] Each of the second gate structures 220 and 220_1 can extend longitudinally in the second direction Y1. Each of the second gate structures 220 and 220_1 can cross the second fin pattern 210. The second gate structures 220 and 220_1 can include a second end gate structure 220 and a second normal gate structure 220_1. The second end gate structure 220 can overlap with an end of the second fin pattern 210. The second end gate structure 220 can overlap with the short sidewall 210b of the second fin pattern 210. For example, the second end gate structure 220 can extend beyond the short sidewall 210b of the second fin pattern 210 in the negative first direction X1.

[0066] The second gate structures 220 and 220_1 can respectively straddle the second nanosheets 215 and 216, and can be spaced apart from each other in the first direction X1. The second normal gate structure 220_1 can surround each of the second normal nanosheets 215. The second end gate structure 220 can surround each of the second dummy nanosheets 216.

[0067] In some embodiments, the first end gate structure 120 and the second end gate structure 220 can contact the first fin liner 111 extending along the sidewall of the first fin cut trench 105t. For example, the first end gate structure 120 and the second end gate structure 220 can contact a top surface of the first fin liner 111.

[0068] The first end gate structure 120 and the second end gate structure 220 can be spaced apart from an upper surface of the first field insulating layer 105 in a height direction of the first fin pattern 110 and a height direction of the second fin pattern 210. For example, a lower surface of the first end gate structure 120 and a lower surface of the second end gate structure 220 can be at (e.g., in the third direction Z1) a higher vertical level than the upper surface of the first field insulating layer 105.

[0069] Between the lower surface of the first end gate structure 120 and the upper surface of the first field insulating layer 105, a portion of the first fin liner 111 can not be covered by the first field insulating layer 105. Between the lower surface of the second end gate structure 220 and the upper surface of the first field insulating layer 105, a portion of the first fin liner 111 can not be covered by the first field insulating layer 105.

[0070] In some embodiments, the first end gate structure 120 and the second end gate structure 220 can not contact the first field insulating layer 105 between the short sidewall 110b of the first fin pattern 110 and the short sidewall 210b of the second fin pattern 210, while the first end gate structure 120 and the second end gate structure 220 can contact the second field insulating layer 106 disposed on the long sidewall 110a of the first fin pattern 110 and the long sidewall 210a of the second fin pattern 210.

[0071] A distance from a center line of the first end gate structure 120 to a center line of the second end gate structure 220 can be a first distance W11. A distance between the first fin pattern 110 and the second fin pattern 210 separated by the first fin cut trench 105t can be a second distance W12. In some embodiments, the second distance W12 can be a distance between the short sidewall 110b of the first fin pattern 110 and the short sidewall 210b of the second fin pattern 210. For example, the second distance W12 can be defined based on an upper surface of the first fin pattern 110 and an upper surface of the second fin pattern 210. In some embodiments, the second distance W12 can be a distance between the first dummy nanosheet 116 and the second dummy nanosheet 216.

[0072] In some embodiments, the first distance W11 can be greater than the second distance W12. For example, a pitch between adjacent gate structures of the first gate structures 120 and 120_1 and the second gate structures 220 and 220_1 can be greater than a separation width between the first fin pattern 110 and the second fin pattern 210 adjacent to each other.

[0073] Each of the first gate structures 120 and 120_1 can include a first gate electrode 130, a first gate insulating layer 135, a first gate spacer 140, a first gate trench 140t, and a first cap pattern 145. Each of the second gate structures 220 and 220_1 can include a second gate electrode 230, a second gate insulating layer 235, a second gate spacer 240, a second gate trench 240t, and a second cap pattern 245.

[0074] Hereinafter, a description will be made with respect to the first gate structures 120 and 120_1. A description of the second gate structures 220 and 220_1 will be understood by the description of the first gate structures 120 and 120_1. For example, a description of the second gate electrode 230, the second gate insulating layer 235, the second gate spacer 240, the second gate trench 240t, and the second cap pattern 245 can be the same as that of the first gate electrode 130, the first gate insulating layer 135, the first gate spacer 140, the first gate trench 140t, and the first cap pattern 145, respectively.

[0075] The first gate spacer 140 can extend lengthwise in the second direction Y1. The first gate spacer 140 can cross the first nanosheets 115 and 116. The first gate spacer 140 can define the first gate trench 140t across the first nanosheets 115 and 116. For example, an inner sidewall of the first gate spacer 140 can define the first gate trench 140t.

[0076] The first gate spacers 140 can be disposed on opposite end portions of the first normal nanosheets 115 extending along the first direction X1, respectively. For example, the first gate spacers 140 can be disposed on opposite sides of the first normal nanosheets 115. The first gate spacers 140 can each include a through portion through which the first normal nanosheet 115 passes.

[0077] Each of the first normal nanosheets 115 can pass through the first gate spacers 140. The first gate spacers 140 can contact the entire circumferential surface of an end portion of each of the first normal nanosheets 115.

[0078] However, the first dummy nanosheets 116 can pass through one of the first gate spacers 140. The first gate spacer 140 through which the first dummy nanosheet 116 passes can contact the entire circumferential surface of one end portion of each of the first dummy nanosheets 116.

[0079] The first gate spacers 140 can be disposed between the first fin pattern 110 and the lowermost nanosheet of each of the first nanosheets 115 and 116 and between the respective nanosheets of the first nanosheets 115 and 116.

[0080] The first gate spacers 140 disposed on the end portions of the first fin pattern 110 can not contact the upper surface of the first field insulating layer 105 between the short sidewall 110b of the first fin pattern 110 and the short sidewall 210b of the second fin pattern 210.

[0081] A portion of the first fin liner 111 that is not covered by the first field insulating layer 105 can be disposed between the first gate spacer 140 and the upper surface of the first field insulating layer 105. For example, the first gate spacer 140 can be above the portion of the first fin liner 111 that is not covered by the first field insulating layer 105.

[0082] A height H11 from a bottom surface of the first fin cut trench 105t to a lower surface of the first gate spacer 140 can be greater than a height H12 from the bottom surface of the first fin cut trench 105t to an upper surface of the first field insulating layer 105. In some embodiments, the bottom surface of the first fin cut trench 105t can be on the same plane as an upper surface of the substrate 100, and the height H11 can be a distance between the upper surface of the substrate 100 and an upper surface of the first fin pattern 110 or the second fin pattern 210.

[0083] The first gate spacers 140 can include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbide nitride (SiOCN), silicon boron nitride (SiBN), silicon oxycarbide boron nitride (SiOBN), silicon oxycarbide (SiOC), or a combination thereof.

[0084] The first gate insulating layer 135 can be disposed along the circumferential surfaces of the first nanosheets 115 and 116. The first gate insulating layer 135 can surround each of the first nanosheets 115 and 116. The first gate insulating layer 135 can be disposed on the upper surface of the second field insulating layer 106 and on the first fin pattern 110. The first gate insulating layer 135 can extend along the inner surfaces of the first gate spacers 140.

[0085] The first gate insulating layer 135 can extend along the sidewalls and the bottom surface of the first gate trench 140t and along the circumferential surfaces of each of the first nanosheets 115 and 116.

[0086] An interface layer (not shown) can be disposed between the first gate insulating layer 135 and each of the first nanosheets 115 and 116 and between the first gate insulating layer 135 and the first fin pattern 110. Depending on the method of forming the interface layer, the interface layer can be formed with the same profile as the first gate insulating layer 135.

[0087] The first gate insulating layer 135 can include silicon oxide, silicon oxynitride, silicon nitride, and / or a high-k dielectric material having a higher dielectric constant than silicon oxide. The first gate insulating layer 135 can include a high-k dielectric material such as hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate.

[0088] The first gate electrode 130 can traverse the first fin pattern 110 and the first nanosheets 115 and 116. The first gate electrode 130 can surround the circumferential surfaces of each of the first nanosheets 115 and 116. The first gate electrode 130 can be disposed in the space between the first fin pattern 110 and the lowermost nanosheet of each of the first nanosheets 115 and 116. The first gate electrode 130 can be disposed between the first gate spacers 140. The first gate electrode 130 can fill a portion of the first gate trench 140t and can extend lengthwise in the second direction Y1.

[0089] The first gate electrode 130 can include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbon nitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbon nitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination thereof. The first gate electrode 130 can include a conductive metal oxide or a conductive metal oxynitride. The first gate electrode 130 can include an oxidized form of the above-mentioned materials.

[0090] The first gate electrode 130 can be formed by a replacement process or a gate-last process, but is not limited thereto.

[0091] The first cap pattern 145 can be disposed on the first gate electrode 130. The first cap pattern 145 can fill the remaining portion of the first gate trench 140t with the first gate electrode 130. In some embodiments, an upper surface of the first cap pattern 145 can be coplanar with an upper surface of the first gate spacer 140.

[0092] Although the first gate insulating layer 135 is illustrated as not being disposed between the first gate spacer 140 and the first cap pattern 145, this is for ease of explanation, and the inventive concept is not limited thereto. For example, in some embodiments, the first gate insulating layer 135 can be disposed between the first gate spacer 140 and the first cap pattern 145.

[0093] In Figure 2 In some embodiments, the first cap pattern 145 can be disposed on the upper surface of the first gate spacer 140. In some embodiments, the first cap pattern 145 can be disposed on the upper surface of the first gate electrode 130. In some embodiments, the first cap pattern 145 can be disposed on both the upper surface of the first gate spacer 140 and the upper surface of the first gate electrode 130. In some embodiments, the first cap pattern 145 can be disposed on the upper surface of the first gate spacer 140 and the upper surface of the first gate electrode 130, and can fill the remaining portion of the first gate trench 140t. In some embodiments, the first cap pattern 145 can be disposed on the upper surface of the first gate spacer 140 and the upper surface of the first gate electrode 130, and can fill the remaining portion of the first gate trench 140t and the remaining portion of the second gate trench 240t.

[0094] An upper surface of the first cap pattern 145 can be coplanar with an upper surface of the underlying interlayer insulating layer 191. The first cap pattern 145 can include a material having etch selectivity with respect to a material of the underlying interlayer insulating layer 191. The first cap pattern 145 can include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or a combination thereof.

[0095] The first epitaxial pattern 150 can be disposed between adjacent first gate structures 120 and 120_1. The first epitaxial pattern 150 can be disposed on the first fin pattern 110. The first epitaxial pattern 150 can be disposed on opposite sides of the first normal nanosheet 115. The first epitaxial pattern 150 can be disposed on one side of the first dummy nanosheet 116. For example, the first epitaxial pattern 150 can be disposed between the first normal nanosheet 115 and the first dummy nanosheet 116. The first epitaxial pattern 150 can be connected to the first nanosheets 115 and 116. For example, the first epitaxial pattern 150 can contact the first nanosheets 115 and 116.

[0096] The second epitaxial pattern 250 can be disposed between adjacent second gate structures 220 and 220_1. The second epitaxial pattern 250 can be disposed on the second fin pattern 210. The second epitaxial pattern 250 can be disposed on opposite sides of the second normal nanosheet 215. The second epitaxial pattern 250 can be disposed on one side of the second dummy nanosheet 216. For example, the second epitaxial pattern 250 can be disposed between the second normal nanosheet 215 and the second dummy nanosheet 216. The second epitaxial pattern 250 can be connected to the second nanosheets 215 and 216. For example, the second epitaxial pattern 250 can contact the second nanosheets 215 and 216.

[0097] The first epitaxial pattern 150 and the second epitaxial pattern 250 can be formed through an epitaxial growth process.

[0098] The first epitaxial pattern 150 can be included in a source / drain of a transistor that utilizes the first normal nanosheet 115 as a channel region. The second epitaxial pattern 250 can be included in a source / drain of a transistor that utilizes the second normal nanosheet 215 as a channel region.

[0099] The first and second epitaxial patterns 150 and 250 can be included in source / drain of transistors of the same conductivity type. When each of the first and second epitaxial patterns 150 and 250 is included in source / drain of a PMOS transistor, each of the first and second epitaxial patterns 150 and 250 can include a compressive stress material. The compressive stress material can be a material having a larger lattice constant than silicon. For example, the compressive stress material can be silicon germanium (SiGe). When each of the first and second epitaxial patterns 150 and 250 is included in source / drain of an NMOS transistor, each of the first and second epitaxial patterns 150 and 250 can include a tensile stress material. For example, the tensile stress material can be silicon (Si) or silicon carbide (SiC).

[0100] The first insulating liner 155 can extend along the profile of the first epitaxial pattern 150, the profile of the second epitaxial pattern 250, the outer sidewall of the first gate spacer 140, the outer sidewall of the second gate spacer 240, and the upper surface of the first field insulating layer 105. For example, the first insulating liner 155 can contact the top surface of the first and second epitaxial patterns 150 and 250, the outer sidewall of the first and second gate spacers 140 and 240, and the upper surface of the first field insulating layer 105.

[0101] The first insulating liner 155 can contact the first fin liner 111 between the first gate spacer 140 and the first field insulating layer 105 and between the second gate spacer 240 and the first field insulating layer 105. For example, the first insulating liner 155 can contact the first fin liner 111 between the first end gate structure 120 and the first field insulating layer 105 and between the second end gate structure 220 and the first field insulating layer 105.

[0102] A portion of the first insulating liner 155 can be disposed between the first gate spacer 140 and the upper surface of the first field insulating layer 105, such that the first gate spacer 140 can not contact the first field insulating layer 105. A portion of the first insulating liner 155 can be disposed between the second gate spacer 240 and the upper surface of the first field insulating layer 105, such that the second gate spacer 240 can not contact the first field insulating layer 105.

[0103] The first insulating liner 155 can be disposed along at least a portion of the exposed region 105t_E of the first fin cut trench 105t. The first insulating liner 155 can be disposed on a portion of the first liner trench 111t defined by the first fin liner 111.

[0104] The first insulating liner 155 can include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbon nitride (SiCN), silicon oxygen carbon nitride (SiOCN), or a combination thereof. The first insulating liner 155 can include a material having etch selectivity with respect to the underlying interlayer insulating layer 191.

[0105] The interlayer insulating layer 190 can be disposed on the first insulating liner 155. The interlayer insulating layer 190 can cover the outer sidewall of the first gate spacer 140 and the outer sidewall of the second gate spacer 240.

[0106] The interlayer insulating layer 190 can include a lower interlayer insulating layer 191 and an upper interlayer insulating layer 192 on the lower interlayer insulating layer 191. The lower interlayer insulating layer 191 can be disposed between adjacent gate structures of the first and second gate structures 120, 120_1, 220, and 220_1. For example, the lower interlayer insulating layer 191 can be disposed on and can contact the first insulating liner 155. The upper interlayer insulating layer 192 can be disposed on the first gate structures 120 and 120_1 and the second gate structures 220 and 220_1. The lower interlayer insulating layer 191 and the upper interlayer insulating layer 192 can include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0107] Reference will be made to Figures 4A to 4D A cross-section taken in the second direction Y1 of the example first normal nanosheet 115 will be described.

[0108] Reference will be made to Figure 4A The cross-section 115s of the first normal nanosheet 115A can be a shape formed by a combination of four straight lines 115m and four curved lines 115n. For example, the cross-section 115s of the first normal nanosheet 115A can be a quadrilateral having rounded corners. In the cross-section 115s of the first normal nanosheet 115A, the width L1 of the first normal nanosheet 115A can be different from the height L2 of the first normal nanosheet 115A. For example, the cross-section 115s of the first normal nanosheet 115A can be a rectangle having rounded corners, but is not limited thereto.

[0109] Reference will be made to Figure 4B In the cross-section 115s of the first normal nanosheet 115B, the width L1 of the first normal nanosheet 115B and the height L2 of the first normal nanosheet 115B can be the same. For example, the cross-section 115s of the first normal nanosheet 115B can be a square having rounded corners, but is not limited thereto.

[0110] Reference will be made to Figure 4CIn the cross-section 115s of the first normal nanosheet 115C, a width L11 of one of the opposite sides of the first normal nanosheet 115C can be different from a width L12 of the other of the opposite sides of the first normal nanosheet 115C. For example, the cross-section 115s of the first normal nanosheet 115C can be a trapezoid with rounded corners, but is not limited thereto.

[0111] Referring to Figure 4D , the cross-section 115s of the first normal nanosheet 115D can be a shape formed by a combination of curved lines 115n, such as a circle.

[0112] In some embodiments, the cross-section 115s of the first normal nanosheet 115 can be a shape formed by a combination of straight lines (e.g., a polygon), unlike those shown in Figures 4A to 4D . For example, the cross-section 115s of the first normal nanosheet 115 can be a shape formed by four linear segments intersecting each other (e.g., a quadrilateral without rounded corners). As another example, the cross-section 115s of the first normal nanosheet 115 can be a shape formed by three linear segments intersecting each other (e.g., a triangle).

[0113] An example cross-section of the first normal nanosheet 115 taken in the first direction Xl will be described with reference to Figures 5A to 5C .

[0114] Referring to Figure 5A , the thickness of the first normal nanosheet 115E can be substantially constant in a direction extending away from the first epitaxial pattern 150 and the first gate spacer 140 (e.g., in the first direction Xl). For example, a thickness t1_a of an end portion of the first normal nanosheet 115E adjacent to the first epitaxial pattern 150 can be equal to a thickness t1_b of a central portion of the first normal nanosheet 115E. The thickness can refer to a thickness or height measured in a direction perpendicular to a top surface of the substrate 100 (e.g., the third direction Z1).

[0115] Referring to Figure 5B , the thickness of the first normal nanosheet 115F can decrease in a direction extending away from the first epitaxial pattern 150 and the first gate spacer 140. For example, a thickness t1_a of opposite end portions of the first normal nanosheet 115F adjacent to the first epitaxial pattern 150 can be greater than a thickness t1_b of a central portion of the first normal nanosheet 115F. In some embodiments, an upper surface of the first normal nanosheet 115F can have a concave shape with respect to a top surface of the substrate 100, and a lower surface of the first normal nanosheet 115F can have a convex shape with respect to the top surface of the substrate 100.

[0116] Referring to Figure 5CThe thickness of the first normal nanosheet 115G can increase in a direction extending away from the first epi-pattern 150 and the first gate spacer 140. For example, a thickness t1_a of opposite end portions of the first normal nanosheet 115G adjacent to the first epi-pattern 150 can be less than a thickness t1_b of a central portion of the first normal nanosheet 115G. In some embodiments, an upper surface of the first normal nanosheet 115G can have a convex shape with respect to a top surface of the substrate 100, and a lower surface of the first normal nanosheet 115G can have a concave shape with respect to the top surface of the substrate 100.

[0117] In Figure 5B and Figure 5C , the thickness of the first normal nanosheet 115F and 115G can continuously vary in a direction extending away from the first epi-pattern 150 and the first gate spacer 140. For example, the thickness of the first normal nanosheet 115F can gradually and continuously decrease in a direction toward a middle of the first normal nanosheet 115F, and the thickness of the first normal nanosheet 115G can gradually and continuously increase in a direction toward a middle of the first normal nanosheet 115G.

[0118] An example cross-section of the first normal nanosheet 115H taken in the first direction X1 will be described with reference to Figure 6

[0119] The first normal nanosheet 115H can be a trimmed sheet pattern. The first normal nanosheet 115H can include a first portion 115a and a second portion 115b. The second portion 115b of the first normal nanosheet 115H can be disposed on opposite sides of the first portion 115a of the first normal nanosheet 115H. The second portion 115b of the first normal nanosheet 115H can overlap the first gate spacer 140. The first portion 115a of the first normal nanosheet 115H can overlap the first gate insulating layer 135 and the first gate electrode 130.

[0120] The thickness t1_c of the second portion 115b of the first normal nanosheet 115 can be greater than the thickness t1_d of the first portion 115a of the first normal nanosheet 115. The change from the thickness t1_c to the thickness t1_d (or vice versa) can be abrupt, such that an internal vertical sidewall can be formed in the first normal nanosheet 115H. The internal vertical sidewall can include an upper internal vertical sidewall 115c_u and a lower internal vertical sidewall 115c_l of the second portion 115b. The upper internal vertical sidewall 115c_u can connect a planar upper surface of the second portion 115b to a planar upper surface of the first portion 115a, and the lower internal vertical sidewall 115c_l can connect a planar lower surface of the second portion 115b to a planar lower surface of the first portion 115a.

[0121] With​Figure 6 As shown in the different, in some embodiments, the connecting portion between the second portion 115b of the first normal nanosheet 115H and the first portion 115a of the first normal nanosheet 115H can be rounded. Figure 6 In the drawings, although the thickness of the first portion 115a of the first normal nanosheet 115H is shown as constant regardless of its position, this is for ease of illustration, and the inventive concept is not limited thereto. For example, the thickness of the first portion 115a of the first normal nanosheet 115H can vary as shown in the different. Figure 5B Or Figure 5C as shown.

[0122] Figure 7 are views showing a semiconductor device according to an example embodiment of the inventive concept. In Figure 7 In the drawings, the main differences between the present embodiment and the embodiment of Figures 1 to 6 will be described.

[0123] Referring to Figure 7 , the semiconductor device according to an example embodiment of the inventive concept can further include a semiconductor nodule 150dN protruding from the short sidewall 110b of the first fin pattern 110 toward the second fin pattern 210.

[0124] The semiconductor nodule 150dN can also be provided on the short sidewall 210b of the second fin pattern 210. The semiconductor nodule 150dN can be formed on a region of the first fin pattern 110 and / or the second fin pattern 210 corresponding to the exposed region 105t_E of the first fin cut trench 105t.

[0125] The semiconductor nodule 150dN can be provided on the short sidewall 110b of the first fin pattern 110 between the lower surface of the first end gate structure 120 and the upper surface of the first field insulating layer 105. In addition, the semiconductor nodule 150dN can be provided on the short sidewall 210b of the second fin pattern 210 between the lower surface of the second end gate structure 220 and the upper surface of the first field insulating layer 105.

[0126] In some embodiments, the semiconductor nodule 150dN can be provided on one of the first fin pattern 110 and the second fin pattern 210.

[0127] The first fin liner 111 can be partially provided on the exposed region 105t_E of the first fin cut trench 105t. For example, the first fin liner 111 can be provided on a portion of the exposed region 105t_E of the first fin cut trench 105t, and can not be provided on the remaining portion of the exposed region 105t_E of the first fin cut trench 105t.

[0128] An exposed region 105t_E of the first fin cut trench 105t on which the first fin liner 111 is not disposed can not be covered by the first field insulating layer 105, the first gate spacer 140, and the second gate spacer 240.

[0129] The semiconductor nodules 150dN can be disposed on the short sidewalls 110b of the first fin pattern 110 and / or the short sidewalls 210b of the second fin pattern 210 that are not covered by the first fin liner 111, the first field insulating layer 105, the first gate spacer 140, and the second gate spacer 240. In some embodiments, the semiconductor nodules 150dN formed on the first fin pattern 110 can contact the upper surface of the first fin liner 111 and the lower surface of the first gate spacer 140, and the semiconductor nodules 150dN formed on the second fin pattern 210 can contact the upper surface of the first fin liner 111 and the lower surface of the second gate spacer 240.

[0130] The semiconductor nodules 150dN can include materials included in the first epitaxial pattern 150 and the second epitaxial pattern 250.

[0131] The first insulating liner 155 can extend along the profile of the semiconductor nodules 150dN. For example, the first insulating liner 155 can contact the semiconductor nodules 150dN.

[0132] As shown in FIG. 1A, the semiconductor nodules 150dN can be disposed between the first gate spacer 140 and the first fin liner 111 and between the second gate spacer 240 and the first fin liner 111, but the inventive concept is not limited thereto. Figure 7

[0133] In some embodiments, a portion of the first fin liner 111 can remain between the semiconductor nodules 150dN and the first gate spacer 140 and / or between the semiconductor nodules 150dN and the second gate spacer 240.

[0134] In some embodiments, the semiconductor nodules 150dN protruding from the first fin pattern 110 can contact the semiconductor nodules 150dN protruding from the second fin pattern 210.

[0135] Figure 8 FIG. 1A is a view showing a semiconductor device according to an example embodiment of the inventive concept. In Figure 8 the main differences between the present embodiment and the embodiment of Figures 1 to 6 will be described.

[0136] Referring to Figure 8 ​In the semiconductor device according to the example embodiment of the present inventive concept, a portion of the first gate spacer 140 and a portion of the second gate spacer 240 can be disposed along the sidewall of the first fin cut trench 105t. For example, a lower surface of the first gate spacer 140 and a lower surface of the second gate spacer 240 can be at a lower vertical level than an upper surface of the first fin pattern 110 and an upper surface of the second fin pattern 210.

[0137] The first fin liner 111 can be disposed on the short sidewall 110b of the first fin pattern 110 and the short sidewall 210b of the second fin pattern 210, defining a portion of the sidewall of the first fin cut trench 105t. The first end gate structure 120 and the second end gate structure 220 can be disposed on the short sidewall 110b of the first fin pattern 110 and the short sidewall 210b of the second fin pattern 210, respectively, defining the remaining portion of the sidewall of the first fin cut trench 105t. In some embodiments, the first gate insulating layer 135 of the first end gate structure 120 can be disposed on the short sidewall 110b of the first fin pattern 110, and the second gate insulating layer 235 of the second end gate structure 220 can be disposed on the short sidewall 210b of the second fin pattern 210. In some embodiments, the first gate insulating layer 135 can be disposed between the first gate spacer 140 and the short sidewall 110b of the first fin pattern 110, and the second gate insulating layer 235 can be disposed between the second gate spacer 240 and the short sidewall 210b of the second fin pattern 210.

[0138] The first end gate structure 120 and the second end gate structure 220 can contact the first fin liner 111 disposed along the sidewall of the first fin cut trench 105t.

[0139] Figure 9 is a view showing a semiconductor device according to an example embodiment of the present inventive concept. In Figure 9 In the present embodiment, the main differences between the present embodiment and the embodiment of Figures 1 to 6 will be described.

[0140] Referring to Figure 9 In the semiconductor device according to the example embodiment of the present inventive concept, the first insulating liner 155 can include a first lower insulating liner 155a and a first upper insulating liner 155b.

[0141] The first lower insulating liner 155a can contact the first fin liner 111 along the exposed region 105t_E of the first fin cut trench 105t. Also, the first lower insulating liner 155a can contact the upper surface of the first field insulating layer 105, the upper surfaces of the first and second epitaxial patterns 150 and 250, and the side surfaces of the first and second gate spacers 140 and 240. The first upper insulating liner 155b can be disposed on the first lower insulating liner 155a.

[0142] The first lower insulating liner 155a can include, for example, silicon oxycarbonitride (SiOCN). The first upper insulating liner 155b can include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), or a combination thereof.

[0143] Figure 10 is a view showing a semiconductor device according to an example embodiment of the present inventive concept. In Figure 10 , main differences between the present embodiment and the embodiment of Figures 1 to 6 will be described.

[0144] Referring to Figure 10 , in a semiconductor device according to an example embodiment of the present inventive concept, each of the first and second gate structures 120 and 120_1 and 220 and 220_1 can not include a cap pattern on the first and second gate electrodes 130 and 230.

[0145] In Figure 10 , because the first cap pattern (see, for example, the first cap pattern 145 of Figure 2 ) is not disposed on the first gate electrode 130 and the second cap pattern (see, for example, the second cap pattern 245 of Figure 2 ) is not disposed on the second gate electrode 230, the upper surface of the first gate electrode 130 and the upper surface of the second gate electrode 230 can be coplanar with the upper surface of the lower interlayer insulating layer 191.

[0146] Figure 11 is a plan view showing a semiconductor device according to an example embodiment of the present inventive concept. Figure 12 is a cross-sectional view taken along line C-C of Figure 11 . In Figure 11 and Figure 12 , main differences between the present embodiment and the embodiment of Figures 1 to 6 will be described.

[0147] Referring to Figure 11 and Figure 12The semiconductor device according to the example embodiment of the present inventive concept can further include a dummy gate structure 170 extending lengthwise in the second direction Y1 disposed between the first end gate structure 120 and the second end gate structure 220. An underlayer interlayer insulating layer 191 can be disposed between the first end gate structure 120 and the dummy gate structure 170 and between the second end gate structure 220 and the dummy gate structure 170.

[0148] The dummy gate structure 170 can pass between the short sidewall 110b of the first fin pattern 110 and the short sidewall 210b of the second fin pattern 210. The dummy gate structure 170 can not cross the first fin pattern 110 and the second fin pattern 210. The dummy gate structure 170 can not overlap the first fin pattern 110 and the second fin pattern 210. For example, the dummy gate structure 170 can maintain a constant distance from the short sidewall 110b of the first fin pattern 110 in the first direction X1 and maintain a constant distance from the short sidewall 210b of the second fin pattern 210 in the first direction X1.

[0149] The dummy gate structure 170 can be disposed on the first field insulating layer 105 in the first fin cut trench 105t. The dummy gate structure 170 can be disposed on an upper surface of the first field insulating layer 105. The dummy gate structure 170 can be disposed on the first field insulating layer 105 between the first fin pattern 110 and the second fin pattern 210.

[0150] The dummy gate structure 170 can contact the upper surface of the first field insulating layer 105.

[0151] Since the dummy gate structure 170 does not cross the first fin pattern 110 or the second fin pattern 210, the first fin liner 111 extending along the sidewall and the bottom surface of the first fin cut trench 105t can not contact the dummy gate structure 170.

[0152] An upper surface of a portion of the first field insulating layer 105 that is in contact with the dummy gate structure 170 can be higher than an upper surface of another portion of the first field insulating layer 105 that is in contact with the first fin liner 111 on a sidewall of the first fin cut trench 105t. The first field insulating layer 105 under the first end gate structure 120 and the second end gate structure 220 can be partially removed in a process of forming the first epitaxial pattern 150 and the second epitaxial pattern 250. Accordingly, a height of the upper surface of the first field insulating layer 105 under the dummy gate structure 170 can be greater than a height of the upper surface of the first field insulating layer 105 under the first end gate structure 120 and the second end gate structure 220 with respect to an upper surface of the substrate 100. In some embodiments, the upper surface of the first field insulating layer 105 under the dummy gate structure 170 can be at a same vertical level (e.g., in the third direction Z1) as upper surfaces of the first fin pattern 110 and the second fin pattern 210.

[0153] A distance between a centerline of the first end gate structure 120 and a centerline of the second end gate structure 220 can be a third distance W21, with the dummy gate structure 170 between the first end gate structure 120 and the second end gate structure 220. A distance between the first fin pattern 110 and the second fin pattern 210 with the dummy gate structure 170 therebetween can be a fourth distance W22. In some embodiments, the fourth distance W22 can be a distance between a short sidewall 110b of the first fin pattern 110 and a short sidewall 210b of the second fin pattern 210. As an example, the third distance W21 can be greater than the fourth distance W22.

[0154] The dummy gate structure 170 can include a dummy gate electrode 171, a dummy gate insulating layer 172, a dummy gate spacer 173, a dummy gate trench 173t, and a dummy cap pattern 174.

[0155] The dummy gate spacer 173 can extend lengthwise in the second direction Y1. The dummy gate spacer 173 can define the dummy gate trench 173t.

[0156] The dummy gate insulating layer 172 can extend along a bottom surface and sidewalls of the dummy gate trench 173t. The dummy gate insulating layer 172 can contact an upper surface of the first field insulating layer 105 under the dummy gate structure 170.

[0157] The dummy gate electrode 171 can be disposed between the dummy gate spacers 173. The dummy gate electrode 171 can be disposed on the dummy gate insulating layer 172. An upper surface of the dummy gate electrode 171 can be coplanar with an upper surface of the dummy gate insulating layer 172. The dummy gate electrode 171 can partially fill the dummy gate trench 173t.

[0158] A dummy cap pattern 174 can be disposed on the dummy gate electrode 171. The dummy cap pattern 174 can contact an upper surface of the dummy gate insulating layer 172. The dummy cap pattern 174 can fill a remaining portion of the dummy gate trench 173t with the dummy gate electrode 171. An upper surface of the dummy cap pattern 174 can be coplanar with an upper surface of the dummy gate spacer 173 and the lower interlayer insulating layer 191.

[0159] Figure 13 is a plan view showing a semiconductor device according to an example embodiment of the present inventive concept. Figure 14 is a cross-sectional view taken along Figure 13 line D-D of Figure 15 is a view for comparing a thickness of a first insulating liner in a first region I of Figure 13 and a thickness of a second insulating liner in a second region II of Figure 13 .

[0160] is a cross-sectional view taken along Figure 13 line A-A of Figure 2 , Figure 7 and Figure 8 may be substantially identical to one of the views of

[0161] In addition, the first fin pattern 110, the second fin pattern 210, the first normal nanosheet 115, the first dummy nanosheet 116, the second normal nanosheet 215, the second dummy nanosheet 216, the first gate structure 120 and 120_1, the second gate structure 220 and 220_1, the first fin liner 111, and the first insulating liner 155 as shown in the first region I of Figure 13 may be substantially identical to that described with reference to Figure 13 . Thus, the description of Figures 1 to 8 will mainly refer to what is shown in the second region II. Figures 13 to 15

[0162] Referring to Figures 13 to 15 , a semiconductor device according to an example embodiment of the present inventive concept can include a first fin pattern 110, a second fin pattern 210, a third fin pattern 310, a fourth fin pattern 410, a first normal nanosheet 115, a first dummy nanosheet 116, a second normal nanosheet 215, a second dummy nanosheet 216, a third normal nanosheet 315, a third dummy nanosheet 316, a fourth normal nanosheet 415, a fourth dummy nanosheet 416, a first gate structure 120 and 120_1, a second gate structure 220 and 220_1, a third gate structure 320 and 320_1, a fourth gate structure 420 and 420_1, a first fin liner 111, a second fin liner 311, a first insulating liner 155, and a second insulating liner 355. ​

[0163] The substrate 100 can include a first region I and a second region II. The first region I can be a PMOS region. The second region II can be an NMOS region.

[0164] Each of the first normal nanosheet 115 in the first region I and the second normal nanosheet 215 can be used as a channel region of a PMOS transistor. For example, the first normal nanosheet 115 can be used as one channel region of a PMOS transistor, and the second normal nanosheet 215 can be used as the other channel region of the PMOS transistor. Each of the third normal nanosheet 315 and the fourth normal nanosheet 415 in the second region II can be used as a channel region of an NMOS transistor. For example, the third normal nanosheet 315 can be used as one channel region of an NMOS transistor, and the fourth normal nanosheet 415 can be used as the other channel region of the NMOS transistor.

[0165] The third fin pattern 310 and the fourth fin pattern 410 can protrude (e.g., in a sixth direction Z2 perpendicular to the fourth direction X2 and the fifth direction Y2) from the substrate 100. Each of the third fin pattern 310 and the fourth fin pattern 410 can extend lengthwise in the fourth direction X2. For example, the third fin pattern 310 and the fourth fin pattern 410 can have long sidewalls 310a and 410a, respectively, extending in the fourth direction X2 and have short sidewalls 310b and 410b, respectively, extending in the fifth direction Y2. The fourth direction X2 and the fifth direction Y2 can be perpendicular to each other and can be parallel to an upper surface of the substrate 100. In some embodiments, the first direction X1, the second direction Y1, and the third direction Z1 can be the same as the fourth direction X2, the fifth direction Y2, and the sixth direction Z2, respectively. In other embodiments, the first direction X1, the second direction Y1, and the third direction Z1 can be different from the fourth direction X2, the fifth direction Y2, and the sixth direction Z2, respectively.

[0166] The third fin pattern 310 and the fourth fin pattern 410 can be arranged in the fourth direction X2 as a length direction thereof. The third fin pattern 310 can be spaced apart from the fourth fin pattern 410 in the fourth direction X2. For example, the third fin pattern 310 and the fourth fin pattern 410 can be arranged in a row in the fourth direction X2. An upper surface of the third fin pattern 310 and an upper surface of the fourth fin pattern 410 can be coplanar to each other.

[0167] The short sidewall 310b of the third fin pattern 310 can face the short sidewall 410b of the fourth fin pattern 410. The third fin pattern 310 and the fourth fin pattern 410 can be separated by the second fin cut trench 107t. The short sidewall 310b of the third fin pattern 310 and the short sidewall 410b of the fourth fin pattern 410 can be defined by the second fin cut trench 107t.

[0168] Each of the third fin pattern 310 and the fourth fin pattern 410 can be formed by etching a portion of the substrate 100, or can include an epitaxial layer grown from the substrate 100. Each of the third fin pattern 310 and the fourth fin pattern 410 can include a semiconductor material, such as silicon (Si) or germanium (Ge). In some embodiments, each of the third fin pattern 310 and the fourth fin pattern 410 can include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0169] The third fin pattern 310 and the fourth fin pattern 410 can include the same material. In some embodiments, each of the third fin pattern 310 and the fourth fin pattern 410 can be a silicon fin pattern including silicon.

[0170] The second fin liner 311 can extend along at least a portion of a bottom surface and sidewalls of the second fin cut trench 107t. In some embodiments, the second fin liner 311 can be disposed on an entire sidewall of the second fin cut trench 107t.

[0171] The second fin liner 311 can have a lower surface facing the third fin pattern 310 and the fourth fin pattern 410, and an upper surface opposite the lower surface. For example, the lower surface of the second fin liner 311 can contact the third fin pattern 310 and the fourth fin pattern 410, and the upper surface of the second fin liner 311 can contact the third field insulating layer 107. Because the second fin liner 311 extends along the surfaces of the second fin cut trench 107t, a second liner trench 311t can be defined by the upper surface of the second fin liner 311.

[0172] The second fin liner 311 can include, for example, silicon oxynitride, silicon nitride, and / or silicon oxide.

[0173] The third field insulating layer 107 can fill a portion of the second fin cut trench 107t. The third field insulating layer 107 can be disposed on the short sidewall 310b of the third fin pattern 310 and on the short sidewall 410b of the fourth fin pattern 410.

[0174] The third field insulating layer 107 can fill at least a portion of the second liner trench 311t. The third field insulating layer 107 can cover the second fin liner 311 extending along the sidewalls of the second fin cut trench 107t. In some embodiments, the second fin liner 311 can be disposed between the third field insulating layer 107 and the third fin pattern 310 and between the third field insulating layer 107 and the fourth fin pattern 410. For example, the second fin liner 311 can contact the short sidewall 310b of the third fin pattern 310, the short sidewall 410b of the fourth fin pattern 410, and an upper surface of the substrate 100, and the third field insulating layer 107 can contact the second fin liner 311.

[0175] The third nanosheets 315 and 316 can be disposed on the substrate 100. The third nanosheets 315 and 316 can be disposed on the third fin pattern 310. The third nanosheets 315 and 316 can include a third normal nanosheet 315 and a third dummy nanosheet 316.

[0176] The third epitaxial pattern 350 can be disposed between the third nanosheets 315 and 316 spaced apart from each other in the fourth direction X2. The third dummy nanosheet 316 can be connected to one third epitaxial pattern 350. For example, the third dummy nanosheet 316 can be disposed adjacent to one third epitaxial pattern 350 and can contact one third epitaxial pattern 350. The third normal nanosheet 315 can be connected to two third epitaxial patterns 350 disposed at opposite sides of the third normal nanosheet 315 in the fourth direction X2. For example, the third normal nanosheet 315 can be disposed between two third epitaxial patterns 350 and can contact the two third epitaxial patterns 350.

[0177] The fourth nanosheets 415 and 416 can be disposed on the substrate 100. The fourth nanosheets 415 and 416 can be disposed on the fourth fin pattern 410. The fourth nanosheets 415 and 416 can include a fourth normal nanosheet 415 and a fourth dummy nanosheet 416.

[0178] The fourth epitaxial pattern 450 can be disposed between the fourth nanosheets 415 and 416 spaced apart from each other in the fourth direction X2. The fourth dummy nanosheet 416 can be connected to one fourth epitaxial pattern 450. For example, the fourth dummy nanosheet 416 can be disposed adjacent to one fourth epitaxial pattern 450 and can contact one fourth epitaxial pattern 450. The fourth normal nanosheet 415 can be connected to two fourth epitaxial patterns 450 disposed at opposite sides of the fourth normal nanosheet 415 in the fourth direction X2. For example, the fourth normal nanosheet 415 can be disposed between the two fourth epitaxial patterns 450 and can contact the two fourth epitaxial patterns 450.

[0179] Each of the third nanosheets 315 and 316 and the fourth nanosheets 415 and 416 can include a semiconductor material, such as silicon or germanium. In some embodiments, each of the third nanosheets 315 and 316 and the fourth nanosheets 415 and 416 can include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0180] The third nanosheets 315 and 316 can include the same material as the respective nanosheets at the same height level in the fourth nanosheets 415 and 416.

[0181] Each of the third gate structures 320 and 320_1 can extend lengthwise in the fifth direction Y2. The third gate structures 320 and 320_1 can cross the third fin pattern 310. The third gate structures 320 and 320_1 can include a third end gate structure 320 and a third normal gate structure 320_1. The third end gate structure 320 can overlap with an end of the third fin pattern 310. The third end gate structure 320 can overlap with a short sidewall 310b of the third fin pattern 310. For example, the third end gate structure 320 can extend beyond the short sidewall 310b of the third fin pattern 310 in the fourth direction X2.

[0182] The third gate structures 320 and 320_1 can respectively straddle third nanosheets 315 and 316 spaced apart from each other in the fourth direction X2. The third normal gate structure 320_1 can surround the third normal nanosheet 315. The third end gate structure 320 can surround the third dummy nanosheet 316.

[0183] Each of the fourth gate structures 420 and 420_1 can extend in the fifth direction Y2. The fourth gate structures 420 and 420_1 can cross the fourth fin pattern 410. The fourth gate structures 420 and 420_1 can include a fourth end gate structure 420 and a fourth normal gate structure 420_1. The fourth end gate structure 420 can overlap with an end of the fourth fin pattern 410. The fourth end gate structure 420 can overlap with a short sidewall 410b of the fourth fin pattern 410. For example, the fourth end gate structure 420 can extend beyond the short sidewall 410b of the fourth fin pattern 410 in the negative fourth direction X2.

[0184] The fourth gate structures 420 and 420_1 can respectively straddle fourth nanosheets 415 and 416 spaced apart from each other in the fourth direction X2. The fourth normal gate structure 420_1 can surround the fourth normal nanosheet 415. The fourth end gate structure 420 can surround the fourth dummy nanosheet 416.

[0185] In some embodiments, the third end gate structure 320 and the fourth end gate structure 420 can contact the third field insulating layer 107 disposed between the short sidewall 310b of the third fin pattern 310 and the short sidewall 410b of the fourth fin pattern 410.

[0186] A distance from a center line of the third end gate structure 320 to a center line of the fourth end gate structure 420 can be a fifth distance W31. A distance between the third fin pattern 310 and the fourth fin pattern 410 separated by the second fin cut trench 107t can be a sixth distance W32. In some embodiments, the sixth distance W32 can be a distance between the short sidewall 310b of the third fin pattern 310 and the short sidewall 410b of the fourth fin pattern 410.

[0187] In some embodiments, the fifth distance W31 can be greater than the sixth distance W32. For example, a pitch between adjacent gate structures of the third gate structures 320 and 320_1 and the fourth gate structures 420 and 420_1 can be greater than a separation width between the third fin pattern 310 and the fourth fin pattern 410 adjacent to each other.

[0188] Each of the third gate structures 320 and 320_1 can include a third gate electrode 330, a third gate insulating layer 335, a third gate spacer 340, a third gate trench 340t, and a third cap pattern 345. Each of the fourth gate structures 420 and 420_1 can include a fourth gate electrode 430, a fourth gate insulating layer 435, a fourth gate spacer 440, a fourth gate trench 440t, and a fourth cap pattern 445.

[0189] A third epitaxial pattern 350 can be disposed between adjacent third gate structures 320 and 320_1. The third epitaxial pattern 350 can be disposed on the third fin pattern 310. A fourth epitaxial pattern 450 can be disposed between adjacent fourth gate structures 420 and 420_1. The fourth epitaxial pattern 450 can be disposed on the fourth fin pattern 410.

[0190] The second insulating liner 355 can be formed along an outline of the third epitaxial pattern 350, an outline of the fourth epitaxial pattern 450, an outer sidewall of the third gate spacer 340, an outer sidewall of the fourth gate spacer 440, and an upper surface of the third field insulating layer 107.

[0191] In some embodiments, the second insulating liner 355 can not contact the second fin liner 311. A portion of the third field insulating layer 107 can be disposed between the second insulating liner 355 and the second fin liner 311. For example, the third field insulating layer 107 can contact a lower surface of the third gate spacer 340 and a lower surface of the fourth gate spacer 440.

[0192] The second insulating liner 355 can include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiOCN), or a combination thereof. The second insulating liner 355 can include a material having etch selectivity with respect to the underlayer interlayer insulating layer 191.

[0193] Referring to Figure 15The first insulating liner 155 can have a thickness that is a distance from a lower surface of the first insulating liner 155 to an upper surface of the first insulating liner 155, and the second insulating liner 355 can have a thickness that is a distance from a lower surface of the second insulating liner 355 to an upper surface of the second insulating liner 355. In some embodiments, the thickness of the first insulating liner 155 can be the same throughout the first region I, and the thickness of the second insulating liner 355 can be the same throughout the second region II. As shown in FIG. 3, in the first region I, the thickness of the first insulating liner 155 between the first field insulating layer 105 and the underlayer interlayer insulating layer 191 can be a first thickness t11. In the second region II, the thickness of the second insulating liner 355 between the third field insulating layer 107 and the underlayer interlayer insulating layer 191 can be a second thickness t12. For example, the first thickness t11 can be greater than the second thickness t12. Figure 15

[0194] Figure 16 is a view showing a semiconductor device according to an example embodiment of the present inventive concept. Main differences between the present embodiment and the embodiment of Figures 13 to 15 will be described. Figure 16 is a view for comparing the first insulating liner in the first region I with the second insulating liner in the second region II.

[0195] Referring to Figure 16 , in a semiconductor device according to an example embodiment of the present inventive concept, the first insulating liner 155 can include a first lower insulating liner 155a and a first upper insulating liner 155b stacked sequentially on the first fin liner 111.

[0196] The material included in the second insulating liner 355 can be the same as the material included in the first upper insulating liner 155b. For example, the first upper insulating liner 155b and the second insulating liner 355 can be films formed in the same manufacturing process.

[0197] The thickness of the first insulating liner 155 can be greater than the thickness of the second insulating liner 355.

[0198] Figure 17 is a view showing a semiconductor device according to an example embodiment of the present inventive concept. In Figure 17 , main differences between the present embodiment and the embodiment of Figures 13 to 15 will be described.

[0199] Referring to Figure 17 , in a semiconductor device according to an example embodiment of the present inventive concept, the third field insulating layer 107 can not cover a portion of the second fin liner 311 extending along a sidewall of the second fin cut trench 107t. ​

[0200] A portion of the second fin liner 311 can protrude beyond the upper surface of the third field insulating layer 107 with respect to the bottom surface of the second fin cut trench 107t.

[0201] In some embodiments, the third end gate structure 320 and the fourth end gate structure 420 can not contact the third field insulating layer 107 between the short sidewall 310b of the third fin pattern 310 and the short sidewall 410b of the fourth fin pattern 410.

[0202] The second insulating liner 355 can contact the second fin liner 311 between the third gate spacer 340 and the third field insulating layer 107 and between the fourth gate spacer 440 and the third field insulating layer 107. The second insulating liner 355 can contact the second fin liner 311 between the third end gate structure 320 and the third field insulating layer 107 and between the fourth end gate structure 420 and the third field insulating layer 107.

[0203] A portion of the second insulating liner 355 can be disposed between the third gate spacer 340 and the upper surface of the third field insulating layer 107, so that the third gate spacer 340 can not contact the third field insulating layer 107. A portion of the second insulating liner 355 can be disposed between the fourth gate spacer 440 and the upper surface of the third field insulating layer 107, so that the fourth gate spacer 440 can not contact the third field insulating layer 107.

[0204] While the present concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the disclosure as defined by the following claims.

[0205] This application claims priority to Korean Patent Application No. 10-2019-0059798, filed on May 22, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor device, comprising: A first fin pattern and a second fin pattern are separated by a first groove, each of the first fin pattern and the second fin pattern extending longitudinally in a first direction; A first nanosheet disposed on the first fin pattern; A second nanosheet disposed on the second fin pattern; A third nanosheet disposed on the first fin pattern is spaced apart from the first nanosheet in the first direction; An epitaxial pattern is disposed between the first nanosheet and the third nanosheet; A first fin liner extending along at least a portion of the bottom surface and sidewalls of the first groove; A first field insulation layer is disposed on the first fin liner and fills a portion of the first trench; as well as A first gate structure that overlaps with the end of the first fin pattern and includes a first gate spacer. A portion of the first fin liner protrudes above the upper surface of the first field insulating layer relative to the bottom surface of the first trench; The first fin liner does not overlap with the extension pattern in the first direction; The height from the bottom surface of the first trench to the bottom surface of the epitaxial pattern is greater than the height from the bottom surface of the first trench to the upper surface of the first field insulating layer; as well as Wherein, the height from the bottom surface of the first trench to the lower surface of the first gate spacer is greater than the height from the bottom surface of the first trench to the upper surface of the first field insulating layer.

2. The semiconductor device according to claim 1, in, The first trench includes an exposed region between the lower surface of the first gate spacer and the upper surface of the first field insulating layer, and The first fin liner extends along at least a portion of the exposed area of ​​the first trench.

3. The semiconductor device according to claim 1, further comprising: Semiconductor nodules protruding from the sidewall of the first fin pattern toward the second fin pattern.

4. The semiconductor device according to claim 1, further comprising: An insulating liner extends along the outer wall of the first gate spacer and the upper surface of the first field insulating layer, and contacts the first fin liner.

5. The semiconductor device according to claim 4, in, The insulating liner includes a lower insulating liner and an upper insulating liner disposed on the lower insulating liner, and The lower insulating liner contacts the first fin liner.

6. The semiconductor device according to claim 1, further comprising: The third fin pattern and the fourth fin pattern are separated by the second groove and extend in the second direction; A fourth nanosheet is disposed on the third fin pattern; A fifth nanosheet is disposed on the fourth fin pattern; A second fin liner extending along a portion of the bottom surface and sidewall of the second groove; A second field insulation layer is disposed on the second fin liner and fills a portion of the second trench; as well as A second gate structure that overlaps with the end of the third fin pattern and includes a second gate spacer. The second gate structure contacts the upper surface of the second field insulating layer.

7. The semiconductor device according to claim 6, in, The first fin pattern and the second fin pattern are disposed in the PMOS region, and The third fin pattern and the fourth fin pattern are disposed in the NMOS region.

8. The semiconductor device according to claim 6, further comprising: A first insulating liner extending along the outer wall of the first gate spacer and the upper surface of the first field insulating layer; as well as A second insulating liner extending along the outer wall of the second gate spacer and the upper surface of the second field insulating layer. The thickness of the first insulating liner is greater than the thickness of the second insulating liner.

9. The semiconductor device according to claim 1, wherein, The first gate structure is spaced apart from the upper surface of the first field insulating layer.

10. A semiconductor device, comprising: A first fin pattern and a second fin pattern are separated by a first groove, each of the first fin pattern and the second fin pattern extending longitudinally in a first direction; A first nanosheet disposed on the first fin pattern; A second nanosheet disposed on the second fin pattern; A third nanosheet disposed on the first fin pattern is spaced apart from the first nanosheet in the first direction; An epitaxial pattern is disposed between the first nanosheet and the third nanosheet; A first field insulating layer that fills at least a portion of the first trench; A first gate structure that overlaps with the end of the first fin pattern and includes gate spacers; A first fin liner is disposed between the sidewall of the first fin pattern and the first field insulating layer, and extends along at least a portion of the bottom surface and sidewall of the first groove. as well as A first insulating liner extends along the outer sidewall of the first gate structure and the upper surface of the first field insulating layer, and contacts the first fin liner. The first fin liner does not overlap with the extension pattern in the first direction; The height from the bottom surface of the first trench to the bottom surface of the epitaxial pattern is greater than the height from the bottom surface of the first trench to the upper surface of the first field insulating layer.

11. The semiconductor device according to claim 10, wherein, The first gate structure is spaced apart from the upper surface of the first field insulating layer.

12. The semiconductor device according to claim 10, further comprising: A semiconductor junction protrudes from the sidewall of the first fin pattern and is disposed between the lower surface of the first gate structure and the upper surface of the first field insulating layer.

13. The semiconductor device according to claim 10, further comprising: A second gate structure is disposed on and in contact with the first field insulating layer.

14. The semiconductor device according to claim 10, in, The sidewalls of the first fin pattern include long sidewalls extending in the first direction and short sidewalls extending in a second direction different from the first direction. Wherein, the short sidewall of the first fin pattern is defined by the first groove, and The first gate structure does not contact the first field insulating layer.

15. The semiconductor device of claim 14, further comprising: A second field insulating layer is disposed on the long sidewall of the first fin pattern. The first gate structure contacts the second field insulating layer.

16. The semiconductor device of claim 10, further comprising: The third fin pattern and the fourth fin pattern are separated by the second groove and extend in the second direction; A fourth nanosheet is disposed on the third fin pattern; A fifth nanosheet is disposed on the fourth fin pattern; A second fin liner extending along a portion of the bottom surface and sidewall of the second groove; A second insulating layer is disposed on the second fin liner and fills at least a portion of the second trench; The second gate structure overlaps with the end of the third fin pattern and includes a second gate spacer; as well as The second insulating liner extends along the sidewall of the second gate structure and the upper surface of the second field insulating layer. The second insulating liner is spaced apart from the second fin liner.

17. The semiconductor device according to claim 16, wherein, The thickness of the first insulating liner is greater than the thickness of the second insulating liner.

18. A semiconductor device, comprising: A first fin pattern and a second fin pattern separated by grooves, each of the first fin pattern and the second fin pattern extending longitudinally in a first direction; A first nanosheet disposed on the first fin pattern; A second nanosheet disposed on the second fin pattern; A third nanosheet disposed on the first fin pattern is spaced apart from the first nanosheet in the first direction; An epitaxial pattern is disposed between the first nanosheet and the third nanosheet; A fin liner extends along a portion of the bottom surface and sidewalls of the groove and defines the liner groove; A field insulation layer is disposed on the fin liner and fills at least a portion of the trench; as well as The gate structure overlapping the end of the first fin pattern. A portion of the fin liner protrudes above the upper surface of the field insulating layer relative to the bottom surface of the trench; The fin liner does not overlap with the epitaxial pattern in the first direction; The height from the bottom surface of the trench to the bottom surface of the epitaxial pattern is greater than the height from the bottom surface of the trench to the upper surface of the field insulating layer; as well as Each of the first fin pattern, the second fin pattern, the first nanosheet, and the second nanosheet comprises a group IV-IV compound semiconductor or a group III-V compound semiconductor.

19. The semiconductor device of claim 18, further comprising: An insulating liner extends along the sidewalls of the gate structure and the upper surface of the field insulating layer, and contacts the fin liner.

Images