Power supply

Abstract

Embodiments of the present disclosure relate to power supply devices. The present disclosure relates to a device, comprising: a voltage converter, providing a second DC voltage at an output terminal of the converter from a first DC voltage, the second DC voltage having a current value determined by a third voltage at a control terminal of the converter; a circuit, configured to: when a set point value of the second voltage switches from a first set point value to a second set point value less than the first value, generate a ramp signal, the ramp signal sequentially representing a first value, a plurality of decreasing intermediate values ​​between the first value and the second value, and a second value; and an amplifier, providing a first signal, the first signal representing a difference between the ramp signal and a signal representing the current value of the second voltage, the third voltage being determined by the first signal.

Description

Technical Field

[0001] The present disclosure generally relates to a device for providing power supply power from a power source to a load. The present application more specifically relates to a power supply interface connected between a power source and a USB-C type connector, which is intended to be electrically coupled (particularly via a USB-C type cable) to a load to be powered. Background Art

[0002] Although wireless connectivity is currently one of the main research directions in the field of power and data exchange, cables still seem to be the most reliable way to connect multiple electronic devices, whether it is to exchange data or to power or charge one or more electronic devices.

[0003] Among the different types of cables and connectors of the USB standard, the USB-C type is one of the types that enable the exchange of data and power. USB-PD technology (PD stands for "power delivery") is a technology applicable to USB-C type cables and connectors. This technology enables the management of power supply to electronic devices. Summary of the invention

[0004] It would be desirable to be able to at least partially improve certain aspects of an apparatus for providing supplied power from a power source to a load via a cable, particularly via a USB-C cable adapted for USB-PD technology.

[0005] Embodiments overcome all or part of the disadvantages of known devices for providing supply power from a power source to a load.

[0006] One embodiment provides a device, comprising:

[0007] - a voltage converter configured to provide, from the first DC voltage, a second DC voltage at an output terminal of the converter, the second DC voltage having a current value determined by a third voltage at a control terminal of the converter;

[0008] - a circuit configured to: when the set point value of the second voltage switches from the first set point value to a second set point value less than the first value, generate a first ramp signal, the first ramp signal sequentially representing the first set point value, a plurality of decreasing intermediate values ​​between the first set point value and the second set point value, and the second set point value; and

[0009] - an error amplifier configured to provide a second signal representing a difference between the first signal and a third signal representing a present value of a second voltage, the third voltage being determined by the second signal.

[0010] According to one embodiment, the first set point value and the second set point value are selected from a set of predefined set point values.

[0011] According to one embodiment, the first set point value is smaller than a predefined set point value selected from a set of predefined set point values, the first set point value being determined from the selected predefined set point values, and the second set point value being selected from the above set.

[0012] According to one embodiment, the first set point value is also determined from a difference between the current available at the output terminals of the converter and a predefined maximum current.

[0013] According to one embodiment, the circuit is configured such that: when the set point value of the second voltage is switched from the first set point value to the second set point value,

[0014] - storing a fourth signal representative of the first set point value;

[0015] - generating a fifth ramp signal which sequentially represents the selected predefined set point value, a plurality of decreasing intermediate values ​​between the selected predefined set point value and the second set point value, and the second set point value; and

[0016] - generating a first signal, the first signal being equal to the fourth signal until the fifth signal is equal to the fourth signal, and at this time the first signal is equal to the fifth signal.

[0017] According to one embodiment, the circuit includes a comparator configured to provide a sixth signal representing a comparison of the fourth signal and the fifth signal.

[0018] According to one embodiment, the circuit is configured to determine the first signal from the fourth signal, the fifth signal and the sixth signal.

[0019] According to one embodiment:

[0020] a voltage-dividing bridge is connected between the output terminal of the converter and the node for applying the reference potential, the intermediate node of the bridge being connected to the control terminal of the converter; and

[0021] A transistor is connected between the intermediate node of the bridge and the node for applying the reference potential, the control terminal of the transistor being configured to receive the second signal.

[0022] According to one embodiment, the circuit comprises a control unit and a digital-to-analog converter.

[0023] According to one embodiment, the control unit is configured to: when the set point value of the second voltage switches from the first set point value to the second set point value, provide binary control codes to the analog-to-digital converter in sequence, the codes representing the first set point value, the above-mentioned decreasing intermediate value and the second set point value respectively, and the first signal is available at the output terminal of the digital-to-analog converter.

[0024] According to one embodiment, the control unit is configured to: when the set point value of the second voltage switches from the first set point value to the second set point value, provide binary control codes in sequence to the analog-to-digital converter, the above codes respectively representing the above selected predefined set point value, the above multiple decreasing intermediate values ​​between the selected predefined set point value and the second set point value, and the second set point value, and a fifth signal is available at the output terminal of the digital-to-analog converter.

[0025] According to one embodiment:

[0026] - an output terminal of the digital-to-analog converter is coupled to a first internal node via a first switch;

[0027] - a capacitor is connected to the first internal node; and

[0028] - the fourth signal is available at a second internal node, the second internal node being coupled via a second switch to the first internal node, at which the first signal is available.

[0029] According to one embodiment, the control circuit is configured to:

[0030] - when the set point value of the second voltage switches from the first set point value to the second set point value, turning off the second switch; and

[0031] - When the fifth signal becomes equal to the fourth signal, the first switch is turned on.

[0032] A further embodiment provides a connection interface between a power source and a USB-C connector, the interface comprising the described device, wherein a first voltage is provided by the power source and a second voltage is intended to power the load when the load is coupled to the USB-C connector.

[0033] A further embodiment provides a method of controlling a voltage converter that provides a second DC voltage from a first DC voltage, the second DC voltage having a current value determined by a third voltage, the method comprising: when a set point value of the second voltage switches from a first set point value to a second set point value that is less than the first set point value, performing the following steps:

[0034] - generating, by means of a circuit, a first ramp signal which sequentially represents a first set point value, a plurality of decreasing intermediate values ​​ranging from the first set point value to a second set point value, and the second set point value;

[0035] - providing, by means of the error amplifier, a second signal representing the difference between the first signal and a third signal, the third signal representing the current value of the second voltage; and

[0036] - determining a third voltage from the second signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings, in which:

[0038] Figure 1 is a simplified diagram illustrating the connections between a power source and an electronic device;

[0039] Figure 2 This diagram is used to Figure 1 A simplified diagram of one embodiment of an electronic device for providing power to an electronic device;

[0040] Figure 3 Shown in detail Figure 2 an embodiment of a portion of a power supply device; and

[0041] Figure 4 Shown in detail Figure 2 An alternative embodiment of a portion of a power supply device. DETAILED DESCRIPTION

[0042] In different drawings, the same elements are indicated by the same reference numerals. In particular, structural and / or functional elements common to different embodiments may be designated by the same reference numerals and may have the same structure, size and material properties.

[0043] For the sake of clarity, only those steps and elements that are useful for understanding the described embodiments are shown and described in detail. In particular, the management of the negotiation phase related to the supply power to be provided from the power source to the load is not described in detail. Moreover, only the relevant aspects of the USB-C and USB-PD technologies are described, other aspects can be adapted without modification. In particular, the functionality of data exchange via a connector and possibly via a USB-C type cable (preferably suitable for USB-PD technology) is not described, the described embodiments being compatible with the conventional data exchange functionality of USB-C and USB-PD technologies.

[0044] Throughout this disclosure, the term “connected” is used to designate a direct electrical connection between circuit elements without intervening elements other than conductors, while the term “coupled” is used to designate an electrical connection between circuit elements, either directly or via one or more intervening elements.

[0045] In the following description, when referring to terms defining absolute positions (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or relative positions (such as terms "above", "below", "upper", "lower", etc.), or referring to terms defining directions (such as terms "horizontal", "vertical", etc.), unless otherwise specified, this refers to the orientation of the drawings.

[0046] The terms "about," "substantially," and "approximately" are used herein to mean plus or minus 10%, preferably plus or minus 5%, of the value in question.

[0047] Figure 1 1 is a simplified diagram illustrating power transmission between an electronic device 200 having a power supply (SOURCE) role and an electrical device 400 to be powered having a load (SINK) role. The device 200 and the device 400 are connected via a USB-C type cable C, which in this example is adapted for USB-PD or USB "power delivery" technology.

[0048] The device 200 includes a power supply 201. The power supply 201 is, for example, a mains power supply or a DC power supply. In the following description, it is considered that the device 200 includes the DC power supply 201, and the device 200 is, for example, a computer, a portable battery, etc., or any other electronic device capable of powering the device and / or charging the battery.

[0049] The cable C comprises, at each of its ends, a connector C1 , C2 of the USB-C type, which in this example is adapted for USB-PD technology. The connectors C1 , C2 are generally identical.

[0050] The source device 200 comprises a connection element 210 comprising a connection interface 214 and a connector 212. The interface 214 couples the source 201 to the connector 212. The connector 212 is configured to cooperate with the connector C1 of the cable C.

[0051] Similarly, the load device 400 includes a connection element 410 including a connection interface 414 and a connector 412. The connection interface 414 couples the connector 412 to the load circuit device 401. The connector 412 is configured to cooperate with the connector C2 of the cable C.

[0052] The interfaces 214, 414 are generally identical. Connecting the interfaces 214, 414 enables the power provided by the power source 201 to be adapted according to the power used by the load circuit device 401 of the load 400. More specifically, in the following description, the connections 214, 414 enable the power provided by the power source 201 to be adapted according to the set point of the supply power used by the load circuit device 401 of the load device 400, in particular in the case where the USB-PD technology is implemented. To this end, the interface 214 includes a power converter (not shown). Figure 1 ), preferably a DC / DC voltage converter, which is controlled to adapt the power provided to the load 400 from the power supply 201.

[0053] In a connection managed by the USB-PD technology, communication is established between the device 200 and the device 400 to determine the power supply for the device 400 to be powered and / or charged. More specifically, the device 400 may indicate the minimum power for its operation, for example, via its interface 414, and the device 200 indicates the power level it can provide, for example, via its interface 214. Then, the negotiation managed by the USB-PD technology in this example begins to define the power that the device 200 will provide to the device 400. After the negotiation is completed, the connection interface 214 adapts the power supply of the power supply 201 according to the result of the negotiation, and then starts the power supply for the device 400. Then, the voltage converter of the interface 214 is controlled according to the result of the negotiation, so as to adapt the power of the power supply 201 to the negotiated power, for example, by adapting the voltage delivered by the converter according to the negotiated power.

[0054] Preferably, the negotiated power supply is selected from a list of predefined power supply levels. The list is recorded, for example, in the interface 214. Preferably, the list is defined by a standard. Each predefined power supply level can be characterized by a plurality of values, in particular by a predefined value of voltage, and may be characterized by a predefined minimum value of current corresponding to the predefined power. In USB-PD technology, each set of values ​​representing a predefined power supply level in the list corresponds to an information set specified by the initials PDO ("Power Data Object"), wherein such a PDO information set can be transmitted between the device 200 and the device 400, and the PDO information set is applicable to the USB-PD technology to define which predefined power levels the device 200 should deliver to the load 400 during negotiation.

[0055] In the following description, a case is considered where the set point value of the voltage delivered by the converter of the interface 214 decreases. Such a decrease in the set point value of the voltage delivered by the converter may be specifically caused by: a renegotiation of the power that the device 200 can provide to the load, a disconnection of the cable C, or a reset of the interface after a fault in the operation of the interface is detected. As an example, after the disconnection of the cable C or the reset of the interface, the set point value of the voltage delivered by the converter will change to a default value, such as 5V.

[0056] In the following description, it is considered that the interface 214 includes an error amplifier having its output signal or voltage, which represents the difference between the signal or voltage (representing the set point value of the voltage delivered by the converter) and the effectively available voltage at the converter output. It is also considered that the converter is controlled by a control signal or voltage that depends on the output signal of the amplifier, that is, controlled by a control signal or voltage determined by the output signal of the amplifier. In this case, when the set point value of the converter output voltage is switched from a first set point value to a second smaller set point value, this may cause an undesirable change in the converter control signal. Such an undesirable change in the control signal may cause degradation, damage or failure of the converter.

[0057] As an example, such a variation may occur when the control voltage of the converter is available at an intermediate node of a voltage-dividing bridge (preferably resistive) connected between the converter output and a node for application of a reference potential, and a transistor controlled by the output voltage of the error amplifier is connected between the intermediate node and the node for application of the reference potential. Indeed, when the setpoint value of the converter output voltage switches from a first setpoint value to a second, smaller setpoint value, the error amplifier may saturate and cause a blocking of the transistor, which results in an overvoltage on the control terminal of the converter receiving the control voltage.

[0058] In order to suppress undesirable changes in the converter control signal, when the set point value of the output voltage of the converter switches from a first set point value to a second set point value, the inventors herein provide a signal representing the set point value of the output voltage of the converter, which signal does not abruptly switch directly from a first state representing the first set point value to a second state representing the second set point value. More specifically, the inventors provide an embodiment of the interface, wherein when the set point value of the output voltage of the converter switches from the first set point value to the second set point value, the signal or voltage representing such set point value is a ramp (such as a step) that sequentially represents a plurality of intermediate decreasing values ​​between the first set point value and the second set point value of the output voltage of the converter.

[0059] Figure 2 is a diagram for Figure 1 Power supply 201 Figure 1 The electronic device 400 is a simplified diagram of an embodiment of an electronic device that provides power to the electronic device. More specifically, Figure 2 An embodiment of the circuit of the USB-C type connection interface 214 is schematically shown. In this example, the USB-C type connection interface 214 is suitable for the USB-PD technology, wherein the interface 414 may be the same as the interface 214 .

[0060] The interface 214 comprises at least two input terminals 2141, 2142 connected to a power source 201 (not shown). A DC voltage Vsource of the power source 201 is applied between the terminals 2141 and 2142, the voltage Vsource being referenced relative to a reference potential (typically ground GND) on the terminal 2142. The interface 214 also comprises a first output terminal 2143 providing a DC supply voltage Vbus, the DC supply voltage Vbus being referenced relative to a second output terminal 2144 at a potential GND. The interface also comprises at least one communication terminal. These output and communication terminals are intended to be coupled to corresponding connectors 212 (not shown), which then allow, for example, connection to the device 400 via connector C1, cable C and connector C2, as Figure 1 In this embodiment, the interface 214 includes two communication terminals CC1, CC2. The advantage of having two communication terminals is that, with the terminals symmetrically positioned on the connector 212, this enables the manufacture of a reversible connector C1, i.e., for example, a rectangular connector C1 that can be coupled to the connector 212 in a first direction and in a second direction opposite to the first direction.

[0061] The interface 214 includes a voltage converter (CONV) 12 , a switch SW and a control unit or circuit (M) 14 .

[0062] In this example, the converter 12 is a DC / DC voltage converter capable of converting a DC voltage Vsource into a DC voltage Vsrc. The converter 12 includes:

[0063] an input terminal 1201 intended to receive a voltage Vsource, the terminal 1201 being coupled (preferably connected) to the terminal 2141 ;

[0064] an input terminal 1202 intended to receive a reference potential, the terminal 1202 being coupled (preferably connected) to the terminal 2142 ;

[0065] an output terminal 1203 providing a converted or adapted voltage Vsrc, the terminal 1203 being coupled to the terminal 2143 ; and

[0066] A control terminal 1204 receiving a control or feedback signal Vfb corresponding to the voltage between the terminal 1204 and the terminal 1202 in this example.

[0067] The switch SW has one of its terminals coupled to the terminal 1203 of the converter 12 and its other terminal coupled (preferably connected) to the output terminal 2143 providing the voltage Vbus. In this embodiment, the switch SW is controlled by the control unit 14 and more specifically by a control signal provided by the terminal 1400 of the unit 14. When the switch SW is open, the output terminal 1203 of the converter is electrically isolated from the output terminal 2143 of the interface, or in other words, the converter 12 is electrically isolated from a possible load 400 coupled to the interface 214.

[0068] The unit 14 comprises one or more communication terminals, which are coupled (preferably connected) to the communication terminal(s) CC1, CC2 of the interface 214. In this example, the unit 14 comprises two terminals 1403, 1404, which are connected to respective terminals CC1 and CC2.

[0069] In this embodiment, the control unit 14 is powered by the voltage Vsrc and comprises a terminal 1401 coupled (preferably connected) to the terminal 1203 of the converter 12 and comprises a terminal 1402 coupled (preferably connected) to the potential GND (terminals 2142 and 2144).

[0070] The unit 14 is configured to observe the value of the voltage Vsrc provided by the converter 12 , receiving the voltage Vsrc at its terminal 1401 in this example.

[0071] According to one embodiment, the unit 14 is configured to observe the current provided by the converter. More specifically, in this example, the interface 214 includes a resistor Rsense connected between the terminal 1203 of the converter 12 and a node 2145 connected to the switch SW, which is then coupled (preferably, connected) to the terminal 1405 of the unit 14.

[0072] Unit 14 includes processing circuitry 1406 (ctrl), for example, including a state machine, a microprocessor, a programmable logic circuit, or the like.

[0073] The circuit 1406 is configured to select a predefined power from a list of predefined supply powers.

[0074] The circuit 1406 is also configured to provide a control signal for the switch SW.

[0075] Circuit 1406 is also configured to provide a signal Vref representing a set point value of voltage Vsrc

[0076] (eg, voltage), the set point value being determined, for example, in part by the selected predefined power. The voltage Vref is available at a terminal 14060 of the circuit 1406.

[0077] The unit 14 also includes an error amplifier 1407, whose feedback loop is not shown. The error amplifier 1407 is configured to provide a signal Verr (here, a voltage) representing the difference between the value of the voltage Vsrc and its set point value. The signal Verr is provided to the output terminal 1408 of the circuit 14.

[0078] More specifically, according to the illustrated embodiment, amplifier 1407 is configured to provide a voltage Verr, which is equal to the difference between voltage Vscr' (representing the current value of voltage Vscr) and voltage Vref (representing the set point value of voltage Vsrc). Thus, an input terminal of amplifier 1407 is coupled (preferably connected) to terminal 14060 of circuit 1406, the other input terminal of amplifier 1407 receives voltage Vsrc', and an output terminal of amplifier 1407 provides voltage Verr. Voltage Verr is available at output terminal 1408 of cell 14.

[0079] In this example, the voltage Vsrc' varies like the voltage Vsrc, that is, when the voltage Vsrc increases or decreases, the voltage Vsrc' increases or decreases, respectively. In addition, the voltage Vref varies like the set point value it represents, that is, when the set point value of the voltage Vsrc increases or decreases, respectively, the voltage Vref increases or decreases, respectively.

[0080] In this example, voltage Vref is applied to the non-inverting terminal or input (+) of error amplifier 1407, and voltage Vsrc' is applied to the inverting terminal or input (-) of error amplifier 1407. Therefore, when voltage Vref decreases faster than voltage Vsrc', voltage Verr decreases.

[0081] As described above, the control voltage Vfb of the converter 12 depends on the voltage Verr, or in other words, it is determined by the voltage Verr. The voltage Vfb also depends on the value of the voltage Vsrc provided by the converter 12.

[0082] More specifically, in this embodiment, the interface 214 includes a feedback control circuit 16, and the feedback control circuit 16 includes a voltage divider bridge 13 (in Figure 2 The dotted line in FIG. 1 shows a resistive voltage divider bridge (in this example) and a transistor 15 (preferably a MOS transistor). The voltage divider bridge 13 is connected between the terminal 1203 of the converter 12 and the application node (terminals 2142 and 2144) of the reference potential GND. The intermediate node 1301 of the bridge 13 is connected to the terminal 1204 of the converter 12. The voltage Vfb is available at the node 1301.

[0083] In this example, the bridge 13 includes two resistors R1 and R2 connected in series between the terminal 1203 and the terminal 2142. The resistor R1 is connected to the terminal 1203, the resistor R2 is connected to the terminal 2142, and the node 1301 corresponds to a connection node between the resistors R1 and R2.

[0084] The transistor 15 is connected between the node 1301 and a node at the reference potential GND (terminals 2141 and 2144). The control terminal of the transistor 15 receives the signal Verr and is thus coupled (preferably connected) to the terminal 1408 of the cell 14. In this example, the transistor 15 has an N channel, a source thereof is coupled (preferably connected) to the application node of the potential GND, and a drain thereof is coupled (preferably connected) to the node 1301.

[0085] Although not in Figure 2 12 , but the converter comprises an output capacitor between its terminals 1203 and 1202, across which the voltage Vsrc is available. The output capacitor of the converter 12 and possible other components of the converter 12 (such as an inductor, other capacitors and / or one of the resistors) may be arranged outside the converter 12, arranged in the interface 214.

[0086] The operation of interface 214 will now be described.

[0087] After the negotiation or renegotiation phase, a predefined power has been selected in the list of predefined supplied powers. The selected predefined power determines the set point value of the voltage Vsrc. The circuit 1406 then provides a signal Vref representing the set point value.

[0088] When the value of voltage Vsrc is constant and equal to its set point value, the difference between voltage Vsrc' and Vref is constant, whereby voltage Verr has a constant non-zero value. Transistor 15 then draws a substantially constant non-zero current from node 1301. The value of voltage Vfb is therefore constant and is imposed by the value of voltage Vsrc, and therefore by the converter. More specifically, the constant value of voltage Vfb is determined by the value of voltage Vsrc, by the value of the current drawn by transistor 15, and by the values ​​of resistors R1, R2 of bridge 13.

[0089] When the value of voltage Vsrc moves away from its set point value, e.g. increases relative to the set point value, this causes a corresponding change in voltage Vsrc' and, therefore, a corresponding change in the difference between voltages Vscr' and Vref. The value of voltage Verr is correspondingly modified, whereby the current drawn from node 1301 and, therefore, voltage Vfb is modified. This modification of voltage Vfb controls converter 12 to bring the value of voltage Vsrc back to its set point value.

[0090] When the interface 214 operates in, for example, a stable state, it is considered that: the cable C ( Figure 1 ), a renegotiation of the voltage provided by the device 200 to the load 400 towards a lower value, or a reset of the interface 214. More generally, it is considered that the set point value of the voltage Vsrc is switched from a first set point value Vsrc1 (e.g., selected in a list or a set of predefined set point values) to a second set point value Vsrc2 (e.g., selected in a set of predefined set point values) which is less than the value Vsrc1.

[0091] In this embodiment, instead of abruptly switching the voltage Vref from a first value Vref1 representing a set point value Vsrc1 to a second value Vref2 representing a set point value Vsrc2, the circuit 1406 is configured to provide a voltage ramp Vref, which in this example decreases between the values ​​Vref1 and Vref2. The circuit 1406 then operates as a ramp generator. Thus, the voltage Vref successively represents the set point value Vsrc1, a plurality of decreasing intermediate values, and the set point value Vsrc2, the intermediate values ​​being between the set point values ​​Vsrc1 and Vsrc2. The lack of abrupt changes in the voltage Vref enables to ensure that the error amplifier operates in the regulation mode when the set point value of the voltage Vsrc changes, i.e., the error amplifier is not saturated. As long as the amplifier 1407 operates in the regulation mode, the voltage Vref is non-zero, and the transistor 15 continues to draw current from the node 1301, and then the voltage Vfb is constant when the voltage Vsrc is constant and equal to its set point value.

[0092] In the absence of such a voltage ramp Vref, i.e. if the circuit 1406 switches the voltage Vref from the value Vref1 to the value Vref2 in an all or nothing manner, the amplifier 1407 will no longer operate in the regulation mode and its output voltage Verr will become zero. A zero voltage Verr would cause the transistor 15 to switch off, resulting in a voltage peak or overvoltage on the control voltage Vfb of the converter 12. Such an overvoltage on the terminal 1204 should be avoided, since it may cause a malfunction of the converter 12, for example, because the voltage Vfb exceeds a threshold value, beyond which the converter 12 enters the configuration phase. Such an overvoltage on the terminal 1204 may even cause a degradation of the converter 12, or even damage it.

[0093] Preferably, when the set point value of the voltage Vsrc changes from the value Vsrc1 to the value Vscr2 lower than the value Vscr1, the unit 14 (e.g., the circuit 1406) is configured to turn off the switch SW and turn on another switch (not shown), so as to enable the voltage Vsrc to be discharged to the ground GND through the discharge resistor (not shown) to reduce the value of the voltage Vsrc. In fact, the voltage Vsrc corresponds to the voltage across the filter or output capacitor (not shown) of the converter 12. Therefore, the voltage Vsrc is discharged at a speed regulated by the value R of the discharge resistor and the value C of the output capacitor of the converter 12. Based on the above functional indications, and in particular based on a time constant equal to the product of the values ​​R and C, it is within the capabilities of a person skilled in the art to determine the maximum slope of the voltage Vref between the values ​​Vref1 and Vref2 to ensure that the amplifier 1407 operates in the regulation mode for the entire ramp duration. Preferably, the slope of the ramp of the voltage Vref between the values ​​Vref1 and Vref2 is determined from the time constant RC to avoid exceeding the slope of the voltage Vsrc' in absolute value.

[0094] Figure 3 In more detail, the Figure 2 More specifically, in Figure 3 , only a portion of the unit 14 is shown.

[0095] In this embodiment, a voltage Vsrc′ representing the value of the voltage Vsrc is available at a node 1409 of the connection between two resistors R3 and R4 connected in series between the terminals 1401 and 1402 of the cell 14 .

[0096] Furthermore, according to one embodiment, the unit 14 comprises an amplifier 1410 having its input terminals connected to the terminals 1401 and 1405 of the unit 14, respectively, and ... Figure 2 , and more specifically an output terminal of a signal MesI of a current provided by terminal 1203 of converter 12. Signal MesI is provided to terminal 14061 of circuit 1406. As a variant, amplifier 1410 may be omitted.

[0097] Circuit 1410 may include other input terminals, which are intended to be coupled to a temperature sensor to detect faults in interface operation, to be coupled to terminal 1401 to receive voltage Vsrc, to be coupled to power supply circuit 1406, etc. (shown herein in the form of a single terminal 14062).

[0098] According to one embodiment, circuit 1406 includes a terminal 14063 connected to terminal 1400 of cell 14 to provide a switch SW ( Figure 2 ) control signal.

[0099] In the illustrated embodiment, the circuit 1406 comprises a control circuit or unit 14064. The circuit 14064 comprises in particular a state machine. As an example, the circuit 14064 implements the steps of negotiation for the supply power, and then the circuit 14064 is coupled to the terminals 1403 and 1404 ( Figure 2 ). In this example, circuit 14064 provides a control signal for switch SW to terminal 1400 of unit 14.

[0100] In this embodiment, circuit 1406 includes a digital-to-analog converter (DAC) 14065 having an output thereof providing a voltage Vref. Converter 14065 is controlled by state machine 14064. In particular, state machine 14064 is configured to provide a digital signal to converter 14065 via a plurality of bits or a binary code when a set point value for a voltage is selected from a list of predefined set point values, so that the converter provides a voltage Vref representing the selected predefined set point value for voltage Vsrc.

[0101] In this embodiment, when the state machine 14064 implements a change in the set point value of the voltage Vsrc from a predefined set point value Vsrc1 to a predefined set point value Vsrc2, instead of providing the converter 14065 with a binary code B1 corresponding to the value Vref1 of the voltage Vref, and then, for example, at the next cycle T of the clock signal that rates the operation of the circuit 14064, providing a binary code B2 corresponding to the value Vref2 of the voltage Vref, the state machine 14064 sequentially provides the binary code B1, a plurality of binary codes B, and a binary code B2. The binary code B corresponds to an intermediate value of the voltage Vref, which is between the values ​​Vref1 and Vref2. More specifically, the binary code B is continuously provided, for example, at each cycle of the clock signal to decrement the corresponding intermediate value of the voltage Vref. Therefore, the signal Vref exhibits a ramp that decrements between the values ​​Vref1 and Vref2, and more specifically herein as a staircase ramp.

[0102] Preferably, the circuit 14064 updates at each period T of its clock signal the binary code supplied to the converter 14065. Preferably, the circuit 14064 supplies in sequence all the binary codes B between the codes B1 and B2.

[0103] As a specific example, consider:

[0104] - the state machine 14064 provides in sequence the binary codes B1, B and B2 by varying the value of the code provided at each cycle T of the clock signal that clocks its operation;

[0105] - when successively providing the codes B1, B and B2, each modification of the code provided to the DAC converter corresponds to the same voltage variation DV of the output voltage of the DAC; and

[0106] - The voltage Vsrc' is equal to Vsrc / A.

[0107] In this case, it is ensured that the value DV / T is smaller than the value (Vsrc2-Vsrc1) / (RC).

[0108] Previously referenced Figure 2 and Figure 3 An embodiment is described in which the set point value of the voltage Vsrc to be delivered by the converter 12 is switched from a value Vscr1 to a value Vscr2, both selected from a list of predefined set point values. The predefined set point value of the voltage Vsrc is determined, for example, by a list of predefined supply powers and a default set point value. As an example, the default set point value corresponds to the lowest predefined set point value in the list of predefined set point values.

[0109] In an alternative embodiment, Figure 2 The described interface 214 operates according to the so-called "constant current" mode.

[0110] In this variant, selecting a predefined power P1 from a list of predefined supply powers is equivalent to selecting a predefined setpoint value Vsrc1 of the voltage Vsrc and the maximum output current Imax of the converter 12. The voltage Vsrc is then not only regulated according to its setpoint value Vsrc1, but also such that the current supplied by the converter does not exceed the maximum current Imax.

[0111] In this variant, the unit 14 is configured to: for example, in this variant, by means of an amplifier 1407, from across the resistor Rsense ( Figure 2) to measure the current provided by the converter 12. When the current provided by the converter 12 exceeds the current Imax, the unit 14 controls the converter 12 so that it provides the voltage Vsrc to a set point value Vsrc3, which is less than the set point value Vsrc1 and is determined by the difference between the current provided by the converter 12 and the current Imax. To this end, in the present example circuit 1406, the unit 14 is configured to adjust the value of the voltage Vref according to the difference between the current provided by the converter 12 and the current Imax, so that the voltage Vref adopts a value Vref3 representing the set point value Vsrc3. More specifically, the value Vref3 is equal to the value Vref1 representing the set point value Vsrc1 minus a percentage of the value Vref1, which is determined by the difference between the current provided by the converter 12 and the current Imax. In other words, the value Vref3 is equal to K multiplied by the value Vref1, K is less than 1 and is determined by the difference between the current provided by the converter 12 and the current Imax. In this variant, in contrast to the setpoint values ​​Vsrc1 and Vsrc2 , the setpoint value Vsrc3 is not a predefined setpoint value.

[0112] As an example, unit 14 (e.g., circuit 1406 thereof) includes an error amplifier ( Figure 2 ), the error amplifier provides a signal representing the difference between the current provided by the converter 12 and the current Imax, the value Vref3 is determined by the output signal of the error amplifier, and the voltage Vref is preferably proportional to or equal to the output signal.

[0113] Furthermore, in this variant, if the value of the voltage Vsrc becomes less than a lower threshold, the unit 14 detects this fault and selects a predefined setpoint value Vsrc2, which in this variant is preferably opposed to a default setpoint value of the voltage Vsrc, which causes a change in the setpoint value of the voltage Vsrc from a value Vsrc3 to a value Vsrc2. This lower threshold is determined by the setpoint value Vsrc1 or, in other words, by a predefined power P1.

[0114] As an example, the unit 14 (eg, the circuit 1406 thereof) includes a comparator ( Figure 2 ), which comparator provides a binary signal whose state "1" or "0" depends on the result of the comparison between the signal representing the voltage Vsrc and the signal representing the low threshold.

[0115] When the set point value is changed to Vsrc2, it may then be provided to the voltage Vref as before to exhibit a ramp between the values ​​Vref1 and Vref2. However, this would cause the voltage Vref to suddenly switch from the value Vref3 to the value Vref1 before the voltage ramp from the value Vref1 to the value Vref3. This is undesirable, in particular, because the voltage Vsrc at the converter output would exhibit a voltage peak.

[0116] Thus, in this variant, the cell 14 and more specifically its circuit 1406 is provided with a voltage Vref having a voltage ramp from a value Vref3 to a value Vref2 instead of having a voltage ramp from a value Vref1 to a value Vref2 .

[0117] Preferably, the unit 14 (e.g., the processing circuit 1406 thereof) is configured to store the value Vref3, for example, to store the value Vref at the value Vref3. Then, the circuit 1406 is configured to: provide a voltage ramp Vr from the value Vref1 to the value Vref2, compare the voltage ramp Vr with the stored voltage Vref3, and generate the voltage Vref from the voltage Vr and the stored voltage Vref3. More specifically, the circuit 1406 is configured to generate the voltage Vref such that the voltage Vref is equal to Vref3 as long as the voltage ramp Vr is greater than the voltage Vref3, and such that the voltage Vref is then equal to the voltage Vr.

[0118] Figure 4 In more detail, the embodiment according to the alternative embodiment is shown Figure 2 A portion of an interface 214, wherein the interface operates with a constant current. Figure 4 In FIG. 1 , only a portion of unit 14 is shown. Only a detailed description is given here. Figure 3 Unit 14 and Figure 4 The differences between Unit 14.

[0119] In this alternative embodiment, the unit 14 comprises an amplifier 1410. As previously described, the circuit 1406 (e.g., the circuit 14064) is configured to adapt the value of the voltage Vref in dependence on the difference between the current provided by the converter and the current Imax, for example, to reduce the value of the voltage Vref in dependence on the difference between the current provided by the converter 12 and the current Imax when the current provided by the converter becomes greater than the current Imax.

[0120] In this alternative embodiment, circuit 1406 includes terminal 14062, which is connected to terminal 1401 to receive voltage Vsrc. Although not shown, circuit 1406 includes one or more comparators configured to compare voltage Vsrc with a low threshold value and possibly with a high threshold value. The high threshold and the low threshold are determined by the selected predefined power, and more specifically by the corresponding predefined set point value of voltage Vsrc. As previously described, when predefined value P1 is selected, when voltage Vsrc becomes less than the low threshold value, circuit 1406 (e.g., circuit 14064) is configured to select a smaller set point value of voltage Vsrc, preferably a default set value.

[0121] In this alternative embodiment, capacitor C1 is connected between terminal 14060 and terminal 1402. In addition, switch SW1 is connected between terminal 14060 and the output of converter 14065, and switch SW2 is connected between terminal 14060 and output terminal 140641 of circuit 14064. When the current provided by converter 12 becomes greater than current Imax, circuit 14064 is configured to provide a voltage at a value Vref3, which is determined by the difference between the current provided by converter 12 and current Imax. Preferably, circuit 14064 includes an error amplifier ( Figure 4 ), the error amplifier is connected between a signal representing the current Imax and a signal representing the current provided by the converter 12 (e.g., signal MesI), and then the amplifier provides an output signal representing the difference between the current provided by the converter 12 and the current Imax. Preferably, the error amplifier is configured to provide a voltage Verf3 as an output signal.

[0122] As will be seen in more detail below, capacitor C1 enables storage of voltage Vref at value Vref3 when the setpoint value of voltage Vsrc is changed to set a predefined setpoint value Vsrc2 after voltage Vsrc has exceeded the low threshold.

[0123] In this alternative embodiment, circuit 1406 (e.g., state machine 14064) performs a comparison (eg, a comparison between a signal representing voltage Vsrc and a signal representing a lower threshold value of voltage Vsrc (determined by the selected predefined power). Figure 4 not shown).

[0124] In this alternative embodiment, the circuit 1406 comprises a comparator 14066 configured to compare the voltage available at the output of the DAC converter 14065 with the voltage Vref across the capacitor C1. The output of the comparator 14066 is connected to a terminal 140642 of the state machine 14064.

[0125] In this alternative embodiment, circuit 1406 (eg, state machine 14064 ) is configured to control switches SW1 and SW2 .

[0126] In operation, after the predefined power P1 has been selected, the circuit 1406 maintains the switch SW1 on and maintains the switch SW2 off. In addition, the state machine 14064 provides a binary code B1 to the converter 14065, causing the converter to apply the voltage Vref at the value Vref1 across the capacitor C1, which represents the corresponding predefined set point value Vsrc1 of the voltage Vsrc.

[0127] When the converter 12( Figure 2 ) becomes greater than the current Imax determined by the selected predefined power P1, this is detected by the state machine 14064, in particular from the signal MesI. The state machine 14064 then provides a voltage at its terminal 140641 at a value Vref3, which value Vref3 depends on the difference between the current provided by the converter 12 and the current Imax. The state machine 14064 also controls the switching off of the switch SW1 and the switching on of the switch SW2, whereby the value of the voltage Vref across the capacitor C1 is equal to Vref3. If during constant current regulation the voltage Vsrc is less than the low threshold, this is detected by the state machine 14064. The state machine 14064 controls the switching off of the switch SW2. As a result, the voltage Vref is stored across the capacitor C1 and is equal to Vref3. The state machine 14064 then selects a predefined set point value Vsrc2, which preferably corresponds to a default set point value.

[0128] Then, if Figure 3 As in the embodiment of FIG. 1 , the state machine 14064 provides a series of binary codes B1, B and B2 to the converter 10465. A voltage ramp Vr from the value Vref1 to the value Vref2 is then available at the output of the converter 14065.

[0129] As long as the state machine 14064 receives a signal from the comparator 14066 indicating that the voltage Vref is less than the voltage Vr, it maintains the two switches SW1 and SW2 turned off. The voltage Vref is then maintained at a value Vref3.

[0130] Once the state machine 14064 receives a signal from the comparator 14066 indicating that the voltage Vref is equal to or greater than the voltage Vr, it turns on the switch SW1. The voltage Vr can then be found across the capacitor C1. As a result, the voltage Vref is equal to the voltage Vr and exhibits a voltage ramp from the value Vref3 to the value Vref2.

[0131] A specific example of how the state machine 14064 provides the binary code to the DAC 14065 to generate the ramp Vr (already described in Figure 3 The embodiments described above are also applicable to Figure 4 Embodiment of the invention.

[0132] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art. In particular, although there has been described with respect to Figure 4 An embodiment under constant current is described, in which the value Vref3 is stored across the capacitor C1 and then compared with the voltage ramp Vr to provide a voltage ramp Vref from the value Vref3 to the value Vref2, but other embodiments of the circuit 1406 enabling such a voltage ramp Vref to be provided may be provided. In particular, in order to operate under constant current, the circuit 1406 may be provided to include an analog-to-digital converter enabling a binary code B3 corresponding to the value Vref3 to be obtained when the voltage Vsrc falls below a low threshold, so that from this point on, the circuit 14064 sequentially provides the code B3, the successive codes B and the code B2 to the DAC converter 14065, the code B being between the code B3 and the code B2.

[0133] Finally, based on the functional indications given above, the practical implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, based on the functional indications given above, determining the slope of the voltage Vref so as to keep the amplifier 1407 in regulated operation (e.g. by providing a voltage ramp Vref between two values ​​Vref1 and Vref2, or between two values ​​Vref3 and Vref2 (if the interface is operated with constant current), for at least 1 ms, preferably at least 10 ms) is within the capabilities of a person skilled in the art.

[0134] The various embodiments described above may be combined to provide additional embodiments. These and other changes may be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents to which these claims are given. Therefore, the claims are not limited by the disclosure.

Claims

1. A device comprising: a voltage converter configured to provide a second voltage at an output terminal of the converter from a first voltage, the second voltage having a current value determined by a third voltage at a control terminal of the converter; a ramp generating circuit configured to: when the set point value of the second voltage switches from a first set point value to a second set point value less than the first set point value, generate a first signal including a ramp, the ramp sequentially representing the first set point value, a plurality of decreasing intermediate values ​​between the first set point value and the second set point value, and the second set point value; an error amplifier configured to provide a second signal, the second signal representing a difference between the first signal and a third signal, the third signal representing the current value of the second voltage; as well as A feedback control circuit is configured to set the third voltage based on the second signal. 2 . The apparatus of claim 1 , wherein the ramp generation circuit is configured to select the first set point value and the second set point value from a set of predefined set point values.

3. An apparatus according to claim 1, wherein the first set point value is less than a predefined set point value selected from a set of predefined set point values, the first set point value is determined from the selected predefined set point value, and the second set point value is selected from the set of predefined set point values. 4 . The device of claim 3 , wherein the ramp generation circuit is configured to select the first set point value from a difference between a current available at the output terminal of the converter and a predefined maximum current.

5. The device of claim 3 , wherein the ramp generating circuit is configured to: when the set point value of the second voltage switches from the first set point value to the second set point value, storing a fourth signal representative of the first set point value; generating a fifth signal, the fifth signal comprising a ramp, the ramp sequentially representing the selected predefined set point value, a plurality of decreasing intermediate values ​​between the selected predefined set point value and the second set point value, and the second set point value; as well as The first signal is generated, the first signal being equal to the fourth signal until the fifth signal is equal to the fourth signal, and at this time the first signal is equal to the fifth signal. 6 . The apparatus of claim 5 , wherein the ramp generation circuit comprises a comparator configured to provide a sixth signal representing a comparison of the fourth signal and the fifth signal. 7 . The apparatus of claim 6 , wherein the ramp generation circuit is configured to generate the first signal from the fourth signal, the fifth signal, and the sixth signal.

8. The apparatus of claim 1, wherein the feedback control circuit comprises: A voltage-dividing bridge connected between the output terminal of the converter and a node for applying a reference potential, wherein an intermediate node of the voltage-dividing bridge is connected to the control terminal of the converter; as well as A transistor is connected between the intermediate node of the voltage-dividing bridge and the application node of the reference potential, and a control terminal of the transistor is configured to receive the second signal.

9. The apparatus of claim 3, wherein the ramp generation circuit comprises a state machine and a digital-to-analog converter.

10. The apparatus of claim 9, wherein the state machine is configured to sequentially provide binary control codes to the digital-to-analog converter when the set point value of the second voltage switches from the first set point value to the second set point value, the codes representing the first set point value, the decremented intermediate value, and the second set point value, respectively, the digital-to-analog converter having an output terminal configured to provide the first signal.

11. The apparatus of claim 9, wherein: The ramp generating circuit is configured to: when the set point value of the second voltage switches from the first set point value to the second set point value, storing a fourth signal representative of the first set point value; generating a fifth signal, the fifth signal comprising a ramp, the ramp sequentially representing the selected predefined set point value, a plurality of decreasing intermediate values ​​between the selected predefined set point value and the second set point value, and the second set point value; as well as generating the first signal, the first signal being equal to the fourth signal until the fifth signal is equal to the fourth signal, and at this time the first signal is equal to the fifth signal; and The state machine is configured to, when the set point value of the second voltage switches from the first set point value to the second set point value, sequentially provide binary control codes to the digital-to-analog converter, the codes respectively representing the first set point value, the multiple decreasing intermediate values ​​between the first set point value and the second set point value, and the second set point value, the digital-to-analog converter having an output terminal configured to provide the fifth signal.

12. The apparatus of claim 11 , wherein the ramp generation circuit comprises: a first switch coupling the output terminal of the digital-to-analog converter to a first internal node; as well as a capacitor connected to the first internal node; as well as A second switch couples a second internal node to the first internal node, the first signal being available at the first internal node, and the fourth signal being available at the second internal node.

13. The apparatus of claim 12, wherein the state machine is configured to: When the set point value of the second voltage switches from the first set point value to the second set point value, turning off the second switch; and When the fifth signal becomes equal to the fourth signal, the first switch is turned on.

14. A device comprising: a power supply configured to provide a first voltage; USB-C connector; as well as A connection interface, coupled between the power source and the USB-C connector, the connection interface comprising: a voltage converter configured to provide a second voltage at an output terminal of the converter from the first voltage, the second voltage having a current value determined by a third voltage at a control terminal of the converter, the output terminal of the converter being coupled to the USB-C connector; a ramp generating circuit configured to: when the set point value of the second voltage switches from a first set point value to a second set point value less than the first set point value, generate a first signal including a ramp, the ramp sequentially representing the first set point value, a plurality of decreasing intermediate values ​​between the first set point value and the second set point value, and the second set point value; an error amplifier configured to provide a second signal representing a difference between the first signal and a third signal, the third signal representing the current value of the second voltage; and A feedback control circuit is configured to set the third voltage based on the second signal.

15. The apparatus of claim 14, wherein the feedback control circuit comprises: A voltage-dividing bridge connected between the output terminal of the converter and a node for applying a reference potential, wherein an intermediate node of the voltage-dividing bridge is connected to the control terminal of the converter; as well as A transistor is connected between the intermediate node of the voltage-dividing bridge and the application node of the reference potential, and a control terminal of the transistor is configured to receive the second signal.

16. The apparatus of claim 14, wherein the ramp generation circuit comprises: a state machine configured to: when the set point value of the second voltage switches from the first set point value to the second set point value, sequentially provide binary control codes, the codes representing the first set point value, the decreasing intermediate value, and the second set point value, respectively; as well as A digital-to-analog converter has an input terminal configured to receive the binary control code from the state machine and has an output terminal configured to provide the first signal.

17. The apparatus of claim 14, wherein: the first set point value being less than a predefined set point value selected from a set of predefined set point values, the first set point value being determined from the selected predefined set point values, and the second set point value being selected from the set of predefined set point values; The ramp generating circuit is configured to: when the set point value of the second voltage switches from the first set point value to the second set point value, storing a fourth signal representative of the first set point value; generating a fifth signal, the fifth signal comprising a ramp, the ramp sequentially representing the selected predefined set point value, a plurality of decreasing intermediate values ​​between the selected predefined set point value and the second set point value, and the second set point value; as well as generating the first signal, the first signal being equal to the fourth signal until the fifth signal is equal to the fourth signal, and at this time the first signal is equal to the fifth signal; and The ramp generating circuit comprises: a state machine configured to continuously provide binary control codes when the set point value of the second voltage switches from the first set point value to the second set point value, the codes representing the first set point value, the plurality of decreasing intermediate values ​​between the first set point value and the second set point value, and the second set point value, respectively; as well as A digital-to-analog converter has an input terminal configured to receive the binary control code from the state machine and has an output terminal configured to provide the fifth signal.

18. A method comprising: Controlling a voltage converter, the voltage converter providing a second voltage from a first voltage, the second voltage having a current value determined by a third voltage, the controlling comprising: when a set point value of the second voltage is switched from a first set point value to a second set point value which is less than the first set point value: generating a first signal comprising a ramp, the ramp sequentially representing the first set point value, a plurality of decreasing intermediate values ​​ranging from the first set point value to the second set point value, and the second set point value; an error amplifier that provides a second signal that represents a difference between the first signal and a third signal that represents a present value of the second voltage; and The third voltage is determined from the second signal.

19. The method of claim 18, wherein the first set point value is less than a predefined set point value selected from a set of predefined set point values, the first set point value is determined from the selected predefined set point value, and the second set point value is selected from the set of predefined set point values.

20. The method of claim 19, wherein the first set point value is further determined as a function of a difference between a current available at the output terminals of the converter and a predefined maximum current.

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