Miller clamp device for parallel switching transistors and driver including the same

Abstract

The present invention provides a Miller clamp device for parallel switching transistors and a driver including the same, the Miller clamp device comprising: a driver chip, which comprises an output terminal and a built-in Miller clamp circuit with a Miller clamp terminal, the output terminal of the driver chip is used to output a pulse width modulation signal; and a plurality of auxiliary Miller clamp circuits, each of which is connected between the gate of the corresponding switching transistor and the Miller clamp terminal of the built-in Miller clamp circuit; wherein, when the built-in Miller clamp circuit is triggered for Miller clamping, the Miller current generated by the corresponding switching transistor flows to a first DC voltage through the corresponding auxiliary Miller clamp circuit. The Miller clamp device of the present invention can perform Miller clamping on parallel switching transistors and reduce circuit cost.

Description

Technical Field

[0001] The invention relates to a Miller clamp circuit, in particular to a Miller clamp device for parallel switching transistors and a driver comprising the same. Background Art

[0002] A switching transistor (such as an insulated gate bipolar transistor or a metal oxide semiconductor field effect transistor) has a parasitic Miller capacitance, which can lead to a very significant Miller effect. That is, when the switching transistor is controlled to be turned on, the Miller capacitance of the switching transistor connected to a bridge arm causes the voltage of its gate (that is, its control electrode) to increase, which may cause the switching transistor to be mis-turned on.

[0003] Figure 1 It is a circuit diagram of a driver for a metal oxide semi-conductor field effect transistor in the prior art, wherein the driver includes a driver chip 13 and a driving power amplifier 11, which is powered by a DC power supply 12, wherein the output terminal OUT of the driver chip 13 outputs a pulse width modulation signal PWM, and the driving power amplifier 11 includes an input terminal, a gate output terminal G and a source output terminal S, wherein the gate output terminal G is connected to the gate (or gate, i.e., its control electrode) of the metal oxide semi-conductor field effect transistor Q1 through a driving resistor Rg11, and the source output terminal S is connected to the source of the metal oxide semi-conductor field effect transistor Q1. The input terminal of the driving power amplifier 11 is used to receive the pulse width modulation signal PWM and perform power amplification, and its gate output terminal G outputs a power-amplified pulse width modulation driving signal to control the metal oxide semi-conductor field effect transistor T1 to be turned on or off.

[0004] like Figure 1 As shown, the drain of the MOSFET Q1 has a parasitic drain inductance Ld, the source has a parasitic source inductance Ls, and there is a parasitic Miller capacitance Cm between the drain and the gate.

[0005] When the MOSFET connected to a bridge arm of the MOSFET Q1 is controlled to be turned on, a high transient voltage change will be generated between the drain and source of the MOSFET Q1, and the current path of the Miller current generated thereby is from the drain of the MOSFET Q1, the Miller capacitor Cm, the driving resistor Rg11, the gate output terminal G and the source output terminal S of the driving power amplifier 11 to the source of the MOSFET Q1, thereby generating a Miller voltage across the driving resistor Rg11, resulting in a high voltage drop between the gate and the emitter of the MOSFET Q1. If the voltage drop exceeds the turn-on threshold of the MOSFET Q1, the MOSFET Q1 will be mis-turned on.

[0006] In order to suppress the Miller effect of the switching transistor, most driver chips in the prior art have a built-in Miller clamp circuit to clamp the gate voltage of the switching transistor.

[0007] Figure 2 The present invention is a circuit block diagram of a driver chip with a built-in Miller clamp circuit in the prior art for Miller clamping a switching transistor. Figure 1 Basically the same, the difference is that the driver chip 23 includes a built-in Miller clamp circuit 231, whose Miller clamp terminal CLAMP is connected to the gate G2 of the switching transistor Q2, and the built-in Miller clamp circuit 231 is triggered for Miller clamping, which acts as a current source to absorb Miller current.

[0008] When the switching transistor ( Figure 2 When the internal Miller clamp circuit 231 (not shown) is controlled to be turned on, the driver chip 23 is triggered for Miller clamping, so that the built-in Miller clamp circuit 231 is in a low resistance state and acts as a current source to absorb the induced Miller current. That is, the Miller current flows from the gate G2 of the switching transistor Q2 to the Miller clamp terminal CLAMP of the built-in Miller clamp circuit 231, so that the voltage of the gate G2 of the switching transistor Q2 is clamped to a low level, ensuring that the switching transistor Q2 is in a cut-off state to avoid its mis-conduction.

[0009] In a three-phase uninterruptible power supply, a high-power power converter is an application trend. In order to realize a high-power power converter, switching transistors are usually connected in parallel.

[0010] Figure 3 FIG. 1 is a circuit block diagram of a driver for parallel switching transistors in the prior art. Figure 3 As shown, the switching transistors Q31, Q32 and Q33 are connected in parallel, that is, the sources are connected to each other, and the drains are connected to each other. The output terminal OUT of the driver chip 33 outputs the pulse width modulation signal PWM to the input terminals of the driving power amplifiers 311, 312 and 313, and the driving power amplifiers 311, 312 and 313 are connected to the switching transistors Q31, Q32 and Q33 through the driving resistors Rg31, Rg32 and Rg33 respectively. The Miller clamp terminal CLAMP of the built-in Miller clamp circuit 331 of the driver chip 33 is connected to the gates of the switching transistors Q31, Q32 and Q33.

[0011] When the built-in Miller clamp circuit 331 is triggered for Miller clamping, it is in a low resistance state and acts as a current source to absorb Miller current. On the one hand, the current absorption capacity of the built-in Miller clamp circuit 331 is limited, and it can only absorb the Miller current generated by a single switching transistor, and cannot absorb the Miller current generated by multiple switching transistors in parallel. On the other hand, the transmission paths from the driver chip 33 to the driving power amplifier devices 311, 312, and 313 are different, and the resistance values ​​between the driving power amplifier devices 311, 312, and 313 and the switching transistors Q31, Q32, and Q33 are different, which may cause the switching of the switching transistors Q31, Q32, and Q33 to be asynchronous, thereby causing damage to the switching transistors Q31, Q32, and Q33. On the other hand, the current path from the Miller clamp terminal CLAMP to the gate of the switching transistors Q31, Q32 and Q33 is usually long, and therefore has a certain equivalent resistance. The Miller current will still produce a certain voltage drop in the equivalent resistance, which may make the voltage drop between the gate and source of the switching transistors Q31, Q32 and Q33 greater than their turn-on threshold voltage, thereby reducing the performance of the Miller clamp.

[0012] Therefore, the existing driver chip cannot effectively perform Miller clamping on the parallel switching transistors. Summary of the invention

[0013] In view of the above technical problems existing in the prior art, an embodiment of the present invention provides a Miller clamp device for parallel switching transistors, wherein the Miller clamp device comprises:

[0014] a driver chip comprising an output terminal and a built-in Miller clamp circuit having a Miller clamp terminal, the output terminal of the driver chip being used to output a pulse width modulated signal; and

[0015] A plurality of auxiliary Miller clamp circuits, each of which is connected between the gate of a corresponding switch transistor and a Miller clamp terminal of the built-in Miller clamp circuit;

[0016] When the built-in Miller clamp circuit is triggered for Miller clamping, the Miller current generated by the corresponding switch transistor flows to the first DC voltage through the corresponding auxiliary Miller clamp circuit.

[0017] Preferably, each of the auxiliary Miller clamp circuits includes: a controllable transistor, which includes a control electrode, a first electrode and a second electrode, the control electrode of the controllable transistor is connected to the Miller clamp terminal of the built-in Miller clamp circuit, and the second electrode is connected to the first DC voltage; a first diode, whose anode is connected to the gate of the corresponding switching transistor, and whose cathode is connected to the second DC voltage; and a second diode, whose anode is connected to the anode of the first diode, and whose cathode is connected to the first electrode of the controllable transistor; wherein, when the second DC voltage is greater than the first DC voltage, the built-in Miller clamp circuit is triggered for Miller clamping, so that the first electrode and the second electrode of the controllable transistor are conductive.

[0018] Preferably, the built-in Miller clamp circuit is a current source for absorbing Miller current, and the controllable transistor is a first PNP transistor or a P-type metal oxide semi-field effect transistor; the base of the first PNP transistor or the gate of the P-type metal oxide semi-field effect transistor is connected to the Miller clamp terminal of the built-in Miller clamp circuit, the emitter of the first PNP transistor or the source of the P-type metal oxide semi-field effect transistor is connected to the gate of the corresponding switching transistor, and the collector of the first PNP transistor or the drain of the P-type metal oxide semi-field effect transistor is connected to the first DC voltage; each of the auxiliary Miller clamp circuits also includes a first resistor connected between the Miller clamp terminal and the emitter of the first PNP transistor or the source of the P-type metal oxide semi-field effect transistor.

[0019] Preferably, each of the Miller clamp circuits further includes a second resistor connected between the Miller clamp terminal and the base of the first PNP transistor or the gate of the P-type metal oxide semi-field effect transistor.

[0020] Preferably, each of the auxiliary Miller clamp circuits further includes a first capacitor connected between the base and the emitter of the first PNP transistor or between the gate and the source of the P-type metal oxide semi-conductor field effect transistor.

[0021] Preferably, the driver further comprises a pulse width modulation signal locking device connected between the output terminal of the driver chip and the Miller clamp terminal, which is used to lock the potential of the Miller clamp terminal.

[0022] Preferably, the pulse width modulation signal locking device comprises a third diode and a third resistor connected in series.

[0023] Preferably, the built-in Miller clamp circuit is a voltage source that outputs a Miller enable signal; the controllable transistor is a first NPN transistor or an N-type metal oxide semi-field effect transistor, the base of the first NPN transistor or the gate of the N-type metal oxide semi-field effect transistor is connected to the Miller clamp terminal of the built-in Miller clamp circuit, the collector of the first NPN transistor or the drain of the N-type metal oxide semi-field effect transistor is connected to the gate of the corresponding switching transistor, and the emitter of the first NPN transistor or the source of the N-type metal oxide semi-field effect transistor is connected to the first DC voltage.

[0024] Preferably, each of the auxiliary Miller clamp circuits further includes a fourth resistor connected between the Miller clamp terminal and the base of the NPN transistor or the gate of the N-type metal oxide semi-conductor field effect transistor.

[0025] Preferably, each of the auxiliary Miller clamp circuits further includes a second capacitor connected between the base and collector of the first NPN transistor or between the gate and drain of the N-type metal oxide semi-conductor field effect transistor.

[0026] Preferably, each of the auxiliary Miller clamp circuits further includes a fourth diode connected between the anode of the first diode and the collector of the first NPN transistor or the drain of the N-type metal oxide semi-field effect transistor.

[0027] Preferably, each of the auxiliary Miller clamp circuits is close to the gate of the corresponding switching transistor.

[0028] The present invention provides a driver, comprising:

[0029] A Miller clamp arrangement for parallel connected switching transistors as described above; and

[0030] A plurality of driving power amplifying devices, each of which comprises an input terminal, a gate output terminal and a source output terminal, wherein the input terminal is connected to the output terminal of the driver chip in the Miller clamp device, the gate output terminal is connected to the gate of the corresponding switching transistor through a driving resistor, and the source output terminal is connected to the source of the corresponding switching transistor, and each of the driving power amplifying devices is used to power amplify the pulse width modulation signal output by the driver chip.

[0031] Preferably, each of the driving power amplifier devices includes: a second NPN transistor and a second PNP transistor, the base of the second NPN transistor and the base of the second PNP transistor are connected to the output terminal of the driver chip, the collector of the second NPN transistor is connected to the third DC voltage, the collector of the second PNP transistor is connected to the fourth DC voltage, the emitter of the second NPN transistor and the emitter of the second PNP transistor are connected and serve as the gate output terminal of the driving power amplifier device, and the third DC voltage is greater than the fourth DC voltage; and three capacitors, one ends of the three capacitors are respectively connected to the third DC voltage, the fourth DC voltage and the gate output terminal, and the other ends thereof are connected and serve as the source output terminal of the driving power amplifier device.

[0032] The Miller clamp device of the present invention isolates the gates of the parallel switch transistors from each other and can implement Miller clamping on the parallel switch transistors. It also amplifies the current absorption capability of the built-in Miller clamp circuit of the driver chip, saving circuit cost. It reduces the conduction path of the Miller current and the equivalent resistance in the conduction path of the Miller current, thereby improving the effect of Miller clamping. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0034] Figure 1 The present invention is a circuit diagram of a driver for a metal oxide semiconductor field effect transistor in the prior art.

[0035] Figure 2 The present invention is a circuit block diagram of a driver chip with a built-in Miller clamp circuit in the prior art for Miller clamping a switching transistor.

[0036] Figure 3 is a circuit block diagram of a driver for parallel switching transistors in the prior art.

[0037] Figure 4 is a block diagram of a driver for parallel switching transistors according to a preferred embodiment of the present invention.

[0038] Figure 5 is a circuit diagram of a driver for parallel switching transistors according to a second embodiment of the present invention.

[0039] Figure 6 is a circuit diagram of a driver for parallel switching transistors according to a third embodiment of the present invention.

[0040] Figure 7 is a circuit diagram of a driver for parallel switching transistors according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings.

[0042] For the convenience of the following description, the high level and low level defined below are well-known technical concepts or terms in the field of analog circuits or digital circuits. For example, the high level can be a voltage of 5 volts, 12 volts or 24 volts, and the low level can be a voltage less than 1 volt or a negative voltage lower than the logical ground or actual ground voltage.

[0043] Figure 4 FIG. 1 is a block diagram of a driver for parallel switching transistors according to a preferred embodiment of the present invention. Figure 4 As shown, the driver 4 and Figure 3 The drivers shown are basically the same, except that the driver 4 further includes an auxiliary Miller clamp circuit 401, an auxiliary Miller clamp circuit 402 and an auxiliary Miller clamp circuit 403, wherein the auxiliary Miller clamp circuit 401 is connected between the gate of the switching transistor Q41 and the Miller clamp terminal CLAMP of the built-in Miller clamp circuit 431 of the driver chip 43, the auxiliary Miller clamp circuit 402 is connected between the gate of the switching transistor Q42 and the Miller clamp terminal CLAMP of the Miller clamp circuit 431, and the auxiliary Miller clamp circuit 403 is connected between the gate of the switching transistor Q43 and the Miller clamp terminal CLAMP of the Miller clamp circuit 431. The DC power supply 42 is used to provide the same DC voltage to the auxiliary Miller clamp circuit 401 and the driving power amplifier 411, to provide the same DC voltage to the auxiliary Miller clamp circuit 402 and the driving power amplifier 412, and to provide the same DC voltage to the auxiliary Miller clamp circuit 403 and the driving power amplifier 413.

[0044] When the pulse width modulation signal PWM outputted from the output terminal OUT of the driver chip 43 is at a high level, the driving power amplifier devices 411, 412 and 413 respectively amplify the pulse width modulation signal PWM to output a pulse width modulation driving signal, which is outputted to the gates of the switching transistors Q41, Q42 and Q43 through the driving resistors Rg41, Rg42 and Rg43 respectively, thereby controlling the switching transistors Q41, Q42 and Q43 to be turned on.

[0045] When the pulse width modulation signal outputted from the output terminal OUT of the driver chip 43 is at a low level, the driving power amplifiers 411, 412 and 413 respectively output low levels to the switching transistors, and the Miller currents generated by the switching transistors Q41, Q42 and Q43 pass through the parasitic Miller capacitors ( Figure 4At this time, when the built-in Miller clamp circuit 431 is triggered for Miller clamping, a conductive path is formed in the auxiliary Miller clamp circuits 401, 402 and 403, so that the Miller current generated by the switching transistors Q41, Q42 and Q43 flows from their gates through the auxiliary Miller clamp circuits 401, 402, 403 to the low-level DC voltage.

[0046] No current path of Miller current is formed between the gate and source of each of the switch transistors Q41, Q42 and Q43, so the switch transistors Q41, Q42 and Q43 remain in the off state and will not be mistakenly turned on. Therefore, the auxiliary Miller clamping device 40 of the present invention can be used for Miller clamping of multiple parallel switch transistors.

[0047] The auxiliary Miller clamp circuits 401 , 402 and 403 isolate the gates of the switch transistors Q41 , Q42 and Q43 from each other, thereby preventing the switch transistors Q41 , Q42 and Q43 from being damaged due to asynchronous switching.

[0048] The auxiliary Miller clamp circuits 401 , 402 and 403 may be arranged on the circuit board close to the switching transistors Q41 , Q42 and Q43 , respectively, thereby shortening the current path of the Miller current generated by Q41 , Q42 and Q43 and improving the Miller clamp performance.

[0049] Figure 5 FIG. 1 is a circuit diagram of a driver for parallel switching transistors according to a second embodiment of the present invention. Figure 5 As shown, the driver 5 includes driving power amplifiers 511, 512 and 513, and a Miller clamp device 50. The Miller clamp device 50 includes a driver chip 53 and auxiliary Miller clamp circuits 501, 502 and 503. The output terminal OUT of the driver chip 53 is connected to the input terminals of the driving power amplifiers 511, 512 and 513. The auxiliary Miller clamp circuit 501 is connected between the Miller clamp terminal CLAMP of the built-in Miller clamp circuit 531 of the driver chip 53 and the gate of the metal oxide semi-field effect transistor Q51. The auxiliary Miller clamp circuit 502 is connected between the Miller clamp terminal CLAMP of the built-in Miller clamp circuit 531 and the gate of the metal oxide semi-field effect transistor Q52. The auxiliary Miller clamp circuit 503 is connected between the Miller clamp terminal CLAMP of the built-in Miller clamp circuit 531 and the gate of the metal oxide semi-field effect transistor Q53.

[0050] The DC power supply ( Figure 5(not shown) provides a high-level DC voltage Vdd1 and a low-level DC voltage Vss1 to each of the driving power amplifier 511 and the auxiliary Miller clamp circuit 501, provides a high-level DC voltage Vdd2 and a low-level DC voltage Vss2 to each of the driving power amplifier 512 and the auxiliary Miller clamp circuit 502, and provides a high-level DC voltage Vdd3 and a low-level DC voltage Vss3 to each of the driving power amplifier 513 and the auxiliary Miller clamp circuit 503. The voltage values ​​of the high-level DC voltages Vdd1, Vdd2 and Vdd3 are equal, and the voltage values ​​of the low-level DC voltages Vss1, Vss2 and Vss3 are equal.

[0051] The auxiliary Miller clamp circuits 501 , 502 and 503 have the same circuit structure, and only the auxiliary Miller clamp circuit 501 is taken as an example for description. The auxiliary Miller clamp circuit 501 includes a PNP transistor T51, a resistor R51, a resistor R52, a capacitor C51, a diode D51 and a diode D52, wherein the capacitor C51 is connected between the emitter and the base of the PNP transistor T51, the resistor R51 is connected between the Miller clamp terminal CLAMP of the built-in Miller clamp circuit 531 and the emitter of the PNP transistor T51, the resistor R52 is connected between the Miller clamp terminal CLAMP of the built-in Miller clamp circuit 531 and the base of the PNP transistor T51, the collector of the PNP transistor T51 is connected to the low-level DC voltage Vss1, the node formed by the positive electrode of the diode D51 and the positive electrode of the diode D52 is connected to the gate of the metal oxide semi-field effect transistor Q51, the cathode of the diode D51 is connected to the high-level DC voltage Vdd1, and the cathode of the diode D52 is connected to the emitter of the PNP transistor T51.

[0052] The driving power amplifier devices 511, 512 and 513 have the same circuit structure, and only the driving power amplifier device 511 is used as an example for description. The driving power amplifier device 511 includes an NPN transistor T52 and a PNP transistor T53, and capacitors C52, C53 and C54, wherein the NPN transistor T52 and the PNP transistor T53 are connected in a push-pull structure, that is, the bases of the NPN transistor T52 and the PNP transistor T53 are connected to the output terminal OUT of the driver chip 53, the collector of the NPN transistor T52 is connected to the DC voltage Vdd1, the collector of the PNP transistor T53 is connected to the DC voltage Vss1, and the node formed by the emitter of the PNP transistor T53 and the emitter of the NPN transistor T52 is used as the gate output terminal of the driving power amplifier device 511. One end of the capacitors C52, C53, and C54 are connected and serve as the source output terminal S of the driving power amplifier device 511, and the other ends thereof are respectively connected to the DC voltages Vdd1, Vss1 and the gate output terminal G. The capacitors C52, C53, and C54 are used for voltage stabilization to prevent the high level of the pulse width modulation driving signal output by the driving power amplifier device 511 from being reduced.

[0053] When the pulse width modulation signal output from the output terminal OUT of the driver chip 53 is at a high level (i.e., greater than the turn-on voltage of the transistor), the NPN transistor T52 is turned on and the PNP transistor T53 is turned off. At this time, the voltage of the gate output terminal G of the driving power amplifier device 511 is equal to or slightly less than the DC voltage Vdd1, and the current is greater than the base current, thereby driving the high level output of the driving power amplifier device 511 to control the metal oxide semi-field effect transistor Q51 to turn on.

[0054] When the pulse width modulation signal outputted from the output terminal OUT of the driver chip 53 is at a low level (i.e., less than the transistor turn-on voltage), the NPN transistor T52 is turned off and the PNP transistor T53 is turned on. At this time, the voltage at the gate output terminal G of the driving power amplifier device 511 is equal to or approximately equal to the DC voltage Vss1, so the low level outputted by the driving power amplifier device 511 controls the metal oxide semi-conductor field effect transistor Q51 to be turned off. At this time, the Miller current generated by the metal oxide semi-conductor field effect transistor Q51 flows from the drain through the Miller capacitor to the gate, and then flows to the node N5 formed by connecting the anodes of the diodes D51 and D52 in the auxiliary Miller clamp circuit 501. Since the built-in Miller clamp circuit 531 is triggered to a low-resistance state when the output terminal OUT outputs a low level and is used to absorb the Miller current, a small amount of current will flow through the resistor R51, causing a voltage drop across its two ends, and the voltage drop across the resistor R51 is greater than the sum of the forward bias voltage of the emitter junction of the PNP transistor T51 and the conduction voltage of the diode D52, so that the PNP transistor T51 is turned on, and the Miller current flows from the node N5 through the diode D52 and the PNP transistor T51 in the on state to the DC voltage Vss1.

[0055] According to the above Miller clamping principle, a very small part of the Miller current generated by the MOSFETs Q51, Q52 and Q53 flows into the built-in Miller clamping circuit 531, and most of the Miller current flows to the DC voltages Vss1, Vss2 and Vss3 respectively through the auxiliary Miller clamping circuits 501, 502 and 503 that are in conduction. The auxiliary Miller clamping circuits 501, 502 and 503 amplify the current absorption capability of the built-in Miller clamping circuit 531, so only one driver chip 53 is used to absorb the Miller current generated by multiple MOSFETs in parallel. Compared with using multiple driver chips 53, the Miller clamping device 50 of the present invention saves circuit costs.

[0056] The gates of the parallel-connected MOSFETs Q51, Q52 and Q53 are isolated from each other, so the MOSFETs Q51, Q52 and Q53 will not be damaged due to asynchronous switching of the MOSFETs Q51, Q52 and Q53.

[0057] When the auxiliary Miller clamping circuits 501, 502, 503 are arranged on the circuit board, the auxiliary Miller clamping circuits 501, 502, 503 can be placed close to the gates of the switching transistors Q51, Q52, and Q53, thereby reducing the conduction path of the Miller current, thereby reducing the equivalent resistance in the conduction path of the Miller current, improving the effect of the Miller clamping, and ensuring that the metal oxide semi-field effect transistors Q51, Q52, and Q53 will not be mis-turned on.

[0058] The resistor R51 can be selected with a relatively large resistance value (for example, several thousand ohms) to be used as a voltage-dividing resistor, and the voltage across the resistor R51 is greater than the forward bias voltage of the emitter junction of the PNP transistor T51, so as to turn on the PNP transistor T51. The resistor R52 can be selected with a relatively small resistance value (for example, several ohms to tens of ohms) to be used as a base current-limiting resistor to prevent the base current of the PNP transistor T51 from being too large and being damaged.

[0059] Capacitor C51 can be used as a high-frequency negative feedback capacitor with a suitable capacitance value to improve the stability of the PNP transistor T51 and avoid high-frequency parasitic oscillation.

[0060] The diode D51 is used to clamp the gate voltage of the MOSFET Q51. When the gate voltage of the MOSFET Q51 is much greater than the DC voltage Vdd1, the diode D51 is turned on, thereby clamping the gate voltage of the MOSFET Q51 to the sum of the DC voltage Vdd1 and the conduction voltage of the diode D51. The diode D52 is connected between the emitter of the PNP transistor T51 and the gate of the MOSFET Q51 to prevent the emitter current of the PNP transistor T51 from flowing in reverse into the gate of the MOSFET Q51, thereby affecting its switching state or causing damage to it.

[0061] Figure 6 FIG. 1 is a circuit diagram of a driver for parallel switching transistors according to a third embodiment of the present invention. Figure 6 As shown, the driver 6 and Figure 5 The driver 5 shown is basically the same, except that the Miller clamp device 60 further includes a pulse width modulation signal locking device 64 connected between the output terminal OUT of the driver chip 63 and the Miller clamp terminal CLAMP of the built-in Miller clamp circuit 631, and one end of the resistor R61 in the auxiliary Miller clamp circuit 601 is connected to the Miller clamp terminal CLAMP of the built-in Miller clamp circuit 631, and the other end is connected to the node formed by connecting the cathode of the diode D62 and the emitter of the PNP transistor T61. The auxiliary Miller clamp circuits 602 and 603 are the same as the auxiliary Miller clamp circuit 601, and are not described in detail here.

[0062] The pulse width modulation signal locking device 64 includes a resistor R64 and a diode D64 connected in series. When the pulse width modulation signal outputted by the output terminal OUT of the driver chip 63 is at a low level VL, its Miller clamp terminal CLAMP is triggered to a low resistance state, and the resistor R64 and the diode D64 form a conductive path, thereby making the voltage of the Miller clamp terminal CLAMP less than VL minus the voltage drop of the diode D64, thereby clamping the voltage of the Miller clamp terminal CLAMP at a low level, avoiding signal interference from causing the potential of the Miller clamp terminal CLAMP to change, thereby affecting the switching state of the PNP transistor T61, and further avoiding the mis-conduction of the parallel metal oxide semi-field effect transistor.

[0063] Figure 7 1 is a circuit diagram of a driver for parallel switching transistors according to a fourth embodiment of the present invention. Figure 7 As shown, the driver 7 and Figure 5 The driver 5 shown is basically the same, except that the Miller clamp device 70 includes a driver chip 73 and the same auxiliary Miller clamp circuits 701, 702 and 703. The built-in Miller clamp circuit 731 of the driver chip 73 is a voltage source, which is used to output a high-level Miller enable signal. Each of the auxiliary Miller clamp circuits 701, 702, and 703 uses an NPN transistor to replace the PNP transistor in the auxiliary Miller clamp device 501, 502 or 503, and omits the resistor connected between the positive or negative electrode of the diode D72 and the Miller clamp terminal CLAMP of the built-in Miller clamp circuit 731.

[0064] Specifically, the auxiliary Miller clamp circuit 701 includes an NPN transistor T71, diodes D71 and D72, a resistor R72 and a capacitor C71, wherein the capacitor C71 is connected between the base and the collector of the NPN transistor T71, the resistor R72 is connected between the base of the NPN transistor T71 and the Miller clamp terminal CLAMP of the Miller clamp circuit 731, the cathode of the diode D71 is connected to the high-level DC voltage Vdd1, the node formed by the anode of the diode D71 and the anode of the diode D72 is connected to the gate of the metal oxide semi-field effect transistor Q71, and the cathode of the diode D72 is connected to the collector of the NPN transistor T71, and the emitter of the NPN transistor T71 is connected to the low-level DC voltage.

[0065] When the MOSFET Q71 is connected to a bridge arm, the MOSFET ( Figure 7When the MOSFET Q71 (not shown) is controlled to be turned on, the Miller current generated by the MOSFET Q71 flows from the drain to its gate through the parasitic Miller capacitor, and at the same time, the Miller clamp circuit 831 outputs a high-level Miller enable signal, so that the emitter junction of the NPN transistor T71 is forward biased, thereby the NPN transistor T71 is turned on, and the Miller current flows from the gate of the MOSFET Q71 through the diode D72 and the turned-on NPN transistor T71 to the low-level DC voltage Vss1. Therefore, no voltage drop will be generated between the gate and source of the MOSFET Q71, avoiding the mis-conduction of the MOSFET Q71.

[0066] In another embodiment of the present invention, the Miller clamp device 50 further includes Figure 6 The pulse width modulation signal in the locking device 64.

[0067] In other embodiments of the present invention, controllable transistors such as P-type metal oxide semiconductor field effect transistors can also be used instead of Figure 5 The PNP transistors or Figure 6 The PNP transistors in the auxiliary Miller clamp circuits 601, 602, and 603 are configured such that the gate of the P-type metal oxide semi-conductor field effect transistor is the control electrode, the source of the P-type metal oxide semi-conductor field effect transistor is connected to the gate of the corresponding switch transistor, and the drain of the P-type metal oxide semi-conductor field effect transistor is connected to the low-level DC voltage. In other embodiments of the present invention, controllable transistors such as N-type metal oxide semi-conductor field effect transistors can also be used instead of Figure 7 In the auxiliary Miller clamp circuits 701, 702, and 703, the gate of the N-type MOSFET is the control electrode, the drain is connected to the gate of the corresponding switch transistor, and the source is connected to a low-level DC voltage. The MOSFET has a faster switching speed and can achieve better dynamic performance.

[0068] The Miller clamp device of the present invention can also be used to perform Miller clamping on a plurality of parallel-connected switching transistors such as insulated gate bipolar transistors. The number of parallel-connected switching transistors is not limited to three, and can be more or less than three.

[0069] The driver of the present invention can select various models and types of driving power amplifiers, and can select various driving power amplifiers in the prior art that can amplify the power of pulse width modulation signals.

[0070] The Miller clamp device of the present invention can select various models and types of driver chips with built-in Miller clamp circuits.

[0071] Although the present invention has been described through preferred embodiments, the present invention is not limited to the embodiments described herein but includes various changes and modifications that may be made without departing from the scope of the present invention.

Claims

1. A Miller clamp device for parallel switching transistors, characterized in that: The Miller clamp device comprises: a driver chip comprising an output terminal and a built-in Miller clamp circuit having a Miller clamp terminal, the output terminal of the driver chip being used to output a pulse width modulated signal; and A plurality of auxiliary Miller clamp circuits, each of which is connected between the gate of a corresponding switch transistor and a Miller clamp terminal of the built-in Miller clamp circuit; Wherein, when the built-in Miller clamp circuit is triggered for Miller clamping, the Miller current generated by the corresponding switching transistor flows to the first DC voltage through the corresponding auxiliary Miller clamp circuit, and no current path of the Miller current is formed between the gate and source of each of the switching transistors; Each of the auxiliary Miller clamp circuits comprises: a controllable transistor comprising a control electrode, a first electrode and a second electrode, wherein the control electrode of the controllable transistor is connected to a Miller clamp terminal of the built-in Miller clamp circuit, and the second electrode is connected to the first DC voltage; A first diode, an anode of which is connected to the gate of the corresponding switch transistor, and a cathode of which is connected to the second DC voltage; and a second diode, an anode of which is connected to the anode of the first diode, and a cathode of which is connected to the first electrode of the controllable transistor; The second DC voltage is greater than the first DC voltage, and when the built-in Miller clamp circuit is triggered for Miller clamping, the first electrode and the second electrode of the controllable transistor are conductive.

2. The Miller clamp device according to claim 1, characterized in that: The built-in Miller clamp circuit is a current source for absorbing Miller current, and the controllable transistor is a first PNP type triode or a P-type metal oxide semi-field effect transistor; The base of the first PNP transistor or the gate of the P-type metal oxide semi-field effect transistor is connected to the Miller clamp terminal of the built-in Miller clamp circuit, the emitter of the first PNP transistor or the source of the P-type metal oxide semi-field effect transistor is connected to the gate of the corresponding switch transistor, and the collector of the first PNP transistor or the drain of the P-type metal oxide semi-field effect transistor is connected to the first DC voltage; Each of the auxiliary Miller clamp circuits further includes a first resistor connected between the Miller clamp terminal and the emitter of the first PNP transistor or the source of the P-type metal oxide semi-conductor field effect transistor.

3. The Miller clamp device according to claim 2, characterized in that: Each of the Miller clamp circuits further includes a second resistor connected between the Miller clamp terminal and the base of the first PNP transistor or the gate of the P-type metal oxide semi-conductor field effect transistor.

4. The Miller clamp device according to claim 2, characterized in that: Each of the auxiliary Miller clamp circuits further includes a first capacitor connected between the base and the emitter of the first PNP transistor or between the gate and the source of the P-type metal oxide semi-conductor field effect transistor.

5. The Miller clamp device according to claim 2, characterized in that: The driver further comprises a pulse width modulation signal locking device connected between the output terminal of the driver chip and the Miller clamp terminal, which is used to lock the potential of the Miller clamp terminal.

6. The Miller clamp device according to claim 5, characterized in that: The pulse width modulation signal locking device comprises a third diode and a third resistor connected in series.

7. The Miller clamp device according to claim 1, characterized in that: The built-in Miller clamp circuit is a voltage source that outputs a Miller enable signal; The controllable transistor is a first NPN transistor or an N-type metal oxide semi-field effect transistor, the base of the first NPN transistor or the gate of the N-type metal oxide semi-field effect transistor is connected to the Miller clamp terminal of the built-in Miller clamp circuit, the collector of the first NPN transistor or the drain of the N-type metal oxide semi-field effect transistor is connected to the gate of the corresponding switching transistor, and the emitter of the first NPN transistor or the source of the N-type metal oxide semi-field effect transistor is connected to the first DC voltage.

8. The Miller clamp device according to claim 7, characterized in that: Each of the auxiliary Miller clamp circuits further includes a fourth resistor connected between the Miller clamp terminal and the base of the first NPN transistor or the gate of the N-type metal oxide semi-conductor field effect transistor.

9. The Miller clamp device according to claim 7, characterized in that: Each of the auxiliary Miller clamp circuits further includes a second capacitor connected between the base and collector of the first NPN transistor or between the gate and drain of the N-type metal oxide semi-conductor field effect transistor.

10. The Miller clamp device according to claim 7, characterized in that: Each of the auxiliary Miller clamp circuits further includes a fourth diode connected between the anode of the first diode and the collector of the first NPN transistor or the drain of the N-type metal oxide semi-conductor field effect transistor.

11. The Miller clamp device according to any one of claims 1 to 10, characterized in that: Each of the auxiliary Miller clamp circuits is close to the gate of the corresponding switching transistor.

12. A driver, characterized in that: include: A Miller clamp device for parallel switching transistors according to any one of claims 1 to 11; as well as A plurality of driving power amplifying devices, each of which comprises an input terminal, a gate output terminal and a source output terminal, wherein the input terminal is connected to the output terminal of the driver chip in the Miller clamp device, the gate output terminal is connected to the gate of the corresponding switching transistor through a driving resistor, and the source output terminal is connected to the source of the corresponding switching transistor, and each of the driving power amplifying devices is used to power amplify the pulse width modulation signal output by the driver chip.

13. The driver according to claim 12, characterized in that: Each of the driving power amplifying devices comprises: a second NPN transistor and a second PNP transistor, the base of the second NPN transistor and the base of the second PNP transistor are connected to the output terminal of the driver chip, the collector of the second NPN transistor is connected to a third DC voltage, the collector of the second PNP transistor is connected to a fourth DC voltage, the emitter of the second NPN transistor and the emitter of the second PNP transistor are connected and serve as the gate output terminal of the driving power amplifier device, and the third DC voltage is greater than the fourth DC voltage; and Three capacitors, one end of each of the three capacitors is connected to the third DC voltage, the fourth DC voltage and the gate output terminal respectively, and the other ends of each of the three capacitors are connected and serve as the source output terminal of the driving power amplifier device.

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