Resist and Etch Modeling

Abstract

A computer-implemented method and computer program product have instructions for generating a transfer function that relates segments on a lithography photomask to features produced by lithography and etching operations using such segments. The method may be characterized by: (a) receiving detection results generated from post-development inspection of one or more first test substrates, where resist has been applied and patterned using a set of design layout segments; (b) receiving detection results generated from post-etch inspection of one or more second test substrates, where the one or more second test substrates were etched after resist was applied and patterned using the set of design layout segments; and (c) using the set of design layout segments together with corresponding detection results from post-development inspection and corresponding detection results from post-etch inspection to generate the transfer function.

Description

[0001] Incorporated by Reference

[0002] The PCT application form is filed concurrently with this specification as a part of this application. Each application to which this application claims the benefit or priority as identified in the concurrently filed PCT application form is incorporated herein by reference in its entirety and for all purposes. Background Art

[0003] The performance of semiconductor device manufacturing operations such as plasma assisted etching processes is often important to the success of semiconductor device processing flows. However, the optimization or adjustment of etching processes and / or tools associated therewith (e.g., etching reactors, photolithography masks, etc.) can prove to be technically difficult and time consuming, often involving a technician manually adjusting etching process parameters or tool component designs to generate a desired target feature profile. Although some progress has been made in developing automated procedures to determine mask designs and process parameters responsible for a desired etching profile, much room for improvement remains.

[0004] The background and context descriptions contained herein are provided only for the purpose of generally presenting the context of the present disclosure. Most of this disclosure presents the work results of the inventors, and it is not an admission that such work is prior art simply because it is described in the background section or presented as background elsewhere herein. Summary of the invention

[0005] Certain aspects of the present disclosure relate to methods for generating transfer functions that relate segments on a lithography photomask to features produced by lithography and etching operations using such segments. In some embodiments, the method can be characterized by the following operations: (a) receiving a set of design layout segments; (b) determining a resist feature profile from a computational resist model, wherein the set of design layout segments is provided as input to the computational resist model; (c) determining an etch feature profile from a computational etch model, wherein the photoresist feature profile is provided as input to the computational etch model; and (d) generating the transfer function using the set of design layout segments and the corresponding etch feature profile. Certain of the methods also include applying an inverse function of the transfer function to determine a design layout for a lithography mask.

[0006] In certain embodiments, the design layout section is a fragment or gauge provided in a GDS format.In certain embodiments, the resist feature profile and / or the etch feature profile is provided in a three-dimensional form.

[0007] In some embodiments, the method further comprises optimizing the computational resist model by using the inspection results of a wafer that has been subjected to lithography, wherein the lithography is performed on the wafer using one or more fragments from a design fragment database. In some such embodiments, optimizing the computational resist model is performed before (b). In some embodiments, the method further comprises optimizing the computational etch model by using the inspection results of a wafer that has been subjected to lithography and etching, wherein the lithography and etching are performed on the wafer using one or more fragments from a design fragment database. In some such embodiments, optimizing the computational etch model is performed before (c).

[0008] In some cases, the method further includes the following operations: (e) running the computational etching model multiple times, each time using a different set of process conditions; and (f) identifying, from the output of the computational etching model generated during (e), a selected set of process conditions for use during operation of the etching chamber.

[0009] Certain aspects of the present disclosure relate to a computer program product comprising a non-transitory computer-readable medium on which computer-executable instructions are provided for causing a computing system to generate a transfer function that relates segments on a lithography mask to features produced by lithography and etching operations using the segments. The computer-executable instructions may include instructions for: (a) receiving a set of design layout segments; (b) determining a resist feature profile from a computational resist model, wherein the set of design layout segments is provided as input to the computational resist model; (c) determining an etch feature profile from a computational etch model, wherein the resist feature profile is provided as input to the computational etch model; and (d) generating the transfer function using the set of design layout segments and the corresponding etch feature profile. In certain embodiments, the computer-executable instructions further include instructions for applying an inverse function of the transfer function to determine a design layout for a lithography mask.

[0010] For some computer program products, the design layout section is a snippet or gauge provided in a GDS format.For some computer program products, the resist feature profile and / or the etch feature profile is provided in a three-dimensional form.

[0011] In some embodiments, the computer executable instructions further include instructions for the following operations: optimizing the computational resist model by using the inspection results of a wafer that has been subjected to lithography, wherein the lithography is performed on the wafer using one or more fragments from a design fragment database. As an example, the instructions for optimizing the computational resist model may be configured to be executed before the instructions for (b). In some implementation schemes, the computer executable instructions further include instructions for the following operations: optimizing the computational etching model by using the inspection results of a wafer that has been subjected to lithography and etching, wherein the lithography and etching are performed on the wafer using one or more fragments from a design fragment database. As an example, the instructions for optimizing the computational etching model may be configured to be executed before the instructions in (c).

[0012] In some implementations, the computer-executable instructions further include instructions for: (e) running the computational etch model multiple times, each time using a different set of process conditions; and (f) identifying, from the output of the computational etch model generated during (e), a selected set of process conditions for use during operation of the etch chamber.

[0013] Other aspects of the disclosure relate to methods for generating transfer functions that relate segments on a lithographic photomask to features produced by lithography and etching operations using the segments. The method may be characterized by the following elements: (a) receiving detection results generated from post-development inspection of one or more first test substrates, where resist has been applied to the one or more first test substrates and patterned using a set of design layout segments; (b) receiving detection results generated from post-etch inspection of one or more second test substrates, where the one or more second test substrates were etched after resist was applied and patterned using the set of design layout segments; and (c) using the set of design layout segments together with corresponding detection results of post-development inspection and corresponding detection results of post-etch inspection to generate the transfer function. In certain embodiments, generating the transfer function involves running a computational resist model multiple times to provide a set of predicted post-development resist profiles.

[0014] In some cases, the method further comprises correcting the computational resist model using the detection results of the post-development inspection. In some cases, the method further comprises correcting the computational etch model using the detection results of the post-etch inspection. In some examples, generating the transfer function involves running the computational etch model multiple times to provide a set of predicted etch feature profiles.

[0015] In certain embodiments, the test results of the post-development inspection and / or the test results of the post-etching inspection are provided in a three-dimensional form. In certain embodiments, the test results of the post-development inspection and / or the test results of the post-etching inspection are provided as an xy profile using CD-SEM. In certain embodiments, the test results of the post-development inspection and / or the test results of the post-etching inspection are provided as an xz profile using TEM or CD-SAXS technology.

[0016] In certain embodiments, the set of design layout sections comprises snippets or gauges provided in a GDS format. In certain cases, the method further comprises applying an inverse function of the transfer function to determine a design layout for a lithography mask.

[0017] Certain other aspects of the present disclosure relate to a computer program product comprising a non-transitory computer-readable medium on which are provided computer-executable instructions for causing a computing system to generate a transfer function that relates segments on a lithography mask to features produced by lithography and etching operations using the segments. The computer-executable instructions may include instructions for: (a) receiving detection results generated from post-development inspection of one or more first test substrates, where resist has been applied to the one or more first test substrates and patterned using a set of design layout segments; (b) receiving detection results generated from post-etch inspection of one or more second test substrates, where the one or more second test substrates were etched after resist was applied and patterned using the set of design layout segments; and (c) using the set of design layout segments together with corresponding detection results from post-development inspection and corresponding detection results from post-etch inspection to generate the transfer function. In certain embodiments, the computer-executable instructions also include instructions for applying an inverse function of the transfer function to determine a design layout for a lithography mask.

[0018] In some implementations, the computer executable instructions further include instructions for correcting the computational resist model using the detection results of the post-development inspection. In some examples, the instructions for generating the transfer function include instructions for running the computational resist model multiple times to provide a set of predicted post-development resist profiles. In some implementations, the computer executable instructions further include instructions for correcting the computational etching model using the detection results of the post-etch inspection. In some examples, the instructions for generating the transfer function include instructions for running the computational etching model multiple times to provide a set of predicted etch feature profiles.

[0019] For some computer program products, the test results of the post-development inspection and / or the test results of the post-etch inspection are provided in three-dimensional form. For some program products, the test results of the post-development inspection and / or the test results of the post-etch inspection are provided as an xy outline of an image produced by a CD-SEM. For some computer program products, the test results of the post-development inspection and / or the test results of the post-etch inspection are provided as an xz outline of an image produced by a TEM or CD-SAXS. For some computer program products, the grouped design layout segments include fragments or gauges provided in a GDS format.

[0020] These and other features of the present disclosure will be presented in more detail below with reference to the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A system diagram is provided to depict the various operations (primarily detection operations) and logic modules (generally implemented in software) used to optimize resist models and etch models and to generate transfer functions that can be used to transform between patterns on a lithography mask (and segments including such patterns) and the contours produced by transferring such patterns to a resist and subsequently etching the substrate beneath the resist pattern.

[0022] Figure 2 is a diagram showing, in simplified and hypothetical form: the outline of a segment on a lithography photomask; the outline of a developed resist feature, which is exposed using the segment; and the outline of an etched feature produced by etching through the resist feature.

[0023] Figure 3A A family of gauges is described that may be used in a design snippet database, or otherwise used to (i) optimize a process simulation model (eg, a resist model or an etch model) and / or (ii) generate an approximate correction transfer function.

[0024] Figure 3B A segment or gauge illustrating different feature sizes (left) and a series of associated outlines produced by lithography, or by a resist pattern from a lithographic process.

[0025] Figure 4 An xz plane TEM micrograph of the developed resist coated with a conformal layer of material (dark grey layer on light grey resist features) is shown.

[0026] Figure 5A and 5B Examples of xz profiles of developed resist features are presented. Figure 5A Various resist feature profiles are illustrated in .

[0027] Figure 5C Exemplary xy profiles of developed resist features and subsequent etched features using the developed resist having the features are illustrated.

[0028] Figure 6 An exemplary computing system that may be used to optimize and / or use a process simulation model and / or generate a transfer function is shown. DETAILED DESCRIPTION

[0029] Technology and Model

[0030] Figure 1 An example system and related method for generating a transfer function, or a tool for using such a function in proximity correction, is provided to simultaneously account for both photolithography and certain other semiconductor device manufacturing operations such as etching operations. Other semiconductor device manufacturing operations are performed on a substrate having a patterned photoresist (or a mask pattern generated therefrom) to selectively etch or otherwise process areas of the substrate. For example, the profile of the etched features depends primarily on the profile of the resist features that form the mask for the etching process. See, for example, Figure 5B In addition, it has been found that the predictive power of the etch model (and the physical etching process itself) is strongly affected by the profile of the developed resist features provided as input to the etch model.

[0031] The system may have to correct or optimize the resist model and / or the device manufacturing operation model (e.g., etching model) to generate the appropriate transfer function. Although the description herein uses etching as an example of a device manufacturing operation and related models, the present disclosure extends to other device manufacturing operations such as epitaxial growth, selective deposition, and the like. In addition, although the description focuses on resist development to produce surface patterns, the present disclosure also extends to other patterning generation techniques. In general, the present disclosure relates to the joint optimization of two or more sequential semiconductor device manufacturing operations. In various embodiments, a transfer function is generated that takes into account the propagation of patterns across two or more consecutive manufacturing operations.

[0032] exist Figure 1 In the diagram, certain physical operations and tests are performed on one or more display wafers. These operations are depicted in the upper portion of the diagram. Various processing or software operations are performed on a combination of: (i) gauges or clips from a database, and (ii) data generated from the tests. The software / processing operations are presented as modules in the lower portion of the diagram.

[0033] In certain embodiments, Figure 1The systems and methods described in the present invention are used to design lithography photomasks for one or more semiconductor device manufacturing operations used in the production of integrated circuit chips. Other applications include designing improved lithography conditions and / or improved process windows for device manufacturing operations such as etching processes. Still other applications include designing improved lithography equipment and / or improved device manufacturing equipment such as etchers.

[0034] Design snippet database definition

[0035] exist Figure 1 In the embodiment of the present invention, a design snippet database is defined in operation 103. A snippet or gauge is a geometric feature or segment that can represent a small portion of a design layout. Although a full chip layout has all the segments of the full integrated circuit layer, a snippet or gauge is a small discrete segment that may be repeated throughout the full chip layout. Examples of snippets or gauges are small polygonal structures such as L-shaped structures, E-shaped structures, and the like. Figure 3A Presents an example of a gauge series, while Figure 3B The left figure shows an example of a gauge. The design snippet database is a collection of different snippets or gauges, whose common representation generally occurs in a full chip design layout or a series of different sections selected for some different purposes.

[0036] In certain embodiments, the design snippet database defines segments that are useful for one or more of the following functions: (1) optimizing resist models, (2) optimizing etch models, and (3) generating a set of segments and associated contours for producing transfer functions that account for both lithography and etch variations.

[0037] The design snippet database may contain snippets of an expected series of segment geometries that may occur in one or more photomasks for one or more integrated circuit chips. Typically, these segments will be expected to exist in photomasks for a process that uses lithography conditions and etching conditions for a given manufacturing operation. Ultimately, the resulting database may be reused for other processes that include the same or similar conditions and mask geometries.

[0038] Expose Demonstration Wafer

[0039] One or more demonstration wafers are provided to generate experimental results that can be used to correct or optimize the resist model and / or etch model for the production process. The demonstration wafer can be first coated with resist (generally as used for production) and then exposed to a radiation pattern (e.g., through a lithography photomask or by an electron beam). See operation 105. The lithography photomask is patterned with certain sections that constitute the design fragment database from operation 103. The lithography process conditions (e.g., focus and exposure) are recorded or otherwise made available for subsequent computational operations such as optimization or adjustment of the resist model. Although the present disclosure describes lithography and resist exposure in terms of lithography, the concepts can be directly transferred to electron beam lithography and other types of resist exposure used to define patterns in semiconductor device manufacturing operations.

[0040] After the one or more demonstration wafers are exposed in 105, they are developed under conditions (sometimes referred to as photolithography process windows) intended for use in a production process. As is known in the art, the exposed resist on the one or more demonstration wafers is chemically converted to allow for selective removal of portions of the photoresist that were exposed to radiation (e.g., UV light or an electron beam) or portions that were not exposed to radiation. Developed photoresist exists after removal of the exposed or unexposed portions.

[0041] The term "demonstration wafer" should be interpreted as including any non-production wafer or other substrate having features suitable for being measured, for example, in an inspection manner. A coupon, which may be a small portion of a wafer, is an example of a demonstration wafer. In addition to coupons and other non-standard forms of substrates having features, demonstration wafers may also be standard size wafers such as 200 mm wafers, 300 mm wafers, 450 mm wafers.

[0042] ADI Detection and Characterization

[0043] As in Figure 1 As described in , the one or more exposed demonstration wafers are subjected to post-development inspection (ADI) inspection and characterization. See operations 107 and 109. Examples of ADI inspection include critical dimension scanning electron microscope (CDSEM) and optical critical dimension (OCD) inspection. Other examples include transmission electron microscope (TEM) and critical dimension small angle X-ray scattering (CDSAXS). These inspections can be performed in the xy plane, which is viewed from top to bottom on the wafer and / or from a vantage point on the mask; or in the xz plane, which is viewed as a cross-section of the wafer features showing aspect ratios and feature profiles. Figure 5A and 5B An example of an xz profile of a feature of developed resist is illustrated in FIG. Figure 5AVarious resist feature profiles 503 are illustrated in FIG. 504. In certain embodiments, one or more inspections are selected to gather information in all three dimensions.

[0044] In certain embodiments, the developed photoresist is first coated with a material that does not significantly change the feature size in the photoresist and allows the features to be captured by TEM or other detection means. Figure 4 TEM micrograph of the developed resist profile coated with a conformal layer of display material (dark gray layer on light gray resist features) in the xz plane. The profile of the developed resist is shown as profile 403 (highlight line following the interface of the dark gray material and the light gray resist). The software program can be configured to define profile 403 by a cross-sectional micrograph of the developed resist coated with a conformal layer. In certain embodiments, the developed resist is conformally coated with an oxidized or nitrided material before imaging. Examples of such oxidized or nitrided materials and their imaging are described in U.S. Patent Application No. 16 / 015,096, filed on June 21, 2018, entitled "Protective Coating on Photoresist for Photoresist Metrology," which is incorporated herein by reference in its entirety.

[0045] The direct output of operation 109 is an image and / or data representing the two-dimensional (xy and / or xz) and / or three-dimensional profiles of the developed features in the photoresist of the one or more display wafers. The goal of operations 107 and 109 is to provide the profiles of the developed features in the photoresist (e.g., two-dimensional outlines in two perpendicular planes or full three-dimensional representations) that correspond to the segments in the design segment database. In other words, the inspection and characterization provide information of a one-to-one correspondence between the segments on the lithography photomask (generally directly corresponding to the geometry of the segments or gauges in the database) and the profiles of the photoresist features produced by exposure or development using the segments on the lithography photomask. With this information, a resist model can be corrected or optimized that predicts the photoresist profile produced using the lithography photomask segments. Additionally or alternatively, the xy resist pattern profiles or full three-dimensional representations obtained by inspection can be used to develop transfer functions, as described more fully below.

[0046] It is worth noting that lithographic conditions may vary from layer to layer during the manufacture of integrated circuit chips. Therefore, these demonstration wafers may be exposed to different lithographic conditions to provide various examples for optimizing resist models and / or generating transfer functions. Of course, ADI detection and characterization are performed for each experiment, which together spans a range of mask sections and / or lithographic process conditions.

[0047] Etched Demonstration Wafer

[0048] One or more demonstration wafers developed using a lithography photomask having sections corresponding to the segments or gauges in the design segment database are etched. See operation 111. The etching conditions are those used for the production process (or at least simulate the feature profiles produced using the production process). These etched demonstration wafers can be the same or different from the demonstration wafers used for ADI inspection in operation 109. It is worth noting that the ADI inspection process in operation 107 may render the photoresist unsuitable for use in the subsequent etching process, in which case a new demonstration wafer that was exposed as in operation 105 but not subjected to ADI inspection is used in etching operation 111.

[0049] Sometimes the etching conditions are collectively referred to as process windows, and they can be defined by various chemical and / or physical parameters such as etching reactor pressure, susceptor temperature, plasma generation conditions, process gas conditions (composition, flow rate, partial pressure, etc.), etc. These etching process conditions are recorded and made available for subsequent computational operations such as optimization or adjustment of etching models.

[0050] The demonstration wafer may be made of, or behave as, the material or material stack being etched, to be etched by a production process. In this way, the experimental etching results provide an accurate representation of the etching process to be modeled.

[0051] AEI detection and characterization

[0052] The one or more etched demonstration wafers (from operation 111) are subjected to post-etch inspection (AEI) testing and characterization. See operations 113 and 115. Examples of AEI testing include critical dimension scanning electron microscopy (CDSEM) and optical critical dimension (OCD) testing. Other examples include transmission electron microscopy (TEM). As with ADI testing and characterization, any of these tests can be performed in the xy plane or the xz plane. In certain embodiments, one or more tests are selected to collect information in all three dimensions.

[0053] The direct output of operation 115 is an image and / or data representing one or more two-dimensional (xy and / or xz) and / or three-dimensional profiles of features etched in the display wafer. The goal of these operations 113 and 115 is to provide profiles (e.g., two-dimensional outlines in two perpendicular planes or full three-dimensional representations) of features etched in the material or material stack being etched in the display wafer. These etched features correspond to segments in the design segment database. In other words, the detection and characterization provide information about the one-to-one correspondence between the segments on the lithography mask (which generally directly correspond to the geometry of the segments or gauges in the database) and the profiles of the etched features produced by the etched pattern produced by using the segments on the lithography mask. Using this information, an etching model can be corrected or optimized, which predicts the etching profile produced using the lithography mask segments. In addition or alternatively, the xy outlines of the etched features obtained by the detection can be used to develop transfer functions, as described more fully below.

[0054] As mentioned, the developed resist feature profile for a given process affects the etch feature profile generated in a subsequent etch process. Figure 5C An exemplary xy profile of a developed resist feature (513) and a subsequent etched feature (515) produced using the developed resist having feature 513 is illustrated.

[0055] It is worth noting that during the integrated circuit chip manufacturing process, etching conditions can vary from layer to layer. Therefore, these demonstration wafers can be exposed to different etching process windows to provide various examples for optimizing etching models and / or generating transfer functions. Of course, AEI detection and characterization are performed for each experiment, spanning a series of mask sections and / or etching process windows. AEI can vary from layer to layer in an integrated circuit wafer.

[0056] Figure 1 The boxes in the upper portion (above the dashed box) are used to generate data (optionally containing images). Such data can be fed into a program for generating a transfer function representing the outline or three-dimensional representation of the conversion of one or more segments on a lithography photomask to features printed on and subsequently etched into a substrate. Such data can alternatively or additionally be used to correct or optimize the resist model and the etch model.

[0057] Generate transfer function

[0058] The box inside the dashed rectangle is a collection of software modules and routines that can be used to generate a transfer function that takes into account the variations introduced by both lithography and etching (or more generally, any two consecutive device manufacturing operations that transfer a given pattern). The transfer function can show how the lithography process and the subsequent etching process transfer the outline of a lithography photomask (reticle) segment to the outline or three-dimensional representation of the feature resulting from the lithography and etching processes.

[0059] In some embodiments, as represented by the components in the dashed box, a semiconductor device manufacturer utilizes a software tool 117 for generating transfer functions to develop lithography photomasks for one of its specific etching and lithography processes. In some embodiments, a supplier of semiconductor manufacturing equipment (such as a supplier of lithography equipment and / or etching equipment) utilizes a software tool for generating transfer functions (proximity correction tool).

[0060] Resist Model

[0061] Within the software 117 is a resist model 119, which optionally requires correction or optimization. In certain embodiments, the resist model 119 is a focus exposure matrix (FEM) model. It can be implemented in various forms such as a regression model or a neural network (e.g., a convolutional neural network). For a given set of lithography conditions such as focus and exposure, it receives one or more lithography mask segments and outputs a predicted profile (e.g., three-dimensional profile, thickness, sidewall angle, footing, fillet, etc.) of the developed photoresist, which is developed under the lithography condition set and exposed via one or more photomask segments. Examples of suitable resist modeling software include Prolith, available from KLA-Tencor (Milpitas, CA). TM series simulators, and the Hyperlith available from Panoramic Technology Inc (Burlingame, CA) TM .

[0062] In certain embodiments, the resist model outputs a three-dimensional representation of the developed resist features. In certain embodiments, the resist model outputs a two-dimensional representation of the developed resist features on an xy or xz plane. In certain embodiments, the resist model outputs two two-dimensional representations, one on the xy plane and the other on the xz plane.

[0063] Optimizing resist models

[0064] In the absence of correction or optimization, the resist model 119 may be suitable for predicting the resist profile of the development. For example, the resist model 119 may have been pre-calibrated for the set of lithography conditions and mask sections to be used for production. However, assuming that the resist model 119 needs to be optimized, at least for process optimization under conditions, the data generated in the ADI characterization 109 can be used to iteratively correct the model. This is reflected in the optimization module 121 and its interaction with the resist model 119. The optimization module 121 receives: (i) data representing the ADI detection results from 109, and (ii) the resist profile after development predicted by the resist model 119. In some embodiments, the optimization module 121 receives multiple pairs of detection results and predicted resist profiles, each pair for different lithography photomask sections (as provided by the fragment or gauge group in the database 103). The difference between the profile predicted by the resist model 119 and the measured ADI result is used to adjust the floating parameters in the resist model or otherwise modify the model to improve its predictive ability. In general, this is an iterative method, wherein the modified resist model is provided with a new fragment or gauge set from the database 103, then the modified resist model predicts the resist profile generated, and then the resist profile is compared with the corresponding ADI detection result via data 109. The program continues iteratively until the model parameters or other adjustable features converge. As described below, the program for optimizing the resist model can share many similarities with the program for optimizing the etching profile. For example, data reduction and cost function optimization programs can be utilized.

[0065] Importing resist outlines into etch models

[0066] In the case where the resist model 119 is optimized, it can be used to reliably predict the resist profile after development. Therefore, the resist model 119 can be used in the next stage of developing the transfer function: optimizing the etch model 125. The process is started by providing a new subset of segments or gauges to the optimized resist model, which predicts the resist profile for those segments or gauges as indicated in operation 123 ("Import Resist Profile").

[0067] As in Figure 2 As illustrated in the simplified example of , the resist outline may have a rounded or rough outer contour 203 compared to a more geometrically precise photomask section 205 (eg, a gauge or segment for tool 117 ).

[0068] Etching Model

[0069] The etching model 125, which may optionally require correction or optimization, may be implemented in various forms such as a regression model, a lookup table, a support vector machine, or a neural network such as a convolutional neural network. Basically, for a given set of etching conditions such as etching reactor temperature, pressure, etchant composition, flow rate, plasma conditions, etc., the etching model 125 receives an initial layout (pre-etched surface topology of the substrate to be etched) defined by, for example, the photoresist profile (e.g., received at 123), and outputs a predicted etching profile (e.g., a two-dimensional or three-dimensional profile) of the substrate features etched under the etching condition set. The etching model 125 is an example of an etching profile model.

[0070] In certain embodiments, the etch model 125 is a SEMulator 3D etch model such as that available from Coventor, Inc. (Lam Research Company) in Cary, North Carolina. TM In some implementations, the behavioral model utilizes process abstraction to predict structural details of features resulting from one or more semiconductor device manufacturing operations. Examples of behavioral models are presented in U.S. Patent No. 9,015,016 filed by Lorenz et al. on November 25, 2008, and U.S. Patent No. 9,659,126 filed by Greiner et al. on January 26, 2015, each of which is incorporated herein by reference in its entirety.

[0071] In certain embodiments, the etching model 125 is a surface dynamic model (SKM) or a similar model that attempts to characterize the etching process by chemical reaction rate constants and / or other mechanical properties of the etching process. Examples of SKM models include specific models of M. Kushner and his collaborators, and certain models of Cooperberg and his collaborators. The former is described in, for example: Y. Zhang, "Low Temperature Plasma Etching Control through Ion Energy Angular Distribution and 3-Dimensional Profile Simulation," Chapter 3, dissertation, University of Michigan (2015), and the latter is described in: Cooperberg, Vahedi, and Gottscho, "Semiempirical profile simulation of aluminum etching in a Cl2 / BCl3 plasma," J. Vac. Sci. Technol. A 20 (5), 1536 (2002), both of which are incorporated herein by reference in their entirety. Additional descriptions of the etching profile model of M. Kushner and co-workers can be found in the following documents: J. Vac. Sci. Technol. A 15(4), 1913 (1997), J. Vac. Sci. Technol. B 16(4), 2102 (1998), J. Vac. Sci. Technol. A 16(6), 3274 (1998), J. Vac. Sci. Technol. A 19(2), 524 (2001), J. Vac. Sci. Technol. A 22(4), 1242 (2004), J. Appl. Phys. 97, 023307 (2005), each of which is also incorporated herein by reference in its entirety.

[0072] In certain embodiments, the etching model outputs a three-dimensional representation of the etching feature. In certain embodiments, the etching model outputs a two-dimensional representation of the etching feature in the xy or xz plane. In certain embodiments, the etching model outputs two two-dimensional representations, one in the xy plane and the other in the xz plane.

[0073] As mentioned, the predictive power of the etch model depends on the accuracy of the characterization of the developed resist profile used to perform the etch process. Figure 5B and 5C As shown in Figure 5C, although 5C shows the detection results of the actual physical etching process.

[0074] Optimizing Etch Models

[0075] In some embodiments, the etch model 125 is suitable for predicting etch profiles without correction or optimization. However, in many cases, it is not suitable and therefore requires optimization. The correction data can come from a variety of sources, but in some embodiments it includes: (a) measurement results of a demonstration wafer that was etched using the process that produced the etch model (the production process); and (b) the input photoresist layout that would be produced by the production lithography process. Figure 1 As depicted in , the etch model 125 may receive the process conditions used to etch the demonstration wafer at 111. The etch model 125 may also receive the resist profile 123 generated by the optimized version of the resist model 119. The resist profile should correspond to the segment or gauge used to etch the demonstration wafer at 111. Alternatively, the input resist profile may come from ADI measurement and characterization (107 and / or 109). The etch model 125 uses these inputs to predict the etch profile.

[0076] In the illustrated embodiment, the optimization module 127 receives (i) data generated in the AEI characterization 115, and (ii) an etch profile predicted by the etch model 125 to correct the etch model 125. In some embodiments, the optimization module 127 receives multiple pairs of detection results and predicted etch profiles, each pair for a different lithography photomask segment (as provided by a segment or gauge set in the database 103). The difference between the profile predicted by the etch model 125 and the measured AEI results 115 is used to adjust the floating parameters in the etch model or otherwise modify the model to improve its predictive ability. Generally speaking, this is an iterative method in which a new set of input resist profiles (predicted by the optimized resist model 119 based on the segment or gauge provided from the database 103) is provided to the modified etch model, and then the modified etch model predicts the resulting etch profile, which is then compared to the corresponding AEI detection results via the data 115. The process continues iteratively until the model parameters or other adjustable features converge.

[0077] Use optimized resist and etch models to generate transfer functions

[0078] When reliable versions of the resist model 119 and etch model 125 exist—via, for example, verification by an optimization process such as described above—they can be used to generate reliably predicted outlines or three-dimensional representations of etched features produced using a combination of the lithography process modeled by the resist model 119 and the subsequent etch process modeled by the etch model 125. Any given segment or gauge can be provided to the resist model 119, which outputs a resist profile for a given set of lithography conditions, which can then be provided as input to the etch model 125. The etch model 125 then processes the resist profile and the etch conditions to output an etch profile for that segment or gauge.

[0079] In some embodiments, using a set of segments or gauges representing multiple sections in a full chip photomask layout, an optimized resist model 119 and an optimized etch model 125 working in conjunction as described above generate a series of etch profiles corresponding to the segments or gauges. Thus, each segment or gauge has a corresponding etch profile that is predicted to be produced by the modeled lithography process and etching process (e.g., a process used to manufacture layers in the production of integrated circuit chips). Figure 2 The exemplary etched feature outline 207 in FIG. 1 shows the context of the photomask segment 205 and the resist feature outline 203 .

[0080] The profile generation module 129 reflects the generation of the profile. It is noteworthy that the resist model 119 and the etching model 125 can generate a three-dimensional profile, which includes the x and y dimensions on the plane parallel to the surface (or on the surface) of the wafer or the integrated circuit chip observed from above, and the z dimension in the direction orthogonal to the wafer surface or the integrated circuit surface. In some scenarios, the profile is a two-dimensional representation that only includes the x and y dimensions. It is noteworthy that only the x and y dimensions are used for the design layout provided by the tapeout and implemented in the lithography photomask. The profile generation module 129 receives the three-dimensional etching profile output from the optimized version of the etching model 125 and outputs the two-dimensional (xy) profile associated with the fragment or gauge used as the input of the resist model 119. In some embodiments, the profile is generated by indicating the z-direction height in the etching profile or by indicating the material of the stack to be etched. In some embodiments, the profile generation module 129 outputs the full three-dimensional representation of the etched feature.

[0081] In some embodiments, the contour is also provided via detection. Thus, for example, the xy contours generated in operations 107 / 109 and / or 113 / 115 (see, for example, Figure 5C ) is used in conjunction with the xy etch profile simulated by the model in the profile generation module or operation 129.

[0082] Finally, the system 117 (which may be implemented as a set of software modules) generates, either alone or in combination with the inspection results, a set of mask segments (selected segments or gauge sets from the database 103) and corresponding three-dimensional representations or outlines of features produced using the expected production photolithography process and etching process. Using these paired mask segments and the resulting etched outlines, the reduced modeling module 131 generates a transfer function. As explained, the transfer function relates the outline of the photomask segment to the outline or three-dimensional representation of the feature produced by the semiconductor device manufacturing operation using the photomask segment to produce the corresponding etched feature. For example, the reduced modeling module 131 identifies patterns in the relationship between the set of mask segments and the corresponding set of etched feature outlines (produced using the resist model and the etching model) to define the transfer function. The module 131 generates the transfer function by any of a variety of protocols. In one example, it uses a machine learning system such as a convolutional neural network or a recurrent neural network. The transfer function itself may be in the form of any of a variety of relationships or models including neural networks, lookup tables, regression models, random forest models, semi-empirical relationships, and the like.

[0083] In certain embodiments, the compact modeling module 131 also uses information about the physics and / or chemistry of the etching process to develop the transfer function. For example, the module 131 may consider plasma constituent fluxes (e.g., ions, radicals, and / or deposited species), visibility kernels (entry into features), etc. The module 131 generates the transfer function regardless of whether the xy profile (or full 3D representation) is used alone or in combination with the physical / chemical characterization of the etching process.

[0084] The inverse of the transfer function (a function that outputs the mask segment that will produce a particular etched feature profile) can be used to provide a proximity correction. The inverse transfer function can be generated using the compact modeling module 131 or another software. Regardless of how it is generated, the inverse transfer function can be used, for example, as shown in FIG. Figure 1 The full chip OPC (optical proximity correction) tool 133 in FIG. As is known in the art, a full chip OPC tool is used to design a proximity corrected lithography photomask for a desired design layout, which may be provided via an approved electronic CAD file of the full chip layer of the integrated circuit design. Examples of full chip OPC tools include the Tachyon 3D printer available from ASML Brion of Veldhoven, The Netherlands. TM SMO, and Calibre available from Mentor Graphics of Fremont, California TM .

[0085] In other embodiments, the processes described herein can be utilized to generate transfer functions for lithography and subsequent semiconductor manufacturing operations other than etching. Examples of such other semiconductor manufacturing operations include deposition on a patterned surface, including selective deposition on a surface having two or more different materials.

[0086] the term

[0087] A snippet or gauge is a section of a full chip layout. The snippet or gauge may be generated from a test mask or a snippet test mask (i.e., containing only one of the polygons of interest) and may be provided in a GDS format (e.g., a GDSII format). GDS is an example of a standard format for design layouts containing so-called polygons: some include GDSII "Graphic Database System" and OASIS (Open Artifact Interchange Standard). A gauge file reader may read a test mask (as known in some optical proximity correction scenarios) to see the location of the sections of interest to be modeled. These are snippets or gauges provided in a design snippet database. Gauges may include coordinates in X / Y, label protocols, CD / spacing designs as drawn in the layout, and the like. Snippets or gauges are provided in two-dimensional form, parallel to the plane of the integrated circuit chip or lithography mask.

[0088] As used herein, a "feature" is a non-planar structure on a substrate surface, typically a surface that is modified during semiconductor device manufacturing operations. Examples of features include: trenches, vias, pads, columns, domes, and the like. Features may be formed by photoresist development, mask definition, photolithographic etching, photolithographic deposition, epitaxial growth, damascene deposition, and the like. Features generally have an aspect ratio (ratio of depth or height to width). Examples of feature aspect ratios include: at least about 1:0.5, at least about 1:1, at least about 2:1, at least about 5:1, at least about 10:1, or higher aspect ratios. In certain embodiments, a feature has a width dimension (which may be a critical dimension) between about 10 nm and 500 nm, such as between about 25 nm and about 300 nm. The feature profile may taper at the feature opening and / or include an overhang. A concave profile is an example of narrowing from the bottom or interior of a feature to the feature opening.

[0089] In various contexts herein, feature profile refers to a three-dimensional representation of the feature, and feature outline refers to a two-dimensional representation of the feature, typically viewed from the top down across the plane of an integrated circuit chip.

[0090] A production process is a photolithography patterning process, an etching process, or other semiconductor device manufacturing operation used to produce a commercial integrated circuit chip. Production processes are used in an integrated circuit manufacturing facility. An integrated circuit supplier (such as Intel or Qualcomm) provides a design for an integrated circuit, and the design is translated into a commercial integrated circuit chip by performing production processes in a manufacturing facility. Multiple production processes are used to manufacture each layer of an integrated circuit chip.

[0091] Transfer Function - A function that converts the outline of one or more segments of a lithographic photomask into the outline and / or three-dimensional representation of one or more features corresponding to the one or more segments and produced by a semiconductor device manufacturing operation (such as lithography or etching or a combination thereof) that attempts to transfer the shape of the one or more segments to a substrate to be processed. The outline of the photomask segment is generally a polygon with sharp vertices and straight lines connecting adjacent vertices. The outline of the corresponding feature produced by a semiconductor device manufacturing operation such as lithography and / or etching is generally more rounded at the vertices and the line segments between the rounded vertices are jagged. As used herein, the term transfer function applies broadly to both the inverse of a transfer function and a transfer function. It should be understood that any transfer function may also be considered an inverse transfer function, depending on the perspective of the user or application.

[0092] The terms "semiconductor wafer", "wafer", "substrate", "wafer substrate", and "partially manufactured integrated circuit" are used interchangeably. Those of ordinary skill in the art will appreciate that the term "partially manufactured integrated circuit" may refer to a semiconductor wafer during any of many stages of integrated circuit fabrication. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. This specific embodiment assumes that the implementation is implemented on a wafer. However, the present disclosure is not limited to this. The workpiece may have a variety of shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various articles of manufacture, such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0093] As used herein, a "semiconductor device manufacturing operation" is a unit operation performed during the manufacture of a semiconductor device. In general, all manufacturing processes include multiple semiconductor device manufacturing operations, each performed in its own semiconductor manufacturing tool, such as a plasma reactor, an electroplating tank, a chemical mechanical planarization tool, a wet etching tool, and the like. Types of semiconductor device manufacturing operations include: subtractive processes, such as etching processes and planarization processes; and material addition processes, such as deposition processes. In the context of an etching process, a substrate etching process includes a process for etching a mask layer, or more generally, a process for etching any material layer previously deposited on a substrate surface and / or otherwise remaining on a substrate surface. Such an etching process can etch stacked layers in a substrate.

[0094] As used herein, a "result of a semiconductor device manufacturing operation" is a feature of a substrate subjected to a semiconductor manufacturing operation. One example of such a result is a geometric profile of a substrate after a semiconductor manufacturing operation. The profile is a set of points in space that represent the location of a feature or a set of features. For example, the profile may be a profile of an etched feature, a profile of a deposited feature, a profile of a planarized feature, and the like. In another example, the result of a semiconductor manufacturing operation is a signal generated by the interaction of incident electromagnetic radiation with one or more substrate features such as an etched feature, a deposited feature, or a planarized feature. In such an example, the result may be, for example, a reflection signal that may include a reflection intensity as a function of wavelength and / or polarization state. The result may also be an elliptically polarized signal. In another example, the result of a semiconductor manufacturing operation is a set of profile parameters such as optical critical dimension ("OCD") profile parameters that characterize the geometry of a feature such as an etched feature, a deposited feature, or a planarized feature. Such profile parameters may characterize the overall characteristics of a feature, such as its average critical dimension, its sidewall angle, its depth, and the like.

[0095] The result of the semiconductor manufacturing operation can be obtained at one time point or multiple time points during the semiconductor manufacturing operation. If the result is only provided at one time point, the time point may be the time point when the semiconductor manufacturing operation is completed.

[0096] As used herein, "computational predictions of semiconductor device manufacturing operations" are predictions of semiconductor device manufacturing operations that are computationally generated, such as by a computational model (e.g., a process simulation model for the device manufacturing operation under consideration). In certain embodiments, the computational process calculates a predicted feature profile represented by geometric profile coordinates. In other cases, the computational process calculates a predicted optical response generated by the interaction of electromagnetic radiation with the predicted feature profile. In other cases, the computational process calculates predicted geometric profile parameters of the feature profile (e.g., a set of OCD profile parameters characterizing the geometry of the calculated etching profile), such as generated by the semiconductor device manufacturing operation. In certain embodiments, the feature profile, optical response, and / or profile parameters are calculated as a function of time (during which the semiconductor device manufacturing operation occurs). In certain embodiments, the computational process predicts local reaction rates at grid points representing the feature profile of the semiconductor substrate to predict the results of the semiconductor device manufacturing operation. This results in a substrate / feature profile that deviates from the initial profile used at the beginning of the calculation.

[0097] Where the computational processing calculates a predicted optical response, it may be possible to calculate a reflection spectrum or ellipsometric response by simulating the reflection of electromagnetic radiation from the calculated etch profile. The reflection spectrum or ellipsometric response may be generated using, for example, a rigorous coupled wave analysis ("RCWA") simulation or a finite difference time domain ("FDTD") simulation.

[0098] In some embodiments, the computational processing generates a time series of geometric profiles or profile parameters of substrate features. In some embodiments, the computational processing generates a time series of calculated reflectance spectra or ellipsometric responses generated by simulating reflections of electromagnetic radiation from the calculated substrate feature profiles at different times. The time series can be generated during different periods of semiconductor device manufacturing operations. Computational predictions of semiconductor device manufacturing operations can be provided for use in substrate removal processing and / or substrate addition processing.

[0099] As used herein, "detection result" means a result generated at least in part by measuring the characteristics of a processed substrate. The determination may be performed during or after the semiconductor device manufacturing operation is performed in a reaction chamber, and the reaction chamber is operated under the condition of the fixed set of process parameter values. In some embodiments, the processed substrate features are measured to generate profile coordinates. In such embodiments, measuring the processed substrate features may include performing microscopy (e.g., SEM, TEM, STEM, REM, AFM) or optical detection on an etched substrate. When optical detection is used, the system can obtain these coordinates by calculating the profile coordinates from the measured optical detection signal. In some embodiments, the detection result is generated by converting the measured feature profile coordinates into a set of geometric profile parameters, which characterize the geometry of the feature in the processed substrate (e.g., critical dimensions, sidewall angles, depth, etc.). In some embodiments, the detection result is generated by performing reflection measurement, dome scattering measurement, angle-resolved scattering measurement, small-angle X-ray scattering, and / or elliptical polarization on the processed substrate. In some embodiments, the detection result is an endpoint detection of a specific process. The endpoint detection that can be determined in situ can be measured by various optical techniques.

[0100] In certain embodiments, the inspection results are provided as a time series of measured geometric profiles, reflectivity or ellipsometric data, or profile parameters of substrate features.These measured inspection results are generated during different periods of semiconductor device manufacturing operations.

[0101] As used herein, a "process simulation model" is a computational model that predicts the outcome of a semiconductor device manufacturing operation. In other words, it outputs the outcome. As explained, examples of outcomes include feature profiles (e.g., detailed Cartesian coordinates of the feature), profile parameters that characterize the feature (e.g., critical dimensions, sidewall angles, depth, etc.), and / or reflectivity / ellipsometry data generated if optical inspection is used to detect the feature. The outcome is based on features generated or adjusted during the simulated semiconductor device manufacturing operation. The outcome can be predicted at one or more time points during the semiconductor device manufacturing operation.

[0102] The input to the process simulation model includes one or more process parameter values ​​that characterize the semiconductor device manufacturing operation. Typically, the process parameters used as input are reactor conditions such as temperature (pedestal, showerhead, etc.), plasma conditions (density, potential, power, etc.), process gas conditions (composition such as component partial pressure, flow rate, pressure, etc.), etc. In general, the process simulation model also receives an initial profile substrate that represents the profile of the substrate surface immediately before being processed by the modeled semiconductor device manufacturing operation. In a simple example, the initial profile is just a flat surface. More generally, the initial profile has features such as mask or photoresist features.

[0103] Sometimes, the process simulation model simulates a subtractive process such as a substrate etching process or a planarization process. In various embodiments, the process simulation model is an etch profile model as described herein. Sometimes, the process simulation model simulates an additive process such as a substrate deposition process (e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.). In certain embodiments, the process simulation model is a resist model as described above.

[0104] As used herein, a "constructed process simulation model" describes a process simulation model constructed with one or floating process model parameters. When so constructed, and after receiving input process parameters and a substrate initial profile, the process simulation model can be executed to predict the results of semiconductor device manufacturing operations.

[0105] As used herein, a "process parameter" is a parameter that characterizes a process that occurs in a reaction chamber or lithography apparatus during a semiconductor device manufacturing operation (often on a substrate surface modified by the operation). In general, a number of such process parameters are required to uniquely characterize the process. Certain process parameters characterize aspects of the process that are relatively easy to control and / or measure. Examples of such process parameters include: temperature (temperature of the pedestal, showerhead, etc.), plasma conditions (plasma density, plasma potential, applied power, etc.), process gas conditions (composition such as component partial pressures, flow rates, pressures, etc.), and adjustable chamber geometry parameters such as the spacing between the pedestal and the showerhead. Other process parameters characterize aspects of the process that are not directly controllable and / or not easily measured. Examples of such process parameters include: local conditions such as plasma density, direction, or energy at a location on the substrate surface; and mechanical properties such as reaction rate constants, adhesion coefficients of reactants and / or products, reactant diffusion constants, product diffusion constants, light dispersion properties, and combinations thereof. The values ​​of process parameters are used as input or construction of a process simulation model. The value can be a scalar, vector, matrix, tensor, etc.

[0106] As used herein, a "fixed process model parameter" is a process parameter required by a process simulation model, but the value of the process parameter is fixed during an optimization process for improving the performance of the process simulation model. In other words, the value of the fixed process model parameter does not change during the optimization process. This is different from a floating process model parameter, the value of which changes during the optimization execution. In certain embodiments, the fixed process model parameter is directly controllable and / or easily determined. Examples include: the temperature in the reaction chamber, one or more applied radio frequency frequencies or plasma conditions in the reaction chamber, one or more processing gas conditions in the reaction chamber, the pressure in the reaction chamber, or any combination thereof. However, the fixed process model parameter may alternatively be a local or mechanical parameter. Sometimes for the convenience of the model optimization process described herein, the value of a fixed process model parameter or a set of such values ​​is represented by the symbol μ.

[0107] As used herein, a "floating process model parameter" is a process parameter that is required by a process simulation model, but during the optimization process, the value of the process parameter floats (changes, adjustments, etc.). Iterative adjustment of the floating process model parameter value from an initial or seed value to a final value is the goal of the model optimization process. If the optimization procedure is successful, the process simulation model constructed with the final value of the floating process model parameter provides better prediction capabilities than the process simulation model constructed with the initial value of the floating process model parameter.

[0108] In some embodiments, the floating process model parameters represent characteristics of the substrate undergoing the semiconductor device manufacturing operation. General examples include difficult to measure local conditions in the reactor and / or mechanical properties of the reaction during the semiconductor device manufacturing operation. In some examples, the characteristic is a reaction rate constant, a sticking coefficient of reactants and / or products, a reactant diffusion constant, a product diffusion constant, a local plasma characteristic (e.g., ion flux, ion direction, free radical flux, etc. at the substrate surface), a light dispersion property, or any combination thereof. However, the floating process model parameters are not limited to such parameters. Parameters that may be more typically used as fixed process model parameters may also be used or used as or as part of these floating process model parameters. Examples of such non-mechanical parameters include: temperature in a reaction chamber, one or more RF conditions in a reaction chamber, one or more process gases in a reaction chamber, pressure in a reaction chamber, applied plasma conditions, or any combination thereof. In some embodiments, the floating process model parameters include more overall focused parameters for a given process, which are represented by a process simulation model. Examples of such floating process model parameters include: longitudinal etch rate, lateral etch rate, vertical etch depth, etch selectivity, longitudinal deposition rate, plasma angle dependence of sputtering rate, and plasma energy dependence of sputtering rate, all for a given material for a given semiconductor device manufacturing operation. Other examples of floating process model parameters include: tilt angle of ion inlet, twist angle of ion inlet, visibility of etching and / or deposition (e.g., inside a feature), angular distribution (sometimes referred to as source sigma), sticking coefficient (sometimes referred to as isotropic ratio), sputter maximum yield angle, sputtering rate, and etch rate per crystal direction, all also for a given material for a given semiconductor device manufacturing operation.

[0109] In various embodiments, the floating process model parameter combines any two or more process model parameters that characterize the substrate undergoing the semiconductor device manufacturing operation. The combination can be the product or sum of individual parameter values, either of which can be weighted based on the relative importance of the individual parameter to the predictive power of the model or based on other factors. Sometimes, the values ​​of some or all of these individual parameters are normalized before the combination. In certain embodiments, the individual values ​​are provided as independent contributions in the form of vectors. In an example, the combination of parameters can be ion density and the reaction rate with the material on the surface. Without considering any other factors, the probability of removal will be proportional to the product of the ion density, reaction rate, substrate material density, and the surface area of ​​the original profile. Therefore, ion density and reaction rate cannot be determined separately, but their product can. In some cases, the floating process model parameters do not have a known association with a specific physical and / or chemical treatment of the device manufacturing operation. When optimizing the behavioral process simulation model, such floating process model parameters can be appropriate.

[0110] During the iterative optimization process, at any iteration, the value of the floating process model parameter is referred to as the "current value" of the floating process model parameter. The value of the parameter during the previous iteration may be referred to as the previous value of the floating process model parameter, and the value of the parameter during the consecutive iteration may be referred to as the consecutive value of the floating process model parameter. The adjustment of the value of the floating process model parameter from one iteration to the next is sometimes referred to as an update of the current value of the floating process model parameter. At the end of the iterative optimization process, the value of the floating process model parameter is referred to as the final value of the floating process model parameter.

[0111] "Optimizing" a process simulation model, such as a resist model or an etch model as described herein, is used to improve the ability of the process simulation model to predict the results of the semiconductor device manufacturing operation that the model is designed to simulate. Generally, in the discussion here, the optimization program optimizes the process simulation model by iteratively adjusting the current values ​​of one or more floating process model parameters. During the optimization, the calculated predicted results of the process simulation model (which use the current values ​​of the floating process model parameters) can be compared with the experimentally determined results (e.g., measured results) when both the predicted results and the experimentally determined results are generated for the same semiconductor device manufacturing operation. The comparison step provides a cost value that reflects the size of the difference (or agreement) between the predicted / simulated results and the experimentally determined results. The optimization program uses the cost value to at least: (i) determine whether the values ​​of the floating process model parameters converge, and (ii) if the values ​​do not converge, decide how to adjust the current values ​​of the floating process model parameters for the next iteration. In some embodiments, the process uses not only the cost value of the current iteration, but also all or some of the previous cost values ​​of the historical iterations to seek the global optimum.

[0112] As used herein, "comparing" the value of the calculated predicted result of the process simulation model with the value of the experimentally measured result (e.g., the detection result) means comparing one or more features or indices of the two results. The comparison provides one or more cost values ​​for optimizing the process. Examples of differences (cost values) include L1 and L2 norms, Euclidean distances, and Mahalanobis distances in a multidimensional result space. As an example of using results with multiple features or indices, the comparison can be completed by extracting multiple indices that describe the differences. As an example, these indices can be critical dimension (CD) differences at multiple heights of the feature, process endpoint differences (e.g., differences at the end of an etching process), thickness differences of a given material, or spectrum differences in a complete spectrum. These indices constitute a cost function for optimization: the function can also be a combination of them, with respective weight factors for each. The cost function is sometimes referred to here as a "difference," which should be interpreted more broadly than the simple mathematical operation A minus B.

[0113] As used herein, when a process simulation model constructed with floating process model parameter values ​​performs properly for an applicable application, the floating process model parameter values ​​"converge". Various convergence criteria are known in the art and can be applied. Some of them are described below. In general, cost values ​​are evaluated in each iteration in the optimization program. The cost values ​​generated during a single iteration can be evaluated individually or in combination with cost values ​​from other iterations. Such an evaluation allows the optimization program to perform a convergence check. If the one or more cost values ​​indicate that the current value of the floating process model parameter provides a process simulation model that performs acceptably and / or no longer significantly improves, the optimization program terminates the process and determines that the current value of the floating process model parameter is the final value. The optimization program has converged. Therefore, in certain embodiments, the convergence method determines when the error of the parameter estimate (cost function) can no longer be improved. This allows the Bayesian diagram to solve the problem. The convergence check can search for a local or global minimum (or maximum, depending on the structure of the cost value) in the cost value.

[0114] Etching Outline Model

[0115] Etch profile models (EPMs) are a type of etching model as described herein. They calculate theoretically determined etch profiles from a set of input etching reaction parameters (independent variables) that characterize certain features of the etching reaction, such as certain potential physical and chemical etching processes and reaction mechanisms. These processes can be modeled as a function of time and position in a grid that represents the etched feature and its surroundings. Examples of input parameters include: plasma parameters such as ion flux, and chemical reaction parameters such as the probability that a particular chemical reaction will occur. Other examples include: characteristics of the substrate being etched (e.g., layer-by-layer description of thickness and material), initial mask layout for one or more features to be etched, processing chamber conditions, and the like. Such parameters can be obtained from a variety of sources, including other models that calculate the parameters from general reactor configurations and process conditions such as pressure, substrate temperature, plasma source parameters (e.g., power, frequency, duty cycle supplied to the plasma source), reactants and their flow rates. In certain embodiments, such models can be part of an EPM.

[0116] EPM treats such parameters as independent variables (which may be fixed and / or floating in the context of the optimization procedure described herein) and functionally generates an etch profile as a response variable. In other words, a set of independent variables are parameters used as model inputs, and the response variable is the etch profile feature calculated by the model. EPM can utilize one or more relationships between reaction parameters and etch profiles. These relationships may include, for example, coefficients, weights, and / or other model parameters (as well as linear functions of reaction parameters and / or other model parameters, quadratic or higher order polynomial functions, etc.), which are applied to the independent variables in a defined manner to generate a response variable associated with the etch profile. Such weights, coefficients, etc. may represent one or more of the above-mentioned reaction parameters. In certain embodiments, these model parameters are floating process model parameter values ​​that are adjusted or regulated during the optimization techniques described herein. In certain embodiments, certain reaction parameters are model parameters to be optimized, while others are used as fixed process model parameters. For example, in certain embodiments, chemical reaction parameters may be floating process model parameters that may be optimized, while plasma parameters may be fixed process model parameters.

[0117] As explained, some EPMs utilize basic reaction mechanical parameters and may be considered the basis of potential chemical and physical properties, so the experimental process engineer generally cannot control these quantities. In the etch profile model, these variables can be applied at each location of the grid and at multiple times separated by defined time steps. In some embodiments, the grid resolution can vary between about a few angstroms and about one micron. In some embodiments using time-dependent modeling, the time step can vary between about le-15 and le-10 seconds. In some embodiments, the optimization uses two mechanical independent variables: (1) local plasma parameters, and (2) local chemical reaction parameters. These parameters are "local" in the sense that these parameters can change the position function, and in some cases can change the resolution of the grid. Examples of plasma parameters include local plasma characteristics, such as flux and energy of particles such as ions, free radicals, photons, electrons, excited substances, deposited substances, and their energy and angular distribution. Examples of chemical and physicochemical reaction parameters include: rate constants (e.g., the probability that a particular chemical reaction will occur at a particular time), adhesion coefficients, energy thresholds for etching, reference energies, energy exponents that define sputtering rates, angular yield functions and their parameters, etc. In addition, parameterized chemical reactions may include reactions in which reactants include the material being etched and an etchant. It should be appreciated that chemical reaction parameters may include various types of reactions in addition to reactions that directly etch the substrate. Examples of such reactions include side reactions, including: parasitic reactions, deposition reactions, reactions of byproducts, and the like. Any of these reactions may affect the overall etching rate. It should also be appreciated that the model may require other input parameters in addition to the above-mentioned plasma and chemical reaction input parameters. Examples of such other parameters include: temperature, partial pressure, or reactants at the reaction site, etc. In some cases, these and / or other non-mechanical parameters may be input into a module that outputs certain mechanical parameters. In some embodiments, the model does not use (at least not directly) mechanical parameters.

[0118] Initial (unoptimized) values ​​for EPM model variables, as well as variables that are fixed during optimization (e.g., plasma parameters in certain embodiments), can be obtained from various sources such as literature, calculations by other computational modules or models, etc. In certain embodiments, independent input variables (such as plasma parameters) can be determined using a model, for example, in the case of plasma parameters, from an etch chamber plasma model. Such a model can calculate applicable input EPM parameters from various process parameters that a process engineer can control (e.g., by turning knobs)—e.g., chamber environmental parameters such as pressure, flow rate, plasma power, wafer temperature, ICP coil current, bias / power, pulse frequency, pulse duty cycle, etc.

[0119] EPM can take any one of many different forms. Ultimately, they provide a relationship between an independent variable and a response variable. The relationship can be linear or nonlinear. In certain embodiments, EPM is referred to in the art as a cell-based Monte Carlo surface reaction model. These models operate in various forms to simulate the topological evolution of wafer features over time in a semiconductor wafer manufacturing scenario. These models emit pseudo-particles with energy and angular distributions generated by plasma models or experimental diagnosis of any radial position on the wafer. The pseudo-particles are statistically weighted to represent the flux of free radicals and ions to the surface. These models solve various surface reaction mechanisms that cause etching, sputtering, mixing, and deposition on the surface to predict profile evolution. During Monte Carlo integration, various ions and neutral pseudo-particles are tracked in the wafer features until they react or leave the computational domain. EPM has advanced functions for predicting etching, stripping, atomic layer etching, ionized metal physical vapor deposition, and plasma-assisted chemical vapor deposition on various materials.

[0120] In certain embodiments, the EPM utilizes a rectilinear mesh in two or three dimensions that has a fine enough resolution to adequately address / model the dimensions of wafer features (although in principle the mesh (whether 2D or 3D) may also use non-rectilinear coordinates). The mesh may be viewed as an array of grid points in two or three dimensions. It may also be viewed as an array of cells representing 2D local areas, or 3D volumes, associated with (or centered around) each grid point. Each cell within the mesh may represent a different solid material or mixture of materials. The choice of a 2D or 3D mesh as the basis for modeling may depend on the class / type of substrate features being modeled. For example, a 2D mesh may be used to model long trench features (e.g., in polysilicon substrates), where the 2D mesh characterizes the cross-sectional shape of the trench under the assumption that the geometry of the ends of the trench is not very relevant to the reaction processes occurring over most of the trench length away from the ends (i.e., for the cross-sectional 2D model, the trench is assumed to be infinite, which is also a reasonable assumption for trench features away from the ends). On the other hand, it may be appropriate to model circular through-hole features (through silicon vias (TSVs)) using a 3D mesh (since the x, y horizontal dimensions of the features are identical to each other).

[0121] The mesh spacing can range from, for example, sub-nanometers (e.g., from 1 angstrom) up to several microns (e.g., 10 microns). In general, each mesh cell is assigned a material property, such as: photoresist, polysilicon, vapor-phase etchant, or plasma (e.g., in regions of space not occupied by features), which can change during profile evolution. Solid-phase materials can be represented by material properties in computational cells; gas-phase materials can be represented by computational pseudo-particles. In this way, the mesh provides a reasonably detailed representation of the substrate features as well as the surrounding gas environment (e.g., plasma) (e.g., for computational purposes) as the geometry / topology of wafer features evolves over time during a reactive etch process.

[0122] Some of the foregoing descriptions focus on process simulation models, such as surface dynamic models, which utilize mechanical representations of semiconductor device manufacturing operations. Such models are described in more detail in U.S. Patent Application Publication No. 20170228482, filed on February 8, 2016, and U.S. Patent Application Publication No. 20170363950, filed on June 21, 2016, both of which are incorporated herein by reference in their entirety. However, certain embodiments use quite different models to represent semiconductor device manufacturing operations. In some cases, the model does not use (at least not directly) mechanical parameters that attempt to explain the underlying chemical or physical properties in the semiconductor device manufacturing operations. For example, a behavioral model can utilize process abstraction to predict the structural details of features produced by one or more semiconductor device manufacturing operations. An example of a behavioral model is SEMulator3D from Coventor (Lam Research Company). TM Examples of behavioral models are shown in US Pat. No. 9,015,016 and US Pat. No. 9,659,126, both of which were previously incorporated by reference.

[0123] In various embodiments, the process simulation models described herein model features in three dimensions. In some cases, the process simulation models described herein predict the impact of semiconductor device manufacturing operations not just on one feature, but on a group of features across an area in a design layout (e.g., in a large multi-device area).

[0124] Although the foregoing description focuses on etch models, the present disclosure also relates to other models such as models for predicting the effects of a planarization process or a deposition process on a substrate.

[0125] Experiment and profilometry

[0126] In order to optimize a process simulation model such as a resist model and / or an etch model, various experiments may be performed to determine, as accurately as the experimentation allows, the actual profiles produced by the actual processes performed under the various process conditions as specified by the various sets of process parameters. Thus, for example, one specifies a first set of values ​​for a set of process parameters such as etchant flow rate, plasma power, temperature, pressure, etc., sets the chamber arrangement accordingly, flows the etchant into the chamber, strikes the plasma, etc., and proceeds to process a first semiconductor substrate to produce a first profile. A second set of values ​​for the same set of process parameters is then specified, a second substrate is processed to produce a second profile, and so on.

[0127] Various combinations of process parameters can be used to appropriately present a broad or concentrated process space to optimize the process simulation model. The same combination of process parameters is then used to calculate (independent variable) input parameters such as mechanical parameters through the process simulation model to provide a profile output (response variable) that can be compared with experimental results. Because experiments can be expensive and time-consuming, techniques can be used to design experiments in a way that reduces the number of experiments that need to be performed to provide a robust training group that optimizes the process simulation model. Techniques such as experimental design (DOE) can be used for this purpose. In general, such techniques determine which set of process parameters to use in various experiments. They select a combination of process parameters by considering statistical interactions between process parameters, randomization, and the like. As an example, DOE can determine a small number of experiments that cover a limited range of parameters around the center point of the completed process.

[0128] In some approaches, the researcher will perform all experiments early in the model optimization process and use only those experiments in the optimization process iterations until convergence. Alternatively, the experimental designer may perform certain experiments for early iterations of the optimization and perform additional experiments thereafter as the optimization progresses. The optimization process may inform the experimental designer of the specific parameters to be evaluated and therefore the specific experiments to be performed for subsequent iterations.

[0129] One or more in-situ or offline inspection tools can be used to measure the experimentally generated profiles that result from these experimental process operations. The measurements can be made at the end of the process, during the process, or at one or more times during the process. When the measurements are made at the end of the process, the measurement method is destructive; when the measurements are made at intervals during the etching process, the measurement method will generally be non-destructive (so etching will not be interrupted). Examples of suitable inspection techniques include, but are not limited to: in-situ reflectometry, OCD, cross-sectional SEM, and others mentioned above. It is worth noting that the inspection tool can directly measure the feature profile, such as in the case of SEM (where the experiment is essentially imaging the etch profile of the feature); or it can indirectly measure the feature etch profile, such as in the case of OCD measurement (where some post-processing is done to back-out the etch profile of the feature from the actual measurement data). Inspection techniques can be classified by where they are performed and what they do to the sample; the classifications include: in-situ, offline non-destructive, and destructive inspection. For example, in-situ inspection includes: reflectometry and ellipsometry; for example, offline non-destructive inspection includes: single wavelength and broadband OCD inspection or scatterometry, dome scatterometry, CD-SAXS, and CD-SEM (top-down SEM); and for example, destructive inspection includes: X-SEM, STEM, and TEM.

[0130] In any event, the result of the experimental and detection procedures is a set of measured profiles, each of which typically comprises a series of values ​​for a series of coordinates or a set of grid values ​​representing the shape of a feature profile as described above. The profiles are then used as input to train, optimize, and improve the computational etch profile model as described herein.

[0131] Reflectometry and ellipsometry spectral analysis and modeling tools

[0132] When using a process simulation model to generate feature profile values, the optical parameters resulting from the geometry can be modeled or predicted using an optical modeling program such as the RCWA method or similar techniques.

[0133] RCWA is just one feature that can be used to describe the reflected (diffracted, scattered) radiation from a periodic structure (such as a grating) or through such a grating. RCWA was primarily developed by Moharam and Gaylord and is described in the scientific literature. See, for example: MG Moharam and TK Gaylord "Rigorous coupled-wave analysis of planar-grating diffraction" J. Opt Soc of America, Vol. 71, Issue 7, pp. 811-818 (1981), which is incorporated herein by reference in its entirety. RCWA calculates the intensity and polarization characteristics of various diffraction orders (zero and higher). Other optical modeling methods that can provide results include, but are not limited to: C-method, modal method, Rayleigh approximation, EFIE (electric field integral equation), and Cf-FFT (conjugate gradient-fast Fourier transform).

[0134] RCWA is a semi-analytical method in computational electromagnetics that is often used to solve scattering from periodic dielectric materials. It is a Fourier space method, so the device and the fields are represented as a sum of spatial harmonics. The method is based on Floquet's theorem, where the solution of periodic differential equations can be expanded by Floquet functions (or sometimes called block waves, especially in solid-state physics). A device is divided into layers that are uniform in the z direction. For curved devices with properties such as dielectric permittivity that varies gradually along the z direction, a step approximation is required. The electromagnetic modes in each layer are calculated and propagation through these layers is analyzed. The boundary conditions are matched at each interface between layers using techniques such as scattering matrices to solve the overall problem. In order to solve the electromagnetic modes determined by the wave vector of an incident plane wave in a periodic dielectric medium, Maxwell's equations (in partial differential form) and boundary conditions are expanded by Floquet functions and transformed into infinite algebraic equations. Depending on the required accuracy and convergence speed, with truncation of higher-order Frog functions, this infinite linear equation becomes finite and can therefore be solved by a computer.

[0135] Another way to computationally generate optical parameters that are generated (or are generable) by the interaction of a beam with substrate features is by using the finite-difference time-domain (FDTD) method. This is a numerical analysis technique for modeling electrodynamics. This is a grid-based finite-difference method for finding approximate solutions to the time-dependent Maxwell equations in partial differential form. The equations are discretized in time and in spatial partial derivatives. The resulting finite-difference equations are solved in a jumpy manner: the components of the electric field vector in a volume of space are solved at a given time instant, followed by the components of the magnetic field vector in the same volume of space at the next instant, and this process is repeated until the desired instantaneous or steady-state electromagnetic field is calculated.

[0136] Convergence Check

[0137] The floating process model parameter optimization procedure may be an iterative nonlinear optimization procedure—for example, it optimizes an error metric or cost value, which is typically a nonlinear function of the input parameters—and, therefore, may use various techniques known in the art for nonlinear optimization. See, for example: Biggs, MC, "Constrained Minimization Using RecursiveQuadratic Programming," Towards Global Optimization (LCWDixon and G.P. Szergo, eds.), North-Holland, pp 341–349, (1975); Conn, NR, NIMGould, and Ph.L. Toint, "Trust-Region Methods," MPS / SIAM Series on Optimization, SIAM andMPS(2000); Moré, JJand DCSorensen, “Computing a Trust Region Step,” SIAMJournal on Scientific and Statistical Computing, Vol.3, pp 553–572, (1983); Byrd, RH, RBSchnabel, and GAShultz, “Approximate Solution of the Trust RegionProblem by Minimization over Two-Dimensional Subspaces," Mathematical Programming, Vol. 40, pp 247–263 (1988); Dennis, JE, Jr., "Nonlinear least-squares," State of the Art in Numerical Analysis ed. D. Jacobs, Academic Press, pp 269–312 (1977); Moré, JJ, "The Levenberg-Marquardt Algorithm: Implementation and Theory," Numerical Analysis, ed. GAWatson, Lecture Notes in Mathematics 630, Springer Verlag, pp 105–116 (1977); Powell, MJD, "A Fast Algorithm for Nonlinearly Constrained Optimization Calculations," Numerical Analysis, G. A. Watson ed., Lecture Notes in Mathematics, Springer Verlag, Vol. 630 (1978), each of which is incorporated by reference in its entirety.

[0138] In general, the comparison for calculating the cost compares the multiple aspects or indices of the calculation prediction with the detection results. The difference between the values ​​generated by the calculation of these indices and the measured values ​​of these indices constitutes the cost function for optimization. Examples of indices include: the critical dimension (CD) difference of multiple heights of materials, the thickness difference of a given material, and the spectrum difference of the overall spectrum. The cost function can be a combination thereof, optionally with weights for each. The difference can be expressed as L1 or L2 norm, Euclidean distance, and Mahalanobis distance, etc. In certain embodiments, these techniques optimize the objective function (here, the cost function / value), which is subject to certain constraints imposed on the input parameters and / or error metrics. In certain such embodiments, the restriction function itself may be nonlinear. For example, in an embodiment in which the calculated etching profile is represented by a set of stacked trapezoids output by a process simulation model, the cost value can be defined as the difference between the area represented by the boundaries of these stacked trapezoids and the area of ​​the experimental etching profile measured. In such a case, the error metric is a non-linear function of the response variable output by the process simulation model, and therefore a constrained optimization technique is chosen from those just described (and from the incorporated references) that allows specification of non-linear constraints.

[0139] Application of optimized process simulation model

[0140] The transfer functions disclosed herein can be useful in semiconductor processing flows where detailed evaluation and characterization of an etch process is required. For example, if a new etch process is developed, the transfer function can be used to determine etch profile characteristics for many combinations of process parameters without having to go into the lab and perform each experiment individually. In this way, the transfer function can allow for faster process development cycles and, in certain embodiments, can significantly reduce the amount of work required to fine-tune a target profile.

[0141] Lithographic operations and mask development can greatly benefit from accurate transfer functions. U.S. Patent Application No. 15 / 367,060, filed December 1, 2016 (incorporated herein by reference in its entirety), describes edge placement error detection and lithographic mask design. It is worth noting that there are at least two levels of design layout correction that can be applied in this context: lithography and etch. In other words, both optical and etch-based considerations can be used to determine mask layout. The etch-based considerations are determined using a model prepared as described herein.

[0142] To make a photolithography mask using layout decisions as described herein, the process starts with a so-called blank, which contains a glass substrate coated with a chromium layer and a resist layer. Sometimes a material other than or in addition to chromium is used. For example, an attenuated phase-shift mask uses an additional layer such as a molybdenum silicide layer. The resist can be a positive resist or a negative resist. During electron beam exposure, the pattern formed is formed on the resist, which can be transferred to the chromium layer below by an etching process. The chromium provides an opaque area on the photolithography mask that casts a shadow during exposure of the semiconductor wafer.

[0143] The fabrication of a photolithography mask is a similar lithography step during semiconductor device fabrication. However, the exposure of the resist is performed by an electron beam rather than light (e.g., deep UV). The blank is exposed to electron beam radiation, which impinges on the resist in locations specified by a mask design layout, which is determined at least in part using an EPM of the type described herein. The mask is then developed to produce a pattern of the layout. The now formed resist pattern is then transferred to the underlying chrome by an appropriate etching process (e.g., plasma or wet etching). Thereafter, the resist is removed and the exposed chrome pattern is covered with a pellicle to prevent contamination.

[0144] The transfer functions disclosed herein may also be useful for solving reciprocal problems: where a specific target etch profile is desired and one or more specific combinations of lithography or process parameters (or EPC input parameters) are desired to achieve the specific target etch profile. Again, this can be accomplished by experimental trial and error, but an accurate transfer function can replace the need for experimentation, or at least replace the need for experimentation in the initial stages of exploring the process / input parameter space until good candidates can be identified for a complete experimental study. For example, the etching model of blocks 125 and 127 can be iteratively run at various process conditions within a process window that is reliably handled by the model, and after each run, the streamlined model determines whether the resulting etch feature profile / outline is within specification or optimized. After locking in a set of process conditions that produce the desired etch feature / outline, the process recipe is fixed. And now, the inverse transfer function identifies the mask layout to be used in conjunction with the process recipe.

[0145] Background of the Disclosed Computing Implementations

[0146] Certain embodiments disclosed herein relate to systems for generating and / or using process simulation models and / or transfer functions. Certain embodiments disclosed herein relate to methods for generating and / or using process simulation models implemented on such systems. The system for generating a process simulation model may be configured to analyze data for correcting or optimizing a representation or relationship, which is used to represent the impact of a semiconductor device manufacturing operation on a substrate. The system for generating a process simulation model and / or a transfer function may also be configured to receive data and instructions such as program codes representing physical processes occurring during semiconductor device manufacturing operations. In this way, a process simulation model and / or a transfer function is generated on such a system and programmed. A programmed system for using a process simulation model and / or a transfer function may be configured to: (i) receive inputs such as process parameters that characterize semiconductor device manufacturing operations and / or initial design layouts or masks for generating features in a substrate, and (ii) execute instructions for determining the impact of semiconductor device manufacturing operations on a substrate. Finally, the system may calculate time-dependent (or time-independent) results of semiconductor device manufacturing operations.

[0147] Many types of computing systems having any of a variety of computer architectures may be implemented as disclosed systems for implementing process simulation models and transfer functions; and algorithms for generating and / or optimizing such models and functions. For example, the system may include software components executed on one or more general purpose processors or specially designed processors, such as programmable logic devices (e.g., field programmable gate arrays (FPGAs)). In addition, the system may be implemented on a single device or distributed across multiple devices. The functions of the computing elements may be merged with each other or further divided into multiple sub-modules.

[0148] In certain embodiments, the code executed during the generation or execution of a process simulation model on an appropriately programmed system may be implemented in the form of a software element that may be stored in a non-volatile storage medium (such as a CD, a flash memory device, a removable hard drive, etc.) and contains a large number of instructions for manufacturing a computer device (such as a personal computer, a server, a network device, etc.).

[0149] At one level, software elements are implemented as a set of commands prepared by a programmer / developer. However, modular software that can be executed by computer hardware is executable code submitted to memory using "machine code" that is selected from a specific machine language instruction set or "native instruction" designed into the hardware processor. The machine language instruction set, or native instruction set, is known to one or more hardware processors and is essentially built into them. This is the "language" by which system and application software communicate with the hardware processors. Each native instruction is a discrete code that is recognized by the processing architecture and that may specify a specific register for arithmetic, addressing, or control functions; a specific memory location or offset; and a specific addressing mode for interpreting operands. More complex operations are constructed by combining these simple native instructions, which are executed in sequence or otherwise directed by control flow instructions.

[0150] The relationship between executable software instructions and hardware processors is structural. In other words, the instructions themselves are a series of symbols or numerical values. They do not inherently convey any information. It is the processor that is pre-configured by design to interpret the symbols / numerical values ​​that gives the instructions meaning.

[0151] The models used herein can be configured to execute on a single machine at a single location, on multiple machines at a single location, or on multiple machines at multiple locations. When multiple machines are used, each machine can be tailored for its specific task. For example, operations that require large blocks of code and / or significant processing power can be implemented on large and / or fixed machines.

[0152] In addition, certain embodiments relate to tangible and / or non-transitory computer-readable media or computer program products, which include program instructions and / or data (including data structures) for performing various computer-implemented operations. Examples of computer-readable media include, but are not limited to: semiconductor memory devices; phase change devices; magnetic media such as disk drives, tapes; optical media such as CDs, magneto-optical media; and hardware devices specifically constructed to store and execute program instructions, such as read-only memory (ROM) and random access memory (RAM). Computer-readable media can be directly controlled by an end user, or the media can be indirectly controlled by an end user. Examples of directly controlled media include media located at the user's plant and / or media that is not shared with other entities. Examples of indirectly controlled media include media that is indirectly accessible to users via an external network and / or via a service that provides shared resources such as the "cloud". Examples of program instructions include: both machine code such as that produced by a compiler and files containing higher-level code that can be executed by a computer using an interpreter.

[0153] In various embodiments, the data or information used in the disclosed methods and devices are provided in electronic format. Such data or information may include: design layout, fixed parameter values, floating parameter values, feature profiles, test results, etc. As used herein, data or other information provided in electronic format can be used for storage on a machine and transmission between machines. Conventionally, data in electronic format is provided in digital form and can be stored as bits and / or bytes in various data structures, lists, databases, etc. The data can be implemented electronically, optically, etc.

[0154] In certain embodiments, the process simulation model and / or transfer function can each be considered a form of application software that interfaces with the user and with the system software. The system software is generally connected to the computer hardware and associated memory. In certain embodiments, the system software includes: operating system software and / or hardware, and any intermediate software and drivers installed in the system. The system software provides the basic non-task specific functions of the computer. In contrast, modules and other application software are used to complete specific tasks. Each native instruction for a module is stored in a memory device and represented by a numerical value.

[0155] An exemplary computer system 800 is depicted in Figure 6As shown, computer system 800 includes an input / output subsystem 802, which can implement an interface for interacting with a human user and / or other computer systems depending on the application. The invention embodiments can be implemented in program code on system 800, which has an I / O subsystem 802 for receiving input program statements and / or data from a human user (e.g., via a GUI or keyboard) and displaying them to the user. I / O subsystem 802 can include, for example: a keyboard, a mouse, a graphical user interface, a touch screen, or other input interface; and, for example: an LED or other flat screen display, or other output interface.

[0156] The program code may be stored in a non-transitory medium such as persistent storage 810 or memory 808 or both. One or more processors 804 read the program code from one or more non-transitory media and execute the code to enable the computer system to perform the methods performed by the embodiments herein, such as those involving the generation or use of process simulation models as described herein. Those skilled in the art will appreciate that the processor may accept source code such as statements for performing training and / or modeling operations, and interpret or compile the source code into machine code that is understandable at the hardware gate level of the processor. The bus couples the I / O subsystem 802, the processor 804, the peripheral device 806, the memory 808, and the persistent storage 810.

[0157] in conclusion

[0158] In this specification, numerous specific details are set forth to provide a full understanding of the embodiments presented. The disclosed embodiments may be practiced without some or all of these specific details. In other cases, known process operations are not described in detail so as not to unnecessarily obscure the disclosed embodiments. Although the disclosed embodiments are described in conjunction with the specific embodiments, it should be understood that the specific embodiments are not intended to limit the disclosed embodiments.

Claims

1. A method of generating a transfer function that relates a segment on a lithography photomask to a feature produced by lithography and etching using the segment, the method comprising: (a) receiving a group of design layout segments; (b) determining a resist feature profile from a computational resist model, wherein the set of design layout segments is provided as input to the computational resist model; (c) determining an etch feature profile from a computational etch model, wherein the resist feature profile is provided as an input to the computational etch model; and (d) generating the transfer function using the set of design layout segments and the corresponding etch feature profiles, wherein: The transfer function is a model for predicting etch characteristics in an input design layout segment resulting from a lithography process represented by the computational resist model and a subsequent etch process represented by the computational etch model.

2. The method according to claim 1, wherein: The design layout section is a snippet or rubric provided in a GDS format.

3. The method of claim 1 further comprising optimizing the computational resist model by using inspection results of wafers that have undergone photolithography, wherein The lithography is performed on the wafer using one or more fragments from a design fragment database.

4. The method of claim 3, wherein the optimization of the computational resist model is performed before (b).

5. The method of any one of the preceding claims, further comprising optimizing the computational etching model by using inspection results of wafers that have been subjected to lithography and etching, wherein The lithography and etching are performed on the wafer using one or more fragments from a design fragment database. The method of claim 5 , wherein said optimizing said computational etching model is performed before (c).

7. The method of any one of claims 1-4, further comprising applying an inverse function of the transfer function to determine a design layout for a lithography mask.

8. The method according to any one of claims 1 to 4, further comprising: (e) running the computational etching model multiple times, each time using a different set of process conditions; and (f) identifying, from the output of the computational etch model generated during (e), a selected set of process conditions for use during operation of the etch chamber.

9. The method according to any one of claims 1 to 4, wherein the resist feature profile and / or the etch feature profile is provided in a three-dimensional form.

10. A computer program product comprising a non-transitory computer readable medium on which are provided computer executable instructions for causing a computing system to generate a transfer function relating segments on a lithography photomask to features produced by lithography and etching operations using the segments, wherein the instructions include instructions for: (a) receiving a group of design layout segments; (b) determining a resist feature profile from a computational resist model, wherein the set of design layout segments is provided as input to the computational resist model; (c) determining an etch feature profile from a computational etch model, wherein the resist feature profile is provided as an input to the computational etch model; and (d) generating the transfer function using the set of design layout segments and corresponding etch feature profiles, wherein: The transfer function is a model for predicting etch characteristics in an input design layout segment resulting from a lithography process represented by the computational resist model and a subsequent etch process represented by the computational etch model.

11. The computer program product according to claim 10, wherein: The design layout section is a snippet or rubric provided in a GDS format.

12. The computer program product of claim 10, further comprising instructions for optimizing the computational resist model by using inspection results of wafers that have undergone photolithography, wherein The lithography is performed on the wafer using one or more fragments from a design fragment database.

13. The computer program product of claim 12, wherein instructions for optimizing the computational resist model are arranged to be executed before instructions for (b).

14. The computer program product of any one of claims 10-13, further comprising optimizing the computational etching model by using inspection results of wafers that have been subjected to lithography and etching, wherein The lithography and etching are performed on the wafer using one or more fragments from a design fragment database.

15. The computer program product of claim 14, wherein instructions for optimizing the computational etch model are arranged to be executed before the instructions in (c).

16. The computer program product of any one of claims 10-13, further comprising instructions for applying an inverse function of the transfer function to determine a design layout for a lithography mask.

17. The computer program product according to any one of claims 10 to 13, further comprising instructions for: (e) running the computational etching model multiple times, each time using a different set of process conditions; and (f) identifying, from the output of the computational etch model generated during (e), a selected set of process conditions for use during operation of the etch chamber.

18. The computer program product according to any one of claims 10-13, wherein the resist feature profile and / or the etch feature profile is provided in three-dimensional form.

19. A method of generating a transfer function that relates a segment on a lithography photomask to a feature produced by a lithography and etching operation using the segment, the method comprising: (a) receiving inspection results resulting from post-development inspection of one or more first test substrates on which a resist has been coated and patterned using a set of design layout segments; (b) receiving a post-etch inspection inspection result generated from one or more second test substrates that were etched after resist was applied and patterned using the set of design layout segments; as well as (c) using the grouped design layout segments together with corresponding post-development inspection results and corresponding post-etch inspection results to generate the transfer function, wherein the transfer function is a model for predicting etch features in the input design layout segments resulting from a photolithography process represented by a computational resist model and a subsequent etching process represented by a computational etch model.

20. The method of claim 19, further comprising correcting the computational resist model using detection results of the post-development inspection.

21. The method of claim 20, wherein generating the transfer function comprises running the computational resist model multiple times to provide a set of predicted post-development resist profiles.

22. The method of any one of claims 19-21, further comprising correcting the computational etch model using detection results of the post-etch inspection.

23. The method of claim 22, wherein generating the transfer function comprises running the computational etch model multiple times to provide a set of predicted etch feature profiles.

24. The method according to any one of claims 19 to 21, wherein the detection result of the post-development inspection and / or the detection result of the post-etching inspection is provided in a three-dimensional form.

25. The method of any one of claims 19-21, wherein the inspection results of the post-development inspection and / or the inspection results of the post-etch inspection are provided as xy profiles using CD-SEM.

26. The method of any one of claims 19-21, wherein the inspection results of the post-development inspection and / or the inspection results of the post-etch inspection are provided as an xz profile using TEM or CD-SAXS techniques.

27. The method of any one of claims 19-21, wherein the set of design layout sections comprises snippets or rubrics provided in a GDS format.

28. The method of any one of claims 19-21, further comprising applying an inverse function of the transfer function to determine a design layout for a lithography mask.

29. A computer program product comprising a non-transitory computer readable medium on which are provided computer executable instructions for causing a computing system to generate a transfer function relating segments on a lithographic photomask to features produced by lithography and etching using the segments, wherein the instructions include instructions for: (a) receiving inspection results resulting from post-development inspection of one or more first test substrates on which a resist has been coated and patterned using a set of design layout segments; (b) receiving a post-etch inspection inspection result generated from one or more second test substrates that were etched after resist was applied and patterned using the set of design layout segments; as well as (c) using the grouped design layout segments together with corresponding post-development inspection results and corresponding post-etch inspection results to generate the transfer function, wherein the transfer function is a model for predicting etch features in the input design layout segments resulting from a photolithography process represented by a computational resist model and a subsequent etching process represented by a computational etch model.

30. The computer program product of claim 29, further comprising computer executable instructions for correcting the computational resist model using detection results of the post-development inspection.

31. The computer program product of claim 30, wherein the instructions for generating the transfer function include instructions for running the computational resist model multiple times to provide a set of predicted post-development resist profiles.

32. The computer program product of any one of claims 29-31, further comprising computer executable instructions for correcting the computational etch model using the detection results of the post-etch inspection.

33. The computer program product of claim 32, wherein the instructions for generating the transfer function include instructions for running the computational etch model multiple times to provide a set of predicted etch feature profiles.

34. The computer program product according to any one of claims 29 to 31, wherein the detection result of the post-development inspection and / or the detection result of the post-etch inspection is provided in a three-dimensional form.

35. The computer program product of any one of claims 29-31, wherein the post-development inspection detection results and / or the post-etch inspection detection results are provided as xy contours of an image generated by a CD-SEM.

36. The computer program product of any one of claims 29-31, wherein the detection results of the post-development inspection and / or the detection results of the post-etch inspection are provided as an xz profile of an image produced by TEM or CD-SAXS.

37. The computer program product of any one of claims 29-31, wherein the set of design layout sections comprises snippets or rubrics provided in a GDS format.

38. The computer program product of any one of claims 29-31, further comprising computer executable instructions for applying an inverse function of the transfer function to determine a design layout for a lithography mask.

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