Charge sharing circuit, method, display driving module and display device

Abstract

The present invention provides a charge sharing circuit, method, display driver module, and display device. The charge sharing circuit includes a control unit and a switch unit. The control unit is electrically connected to the first output control terminals of two clock signal generation units, respectively, and is configured to provide an on control signal to the switch unit via the control signal output terminal when the first output module, under the control of the first output control signal, does not output a first voltage signal. Under the control of the on control signal, the switch unit controls the connection between the clock signal output terminals of the two clock signal generation units. The present invention can reduce the number of level conversion circuits used, saving chip area.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a charge sharing circuit, method, display driving module and display device. Background Art

[0002] In a display device, considering the need for power saving, gate charge sharing needs to be implemented between pixel circuits in different rows, transferring the charge on the gate of the transistor to be turned off to the gate line of the transistor to be turned on, thereby reducing gate turn-on power consumption.

[0003] In a display device, the gate drive signal connected to the gate of the data writing transistor in the pixel circuit is controlled by the clock signal provided by the corresponding clock signal generating circuit. Therefore, a shared switch can be set between the clock signal output ends of the clock signal generating units at different levels to achieve gate charge sharing of the data writing transistors in the pixel circuits of different rows on the display panel.

[0004] In the existing charge sharing circuit, a shared signal is generated based on the first clock signal and the second clock signal, and then the shared signal is converted to a low voltage VGL negative voltage power domain through a level conversion circuit, and then converted to a shared switch power domain through another level conversion circuit to control the on and off of the shared switch; the existing charge sharing circuit uses a large number of level conversion circuits, which occupies a large chip area. Summary of the Invention

[0005] The main purpose of the present invention is to provide a charge sharing circuit, method, display driving module and display device to solve the technical problem that the existing charge sharing circuit adopts a large number of level conversion circuits and occupies a large chip area.

[0006] In order to achieve the above-mentioned object, the present invention provides a charge sharing circuit, which is applied to a display device, wherein the display device includes a gate driving circuit and a clock signal generating circuit, the gate driving circuit includes a multi-stage shift register unit; the clock signal generating circuit includes at least two clock signal generating units; two clock signal generating units in the at least two clock signal generating circuits respectively provide corresponding clock signals for two adjacent shift register units; the clock signal generating unit includes a clock signal output terminal, a first output control terminal and a first output module, the first output module is used to control whether to output a first voltage signal through the clock signal output terminal under the control of a first output control signal provided by the first output control terminal; the charge sharing circuit includes a control unit and a switch unit, wherein,

[0007] The control unit is electrically connected to the first output control terminals included in the two clock signal generating units, respectively, and is configured to provide an opening control signal to the switch unit through the control signal output terminal when the first output module controls not to output the first voltage signal under the control of the first output control signal;

[0008] The switch unit is electrically connected to the control signal output end and the clock signal output ends included in the two clock signal generating units respectively, and is used to control the connection between the clock signal output ends included in the two clock signal generating units under the control of the opening control signal.

[0009] Optionally, the switching unit includes a first switching transistor and a second switching transistor;

[0010] The control electrode of the first switch transistor and the control electrode of the second switch transistor are both electrically connected to the control signal output terminal;

[0011] a first electrode of the first switching transistor electrically connected to a clock signal output terminal of a first clock signal generating unit of the two clock signal generating units, a second electrode of the first switching transistor electrically connected to a first electrode of the second switching transistor, and a second electrode of the second switching transistor electrically connected to a clock signal output terminal of a second clock signal generating unit of the two clock signal generating units;

[0012] The first switch transistor and the second switch transistor are both p-type transistors; or, the first switch transistor and the second switch transistor are both n-type transistors.

[0013] Optionally, the first output module is configured to control not to output the first voltage signal through the clock signal output terminal when the first output control signal is a low voltage signal;

[0014] The control unit includes a NOR gate and a control module;

[0015] The first input terminal of the NOR gate is electrically connected to the first output control terminal of the first clock signal generating unit, and the second input terminal of the NOR gate is electrically connected to the first output control terminal of the second clock signal generating unit;

[0016] The control module is electrically connected to the output end of the NOR gate, and is used to control the first switch transistor and the second switch transistor to be turned on when the NOR gate outputs a high voltage signal through its output end.

[0017] Optionally, both the first switching transistor and the second switching transistor are p-type transistors;

[0018] The control module includes a first level conversion circuit and a first p-type driving circuit;

[0019] The first level conversion circuit is electrically connected to the output terminal of the NOR gate, and is used to perform level conversion on the signal output by the NOR gate through its output terminal, and provide a first control signal obtained by the level conversion to the input terminal of the first p-type driving circuit;

[0020] The output end of the first p-type driving circuit is electrically connected to the control signal output end. The first p-type driving circuit is used to invert the first control signal to obtain a second control signal, and output the second control signal to the control electrode of the first switching transistor through the control signal output end, and can improve the driving capability of the output end of the first p-type driving circuit.

[0021] Optionally, both the first switching transistor and the second switching transistor are n-type transistors;

[0022] The control module includes a first level conversion circuit and a first n-type driving circuit;

[0023] The first level conversion circuit is electrically connected to the output terminal of the NOR gate, and is used to perform level conversion on the signal output by the NOR gate through its output terminal, and provide a first control signal obtained by the level conversion to the input terminal of the first n-type driving circuit;

[0024] The output end of the first n-type driving circuit is electrically connected to the control signal output end. The first n-type driving circuit is used to provide the first control signal to the control electrode of the first switching transistor through the control signal output end, and can improve the driving capability of the output end of the first n-type driving circuit.

[0025] Optionally, the first output module is configured to control the output of the first voltage signal not through the gate drive signal when the first output control signal is a high voltage signal;

[0026] The control unit includes a NAND gate and a control module;

[0027] The first input terminal of the NAND gate is electrically connected to the first output control terminal of the first clock signal generating unit, and the second input terminal of the NAND gate is electrically connected to the first output control terminal of the second clock signal generating unit;

[0028] The control module is electrically connected to the output end of the NAND gate, and is used to control the first switch transistor and the second switch transistor to be turned on when the NAND gate outputs a low voltage signal through its output end.

[0029] The present invention further provides a charge sharing method, which is applied to the above-mentioned charge sharing circuit. The charge sharing method includes:

[0030] When the first output module is controlled not to output the first voltage signal under the control of the first output control signal, the control unit provides an opening control signal to the switch unit through the control signal output terminal;

[0031] The switch unit controls the connection between the clock signal output terminals of the two clock signal generating units under the control of the opening control signal.

[0032] The present invention also provides a display driving module, comprising a clock signal generating circuit and the above-mentioned charge sharing circuit.

[0033] Optionally, the clock signal generating circuit includes a plurality of clock signal generating units;

[0034] The clock signal generating unit includes a clock signal output terminal, a first output control terminal, a second output control terminal, a first output module and a second output module;

[0035] The first output module is used to control whether to output a first voltage signal through the clock signal output terminal under the control of a first output control signal provided by the first output control terminal;

[0036] The second output module is used to control whether to output the second voltage signal through the clock signal output terminal under the control of the second output control signal provided by the second output control terminal.

[0037] The present invention also provides a display device, comprising the above-mentioned display driving module.

[0038] The charge sharing circuit, method, display driving module and display device described in the embodiments of the present invention control the first output control terminal included in two clock signal generating units of the at least two clock signal generating units to control the two clock signal generating units to not output the first voltage signal, and provide an opening control signal to the switching unit. Under the control of the opening control signal, the switching unit controls the connection between the clock signal output terminals included in the two clock signal generating units to perform charge sharing, and can reduce the number of level conversion circuits used, saving chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a structural diagram of an embodiment of a clock signal generating unit;

[0040] Figure 2 is a structural diagram of a charge sharing circuit according to an embodiment of the present invention;

[0041] Figure 3 is a circuit diagram of a charge sharing circuit according to another embodiment of the present invention;

[0042] Figure 4 is a circuit diagram of a specific embodiment of the charge sharing circuit described in the present invention. DETAILED DESCRIPTION

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0044] The transistors used in all embodiments of the present invention may be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor other than the control electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0045] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0046] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0047] The charge sharing circuit according to an embodiment of the present invention is applied to a display device, wherein the display device includes a gate driving circuit and a clock signal generating circuit, wherein the gate driving circuit includes a plurality of shift register units, and the clock signal generating circuit includes at least two clock signal generating units; two clock signal generating units in the at least two clock signal generating circuits respectively provide corresponding clock signals for two adjacent shift register units; the clock signal generating unit includes a clock signal output terminal, a first output control terminal, and a first output module, wherein the first output module is configured to control whether to output a first voltage signal through the clock signal output terminal under the control of a first output control signal provided by the first output control terminal; the charge sharing circuit according to an embodiment of the present invention includes a control unit and a switch unit, wherein:

[0048] The control unit is electrically connected to the first output control terminals included in the two clock signal generating units, respectively, and is configured to provide an opening control signal to the switch unit through the control signal output terminal when the first output module controls not to output the first voltage signal under the control of the first output control signal;

[0049] The switch unit is electrically connected to the control signal output end and the clock signal output ends included in the two clock signal generating units respectively, and is used to control the connection between the clock signal output ends included in the two clock signal generating units under the control of the opening control signal.

[0050] When the charge sharing circuit described in the embodiment of the present invention is in operation, the control unit provides an opening control signal to the switching unit when the first output control terminal included in the two clock signal generating units controls the two clock signal generating units not to output the first voltage signal. Under the control of the opening control signal, the switching unit controls the connection between the clock output terminals included in the two clock signal generating units to perform charge sharing.

[0051] Compared with the existing charge sharing circuit, the embodiment of the present invention no longer controls the on and off of the switch unit (the switch unit is a sharing unit for sharing charge) by level conversion of the shared signal, but controls the on and off of the switch unit through the first output control terminal. When the first output modules in the two clock signal generating units are controlled not to output the first voltage signal, the switch unit is controlled to be turned on to achieve two-way sharing, thereby realizing charge sharing, reducing the number of level conversion circuits used, and saving chip area.

[0052] In specific implementation, the display driver module described in the embodiment of the present invention may include more than one charge sharing circuit described in the embodiment of the present invention to achieve n-way sharing (n is an integer greater than 1), which can save more level conversion circuits.

[0053] In an embodiment of the present invention, when the data writing transistor in the pixel circuit whose control electrode is electrically connected to the gate line is a p-type transistor, the first voltage signal may be a low voltage signal; when the data writing transistor in the pixel circuit whose control electrode is electrically connected to the gate line is an n-type transistor, the first voltage signal may be a high voltage signal; but the present invention is not limited thereto.

[0054] In actual operation, the control electrode of the data write transistor can be electrically connected to the corresponding row gate line, and the first electrode of the data write transistor can be electrically connected to the corresponding column data line. The data write transistor is used to control the data voltage on the corresponding column data line to be written into the corresponding pixel circuit under the control of the gate drive signal on the corresponding row gate line, but is not limited to this.

[0055] In the related art, a display device may include a display driving module, which may include a gate driving circuit, a clock signal generating circuit, and the charge sharing circuit; the gate driving circuit includes a multi-stage shift register unit, and the display device also includes a display panel, which may include multiple rows of gate lines and multiple rows and columns of pixel circuits. The corresponding row shift register unit in the gate driving circuit may provide a gate driving signal to the gate of the transistor in the corresponding row of pixel circuits included in the display panel through the corresponding row of gate lines;

[0056] The clock signal generating circuit is used to provide a gate driving signal for the gate driving circuit;

[0057] The clock signal generating circuit includes at least two clock signal generating units;

[0058] Two clock signal generating units among the at least two clock signal generating units respectively provide corresponding clock signals for two adjacent shift register units.

[0059] In an embodiment of the present invention, when the clock signal generating circuit includes two clock signal generating units, the odd-numbered shift register unit may be electrically connected to the clock signal output terminal of the first clock signal generating unit, and the even-numbered shift register unit may be electrically connected to the clock signal output terminal of the second clock signal generating unit;

[0060] When the clock signal generating circuit includes four clock signal generating units, the 4P-3 level shift register unit can be electrically connected to the clock signal output end of the first clock signal generating unit, the 4P-2 level shift register unit can be electrically connected to the clock signal output end of the second clock signal generating unit, the 4P-1 level shift register unit can be electrically connected to the clock signal output end of the third clock signal generating unit, and the 4P level shift register unit can be electrically connected to the clock signal output end of the fourth clock signal generating unit; P is a positive integer.

[0061] In a display device, to save power, it is necessary to implement gate line charge sharing between gate lines in different rows. This transfers the charge of the gate line to be turned off to the gate line to be turned on, thereby reducing the power consumption of transistors in the display panel when they are turned on. Furthermore, because the gate drive signals on the gate lines are provided by clock signals, charge sharing between the gates of transistors in pixel circuits in different rows of the display panel can be achieved by sharing charge at the clock signal output terminals of two clock signal generation units.

[0062] In the embodiment of the present invention, when charge sharing is performed, the clock signal output terminal of the clock signal generating unit may be in a high impedance state.

[0063] like Figure 1 As shown, an embodiment of the clock signal generating unit may include a clock signal output terminal CLK0, a first output control terminal S1, a second output control terminal S2, a first output module 11, a second output module 12 and an output control module 13;

[0064] The first output module 11 is electrically connected to the first output control terminal S1, the first voltage terminal V1 and the clock signal output terminal CLK0, respectively, and is used to control the connection or disconnection between the clock signal output terminal CLK0 and the first voltage terminal V1 under the control of the first output control signal provided by the first output control terminal S1; the first voltage terminal V1 is used to provide a first voltage signal;

[0065] The second output module 12 is electrically connected to the second output control terminal S2, the second voltage terminal V2 and the clock signal output terminal CLK0, respectively, and is used to control the connection or disconnection between the clock signal output terminal CLK0 and the second voltage terminal V2 under the control of the second output control signal provided by the second output control terminal S2; the second voltage terminal V2 is used to provide a second voltage signal;

[0066] The output control module 13 is electrically connected to the first output control terminal S1 and the second output control terminal S2, respectively, and is configured to provide the first output control signal to the first output control terminal S1 and provide the second output control signal to the second output control terminal S2.

[0067] exist Figure 1 , the clock signal output terminal CLK0 is in a high-impedance state means that: when the first output module 11 controls the clock signal output terminal CLK0 to be disconnected from the first voltage terminal V1 under the control of the first output control signal, and the second output module 12 controls the clock signal output terminal CLK0 to be disconnected from the second voltage terminal V2 under the control of the second output control signal, CLK0 is in a high-impedance state.

[0068] In the embodiment of the present invention, the first output module may include an n-type transistor, and the second output module may include a p-type transistor, but the present invention is not limited thereto.

[0069] In actual operation, the first output module may also include a p-type transistor, and the second output module may also include an n-type transistor.

[0070] In an embodiment of the present invention, the gate driving circuit is used to provide a gate driving signal to the pixel circuit;

[0071] The data writing transistor in the pixel circuit electrically connected to the gate drive signal output terminal is an n-type transistor, the first voltage signal is a low voltage signal, and the second voltage signal is a high voltage signal; or

[0072] The data writing transistor is a p-type transistor, the first voltage signal is a high voltage signal, and the second voltage signal is a low voltage signal.

[0073] like Figure 2 As shown, the charge sharing circuit according to the embodiment of the present invention is applied to a display device, and the display device includes a clock signal generating circuit; the clock signal generating circuit includes a first clock signal generating unit and a second clock signal generating unit, wherein,

[0074] The first clock signal generating unit includes a first clock signal output terminal CLK1, a first first output control terminal S11, a first second output control terminal S12, a first first output module 111, a first second output module 112, and a first output control module 113;

[0075] The first first output module 111 is electrically connected to the first first output control terminal S11, the low voltage terminal, and the first clock signal output terminal CLK1, respectively, and is used to control the connection or disconnection between CLK1 and the low voltage terminal under the control of the first first output control signal provided by S11; the low voltage terminal is used to provide a low voltage signal VGL, which can be a -10V DC voltage signal;

[0076] The first second output module 112 is electrically connected to the first second output control terminal S12, the high voltage terminal, and the first clock signal output terminal CLK1, respectively, and is used to control the connection or disconnection between CLK1 and the high voltage terminal under the control of the first second output control signal provided by the first second output control terminal S12; the high voltage terminal is used to provide a high voltage signal VGH, which can be a 30V DC voltage signal;

[0077] The first output control module 113 is electrically connected to S11 and S12 respectively, and is used to provide the first first output control signal to S11 and the first second output control signal to S12;

[0078] The second clock signal generating unit includes a second clock signal output terminal CLK2, a second first output control terminal S21, a second second output control terminal S22, a second first output module 121, a second second output module 122, and a second output control module 123;

[0079] The second first output module 121 is electrically connected to the second first output control terminal S21, the low voltage terminal, and the second clock signal output terminal CLK2, respectively, and is used to control the connection or disconnection between CLK2 and the low voltage terminal under the control of the second first output control signal provided by S21; the low voltage terminal is used to provide a low voltage signal, which can be a -10V DC voltage signal;

[0080] The second second output module 122 is electrically connected to the second second output control terminal S22, the high voltage terminal, and the second clock signal output terminal CLK2, respectively, and is used to control the connection or disconnection between CLK2 and the high voltage terminal under the control of the second second output control signal provided by S22; the high voltage terminal is used to provide a high voltage signal; the high voltage signal can be a 30V DC voltage signal;

[0081] The second output control module 123 is electrically connected to S21 and S22 respectively, and is used to provide the second first output control signal to S21 and the second second output control signal to S22;

[0082] like Figure 2 As shown, the charge sharing circuit according to the embodiment of the present invention includes a control unit 31 and a switch unit 32, wherein:

[0083] The control unit 31 is electrically connected to S11 and S21 respectively, and is configured to provide an opening control signal to the switch unit 32 through the control signal output terminal when the first first output module 111 controls not to output the low voltage signal through CLK1 under the control of the first first output control signal provided by S11, and when the second first output control module 121 controls not to output the low voltage signal through CLK2 under the control of the second first output control signal provided by S21;

[0084] The switch unit 32 is electrically connected to the control signal output terminal, CLK1 and CLK2 respectively, and is used to control the connection between CLK1 and CLK2 under the control of the opening control signal.

[0085] In the embodiment of the present invention, when both CLK1 and CLK2 output high voltage signals, the switch unit 32 also controls the connection between CLK1 and CLK2. However, since charge sharing does not affect the pixel circuit at this time, it does not affect the function of the entire system.

[0086] Optionally, the switching unit includes a first switching transistor and a second switching transistor;

[0087] The control electrode of the first switch transistor and the control electrode of the second switch transistor are both electrically connected to the control signal output terminal;

[0088] a first electrode of the first switching transistor electrically connected to a clock signal output terminal of a first clock signal generating unit of the two clock signal generating units, a second electrode of the first switching transistor electrically connected to a first electrode of the second switching transistor, and a second electrode of the second switching transistor electrically connected to a clock signal output terminal of a second clock signal generating unit of the two clock signal generating units;

[0089] The first switch transistor and the second switch transistor are both p-type transistors; or, the first switch transistor and the second switch transistor are both n-type transistors.

[0090] In a specific implementation, the first output module may be configured to control the first voltage signal not to be output through the clock signal output terminal when the first output control signal is a low voltage signal;

[0091] The control unit includes a NOR gate and a control module;

[0092] The first input terminal of the NOR gate is electrically connected to the first output control terminal of the first clock signal generating unit, and the second input terminal of the NOR gate is electrically connected to the first output control terminal of the second clock signal generating unit;

[0093] The control module is electrically connected to the output end of the NOR gate, and is used to control the first switch transistor and the second switch transistor to be turned on when the NOR gate outputs a high voltage signal through its output end.

[0094] According to a specific embodiment, both the first switch transistor and the second switch transistor are p-type transistors;

[0095] The control module includes a first level conversion circuit and a first p-type driving circuit;

[0096] The first level conversion circuit is electrically connected to the output terminal of the NOR gate, and is used to perform level conversion on the signal output by the NOR gate through its output terminal, and provide a first control signal obtained by the level conversion to the first p-type driving circuit;

[0097] The output end of the first p-type driving circuit is electrically connected to the control signal output end. The first p-type driving circuit is used to invert the first control signal to obtain a second control signal, and output the second control signal to the control electrode of the first switching transistor through the control signal output end, and can improve the driving capability of the output end of the first p-type driving circuit.

[0098] In actual operation, the first switching transistor and the second switching transistor can both be p-type transistors. In this case, when the gate-source voltage of the first switching transistor is less than the threshold voltage of the first switching transistor and the gate-source voltage of the second switching transistor is less than the threshold voltage of the second switching transistor, the first switching transistor and the second switching transistor are turned on.

[0099] According to another specific embodiment, both the first switch transistor and the second switch transistor are n-type transistors;

[0100] The control module includes a first level conversion circuit and a first n-type driving circuit;

[0101] The first level conversion circuit is electrically connected to the output terminal of the NOR gate, and is used to perform level conversion on the signal output by the NOR gate through its output terminal, and provide a first control signal obtained by the level conversion to the first n-type driving circuit;

[0102] The output end of the first n-type driving circuit is electrically connected to the control signal output end. The first n-type driving circuit is used to provide the first control signal to the control electrode of the first switching transistor through the control signal output end, and can improve the driving capability of the output end of the first n-type driving circuit.

[0103] In actual operation, the first switching transistor and the second switching transistor can both be n-type transistors. In this case, when the gate-source voltage of the first switching transistor is greater than the threshold voltage of the first switching transistor and the gate-source voltage of the second switching transistor is greater than the threshold voltage of the second switching transistor, the first switching transistor and the second switching transistor are turned on.

[0104] In a specific implementation, the first output module may be configured to control the first voltage signal not to be output through the clock signal output terminal when the first output control signal is a high voltage signal;

[0105] The control unit includes a NAND gate and a control module;

[0106] The first input terminal of the NAND gate is electrically connected to the first output control terminal of the first clock signal generating unit, and the second input terminal of the NAND gate is electrically connected to the first output control terminal of the second clock signal generating unit;

[0107] The control module is electrically connected to the output end of the NAND gate, and is used to control the first switch transistor and the second switch transistor to be turned on when the NAND gate outputs a low voltage signal through its output end.

[0108] In an embodiment of the present invention, when the first output transistor included in the first output module is a p-type transistor, when the first output control signal is a high voltage signal, the first voltage signal is controlled not to be output through the clock signal terminal. At this time, the control unit may include a NAND gate and a control module. When the NAND gate outputs a low voltage signal, the control module controls the first switching transistor and the second switching transistor to be turned on.

[0109] like Figure 3 As shown, in Figure 2 Based on the embodiment of the charge sharing circuit shown, the switch unit 32 includes a first switch transistor M1 and a second switch transistor M2;

[0110] The gate of the first switch transistor M1 and the gate of the second switch transistor M2 are both electrically connected to the control signal output terminal;

[0111] The drain of the first switch transistor M1 is electrically connected to G1, the source of the first switch transistor M1 is electrically connected to the drain of M1, and the source of the second switch transistor M1 is connected to G2;

[0112] The first output transistor included in the first first output module 111 and the first output transistor included in the second first output module 121 are both n-type transistors;

[0113] The control unit includes a first NOR gate NOR1 and a control module;

[0114] The first input terminal of NOR1 is connected to S11, and the second input terminal of NOR2 is electrically connected to S21;

[0115] The control module includes a first level conversion circuit 41 and a first p-type driving circuit 50;

[0116] The first level conversion circuit 41 is electrically connected to the output terminal of NOR1, and is used to perform level conversion on the signal output by NOR1 through its output terminal, and provide the first control signal obtained by the level conversion to the first p-type driving circuit 50;

[0117] The first p-type driving circuit 50 is configured to invert the first control signal to obtain a second control signal, and output the second control signal to the gate of the first switching transistor M1 through the control signal output terminal.

[0118] exist Figure 3 In the illustrated embodiment, both M1 and M2 are NMOS transistors (N-type metal-oxide-semiconductor transistors), but the present invention is not limited thereto.

[0119] The present invention Figure 3 When the embodiment of the charge sharing circuit shown is in operation, when S11 and S12 both output low voltage signals, NOR1 outputs a first high voltage, and the first level conversion circuit 41 performs level conversion on the first high voltage output by NOR1 to generate a second high voltage, which is greater than the first high voltage. The first p-type drive circuit 50 performs an inverting operation on the second high voltage to control M1 and M2 to be turned on to achieve charge sharing.

[0120] like Figure 4 As shown, in Figure 3 Based on the embodiment of the charge sharing circuit shown,

[0121] The first first output module 111 includes a first output transistor N1, the first second output module 112 includes a second output transistor P1, the second first output module 121 includes a third output transistor N2, and the second second output transistor 122 includes a fourth output transistor P2;

[0122] The first output control module 113 includes a first inverter F1, a first OR gate OR1, a second OR gate OR2, a second inverter F2, a third inverter F3, a second level conversion circuit 51, a third level conversion circuit 52, a second p-type driving circuit 61 and a first n-type driving circuit 62;

[0123] The input terminal of F1 is connected to the input clock signal CLK_IN, the output terminal of F1 is electrically connected to the first input terminal of OR1, and the second input terminal of OR1 is connected to the shared signal CSEN;

[0124] The first input terminal of OR2 is connected to CSEN, and the second input terminal of OR2 is connected to CLK_IN;

[0125] The input terminal of F2 is electrically connected to the output terminal of OR1, and the input terminal of F3 is electrically connected to the output terminal of OR2;

[0126] The output end of F2 is electrically connected to the input end of the second level conversion circuit 51 , and the output end of F3 is electrically connected to the input end of the third level conversion circuit 52 ;

[0127] The second level conversion circuit 51 is used to perform level conversion on the voltage signal connected to its input terminal to obtain a third control signal, convert the potential of the third control signal to a high voltage domain, and provide the third control signal to the input terminal of the second p-type driving circuit 61;

[0128] The third level conversion circuit 52 is used to perform level conversion on the voltage signal connected to its input terminal to obtain a fourth control signal, convert the potential of the fourth control signal to a negative voltage domain, and provide the fourth control signal to the input terminal of the first n-type driving circuit 62;

[0129] The output terminal of the second p-type driving circuit 61 is electrically connected to the gate of P1, and is used to provide the third control signal to the gate of P1 and enhance the driving capability of the output terminal of the second p-type driving circuit 61;

[0130] The output end of the first n-type driving circuit 62 is electrically connected to the gate of N1, for providing the fourth control signal to the gate of N1 and enhancing the driving capability of the output end of the first n-type driving circuit 62;

[0131] The second output control module 123 includes a fourth inverter F4, a third OR gate OR3, a fourth OR gate OR4, a fifth inverter F5, a sixth inverter F6, a fourth level conversion circuit 53, a fifth level conversion circuit 54, a third p-type driving circuit 63 and a second n-type driving circuit 64;

[0132] The input terminal of F4 is connected to CLK_IN, the output terminal of F4 is electrically connected to the first input terminal of OR3, and the second input terminal of OR3 is connected to the shared signal CSEN;

[0133] The first input terminal of OR4 is connected to CSEN, and the second input terminal of OR4 is connected to CLK_IN;

[0134] The input terminal of F5 is electrically connected to the output terminal of OR3, and the input terminal of F6 is electrically connected to the output terminal of OR4;

[0135] The output end of F5 is electrically connected to the input end of the fourth level conversion circuit 53 , and the output end of F6 is electrically connected to the input end of the fifth level conversion circuit 54 ;

[0136] The fourth level conversion circuit 53 is used to perform level conversion on the voltage signal input to its input terminal to obtain a fifth control signal, convert the potential of the fifth control signal to a high voltage domain, and provide the fifth control signal to the input terminal of the third p-type driving circuit 63;

[0137] The fifth level conversion circuit 54 is used to perform level conversion on the voltage signal connected to its input terminal to obtain a sixth control signal, convert the potential of the sixth control signal into a negative voltage domain, and provide the sixth control signal to the input terminal of the second n-type driving circuit 64;

[0138] The output end of the third p-type driving circuit 63 is electrically connected to the gate of P2, and is used to provide the fifth control signal to the gate of P2 and enhance the driving capability of the output end of the third p-type driving circuit 63;

[0139] The output terminal of the second n-type driving circuit 64 is electrically connected to the gate of N2 , for providing the sixth control signal to the gate of N2 and enhancing the driving capability of the output terminal of the second n-type driving circuit 64 .

[0140] exist Figure 4 In the embodiment shown, NOR2 is a second NOR gate, a first input terminal of NOR2 is connected to the first clock signal CLK_X, a second input terminal of NOR2 is connected to the second clock signal CLK_Y; an output terminal of NOR2 is used to output CSEN.

[0141] exist Figure 4 In the embodiment shown, the potential of the shared signal CSEN can be between 0V and 5V, the high voltage domain can be between 25V and 30V, the negative voltage domain can be between -10V and -5V, the potential of the voltage signal connected to the input end of the second level conversion circuit 51, the potential of the voltage signal connected to the input end of the third level conversion circuit 52, the potential of the voltage signal connected to the input end of the fourth level conversion circuit 53, and the potential of the voltage signal connected to the input end of the fifth level conversion circuit 54 can be switched between 0V and 5V, then the potential of the third control signal and the potential of the fifth control signal can be switched between 25V and 30V, and the potential of the fourth control signal and the potential of the sixth control signal can be switched between -10V and -5V.

[0142] The charge sharing method according to an embodiment of the present invention is applied to the above-mentioned charge sharing circuit, and the charge sharing method includes:

[0143] When the first output module is controlled not to output the first voltage signal under the control of the first output control signal, the control unit provides an opening control signal to the switch unit through the control signal output terminal;

[0144] The switch unit controls the connection between the clock signal output terminals of the two clock signal generating units under the control of the opening control signal.

[0145] When the charge sharing circuit described in the embodiment of the present invention is in operation, the control unit controls the first output control terminals included in two clock signal generating units of the at least two clock signal generating units to prevent the two clock signal generating units from outputting the first voltage signal, and provides an opening control signal to the switching unit. Under the control of the opening control signal, the switching unit controls the connection between the clock signal output terminals included in the two clock signal generating units to perform charge sharing.

[0146] The display driving module described in the embodiment of the present invention includes a clock signal generating circuit and the above-mentioned charge sharing circuit.

[0147] In an embodiment of the present invention, the clock signal generating circuit includes a plurality of clock signal generating units;

[0148] The clock signal generating unit includes a clock signal output terminal, a first output control terminal, a second output control terminal, a first output module and a second output module;

[0149] The first output module is used to control whether to output a first voltage signal through the clock signal output terminal under the control of a first output control signal provided by the first output control terminal;

[0150] The second output module is used to control whether to output the second voltage signal through the clock signal output terminal under the control of the second output control signal provided by the second output control terminal.

[0151] The display device according to the embodiment of the present invention includes the above-mentioned display driving module.

[0152] In the embodiment of the present invention, the display device may be a liquid crystal display device, but is not limited thereto. In actual operation, the display device may also be an OLED (organic light emitting diode) display device.

[0153] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0154] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A charge sharing circuit, applied to a display device, the display device comprising a gate drive circuit and a clock signal generating circuit, the gate drive circuit comprising a multi-stage shift register unit; the clock signal generating circuit comprising at least two clock signal generating units; two clock signal generating units in the at least two clock signal generating circuits respectively providing corresponding clock signals to two adjacent shift register units; the clock signal generating unit comprising a clock signal output terminal, a first output control terminal, and a first output module, the first output module being configured to control whether to output a first voltage signal through the clock signal output terminal under the control of a first output control signal provided by the first output control terminal; characterized in that: The charge sharing circuit includes a control unit and a switch unit, wherein: The control unit is electrically connected to the first output control terminals included in the two clock signal generating units, respectively, and is configured to provide an opening control signal to the switch unit through the control signal output terminal when the first output module controls not to output the first voltage signal under the control of the first output control signal; The switch unit is electrically connected to the control signal output terminal and the clock signal output terminals included in the two clock signal generating units, respectively, and is used to control the connection between the clock signal output terminals included in the two clock signal generating units under the control of the opening control signal; When charge sharing is performed, the clock signal output terminal of the clock signal generating unit is in a high impedance state.

2. The charge sharing circuit according to claim 1, wherein: The switch unit includes a first switch transistor and a second switch transistor; The control electrode of the first switch transistor and the control electrode of the second switch transistor are both electrically connected to the control signal output terminal; a first electrode of the first switching transistor electrically connected to a clock signal output terminal of a first clock signal generating unit of the two clock signal generating units, a second electrode of the first switching transistor electrically connected to a first electrode of the second switching transistor, and a second electrode of the second switching transistor electrically connected to a clock signal output terminal of a second clock signal generating unit of the two clock signal generating units; The first switch transistor and the second switch transistor are both p-type transistors; or, the first switch transistor and the second switch transistor are both n-type transistors.

3. The charge sharing circuit according to claim 2, wherein: The first output module is configured to control not to output the first voltage signal through the clock signal output terminal when the first output control signal is a low voltage signal; The control unit includes a NOR gate and a control module; The first input terminal of the NOR gate is electrically connected to the first output control terminal of the first clock signal generating unit, and the second input terminal of the NOR gate is electrically connected to the first output control terminal of the second clock signal generating unit; The control module is electrically connected to the output end of the NOR gate, and is used to control the first switch transistor and the second switch transistor to be turned on when the NOR gate outputs a high voltage signal through its output end.

4. The charge sharing circuit according to claim 3, wherein: The first switch transistor and the second switch transistor are both p-type transistors; The control module includes a first level conversion circuit and a first p-type driving circuit; The first level conversion circuit is electrically connected to the output terminal of the NOR gate, and is used to perform level conversion on the signal output by the NOR gate through its output terminal, and provide a first control signal obtained by the level conversion to the input terminal of the first p-type driving circuit; The output end of the first p-type driving circuit is electrically connected to the control signal output end. The first p-type driving circuit is used to invert the first control signal to obtain a second control signal, and output the second control signal to the control electrode of the first switching transistor through the control signal output end, and can improve the driving capability of the output end of the first p-type driving circuit.

5. The charge sharing circuit according to claim 3, wherein: The first switch transistor and the second switch transistor are both n-type transistors; The control module includes a first level conversion circuit and a first n-type driving circuit; The first level conversion circuit is electrically connected to the output terminal of the NOR gate, and is used to perform level conversion on the signal output by the NOR gate through its output terminal, and provide a first control signal obtained by the level conversion to the input terminal of the first n-type driving circuit; The output end of the first n-type driving circuit is electrically connected to the control signal output end. The first n-type driving circuit is used to provide the first control signal to the control electrode of the first switching transistor through the control signal output end, and can improve the driving capability of the output end of the first n-type driving circuit.

6. The charge sharing circuit according to claim 2, wherein: The first output module is configured to control the output of the first voltage signal not through the gate drive signal when the first output control signal is a high voltage signal; The control unit includes a NAND gate and a control module; The first input terminal of the NAND gate is electrically connected to the first output control terminal of the first clock signal generating unit, and the second input terminal of the NAND gate is electrically connected to the first output control terminal of the second clock signal generating unit; The control module is electrically connected to the output end of the NAND gate, and is used to control the first switch transistor and the second switch transistor to be turned on when the NAND gate outputs a low voltage signal through its output end.

7. A charge sharing method, applied to the charge sharing circuit according to any one of claims 1 to 6, characterized in that: The charge sharing method comprises: When the first output module is controlled not to output the first voltage signal under the control of the first output control signal, the control unit provides an opening control signal to the switch unit through the control signal output terminal; The switch unit controls the connection between the clock signal output terminals of the two clock signal generating units under the control of the opening control signal; When charge sharing is performed, the clock signal output terminal of the clock signal generating unit is in a high impedance state.

8. A display driver module, characterized in that: The device comprises a clock signal generating circuit and the charge sharing circuit according to any one of claims 1 to 6.

9. The display driving module according to claim 8, wherein: The clock signal generating circuit includes a plurality of clock signal generating units; The clock signal generating unit includes a clock signal output terminal, a first output control terminal, a second output control terminal, a first output module and a second output module; The first output module is used to control whether to output a first voltage signal through the clock signal output terminal under the control of a first output control signal provided by the first output control terminal; The second output module is used to control whether to output the second voltage signal through the clock signal output terminal under the control of the second output control signal provided by the second output control terminal.

10. A display device, characterized in that: Comprising the display driving module as described in claim 8 or 9.

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