Semiconductor Structure and Method for Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The forming method includes: providing a substrate; forming a gate structure on the substrate, and the substrate under the gate structure is used as a channel region; forming trenches in the substrate on both sides of the gate structure; forming doping regions in the substrate at positions near the channel region at the bottom of the trenches and under the channel region, the doping regions contain second-type ions, and the second-type ions are different from the doping ion types of the first-type transistors; after forming the doping regions, forming source-drain doping layers in the trenches. In the embodiment of the present invention, the doping regions make the doping ions in the source-drain doping layers not easily diffuse downward to the region under the channel region, so that the source and the drain in the source-drain doping layers maintain a relatively large distance. Moreover, when the semiconductor structure is working, the doping regions make the depletion layers of the source-drain doping layers not easily expand, so that the barrier introduced by the drain in the source-drain doping layers is not easily reduced and the subthreshold swing is not easily increased, thereby reducing the short-channel effect and improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) has also been continuously shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and drain of the device is also shortened, so the control ability of the gate structure on the channel becomes worse, and it becomes more and more difficult to pinch off the channel with the gate voltage, making the subthreshold leakage phenomenon, namely the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better adapt to the reduction of the feature size, the semiconductor process has gradually started to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFETs, the gate structure has a stronger control ability on the channel and can well suppress the short-channel effect; and FinFETs have better compatibility with existing integrated circuit manufacturing compared to other devices. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, and optimize the electrical performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure for forming a first-type transistor, including: providing a substrate; forming a gate structure on the substrate, and the substrate under the gate structure is used as a channel region; forming trenches in the substrate on both sides of the gate structure; forming doping regions in the substrate at a position near the channel region at the bottom of the trenches and under the channel region, the doping regions contain second-type ions, and the second-type ions are different from the doping ion types of the first-type transistor; after forming the doping regions, forming source / drain doping layers in the trenches.

[0006] Optionally, the second-type ions are doped at a position near the gate structure in the trenches by ion implantation to form the doping regions.

[0007] Optionally, when the semiconductor structure is used to form an NMOS, the process parameters of the second-type ion implantation include: the second-type ions include one or more of boron, gallium, and indium; the implantation energy is 0.5 Kev to 1.5 Kev; the implantation dose of the second-type ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, and the angle between the implantation direction and the substrate normal is 5 degrees to 25 degrees; when the semiconductor structure is used to form a PMOS, the process parameters of the second-type ion implantation include: the second-type ions include one or more of phosphorus, arsenic, and antimony; the implantation energy is 1 Kev to 3 Kev; the implantation dose of the second-type ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter; the angle between the implantation direction and the substrate normal is 5 degrees to 25 degrees.

[0008] Optionally, the step of forming the doped region further includes: doping with C and F.

[0009] Optionally, C and F are doped at a position near the gate structure in the trench by ion implantation to form a doped region.

[0010] Optionally, the process parameters for doping C in the doped region include: the implantation energy is 1 Kev to 3 Kev; the implantation dose of the ions is 1E14 atoms per square centimeter to 5E14 atoms per square centimeter, and the angle between the implantation direction and the substrate normal is 5 degrees to 25 degrees; the process parameters for doping F in the doped region include: the implantation energy is 2 Kev to 4 Kev; the implantation dose of the ions is 3E14 atoms per square centimeter to 1E15 atoms per square centimeter, and the angle between the implantation direction and the substrate normal is 5 degrees to 25 degrees.

[0011] Optionally, after forming the doped region and before forming the source / drain doped layer, an annealing treatment is further included for the doped region.

[0012] Optionally, the annealing treatment includes a first annealing process and a second annealing process, and the temperature of the second annealing process is higher than that of the first annealing process; the first annealing process is used to repair lattice defects; the second annealing process is used to activate ions.

[0013] Optionally, the process parameters of the first annealing process include: the annealing temperature is 400 °C to 600 °C; the annealing time is 10 minutes to 30 minutes.

[0014] Optionally, spike annealing or laser annealing is used for the second annealing process.

[0015] Optionally, the substrate includes a substrate and fins located on the substrate; the step of forming the trench includes: forming the trench in the fins on both sides of the gate structure; in the step of forming the doped region, the doped region is formed at a position near the channel region at the bottom of the trench and in the fins below the channel region.

[0016] Optionally, in the step of forming the doped region, the distance between the top surface of the doped region and the top surface of the fin is greater than one-fourth of the height of the fin and less than or equal to one-half of the height of the fin.

[0017] Optionally, when the semiconductor structure is used to form an NMOS, the material of the source / drain doping layer includes one or more of Si, SiP, and SiC; when the semiconductor structure is used to form a PMOS, the material of the source / drain doping layer includes one or two of Si and SiGe.

[0018] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, which is a first-type transistor, including: a substrate; a gate structure located on the substrate; source / drain doping layers located in the substrate on both sides of the gate structure; a channel region located in the substrate below the gate structure and between the source / drain doping layers; a doped region located in the substrate below the channel region and at the substrate near the gate structure at the bottom of the source / drain doping layer, and the doped region contains second-type ions, and the types of the second-type ions are different from the doping ion types of the first-type transistor.

[0019] Optionally, when the first-type transistor is an NMOS, the second-type ions include one or more of boron, gallium, and indium; the concentration of the second-type ions is from 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter; when the first-type transistor is a PMOS, the second-type ions include one or more of phosphorus, arsenic, and antimony; the concentration of the second-type ions is from 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter.

[0020] Optionally, C and F are also doped in the doped region.

[0021] Optionally, the doping concentration of C is from 1E19 atoms per cubic centimeter to 5E19 atoms per cubic centimeter; the doping concentration of F is from 3E19 atoms per cubic centimeter to 1E20 atoms per cubic centimeter.

[0022] Optionally, the substrate includes a substrate and fins located on the substrate; the source / drain doping layers are located in the fins on both sides of the gate structure; the doped region is located in the fins below the gate structure, and in the fins at the bottom of the source / drain doping layer and in the fins near the gate structure.

[0023] Optionally, the distance between the top surface of the doped region and the top surface of the fin is greater than one-fourth of the height of the fin and less than or equal to one-half of the height of the fin.

[0024] Optionally, when the semiconductor structure is an NMOS, the material of the source / drain doping layer includes one or more of Si, SiP, and SiC; when the semiconductor structure is a PMOS, the material of the source / drain doping layer includes one or two of Si and SiGe.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0026] In the embodiment of the present invention, a gate structure is formed on the substrate, the substrate under the gate structure is used as a channel region, and trenches are formed in the substrates on both sides of the gate structure; doping regions are formed at positions near the channel region at the bottom of the trenches and in the substrate under the channel region, and the doping regions contain second-type ions, which are different from the doping ion types of the first-type transistors; after the doping regions are formed, source / drain doping layers are formed in the trenches. Compared with the case where no doping region is formed, the doping regions make the doping ions in the source / drain doping layers not easily diffuse downward to the channel region, so that the source and drain in the source / drain doping layers maintain a relatively large distance, and when the semiconductor structure operates, the doping regions make the depletion layer of the source / drain doping layers not easily expand, so that the barrier introduced by the drain in the source / drain doping layers is not easily reduced and the subthreshold swing is not easily increased, thereby reducing the short-channel effect and improving the electrical performance of the semiconductor structure. Description of the Drawings

[0027] Figure 1 is a schematic structural diagram of a semiconductor structure;

[0028] Figures 2 to 6 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Embodiments

[0029] As can be seen from the background art, the currently formed devices still have problems with poor performance. The reasons for the poor performance of the devices are analyzed in combination with a method for forming a semiconductor structure.

[0030] Reference Figure 1 , which shows a schematic structural diagram of a semiconductor structure.

[0031] Reference Figure 1, the semiconductor structure includes: a substrate 1 and fin portions 2 located on the substrate 1; a gate structure 3 spanning across the fin portions 2, and the gate structure 3 covering a partial top wall and partial side walls of the fin portions 2; source / drain doping regions 4 are formed in the fin portions 2 on both sides of the gate structure 3.

[0032] With the development of the semiconductor manufacturing process, in the direction perpendicular to the extension direction of the gate structure 3, the width of the gate structure 3 becomes smaller and smaller, so that the distance between the source / drain doping regions 4 on both sides of the gate structure 3 becomes smaller and smaller. When the semiconductor structure operates, the distance of the channel becomes smaller and smaller. The depletion layer of the source / drain doping regions 4 is prone to expand, resulting in the barrier introduced by the drain in the source / drain doping regions 4 being prone to decrease and the subthreshold swing being prone to increase, resulting in a relatively serious short-channel effect and poor electrical performance of the semiconductor structure.

[0033] To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure for forming a first-type transistor, including: providing a substrate; forming a gate structure on the substrate, and the substrate below the gate structure is used as a channel region; forming trenches in the substrate on both sides of the gate structure; forming doping regions at positions near the channel region at the bottom of the trenches and in the substrate below the channel region, the doping regions containing second-type ions, and the second-type ions are different from the doping ion types of the first-type transistor; after forming the doping regions, forming source / drain doping layers in the trenches.

[0034] In the embodiment of the present invention, a gate structure is formed on the substrate, and the substrate below the gate structure is used as a channel region, and trenches are formed in the substrate on both sides of the gate structure; doping regions are formed at positions near the channel region at the bottom of the trenches and in the substrate below the channel region, the doping regions containing second-type ions, and the second-type ions are different from the doping ion types of the first-type transistor; after forming the doping regions, source / drain doping layers are formed in the trenches. Compared with the case where no doping regions are formed, the doping regions make the doping ions in the source / drain doping layers not easily diffuse downward to the channel region, so that the source and drain in the source / drain doping layers maintain a relatively large interval. And when the semiconductor structure operates, the doping regions make the depletion layer of the source / drain doping layers not easily expand, so that the barrier introduced by the drain in the source / drain doping layers is not easily decreased and the subthreshold swing is not easily increased, thereby reducing the short-channel effect and improving the electrical performance of the semiconductor structure.

[0035] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following will describe in detail the specific embodiments of the embodiments of the present invention with reference to the drawings.

[0036] Figures 2 to 6 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0037] Provide a substrate (not labeled).

[0038] The substrate provides a process platform for subsequent formation of a semiconductor structure, and the subsequently formed semiconductor structure is a first-type transistor, and the source-drain doping layer of the first-type transistor is doped with first-type ions.

[0039] In this embodiment, the formed semiconductor structure is taken as an example of a fin field-effect transistor (FinFET). The substrate includes a substrate 100 and fins 101 located on the substrate 100. In other embodiments, the formed semiconductor structure may also be a planar structure.

[0040] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0041] The fins 101 are used to provide a channel region for the subsequent fin field-effect transistor.

[0042] In this embodiment, the fins 101 and the substrate 100 are obtained by etching the same semiconductor layer. In other embodiments, the fins may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fins.

[0043] Therefore, in this embodiment, the material of the fins 101 is the same as that of the substrate 100, and the material of the fins 101 is silicon. In other embodiments, the material of the fins may also be a semiconductor material suitable for forming fins, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fins may also be different from that of the substrate.

[0044] As Figure 3 shown, a gate structure 102 is formed on the substrate, and the substrate below the gate structure 102 is used as a channel region 107.

[0045] When the semiconductor structure works, the channel region 107 serves as a channel. The gate structure 102 is used to turn on or off the channel when the semiconductor structure works.

[0046] Specifically, the gate structure 102 straddles the fins 101, and the gate structure 102 covers a part of the top wall and a part of the side wall of the fins 101. The fin 101 region covered by the gate structure 102 in the fins 101 serves as the channel region 107.

[0047] In this embodiment, the gate structure 102 is a stacked structure. Specifically, the gate structure 102 includes a gate oxide layer 1021 and a gate layer 1022 located on the gate oxide layer 1021. In other embodiments, the gate structure may also be a single-layer structure, that is, the gate structure only includes a gate layer.

[0048] In this embodiment, the material of the gate oxide layer 1021 is silicon oxide. Silicon oxide is a commonly used dielectric material in the process with relatively low cost, and has high process compatibility, which is beneficial to reducing the process difficulty and process cost of forming the gate oxide layer 1021.

[0049] In this embodiment, the gate layer 1022 is polysilicon. In other embodiments, the material of the gate layer may also be amorphous carbon.

[0050] The steps of forming the gate structure 102 include: forming a conformal gate oxide material layer covering the fin 101 (not shown in the figure); forming a gate material layer on the gate oxide material layer (not shown in the figure), the top surface of the gate material layer being higher than the top surface of the fin 101; forming a mask layer 103 on the gate material layer; etching the gate oxide material layer and the gate material layer using the mask layer 103 as a mask, and the remaining gate oxide material layer and the remaining gate material layer serve as the gate structure 102.

[0051] The method for forming the semiconductor structure further includes: after forming the gate structure 102, forming a spacer layer 108 on the sidewalls of the gate structure 102.

[0052] During the subsequent process of forming trenches in the substrate on both sides of the gate structure 102, the spacer layer 108 protects the gate structure 102.

[0053] Reference Figure 4 , forming trenches 104 in the substrate on both sides of the gate structure 102.

[0054] The trenches 104 provide space for subsequent formation of source / drain doping layers.

[0055] Specifically, the trenches 104 are formed in the fins 101 on both sides of the gate structure 102.

[0056] In this embodiment, the trenches 104 are formed by a dry etching process. The dry etching process is an anisotropic etching process, which has good etching profile controllability, is beneficial to reducing damage to other film layer structures, enables the formed trenches 104 to have high quality, and the removal efficiency of the fin 101 material in the dry etching process makes the formation rate of the trenches 104 relatively fast.

[0057] In other embodiments, the trench may also be formed by a wet etching process. The wet etching process is an isotropic etching process. The wet etching process has a high etching rate, simple operation, and low process cost.

[0058] Reference Figure 5 , a doped region 105 is formed in the substrate below the trench 104 near the channel region 107 and below the channel region 107. The doped region 105 contains second-type ions, and the second-type ions are different from the doping ion type of the first-type transistor.

[0059] In this embodiment, the meaning that the second-type ions are different from the doping ion type of the first-type transistor is that the second-type ions are different from the doping ion type of the source-drain doping layer subsequently formed in the trench 104. Therefore, the doped region 105 makes the doping ions in the source-drain doping layer not easily diffuse downward to the channel region 107, so that the source and the drain in the source-drain doping layer maintain a relatively large distance. And when the semiconductor structure operates, the doped region 105 makes the depletion layer of the source-drain doping layer not easily expand, so that the barrier introduced by the drain in the source-drain doping layer is not easily reduced and the subthreshold swing is not easily increased, thereby reducing the short-channel effect and improving the electrical performance of the semiconductor structure.

[0060] Specifically, the doped region 105 is formed in the fin 101 below the trench 104 near the channel region 107 and below the channel region 107.

[0061] In this embodiment, the second-type ions are doped in the trench 104 near the gate structure 102 by ion implantation to form the doped region 105.

[0062] Specifically, after the second-type ions are implanted, the second-type ions diffuse in a direction perpendicular to the extension direction of the gate structure 102 to form the doped region 105.

[0063] It should be noted that in the direction parallel to the normal of the surface of the substrate 100, the distance between the top surface of the doped region 105 and the top surface of the fin 101 should not be too close or too far. If the distance is too close, it is easy for the gate structure 102 to cover the doped region 105 too much. When the semiconductor structure is working, the carriers in the channel are easily scattered, resulting in a low carrier migration rate. If the distance is too far, in the direction perpendicular to the extension direction of the gate structure 102, it is not easy for the doped region 105 to block the diffusion of the doping ions in the subsequently formed source-drain doping layer downward to the channel region 107, and it is not easy to keep the source and the drain in the source-drain doping layer at a relatively far distance. Moreover, when the semiconductor structure is working, the effect of the doped region 105 on suppressing the expansion of the depletion layer of the source-drain doping layer is not significant, resulting in a significant reduction in the barrier introduced by the drain in the source-drain doping layer and a significant increase in the subthreshold swing, and further resulting in a relatively serious short-channel effect, which is not conducive to improving the electrical performance of the semiconductor structure. In this embodiment, in the step of forming the doped region 105, the distance between the top surface of the doped region 105 and the top surface of the fin 101 is greater than one-fourth of the height of the fin 101 and less than or equal to one-half of the height of the fin 101.

[0064] In this embodiment, when the first-type transistor is an NMOS, the second-type ions include one or more of boron, gallium, and indium.

[0065] It should be noted that the implantation dose of the second-type ions should not be too large or too small. If the implantation dose of the second-type ions is too large, it is easy for the concentration of the second-type ions in the formed doped region 105 to be too high, and the second-type ions are easily diffused into the channel region 107. When the semiconductor structure is working, the carriers in the channel are easily scattered, resulting in a low carrier migration rate. If the implantation dose of the second-type ions is too small, it is easy for the concentration of the second-type ions in the doped region 105 to be too low, resulting in a poor formation quality of the doped region 105. It is not easy for the doped region 105 to block the diffusion of the doping ions in the subsequently formed source-drain doping layer downward to the channel region 107, and thus it is not easy to keep the source and the drain in the source-drain doping layer at a relatively far distance. Moreover, when the semiconductor structure is working, the effect of the doped region 105 on suppressing the expansion of the depletion layer of the source-drain doping layer is not significant, resulting in a significant reduction in the barrier introduced by the drain in the source-drain doping layer and a significant increase in the subthreshold swing, and further resulting in a relatively serious short-channel effect, which is not conducive to improving the electrical performance of the semiconductor structure. In this embodiment, the implantation dose of the second-type ions is from 5E12 atoms per square centimeter to 3E13 atoms per square centimeter.

[0066] It should be noted that the implantation energy of the second type of ions should neither be too large nor too small. If the implantation energy of the second type of ions is too large, during the formation of the doped region 105, the lattice damage of the fin portion 101 of the channel region 107 is relatively large. When the semiconductor structure operates, the carrier migration rate in the channel is not high. Moreover, if the implantation energy is too large, it is easy to cause the formed doped region 105 to be far from the channel region 107. When the semiconductor structure operates, the effect of the doped region 105 on suppressing the depletion layer expansion of the source-drain doped layer 106 is not significant, resulting in a significant reduction in the barrier introduced by the drain in the source-drain doped layer and a significant increase in the subthreshold swing, and further leading to a relatively serious short-channel effect, which is not conducive to improving the electrical performance of the semiconductor structure. If the implantation energy of the second type of ions is too small, it is easy to cause the second type of ions to be located on the surface of the trench 104, and then cause the second type doping concentration in the doped region 105 below the channel region 107 to be too low. When the semiconductor structure operates, the effect of the doped region 105 on making the depletion layer of the source-drain doped layer not easy to expand is not significant, resulting in a significant reduction in the barrier introduced by the drain in the source-drain doped layer and a significant increase in the subthreshold swing, and further leading to a relatively serious short-channel effect, which is not conducive to improving the electrical performance of the semiconductor structure. In this embodiment, the implantation energy is 0.5 Kev to 1.5 Kev.

[0067] It should be noted that the angle between the implantation direction of the second type of ions and the normal of the substrate should not be too large, specifically the angle with the normal of the substrate 100. If the angle is too large, it is easy to cause too many of the second type of ions to enter the channel region 107. When the semiconductor structure operates, the problem of carrier scattering easily occurs in the channel, resulting in a low carrier migration rate. If the angle is too small, it is easy to cause the second type of ions not to diffuse easily below the channel region 107, and the doping ions in the subsequently formed source-drain doped layer are easy to diffuse below the channel region 107. The doped region 105 is not easy to keep the source and drain in the source-drain doped layer at a relatively large interval. When the semiconductor structure operates, the effect of the doped region 105 on suppressing the depletion layer expansion of the source-drain doped layer 106 is not significant, resulting in a significant reduction in the barrier introduced by the drain in the source-drain doped layer and a significant increase in the subthreshold swing, and further leading to a relatively serious short-channel effect, which is not conducive to improving the electrical performance of the semiconductor structure. In this embodiment, the angle between the implantation direction of the second type of ions and the normal of the substrate 100 is 5 degrees to 25 degrees.

[0068] In other embodiments, when the semiconductor structure is used to form a PMOS, the process parameters of the second type of ion implantation include: the second type of ions include one or more of phosphorus, arsenic, and antimony; the implantation energy is 1 Kev to 3 Kev; the implantation dose of the second type of ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter; the angle between the implantation direction and the normal of the substrate is 5 degrees to 25 degrees.

[0069] The method for forming the semiconductor structure further includes: the step of forming the doped region 105 further includes: after doping with second-type ions, doping with C and F.

[0070] Lattice defects are generated during the formation of the doped region 105. The C ions will be formed at the lattice defects, so that the doped ions in the source / drain doped layer are not easily diffused in the direction perpendicular to the extension direction of the gate structure 102. When the semiconductor structure is operating, the doped region 105 makes the depletion layer of the source / drain doped layer not easily expand, so that the barrier introduced by the drain in the source / drain doped layer is not easily reduced and the subthreshold swing is not easily increased, thereby reducing the short-channel effect and improving the electrical performance of the semiconductor structure.

[0071] In this embodiment, C ions are doped at a position close to the gate structure 102 in the trench 104 by ion implantation.

[0072] It should be noted that the angle between the C ion implantation direction and the normal of the substrate should not be too large or too small, specifically the angle with the normal of the substrate 100. If the angle is too large, it is easy for C ions to enter the channel region 107 too much, resulting in a low carrier migration rate when the semiconductor structure is operating. If the angle is too small, it is easy for C ions to be implanted too much at the bottom of the trench 104, and there are too few C ions on the sidewall of the trench 104, resulting in too few C ions diffusing into the bottom of the channel region 107, and the formation quality of the doped region 105 is poor. The doped region 105 is not easily blocked from the doped ions in the subsequently formed source / drain doped layer from diffusing downward into the channel region 107, resulting in a short distance between the source and the drain in the source / drain doped layer. And when the semiconductor structure is operating, the effect of the doped region 105 on suppressing the expansion of the depletion layer of the source / drain doped layer 106 is not significant, resulting in a significant reduction in the barrier introduced by the drain in the source / drain doped layer and a significant increase in the subthreshold swing, and further resulting in a more serious short-channel effect, which is not conducive to improving the electrical performance of the semiconductor structure. In this embodiment, the angle between the C ion implantation direction and the normal of the substrate is 5 degrees to 25 degrees.

[0073] It should be noted that the implantation energy of C ions should not be too large or too small. If the implantation energy of the C ions is too large, during the formation of the doped region 105, the lattice damage of the fin 101 in the channel region 107 is relatively large, and it is difficult to repair during the subsequent annealing process. When the semiconductor structure operates, the carrier migration rate in the channel is not high. Moreover, if the implantation energy is too large, it is easy for C ions to pass through the gate structure 102 and enter the channel region 107. When the semiconductor structure operates, it is easy to cause the carrier migration rate to be not high, thereby resulting in poor electrical performance of the semiconductor structure. If the implantation energy of the C ions is too small, it is easy for the C ions to be located on the surface of the trench 104, and then the C ion doping concentration below the channel region 107 is too low. When the semiconductor structure operates, the doped region 105 is not easy to block the doping ions in the source-drain doped layer from diffusing downward to the channel region 107, resulting in a relatively short distance between the source and the drain in the source-drain doped layer. Moreover, when the semiconductor structure operates, the depletion layer of the source-drain doped layer is easy to expand, thereby resulting in a significant reduction in the barrier introduced by the drain in the source-drain doped layer and a significant increase in the subthreshold swing, and further resulting in a relatively serious short-channel effect, which is not conducive to improving the electrical performance of the semiconductor structure. In this embodiment, the implantation energy of the C ions is 1 Kev to 3 Kev.

[0074] It should be noted that the implantation dose of C ions should not be too large or too small. If the implantation dose of the C ions is too large, it is easy for the C ion doping concentration to be too large, which will cause the C ions to diffuse into the channel region 107. When the semiconductor operates, the carrier migration rate is not high, and it is also easy to cause an increase in the leakage current of the junction formed by the subsequent source-drain doped layer and the doped region 105. If the implantation dose of the C ions is too small, it is easy for the C ion doping concentration in the doped region 105 to be too small, and the doped region 105 is not easy to block the doping ions in the subsequent source-drain doped layer from diffusing downward to the channel region 107, resulting in a relatively short distance between the source and the drain in the source-drain doped layer. Thus, when the semiconductor structure operates, the effect of the doped region 105 on suppressing the expansion of the depletion layer of the source-drain doped layer 106 is not significant, thereby resulting in a significant reduction in the barrier introduced by the drain in the source-drain doped layer and a significant increase in the subthreshold swing, and further resulting in a relatively serious short-channel effect, which is not conducive to improving the electrical performance of the semiconductor structure. In this embodiment, the implantation dose of the C ions is from 1E14 atoms per square centimeter to 5E14 atoms per square centimeter.

[0075] The F ions also occupy the lattice defects generated during the formation of the doped region 105, blocking the doped ions in the source / drain doped layer from diffusing in the direction perpendicular to the extension direction of the gate structure 102. Thus, when the semiconductor structure operates, the doped region 105 makes the depletion layer of the source / drain doped layer not easily expand, making it difficult for the barrier introduced by the drain in the source / drain doped layer to decrease and the subthreshold swing not easily increase, thereby reducing the short-channel effect and improving the electrical performance of the semiconductor structure.

[0076] It should be noted that the angle between the F ion implantation direction and the substrate normal should neither be too large nor too small. In this embodiment, the angle between the F ion implantation direction and the substrate normal is 5 degrees to 25 degrees. Specifically, referring to the description of the C ion implantation direction, it will not be elaborated here.

[0077] It should be noted that the implantation energy of the F ions should neither be too large nor too small. In this embodiment, the implantation energy of the F ions is 2 Kev to 4 Kev. Specifically, referring to the description of the C ion implantation energy, it will not be elaborated here.

[0078] It should be noted that the implantation dose of the F ions should neither be too large nor too small. In this embodiment, the implantation dose of the ions is 3E14 atoms per square centimeter to 1E15 atoms per square centimeter. Specifically, referring to the description of the C ion implantation dose, it will not be elaborated here.

[0079] It should also be noted that in semiconductor processes, hydrogen ions are the most common impurities. Doping with F ions can replace hydrogen ions to form stable silicon-fluorine bonds, making it difficult for interface trap charges to form, thereby enhancing the stability of the interface structure, maximizing the improvement of the negative bias temperature instability effect of semiconductor devices, and further extending the working life of semiconductor devices.

[0080] In other embodiments, the method for forming the semiconductor structure may further include: doping C and F first, and then doping the second-type ions.

[0081] The method for forming the semiconductor structure further includes: after forming the doped region 105 and before forming the source / drain doped layer, annealing the doped region 105.

[0082] The annealing treatment includes a first annealing process and a second annealing process, and the temperature of the second annealing process is higher than that of the first annealing process; the first annealing process is used to repair lattice defects; the second annealing process is used to activate ions.

[0083] The process of ion implantation will damage the lattice of the fin 101 under the channel region 107. The first annealing process is used to repair the lattice defects, so that C, F and the second-type ions in the doped region 105 are not prone to transient enhanced diffusion (TED) in the formed lattice defects, and the doped ions are not easy to diffuse into the channel region 107, thus not easily affecting the migration rate of carriers.

[0084] It should be noted that the annealing temperature of the first annealing process should not be too high or too low. If the annealing temperature is too high, the lattice defects generated during the ion implantation process cannot be well repaired, and it is easy to cause the doped ions to diffuse into the channel region 107 through the lattice defects. When the semiconductor structure works, the carriers in the channel are prone to scattering. If the annealing temperature is too low, the rate of repairing the lattice defects is too slow, resulting in too long process time and difficult control of process defects. In this embodiment, the annealing temperature of the first annealing process is 400°C to 600°C.

[0085] It should be noted that the annealing time should not be too long or too short. If the annealing time is too long, it is easy to increase the thermal budget and process cost, and it is also easy to cause the doped ions to diffuse into the channel region 107, resulting in a decrease in the migration rate of carriers when the semiconductor structure works, and an increase in the leakage current of the junction formed by the subsequent source-drain doped layer and the doped region 105. If the annealing time is too short, the lattice defects generated during the ion implantation process are not completely repaired, and it is easy to cause the doped ions in the doped region 105 to diffuse into the channel region 107, resulting in a low migration rate of carriers in the channel when the semiconductor structure works. In this embodiment, the annealing time is 10 minutes to 30 minutes.

[0086] In this embodiment, spike annealing or laser annealing is used to perform the second annealing process. The spike annealing process and the laser annealing process are commonly used annealing processes in the semiconductor field, which is beneficial to improving process compatibility.

[0087] The temperature of the second annealing process is relatively high, which can activate the doped ions in the doped region 105. And because the time of the second annealing process is short, the doped ions in the doped region 105 are not easy to diffuse into the fin 101 under the gate structure 102, so that the electric field strength under the gate structure 102 is not easy to be too strong when the subsequent semiconductor structure works, and the gate structure 102 is not easy to be damaged.

[0088] It should be noted that the second annealing process can also play a role in repairing lattice defects.

[0089] Reference Figure 6 , after forming the doped region 105, in the trench 104 (such as Figure 4A source-drain doping layer 106 is formed in the structure shown in the figure.

[0090] When the semiconductor structure is operating, the source-drain doping layer 106 provides stress to the channel, enabling a higher carrier migration rate.

[0091] In this embodiment, when the semiconductor structure is used to form an NMOS (Negative channel Metal Oxide Semiconductor), the material of the source-drain doping layer 106 includes one or more of Si, SiP, and SiC. Specifically, the source-drain doping layer 106 is also doped with N-type ions. The N-type ions replace the positions of silicon atoms in the lattice. The more N-type ions are doped, the higher the concentration of majority carriers, and the stronger the conductivity. The N-type ions are phosphorus, arsenic, or antimony.

[0092] In other embodiments, when the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor), the material of the source-drain doping layer includes one or both of Si and SiGe. Specifically, the source-drain doping layer is also doped with P-type ions. The P-type ions replace the positions of silicon atoms in the lattice. The more P-type ions are doped, the higher the concentration of majority carriers, and the stronger the conductivity. The P-type ions are boron, gallium, or indium.

[0093] The steps of forming the source-drain doping layer 106 include: epitaxially growing an epitaxial layer in the trench 104, performing in-situ doping during the epitaxial growth of the epitaxial layer, and forming the source-drain doping layer 106 in the trench 104. In other embodiments, an epitaxial layer is formed in the trench through an epitaxial growth process; the epitaxial layer is ion-doped to form the source-drain doping layer 106.

[0094] In this embodiment, a selective epitaxial growth method is used to form the epitaxial layer in the trench 104. The thin film obtained by the selective epitaxial growth method has high purity and few defects, which is beneficial to improving the formation quality of the epitaxial layer, and thus beneficial to optimizing the electrical performance of the semiconductor structure. In other embodiments, a chemical vapor deposition (CVD) process or other processes can also be used to form the epitaxial layer.

[0095] Correspondingly, an embodiment of the present invention also provides a semiconductor structure. Refer to Figure 6 , which shows a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

[0096] The semiconductor structure is a first-type transistor, and the semiconductor structure includes: a substrate; a gate structure 102 located on the substrate; source / drain doping layers 106 located in the substrate on both sides of the gate structure 102; a channel region 107 located in the substrate under the gate structure 102, and the channel region 107 is located between the source / drain doping layers 106; a doping region 105 located in the substrate under the channel region 107 and at the bottom of the source / drain doping layers 106 near the substrate of the gate structure 102. The doping region 105 contains second-type ions, and the second-type ions are different from the doping ion type of the first-type transistor.

[0097] In the embodiment of the present invention, the doping region 105 contains second-type ions, and the meaning that the second-type ions are different from the doping ion type of the first-type transistor is that the second-type ions are different from the doping ion type in the source / drain doping layers 106. The doping region 105 makes the doping ions in the source / drain doping layers 106 not easily diffuse downward to the channel region 107, so that the source and the drain in the source / drain doping layers 106 maintain a relatively large interval. When the semiconductor structure works, the doping region 105 makes the depletion layer of the source / drain doping layers 106 not easily expand, so that the barrier introduced by the drain in the source / drain doping layers 106 is not easily reduced and the subthreshold swing is not easily increased, thereby reducing the short-channel effect and improving the electrical performance of the semiconductor structure.

[0098] The substrate provides a process platform for forming the semiconductor structure. The semiconductor structure is a first-type transistor, and the first-type transistor includes source / drain doping layers 106, and the doping in the source / drain doping layers 106 is first-type ions.

[0099] In this embodiment, the formed semiconductor structure is taken as a fin field-effect transistor as an example. The substrate includes a substrate 100 and fins 101 located on the substrate 100. In other embodiments, the formed semiconductor structure can also be a planar structure.

[0100] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0101] In this embodiment, the fins 101 and the substrate 100 are obtained by etching the same semiconductor layer. In other embodiments, the fins can also be semiconductor layers epitaxially grown on the substrate to achieve the purpose of precisely controlling the height of the fins.

[0102] Therefore, in this embodiment, the material of the fin 101 is the same as that of the substrate 100, and the material of the fin 101 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming fins, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, etc., and the material of the fin may also be different from that of the substrate.

[0103] The gate structure 102 is used to turn on or off the channel when the semiconductor structure is operating.

[0104] Specifically, the gate structure 102 straddles the fin 101, and the gate structure 102 covers a part of the top wall and a part of the side wall of the fin 101.

[0105] In this embodiment, the gate structure 102 is a stacked structure. Specifically, the gate structure 102 includes a gate oxide layer 1021 and a gate layer 1022 located on the gate oxide layer 1021. In other embodiments, the gate structure may also be a single-layer structure, that is, the gate structure only includes a gate layer.

[0106] In this embodiment, the material of the gate oxide layer 1021 is silicon oxide. Silicon oxide is a dielectric material commonly used in the process, with a low cost, and has high process compatibility, which is beneficial to reducing the process difficulty and process cost of forming the gate oxide layer 1021.

[0107] In this embodiment, the gate layer 1022 is polysilicon. In other embodiments, the material of the gate layer may also be amorphous carbon.

[0108] The semiconductor structure further includes: a sidewall layer 108 located on the sidewalls of the gate structure 102.

[0109] The source / drain doping layer 106 is formed in the groove 104 (as Figure 5 shown), and during the process of forming the groove 104, the sidewall layer 108 protects the gate structure 102.

[0110] The channel region 107 is located in the fin 101 below the gate structure 102, and the channel region 107 is located between the source / drain doping layers 106. When the semiconductor structure is operating, the channel region 107 serves as a channel.

[0111] When the semiconductor structure is operating, the source / drain doping layer 106 provides stress to the channel, so that the migration rate of carriers is higher.

[0112] Specifically, the source / drain doping layer 106 is located in the fins 101 on both sides of the gate structure 102.

[0113] In this embodiment, when the semiconductor structure is an NMOS, the material of the source-drain doping layer 106 includes one or more of Si, SiP, and SiC. Specifically, the source-drain doping layer 106 is further doped with N-type ions. The N-type ions replace the positions of silicon atoms in the lattice. The more N-type ions are doped, the higher the concentration of majority carriers, and the stronger the conductivity. The N-type ions are phosphorus, arsenic, or antimony.

[0114] In other embodiments, when the semiconductor structure is a PMOS, the material of the source-drain doping layer includes one or both of Si and SiGe. Specifically, the source-drain doping layer is further doped with P-type ions. The P-type ions replace the positions of silicon atoms in the lattice. The more P-type ions are doped, the higher the concentration of majority carriers, and the stronger the conductivity. The P-type ions are boron, gallium, or indium.

[0115] In this embodiment, when the first-type transistor is an NMOS, the second-type ions include one or more of boron, gallium, and indium.

[0116] It should be noted that the concentration of the second-type ions should not be too high or too low. If the concentration of the second-type ions is too high, the second-type ions are likely to diffuse into the channel region 107. When the semiconductor structure is working, the carriers in the channel are likely to be scattered, resulting in a low carrier migration rate. If the concentration of the second-type ions is too low, the formation quality of the doping region 105 is poor. The doping region 105 is not easy to block the diffusion of the doping ions in the source-drain doping layer 106 downward into the channel region 107, so it is not easy to keep the source and drain in the source-drain doping layer 106 at a relatively large distance. And when the semiconductor structure is working, the effect of the doping region 105 on suppressing the expansion of the depletion layer of the source-drain doping layer 106 is not significant, resulting in a significant reduction in the barrier introduced by the drain in the source-drain doping layer 106 and a significant increase in the subthreshold swing, and thus a relatively serious short-channel effect, which is not conducive to improving the electrical performance of the semiconductor structure. In this embodiment, the concentration of the second-type ions is from 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter.

[0117] In other embodiments, when the first-type transistor is a PMOS, the second-type ions include one or more of phosphorus, arsenic, and antimony; the concentration of the second-type ions is from 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter.

[0118] In this embodiment, the doping region is further doped with C and F.

[0119] Lattice defects are generated during the formation of the doped region 105. The C ions are located at the lattice defects, making the doped ions in the source-drain doped layer 106 not easily diffused in the direction perpendicular to the extension direction of the gate structure 102. When the semiconductor structure operates, the doped region 105 makes the depletion layer of the source-drain doped layer 106 not easily expand, making the barrier introduced by the drain in the source-drain doped layer 106 not easily reduced and the subthreshold swing not easily increased, thereby reducing the short-channel effect and improving the electrical performance of the semiconductor structure.

[0120] It should be noted that the doping concentration of the C ions should not be too large or too small. If the doping concentration of the C ions is too large, it is easy for the C ions to diffuse into the channel region 107. When the semiconductor operates, the carrier migration rate is not high, and it is also easy to increase the leakage current of the junction formed by the source-drain doped layer 106 and the doped region 105. If the doping concentration of the C ions is too small, the doped region 105 is not easy to block the diffusion of the doped ions in the source-drain doped layer 106 downward to the channel region 107, resulting in a relatively short distance between the source and the drain in the source-drain doped layer 106. Therefore, when the semiconductor structure operates, the effect of the doped region 105 on suppressing the expansion of the depletion layer of the source-drain doped layer 106 is not significant, resulting in a significant reduction in the barrier introduced by the drain in the source-drain doped layer 106 and a significant increase in the subthreshold swing, and thus a relatively serious short-channel effect, which is not conducive to improving the electrical performance of the semiconductor structure. In this embodiment, the doping concentration of the C ions is from 1E19 atoms per cubic centimeter to 5E19 atoms per cubic centimeter.

[0121] It should be noted that the doping concentration of F should not be too large or too small. In this embodiment, the doping concentration of F is from 3E19 atoms per cubic centimeter to 1E20 atoms per cubic centimeter. Specifically, the relevant description of the doping concentration of the doped C ions will not be elaborated here.

[0122] It should also be noted that in semiconductor processes, hydrogen ions are the most common impurities. Doping F ions can replace hydrogen ions to form stable silicon-fluorine bonds, making it not easy to form interface trap charges, thereby enhancing the stability of the interface structure, maximizing the improvement of the negative bias temperature instability effect of semiconductor devices, and thus extending the working life of semiconductor devices.

[0123] The doped region 105 is located in the fin 101 below the channel region 107 and in the fin 101 at the bottom of the source-drain doped layer 106 close to the gate structure 102.

[0124] It should be noted that in the direction parallel to the normal of the surface of the substrate 100, the distance between the top surface of the doped region 105 and the top surface of the fin 101 should not be too close or too far. If the distance is too close, it is easy for the gate structure 102 to overly cover the doped region 105. When the semiconductor structure operates, the carriers in the channel are prone to scattering, resulting in a low carrier migration rate. If the distance is too far, in the direction perpendicular to the extension direction of the gate structure 102, it is not easy for the doped region 105 to block the diffusion of the doped ions in the source-drain doped layer 106 downward to the channel region 107, and it is not easy to keep the source and the drain in the source-drain doped layer 106 at a relatively large interval. Moreover, when the semiconductor structure operates, the effect of the doped region 105 on suppressing the expansion of the depletion layer of the source-drain doped layer 106 is not significant, resulting in a significant reduction in the barrier introduced by the drain in the source-drain doped layer 106 and a significant increase in the subthreshold swing, and further leading to a relatively serious short-channel effect, which is not conducive to improving the electrical performance of the semiconductor structure. In this embodiment, the distance between the top surface of the doped region 105 and the top surface of the fin 101 is greater than one-fourth of the height of the fin 101 and less than or equal to one-half of the height of the fin 101.

[0125] The semiconductor structure can be formed by using the formation method described in the foregoing embodiment, or can be formed by using other formation methods. For the specific description of the semiconductor structure in this embodiment, reference can be made to the corresponding description in the foregoing embodiment, and details are not described herein again.

[0126] Although the embodiments of the present invention are disclosed as above, the embodiments of the present invention are not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, for forming a first-type transistor, It is characterized in that include: providing a substrate; forming a gate structure on the substrate, wherein the substrate below the gate structure is used as a channel region; forming trenches in the substrate on both sides of the gate structure, the trenches extending from the top of the fin to the bottom of the fin; A doping region is formed at a position near the channel region at the bottom of the trench and in the substrate below the channel region, wherein the doping region is located between the two trenches in a sheet, and the top of the doping region is spaced apart from the top of the fin, and the doping region contains second-type ions, which are different from the doping ions of the first-type transistor; After the doping region is formed, a source-drain doping layer is formed in the trench, and the doping region is located between the source-drain doping layers on both sides of the gate structure.

2. The method for forming a semiconductor structure according to claim 1, It is characterized in that The second type ions are doped at a position in the trench close to the gate structure by ion implantation to form a doped region.

3. The method for forming a semiconductor structure according to claim 2, It is characterized in that When the semiconductor structure is used to form an NMOS, the process parameters of the second-type ion implantation include: the second-type ions include: one or more of boron, gallium and indium, the implantation energy is 0.5Kev to 1.5Kev, the implantation dose of the second-type ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, and the angle between the implantation direction and the substrate normal is 5 degrees to 25 degrees; When the semiconductor structure is used to form PMOS, the process parameters of the second-type ion implantation include: the second-type ions include: one or more of phosphorus, arsenic and antimony, the implantation energy is 1Kev to 3Kev, the implantation dose of the second-type ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, and the angle between the implantation direction and the substrate normal is 5 degrees to 25 degrees.

4. The method for forming a semiconductor structure according to claim 1, It is characterized in that The step of forming the doped region further includes: doping C and F.

5. The method for forming a semiconductor structure according to claim 4, It is characterized in that C and F are doped at a position in the trench close to the gate structure by ion implantation to form a doped region.

6. The method for forming a semiconductor structure according to claim 4, It is characterized in that The process parameters for doping C in the doped region include: an implantation energy of 1 KeV to 3 KeV, an ion implantation dose of 1E14 atoms per square centimeter to 5E14 atoms per square centimeter, and an angle between the implantation direction and the substrate normal of 5 degrees to 25 degrees; The process parameters for doping F in the doping region include: an implantation energy of 2 KeV to 4 KeV, an ion implantation dose of 3E14 atoms per square centimeter to 1E15 atoms per square centimeter, and an angle between an implantation direction and a normal line of the substrate of 5 degrees to 25 degrees.

7. The method for forming a semiconductor structure according to claim 1, It is characterized in that After forming the doping region and before forming the source-drain doping layer, the method further includes: performing annealing treatment on the doping region.

8. The method for forming a semiconductor structure according to claim 7, It is characterized in that The annealing treatment includes a first annealing process and a second annealing process, and the temperature of the second annealing process is higher than the temperature of the first annealing process; The first annealing process is used to repair lattice defects; The second annealing process is used to activate the ions.

9. The method for forming a semiconductor structure according to claim 8, It is characterized in that The process parameters of the first annealing process include: an annealing temperature of 400° C. to 600° C.; and an annealing time of 10 minutes to 30 minutes.

10. The method for forming a semiconductor structure according to claim 8, It is characterized in that The second annealing process is performed by spike annealing or laser annealing.

11. The method for forming a semiconductor structure according to claim 1, It is characterized in that The base comprises a substrate and a fin located on the substrate; The step of forming the trench comprises: forming the trench in the fins on both sides of the gate structure; In the step of forming the doped region, the doped region is formed at a position of the bottom of the trench close to the channel region and in the fin below the channel region.

12. The method for forming a semiconductor structure according to claim 11, It is characterized in that In the step of forming the doped region, the distance between the top surface of the doped region and the top surface of the fin is greater than one quarter of the height of the fin and less than or equal to one half of the height of the fin.

13. The method for forming a semiconductor structure according to claim 1, It is characterized in that When the semiconductor structure is used to form an NMOS, the material of the source-drain doping layer includes one or more of Si, SiP and SiC; When the semiconductor structure is used to form a PMOS, the material of the source and drain doping layers includes one or both of Si and SiGe.

14. A semiconductor structure, which is a first-type transistor, It is characterized in that A method for forming a semiconductor structure according to any one of claims 1 to 13, comprising: substrate; A gate structure, located on the substrate; A source-drain doped layer is located in the substrate on both sides of the gate structure, and the source-drain doped layer extends from the top of the fin to the bottom of the fin; A channel region is located in the substrate below the gate structure, and the channel region is located between the source and drain doping layers; a doping region is located in the substrate below the channel region, and the bottom of the source and drain doping layers is close to the substrate of the gate structure, the doping region contains second-type ions, and the second-type ions are different from the doping ion type of the first-type transistor, the doping region is located between two grooves in a sheet, and the top of the doping region and the top of the fin are spaced apart, and the doping region is located between the source and drain doping layers on both sides of the gate structure.

15. The semiconductor structure according to claim 14, It is characterized in that When the first-type transistor is an NMOS, the second-type ions include: one or more of boron, gallium and indium, and the concentration of the second-type ions is 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter; When the first type of transistor is a PMOS, the second type of ions includes one or more of phosphorus, arsenic, and antimony, and the concentration of the second type of ions is from 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter.

16. The semiconductor structure according to claim 14, wherein, the doped region is further doped with C and F.

17. The semiconductor structure according to claim 16, wherein, the doping concentration of C is from 1E19 atoms per cubic centimeter to 5E19 atoms per cubic centimeter; the doping concentration of F is from 3E19 atoms per cubic centimeter to 1E20 atoms per cubic centimeter.

18. The semiconductor structure according to claim 14, wherein, the substrate includes a substrate and fins located on the substrate; the source / drain doped layers are located in the fins on both sides of the gate structure; the doped region is located in the fins below the gate structure, and in the fins at the bottom of the source / drain doped layers and in the fins near the gate structure.

19. The semiconductor structure according to claim 18, wherein, the distance between the top surface of the doped region and the top surface of the fin is greater than one-fourth of the height of the fin and less than or equal to one-half of the height of the fin.

20. The semiconductor structure according to claim 18, wherein, when the semiconductor structure is an NMOS, the material of the source / drain doped layer includes one or more of Si, SiP, and SiC; when the semiconductor structure is a PMOS, the material of the source / drain doped layer includes one or two of Si and SiGe.

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