Semiconductor device and method for manufacturing the same

Abstract

The source / drain formation technology disclosed herein provides a FinFET with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etching method for forming a source / drain groove in the source / drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are adjusted to define the position of the source / drain tip. The depth of the source / drain groove after the first anisotropic etch and the isotropic etch is less than the target depth. The second anisotropic etch is adjusted to extend the depth of the source / drain groove to the target depth. The source / drain tip is close to the top of the fin to reduce the channel resistance, while the bottom of the source / drain groove is spaced a certain distance from the gate footing, so that the DIBL can be minimized. The source / drain groove is filled with an epitaxial semiconductor material. Embodiments of the present invention also relate to semiconductor devices and methods for manufacturing the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] This scaling down also increases the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advances. For example, as fin field effect transistor (FinFET) technology advances toward smaller feature sizes (such as 32 nanometers, 28 nanometers, 20 nanometers, and below), advanced techniques are needed to precisely control the profile and / or size of source / drain features to ensure and optimize the reliability of FinFET devices. While existing FinFET source / drain formation techniques are generally adequate for their intended purposes, they have not been completely satisfactory in all respects. Summary of the invention

[0004] Some embodiments of the present invention provide a method for manufacturing a semiconductor device, comprising: forming a source / drain groove in a source / drain region of a fin, wherein forming the source / drain groove comprises: performing a first anisotropic etching process, then performing an isotropic etching process, and then performing a second anisotropic etching process; and filling the source / drain groove with an epitaxial semiconductor material.

[0005] Some other embodiments of the present invention provide a semiconductor device, comprising: a fin having a fin height; a gate stack disposed above a channel region of the fin; a gate spacer disposed along a sidewall of the gate stack, wherein the gate spacer has a gate spacer thickness; and an epitaxial source / drain component disposed in a source / drain region of the fin, wherein the epitaxial source / drain component has a candlelight bulb-shaped cross-sectional profile, so that the epitaxial source / drain component includes: a top portion disposed above a top surface of the fin, a middle portion disposed between the top surface of the fin and a tip of the epitaxial source / drain component, and a bottom portion disposed between the top surface of the fin and a depth of the epitaxial source / drain component in the fin, wherein: a tip depth of the tip of the epitaxial source / drain component is 10% to 40% of the fin height; and a footing proximity of the bottom of the epitaxial source / drain component is greater than 8nm at a depth greater than 80% of the fin height.

[0006] Some further embodiments of the present invention provide a semiconductor device, comprising: a fin disposed above the substrate, wherein the fin extends along a first direction; a gate structure disposed above a channel region of the fin, wherein the gate structure extends along a second direction different from the first direction, the gate structure comprising a metal gate and a gate spacer disposed along a sidewall of the metal gate, the metal gate having a gate footing at an interface between the fin and the metal gate, and the gate spacer having a gate spacer thickness along the first direction; and an epitaxial source / drain component disposed in a source / drain region of the fin, wherein the gate structure is disposed between the epitaxial source / drain components along the first direction, and wherein each of the epitaxial source / drain components comprises: a first portion having a first width along the first direction, wherein the first a second portion disposed above the first portion, wherein the second portion has a second width along the first direction, and the second width decreases from the maximum width of the epitaxial source / drain component along the first direction to the top surface of the fin, a third portion disposed above the second portion, wherein the second portion has a third width along the first direction, wherein the third width is substantially the same from the top surface of the fin to the top surface of the epitaxial source / drain component, and wherein a distance between the maximum width of the epitaxial source / drain component and the sidewall of the metal gate along the first direction is 5 nm to 8 nm, and a distance between the gate footer and the first portion of the epitaxial source / drain component is greater than 6 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a flow chart of a method for fabricating a fin field effect transistor (FinFET) device according to various aspects of the present invention.

[0009] Figure 2 is a perspective view of part or all of a FinFET device having source / drain regions according to various aspects of the present invention.

[0010] FIG. 3A to FIG. 3I According to various aspects of the present invention, Figure 1 The method is related to those of the various source / drain component manufacturing stages in the YZ plane along the line 1–1′ Figure 2 Partial cross-sectional view of a FinFET device.

[0011] FIG. 4A to FIG. 4I According to various aspects of the present invention, Figure 1 The method is related to those of the various source / drain component manufacturing stages in the XZ plane along line 2–2′ Figure 2 Partial cross-sectional view of a FinFET device.

[0012] Figure 5 shows how to adjust the various source / drain component manufacturing stages, such as with Figure 1 Those related to the methods to achieve the desired profiles for source / drain features according to various aspects of the present invention.

[0013] Figure 6 are graphs showing channel resistance characteristics and drain induced barrier lowering characteristics of FinFET devices having epitaxial source / drain features with different profiles according to various aspects of the present invention.

[0014] Figure 7 According to various aspects of the present invention, Fig. 3I and Fig. 4I A similar source / drain component manufacturing stage in the YZ plane along line 1–1′ Figure 2 Partial cross-sectional view of a FinFET device. DETAILED DESCRIPTION

[0015] The present invention relates generally to integrated circuit devices and, more particularly, to fin field effect transistors (FinFETs).

[0016] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, spatially relative terms, such as "lower", "upper", "horizontal", "vertical", "above", "above", "below", "below", "up", "down", "top", "bottom", etc. and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) are used to facilitate the description of the relationship between one component and another component of the present invention. Spatially relative terms are intended to cover different orientations of devices including components. In addition, when "about", "approximately", etc. are used to describe a numerical value or a numerical range, the term is intended to cover a reasonable range of numerical values, taking into account the changes that inherently occur during manufacturing. For example, a numerical value or a numerical range covers a reasonable range of numerical values ​​including the described numerical value, such as within + / -10% of the described numerical value or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm. Furthermore, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] For advanced IC technology nodes, FinFETs (also known as non-planar transistors) have become popular and promising candidates for high performance and low leakage applications. As FinFETs are scaled down through various technology nodes, strained source / drain features (also known as stressor regions or raised source / drain features) have been formed from epitaxial semiconductor materials to enhance carrier mobility and improve device performance. Forming the strained source / drain features typically includes etching grooves in the source / drain regions of the fins and filling the grooves with epitaxial semiconductor material. For example, silicon can be epitaxially grown in the source / drain grooves to form strained source / drain features for n-type FinFETs, and silicon germanium can be epitaxially grown in the source / drain grooves to form strained source / drain features for p-type FinFETs.

[0018] Various techniques for the shape, configuration, and materials of strained source / drain features may be implemented to further improve FinFET performance. For example, it has been observed that the proximity between the strained source / drain features and the channel region of the fin (e.g., defined in the fin below the gate stack) affects the operation of the FinFET. Therefore, conventional methods for manufacturing strained source / drain features tend to focus on configuring the tips of the strained source / drain features as close as possible to the channel region of the fin to reduce the resistance between the strained source / drain features and the channel region, and increase the mobility of carriers in the channel region, thereby improving the operation of the FinFET. However, it has been observed that the profiles of the strained source / drain features manufactured by these conventional methods generally increase drain induced barrier lowering (DIBL), thereby hindering short channel control. In some cases, it has been observed that the deteriorated DIBL eliminates any operational improvements achieved by the resistance reduction.

[0019] To overcome these challenges, the present invention recognizes that the depth of the tip of the strained source / drain component (in other words, the position of the tip relative to the top surface of the fin) and the proximity of the bottom of the strained source / drain component also affect the operation of the FinFET. For example, the present invention proposes a method for manufacturing a strained source / drain component, which controls the position of the tip of the strained source / drain component so that the tip is located in the top of the fin (for example, the distance between the top surface of the fin and the tip is equal to about 10% of the fin height to about 50% of the fin height). Compared with conventional strained source / drain components, the proposed method further increases the distance between the gate stack and the bottom of the strained source / drain component, thereby reducing the capacitance between the gate stack and the strained source / drain component. In some embodiments, the proposed strained source / drain component has a candlelight bulb-shaped cross-section. The proposed strained source / drain component is achieved by implementing a three-step etching process (including a first anisotropic etch, an isotropic etch, and a second anisotropic etch). This three-step etching process allows precise control of the position of the tip of the strained source / drain feature (particularly the depth of the tip in the fin and the distance between the tip and the channel region of the fin), as well as the distance between the bottom of the strained source / drain feature and the channel region and / or the gate stack. The disclosed profile of the strained source / drain feature can reduce resistance and reduce DIBL, thereby providing improved operation and short channel control for FinFETs. In the following description, details of the proposed method for fabricating the strained source / drain feature and the proposed profile for the strained source / drain feature are described herein.

[0020] Figure 11 is a flow chart of a method 100 for manufacturing an integrated circuit device according to various aspects of the present invention. In the present embodiment, the method 100 manufactures an integrated circuit device including a FinFET device. In frame 110 and frame 115, a fin is formed above a substrate, and a gate stack is formed above a channel region of the fin, respectively. The channel region of the fin is disposed between a source region of the fin and a drain region of the fin (collectively referred to as a source / drain region). In frame 120, a gate spacer is formed along a sidewall of the gate stack. Frame 120 may include frame 122, frame 124, and frame 126. For example, forming a gate spacer may include forming a spacer layer above the gate stack and the fin at frame 122, performing a first spacer etch (e.g., a main spacer etch) at frame 124, and performing a second spacer etch (e.g., a spacer over-etch) at frame 126. In some embodiments, a fin spacer is formed along the sidewall of the source / drain region of the fin. The fin spacer may be formed simultaneously with the gate spacer. At box 130, method 100 continues to form source / drain grooves in the source / drain region of the fin. As described in detail herein, the profile of the source / drain groove optimizes FinFET performance. Box 130 includes boxes 132, boxes 134, and boxes 136. For example, forming the source / drain grooves includes performing a first anisotropic etching process at box 132, performing an isotropic etching process at box 134, and performing a second anisotropic etching process at box 136. The depth of the source / drain grooves after the first anisotropic etching process and the depth of the source / drain grooves after the isotropic etching process are less than the target depth of the source / drain grooves. Parameters of the first anisotropic etching process and the isotropic etching process are adjusted to define the position of the tip of the source / drain groove, such as the tip depth and the tip proximity, to minimize the parasitic resistance between the source / drain component and the metal gate of the FinFET device. Parameters of the second anisotropic etch process are adjusted to extend the source / drain recesses to a target depth. Defining the location of the source / drain tips before extending the source / drain recesses to the target depth causes the bottom of the source / drain recesses to be pulled back from the metal gate during the second anisotropic etch process, thereby increasing the distance between any gate footing and the source / drain recesses, which improves short channel control. In some embodiments, the formation of the source / drain recesses may begin with the formation of the gate spacers at block 130, as described below.

[0021] The method 100 then proceeds to block 140, where the source / drain recesses are filled with a semiconductor material to form a semiconductor source / drain feature. In block 145, a dielectric layer is formed over the fins, the gate stack, the gate spacers, and the semiconductor source / drain feature. In block 150, where the method 100 includes a gate-last process, a gate replacement process is performed to replace the gate stack (e.g., a polysilicon dummy gate) with a metal gate stack, which may include a gate electrode disposed over a gate dielectric (e.g., a high-k dielectric layer). Optionally, in some embodiments, the method 100 includes a gate-first process, where the gate stack formed at block 115 is a metal gate stack, such that the method 100 may omit block 150. In yet another alternative, the method 100 includes a hybrid gate-first, gate-last process, which may involve forming portions of the metal gate stack at block 115, block 150, and / or other stages of the method 100. In block 155, the method 100 continues with forming contacts to the semiconductor source / drain features and / or metal gate stack. The process can continue to complete the fabrication of the FinFET device. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be moved, replaced, or eliminated for other embodiments of the method 100.

[0022] Figure 2 is a perspective view of a portion or all of a FinFET device 200 according to various aspects of the present invention. FIG. 3A to FIG. 3I is a partial cross-sectional view of a FinFET device 200 in a YZ plane along line 1 - 1 ′ at various fabrication stages, such as those associated with method 100 , in accordance with various aspects of the present invention. FIG. 4A to FIG. 4I is a partial cross-sectional view of a FinFET device 200 in the XZ plane along line 2–2′ at various stages of manufacturing (such as those associated with method 100) according to various aspects of the present invention. The FinFET device 200 may be included in a microprocessor, memory, and / or other IC devices. In some embodiments, the FinFET device 200 is part of an IC chip, a system on a chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. For clarity, the illustrations have been simplified. Figure 2 , FIG. 3A to FIG. 3I and FIG. 4A to FIG. 4I, to better understand the inventive concept of the present invention. Additional components may be added to the FinFET device 200, and some functions described below may be replaced, modified, or eliminated in other embodiments of the FinFET device 200.

[0023] exist Figure 2 , Figure 3A and Figure 4A In the embodiment depicted, the FinFET device 200 includes a substrate (wafer) 210. In the depicted embodiment, the substrate 210 includes silicon. Alternatively or additionally, the substrate 210 includes another element semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. Optionally, the substrate 210 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be manufactured using isolation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. Depending on the design requirements of the FinFET device 200, the substrate 210 may include various doped regions. For example, the substrate 210 may include a p-type doped region (referred to as a p-well) that may be configured for an n-type FinFET, and an n-type doped region (referred to as an n-well) that may be configured for a p-type FinFET. The N-type doped region is doped with an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. The P-type doped region is doped with a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, the substrate 210 includes a doped region formed by a combination of a p-type dopant and an n-type dopant. Various doped regions may be formed directly on and / or in the substrate 210, for example, providing a p-well structure, an n-well structure, a double-well structure, a raised structure, or a combination thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes may be implemented to form various doped regions of the FinFET device 200.

[0024] A fin structure 220 is formed over the substrate 210. Figure 2In the embodiment, the fin structure 220 includes a plurality of fins extending from the substrate 210, such as fin 222A and fin 222B. The present invention includes embodiments in which the fin structure 220 includes more fins or a single fin extending from the substrate 210. The fins 222A, 222B extend substantially parallel to each other along the y direction and have a length defined in the y direction, a width defined in the x direction, and a height defined in the z direction. For example, the fin height FH of the fins 222A, 222B is defined along the z direction between the top surface of the isolation component 225 and the corresponding top surface of the fins 222A, 222B. In some embodiments, the fin height FH is about 40nm to about 70nm. The fins 222A, 222B respectively have a channel region (C), a source region (S / D), and a drain region (S / D) defined along their lengths (here, along the y direction), wherein the channel region is disposed between the source region and the drain region, and both the source region and the drain region are collectively referred to as source / drain (S / D) regions. In some embodiments, the fins 222A, 222B are part of the substrate 210. For example, in the depicted embodiment in which the substrate 210 includes silicon, the fins 222A, 222B include silicon. Optionally, the fins 222A, 222B are defined in a material layer disposed on the substrate 210, such as a semiconductor material layer. The semiconductor material can be silicon, germanium, silicon germanium, III-V semiconductor materials, other suitable semiconductor materials, or combinations thereof. In some embodiments, the fins 222A, 222B include a stack of semiconductor layers disposed above the substrate 210. The semiconductor layers may include the same or different materials, dopants, etching rates, composition atomic percentages, composition weight percentages, thicknesses, and / or configurations, depending on the design requirements of the FinFET device 200.

[0025] A combination of deposition, lithography, and / or etching processes are performed to define the fins 222A, 222B extending from the substrate 210. For example, forming the fins 222A, 222B includes performing a lithography process to form a patterned mask layer over the substrate 210 (or a material layer disposed over the substrate 210), and performing an etching process to transfer the pattern defined in the patterned mask layer to the substrate 210 (or the material layer). The lithography process may include forming a resist layer over the substrate 210 (e.g., by spin coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a development process. During the exposure process, the resist layer is exposed to radiation energy (such as ultraviolet (UV) light, deep UV (DUV) light or extreme UV (EUV) light), wherein, according to the mask pattern and / or mask type (e.g., binary mask, phase shift mask or EUV mask) of the mask, the mask blocks, transmits and / or reflects radiation to the resist layer, thereby projecting an image corresponding to the mask pattern to the resist layer. Since the resist layer is sensitive to radiation, according to the characteristics of the resist layer and the characteristics of the developing solution used in the developing process, during the developing process, the exposed portion of the resist layer undergoes chemical changes, and the exposed (or unexposed) portion of the resist layer dissolves. After development, the patterned resist layer includes a resist pattern corresponding to the mask. In some embodiments, the patterned resist layer is a patterned mask layer. In such an embodiment, the patterned resist layer is used as an etching mask to remove portions of the substrate 210 (or material layer). In some embodiments, a patterned resist layer is formed over the mask layer formed over the substrate 210 before forming the resist layer, and the patterned resist layer is used as an etching mask to remove portions of the mask layer formed over the substrate 210. In such an embodiment, the patterned mask layer is used as an etching mask to remove portions of the substrate 210 (or material layer). The etching process may include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, a reactive ion etching (RIE) process is used to form the fins 222A, 222B. After the etching process, the patterned resist layer is removed from the substrate 210, for example, by a resist stripping process. In some embodiments, after the etching process, the patterned mask layer is removed from the substrate 210 (in some embodiments, by a resist stripping process). In some embodiments, the patterned mask layer is removed during etching of the substrate 210 (or material layer).Optionally, the fins 222A, 222B are formed by a multiple patterning process, such as a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a dielectric spacer (spacer-is-dielectric) (SID) SADP process, other double patterning processes, or a combination thereof), a triple patterning process (e.g., a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning processes, or a combination thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or a combination thereof. In some embodiments, a directed self-assembly (DSA) technique is implemented to form the fins 222A, 222B. In addition, in some optional embodiments, the exposure process may implement maskless lithography, electron beam writing, and / or ion beam writing for patterning.

[0026] An isolation component 225 is formed above and / or in the substrate 210 to separate and isolate various regions of the FinFET device 200, such as the fin 222A and the fin 222B. In the depicted embodiment, the isolation component 225 surrounds the lower portion L of the fins 222A and 222B. The upper portion U of the fins 222A and 222B extends from the isolation component 225 and the substrate 210 along the z-direction, so that the top surface of the fin 222A and the fin 222B is disposed above the top surface of the isolation component 225 along the z-direction. The isolation component 225 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon or other suitable isolation components), or a combination thereof. The isolation component 225 can be configured as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, and / or a local oxidation of silicon (LOCOS) structure. For example, the isolation component 225 can be an STI component that defines the fins 222A, 222B and electrically isolates the fins 222A, 222B from other device regions (such as fins). The STI component can be formed by etching a trench in the substrate 210 (e.g., by using a dry etching process and / or a wet etching process) and filling the trench with an insulating material (e.g., using a chemical vapor deposition (CVD) process or a spin coating process). A chemical mechanical polishing (CMP) process can be implemented to remove excess insulating material and / or planarize the top surface of the isolation component 225. In another example, the STI component can be formed by depositing an insulating material over the substrate 210 after forming the fins 222A, 222B (in some embodiments, so that the insulating material layer fills the gap (trench) between the fins 222A, 222B) and etching back the insulating material layer to form the isolation component 225. In some embodiments, the STI component includes a multilayer structure that fills the trench, such as a silicon nitride layer disposed over a thermal oxide liner layer. In another example, the STI feature includes a dielectric layer disposed over a doped liner layer including, for example, borosilicate glass (BSG) or phosphosilicate glass (PSG). In yet another example, the STI feature includes a bulk dielectric layer disposed over the liner dielectric layer, wherein the bulk dielectric layer and the liner dielectric layer include materials depending on design requirements of the FinFET device 200.

[0027] A gate stack (such as gate stack 230A and gate stack 230B) is formed over portions of the fins 222A, 222B and over the isolation features 225. The gate stacks 230A, 230B extend longitudinally in a direction different from (e.g., perpendicular to) the longitudinal direction of the fins 222A, 222B. For example, the gate stacks 230A, 230B extend substantially parallel to each other along the x-direction, have a length defined in the x-direction, a width defined in the y-direction, and a height defined in the z-direction. The gate stacks 230A, 230B are disposed between the S / D regions of the fins 222A, 222B, wherein the channel regions of the fins 222A, 222B are located below the gate stacks 230A, 230B. In the XZ plane, the gate stacks 230A, 230B wrap around the top and sidewall surfaces of the fins 222A, 222B. In the YZ plane, the gate stacks 230A, 230B are disposed above the top surfaces of the corresponding channel regions of the fins 222A, 222B. In the depicted embodiment, the gate stacks 230A, 230B are dummy gate stacks, which include a dummy gate electrode 232 and a hard mask 234 disposed above the dummy gate electrode 232. The dummy gate electrode 232 includes a suitable dummy gate material, such as a polysilicon layer. In some embodiments, the gate stacks 230A, 230B can therefore be referred to as polysilicon (PO) gate stacks. The hard mask layer 234 includes silicon oxide, silicon carbide, silicon nitride, other suitable hard mask materials, or combinations thereof. In some embodiments, the gate stacks 230A, 230B also include a gate dielectric disposed between the dummy gate electrode 232 and the fins 222A, 222B, wherein the gate dielectric includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or combinations thereof. In some embodiments, the gate dielectric includes an interface layer (e.g., a silicon oxide layer) disposed above the fins 222A, 222B and a high-k dielectric layer disposed above the interface layer. The gate stacks 230A, 230B may include many other layers, such as a capping layer, an interface layer, a diffusion layer, a barrier layer, or a combination thereof. The gate stacks 230A, 230B are formed by a deposition process, a photolithography process, an etching process, other suitable processes, or a combination thereof. For example, a deposition process is performed to form a dummy gate electrode layer above the fins 222A, 222B and the isolation component 225, and a hard mask layer is formed above the dummy gate electrode layer. In some embodiments, before forming the dummy gate electrode layer, a deposition process is performed to form a gate dielectric layer above the fins 222A, 222B and / or the isolation component 225. In such an embodiment, the dummy gate electrode layer is deposited above the gate dielectric layer.The deposition process includes CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), plasma enhanced ALD (PEALD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other suitable methods or combinations thereof. A gate patterning process (including, for example, various photolithography processes, etching processes and / or cleaning processes) is then performed to pattern the dummy gate electrode layer and the hard mask layer (and in some embodiments, the gate dielectric layer) to form a gate electrode layer such as. Figure 2 Gate stacks 230A, 230B are shown.

[0028] The gate stacks 230A, 230B have a gate length L gl , gate length L gl The gate stack 230A, 230B has a gate footing GF (also called a gate skirt or a grid) disposed along the bottom of the gate stack 230A, 230B, so that the gate stack 230A, 230B has a gate length L greater than the gate length L along the bottom of the gate stack 230A, 230B. g1 The gate length L g2 The gate foot GF has a tapered width that increases along the z direction, so that the gate length L g2Also increases along the z direction. The gate footing GF (or bottom gate profile) of the gate stacks 230A, 230B can vary depending on the patterning environment (e.g., isolated pattern or dense pattern), the location of the gate stacks 230A, 230B on the wafer (e.g., edge or center), and / or the proximity of the area of ​​the gate stacks 230A, 230B to the fins 222A, 222B (e.g., the gate area immediately adjacent to the fins 222A, 222B or the gate area at the ends of the gate stacks 230A, 230B). In some embodiments, as shown, the gate footing GF extends along the entire width of the gate stacks 230A, 230B. In some embodiments, the gate footing GF extends partially along the width of the gate stacks 230A, 230B. In some embodiments, the gate footing GF exists only at the interface region IF between the fins 222A, 222B and the gate stacks 230A, 230B, such as at the corners between the fins 222A, 222B and the gate stacks 230A, 230B. The gate footing GF may be caused by the fact that the conventional etching process cannot obtain the substantially vertical sidewalls of the high aspect ratio gate pattern as expected. The high aspect ratio gate pattern generally refers to a gate pattern having a ratio of gate height (e.g., along the z direction) to gate length (e.g., along the y direction) greater than about 5 (i.e., gate height / gate length ≥ 5). Recently, the gate patterning process has been adjusted to form the gate footing GF in an expected manner to minimize (or eliminate) the gate collapse problem caused by the high aspect ratio gate pattern. However, as the device size decreases, the gate footing GF poses new challenges to source / drain manufacturing. For example, conventional source / drain fabrication techniques fail to take into account the proximity of the source / drain component to the gate footing GF, which affects the capacitive coupling between the source / drain component and the final metal gate of the FinFET. As the proximity between the source / drain component and the gate footing GF decreases, the parasitic capacitance between the source / drain component and the gate footing GF increases, thereby reducing the FinFET performance. In some cases, conventional source / drain fabrication techniques may expose the gate footing GF, causing the source / drain component to physically contact the gate footing GF and cause an electrical short. Therefore, the proposed source / drain fabrication technique takes into account the proximity of the source / drain component to the gate footing GF and obtains a source / drain profile that minimizes the parasitic capacitance between the source / drain component and the gate footing GF. It has been observed that this can provide better control of the short channel effect of the FinFET device, such as by reducing the DIBL, as further described below.

[0029] exist FIG. 3B to FIG. 3D and FIG. 4B to FIG. 4D In some embodiments, gate spacers are formed along sidewalls of the gate stacks 230A and 230B. In some embodiments, fin spacers are also formed along sidewalls of the fins 222A and 222B. Figure 3B and Figure 4B , forming a spacer layer 240 over the FinFET device 200 (e.g., at block 122 of method 100). For example, a deposition process is performed to deposit a dielectric layer over the fins 222A, 222B, the isolation features 225, and the gate stacks 230A, 230B. The deposition process is CVD, PECVD, ALD, PEALD, PVD, other suitable deposition processes, or combinations thereof. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable spacer components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), etc.). In the depicted embodiment, the spacer layer 240 includes silicon and nitrogen (and may therefore be referred to as a silicon nitride layer). In some embodiments, the spacer layer 240 is a single layer, such as a silicon nitride layer. In some embodiments, the spacer layer 240 includes multiple layers, such as a first dielectric layer disposed above the second dielectric layer. For example, the first dielectric layer may include silicon carbonitride, and the second dielectric layer may include silicon nitride. In further embodiments depicted, the thickness t of the spacer layer 240 is from about 5 nm to about 15 nm. In some embodiments, the spacer layer 240 has a substantially uniform thickness along the top and sidewall surfaces of the gate stacks 230A, 230B and the fins 222A, 222B. For example, the thickness of the spacer layer 240 along the top surfaces of the gate stacks 230A, 230B and the top surfaces of the isolation features 225 is substantially the same as the thickness of the spacer layer 240 along the sidewall surfaces of the gate stacks 230A, 230B. The thickness of the spacer layer 240 along the top surfaces of the fins 222A, 222B and the top surfaces of the isolation layer 225 is also substantially the same as the thickness of the spacer layer 240 along the sidewall surfaces of the fins 222A, 222B. In some embodiments, the spacer layer 240 is formed by a conformal deposition process such that the spacer layer 240 conforms to the surface of the FinFET device 200 on which it is deposited (and may therefore be referred to as a conformal spacer layer).

[0030] Then, the process continues to perform a spacer etching process on the spacer layer 240 (e.g., at blocks 124 and 126 of the method 100) to form gate spacers 242 along the sidewalls of the gate stacks 230A, 230B and fin spacers 244 along the sidewalls of the fins 222A, 222B. The spacer etching process includes a first spacer etching ( Figure 3C and Figure 4C , called spacer main etch (SME)) and second spacer etch ( Figure 3D and Figure 4D, referred to as spacer over-etch (SOE)). During the spacer etch process, the first spacer etch and / or the second spacer etch may not remove portions of the fins 222A, 222B in the S / D regions as intended or expected, thereby beginning to form source / drain recesses 250 in the S / D regions of the fins 222A, 222B. In some embodiments, after forming the gate spacers 242, the depth of the source / drain recesses 250 is less than about 20% of the fin height FH. For example, the source / drain recesses 250 have a depth d1 ( Figure 3C and Figure 4C ), and has a depth d2 after the second spacer etch ( Figure 3D and Figure 4D ). After the first spacer etch, a depth d1 is measured between the respective top surfaces of the fins 222A, 222B and the respective portions of the fins 222A, 222B that define the bottommost surface of the source / drain recess 250. After the second spacer etch, a depth d2 is measured between the respective top surfaces of the fins 222A, 222B and the respective portions of the fins 222A, 222B that define the bottommost surface of the source / drain recess 250. In some embodiments, the depth d1 is less than or equal to about 10% of the fin height FH, and the depth d2 is about 10% to about 20% of the fin height FH. In some embodiments, the depth d1 is about 4 nm to about 10 nm. In some embodiments, the depth d2 is about 4 nm to about 15 nm. In some embodiments, the present invention also contemplates embodiments in which the first spacer etch and / or the second spacer etch do not remove portions of the fins 222A, 222B in the S / D region, such that the depth d1 and / or the depth d2 may be equal to 0.

[0031] Go to Figure 3C and Figure 4C, the first spacer etch selectively removes the spacer layer 240 relative to the gate stacks 230A, 230B, the isolation features 225, and / or the fins 222A, 222B. In other words, the first spacer etch substantially removes the spacer layer 240, but does not remove or substantially does not remove the gate stacks 230A, 230B, the isolation features 225, and / or the fins 222A, 222B. The first spacer etch substantially removes the spacer layer 240 from horizontal (lateral) surfaces of the FinFET device 200, such as the top surfaces of the fins 222A, 222B, the top surfaces of the isolation features 225, and the top surfaces of the gate stacks 230A, 230B, thereby forming gate spacers 242 having a thickness t1 along sidewalls of the gate stacks 230A, 230B, and forming fin spacers 244 along sidewalls of the fins 222A, 222B. In some embodiments, the thickness t1 is about 3 nm to about 10 nm. The first spacer etch may also remove portions of the fins 222A, 222B in the S / D regions to begin forming the source / drain recesses 250. For example, after the first spacer etch, the source / drain recesses 250 have a depth d1. In some embodiments, depending on the design and / or process requirements of the FinFET device 200, the gate spacers 242 include more than one set of spacers, such as sealing spacers, biasing spacers, sacrificial spacers, dummy spacers, and / or main spacers.

[0032] The first spacer etch is an anisotropic etch process, which generally refers to an etch process having different etch rates in different directions, such that the etch process removes material in a particular direction, such as substantially in one direction. For example, the vertical etch rate of the first spacer etch is greater than the horizontal etch rate (in some embodiments, the horizontal etch rate is equal to zero). Therefore, the first spacer etch substantially removes material in the vertical direction (here, the z direction), while removing minimal (to no) material in the horizontal direction (here, the x direction and / or the y direction). In some embodiments, the first spacer etch is a dry etch process, such as an RIE process, which uses a fluorine-containing etching gas to remove the material of the spacer layer 240 (e.g., silicon nitride) at a higher rate than the material of the gate stack 230A, 230B (e.g., oxide hard mask or polysilicon), the isolation feature 225 (e.g., silicon oxide), and / or the fin 222A, 222B (e.g., silicon) (i.e., the etchant has a high etch selectivity relative to silicon nitride). In some embodiments, the first spacer etch is configured to generate a fluorine-containing plasma from a fluorine-containing gas, so that the first spacer etch removes a portion of the spacer layer 240 using a fluorine-containing substance excited by the plasma. The fluorine-containing etching gas includes fluorine (F2), fluoromethane (e.g., CH3F2), difluoromethane (e.g., CH2F2), trifluoromethane (e.g., CHF3), tetrafluoromethane (e.g., CF4), hexafluoroethane (e.g., C2F6), sulfur hexafluoride (e.g., SF6), nitrogen trifluoride (e.g., NF3), other fluorine-containing etchants, or combinations thereof. The first spacer etch may alternatively or additionally use a hydrogen-containing etching gas (e.g., H2 and / or CH4), a nitrogen-containing etching gas (e.g., N2 and / or NH3), a chlorine-containing etching gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), an oxygen-containing etching gas (e.g., O2), a bromine-containing etching gas (e.g., HBr and / or CHBr3), an iodine-containing etching gas, other suitable etching gases, or combinations thereof. The first spacer etch can be configured to generate plasma from any etching gas disclosed herein, so that the first spacer etch uses plasma-excited substances for etching. In some embodiments, a carrier gas is used to deliver fluorine-containing etching gas and / or other etching gases. The carrier gas can be an inert gas, such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, other suitable inert gases, or a combination thereof. In some embodiments, the first spacer etch is a wet anisotropic etching process.

[0033] The various etching parameters of the first spacer etching can be adjusted to achieve the selectivity and anisotropic etching of the spacer layer 240, and the various etching parameters are such as etching gas composition, carrier gas composition, etching gas flow rate, carrier gas flow rate, etching time, etching pressure, etching temperature, source power, radio frequency (RF) and / or direct current (DC) bias voltage, RF and / or DC bias power, other suitable etching parameters or combinations thereof. In some embodiments, the first spacer etching utilizes an etching gas including CF4 to selectively etch the spacer layer 240, wherein the flow rate, etching time, etching temperature, etching pressure and / or RF power of CF4 can be adjusted to achieve the desired etching selectivity. In some embodiments, the flow rate of CF4 is about 200sccm to about 300sccm. In some embodiments, the first spacer etching utilizes an etching gas including CF4 and HBr, wherein the ratio of CF4 to HBr, etching time, etching temperature, etching pressure and / or RF power can be adjusted to achieve the desired etching selectivity. In some embodiments, the ratio of the flow rate of CF4 to the flow rate of HBr is about 1:2 to about 2:1. In some embodiments, the flow rate of CF4 is about 200 sccm to about 300 sccm. In some embodiments, the flow rate of HBr is about 200 sccm to about 300 sccm. In some embodiments, the duration of the first spacer etch is about 5 seconds to about 50 seconds. In some embodiments, the RF power used to generate the fluorine-containing plasma for the first spacer etch is about 400 W to about 500 W. In some embodiments, the pressure maintained in the process chamber during the first spacer etch is about 10 mTorr to about 50 mTorr. In some embodiments, the temperature maintained in the process chamber during the first spacer etch is about 20°C to about 70°C. In some embodiments, the various etching parameters of the first spacer etch are adjusted to achieve the desired etching of the fins 222A, 222B. In some embodiments, the various etching parameters of the first spacer etch are adjusted to achieve the desired thickness and / or desired profile of the gate spacer 242 and / or the fin spacer 244.

[0034] Go to Figure 3D and Figure 4D, a second spacer etch is performed to remove any remaining material (e.g., residue) of the spacer layer 240 along horizontal surfaces of the FinFET device 200, such as top surfaces of the fins 222A, 222B, top surfaces of the isolation features 225, and top surfaces of the gate stacks 230A, 230B. For example, the second spacer etch selectively removes any remaining material of the spacer layer 240 relative to the gate stacks 230A, 230B, the isolation features 225, and / or the fins 222A, 222B. In other words, the second spacer etch substantially removes the spacer layer 240, but does not remove or substantially does not remove the gate stacks 230A, 230B, the isolation features 225, and / or the fins 222A, 222B. The second spacer etch may also remove portions of the fins 222A, 222B in the S / D regions to begin and / or continue forming the source / drain recesses 250. For example, the source / drain recesses 250 have a depth d2 after the second spacer etch, wherein the depth d2 is greater than the depth d1. The second spacer etch may also be used to adjust the thickness t1 and / or the profile of the gate spacers 242 and / or the thickness and / or profile of the fin spacers 244.

[0035] The second spacer etch is an anisotropic etching process. For example, the vertical etching rate of the second spacer etch is greater than the horizontal etching rate (in some embodiments, the horizontal etching rate is equal to zero). Therefore, the second spacer etch removes material substantially in the vertical direction (here, the z direction), while the material removal in the horizontal direction (here, the x direction and / or the y direction) is minimal (no). In some embodiments, the etching selectivity of silicon nitride (i.e., the spacer layer 240) to silicon (i.e., the fins 222A, 222B) etched by the second spacer is greater than the etching selectivity of silicon nitride to silicon etched by the first spacer. In such an embodiment, the fins 222A, 222B can be etched more by the first spacer etch than by the second spacer etch, so that the thickness (or depth) of the fins 222A, 222B removed by the first spacer etch is greater than the thickness (or depth) of the fins 222A, 222B removed by the second spacer etch. In some embodiments, the second spacer etch is a dry etching process, such as an RIE process, which uses a fluorine- and hydrogen-containing etching gas to remove the material of the spacer layer 240 (e.g., silicon nitride) at a higher rate than the material of the gate stack 230A, 230B (e.g., oxide hard mask or polysilicon), the isolation feature 225 (e.g., silicon oxide), and / or the fin 222A, 222B (e.g., silicon) (i.e., the etchant has a high etching selectivity with respect to silicon nitride). In some embodiments, the second spacer etch is configured to generate a fluorine- and hydrogen-containing plasma from the fluorine- and hydrogen-containing gas, so that the second spacer etch uses the plasma-excited fluorine- and hydrogen-containing species to remove portions of the spacer layer 240. The fluorine- and hydrogen-containing etching gas includes fluoromethane (e.g., CH3F2), difluoromethane (e.g., CH2F2), trifluoromethane (e.g., CHF3), other fluorine-containing etchants, or combinations thereof. The second spacer etch may alternatively or additionally use a hydrogen-containing etching gas (e.g., H2 and / or CH4), a nitrogen-containing etching gas (e.g., N2 and / or NH3), a chlorine-containing etching gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), an oxygen-containing etching gas (e.g., O2), a bromine-containing etching gas (e.g., HBr and / or CHBr3), an iodine-containing etching gas, a fluorine-containing etching gas (e.g., F2, CF4, C2F6, SF6 and / or NF3), other suitable etching gases, or combinations thereof. The second spacer etch may be configured to generate a plasma from any etching gas disclosed herein, so that the second spacer etch is etched using a plasma-excited substance. In some embodiments, a carrier gas is used to transport a fluorine-containing etching gas and / or other etching gas. The carrier gas may be an inert gas, such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, the second spacer etch is a wet anisotropic etching process.

[0036] The various etching parameters of the second spacer etching can be adjusted to achieve selectivity and anisotropic etching of the spacer layer 240, and the various etching parameters are, for example, etching gas composition, carrier gas composition, etching gas flow rate, carrier gas flow rate, etching time, etching pressure, etching temperature, source power, RF and / or DC bias voltage, RF and / or DC bias power, other suitable etching parameters, or combinations thereof. In some embodiments, the second spacer etching utilizes an etching gas including CH3F and O2, wherein the ratio of CH3F to O2, etching time, etching temperature, etching pressure, and / or RF power can be adjusted to achieve the desired etching selectivity. In some embodiments, the ratio of the flow rate of CH3F to the flow rate of O2 is about 1:1 to about 4:1. In some embodiments, the flow rate of CH3F is about 100 sccm to about 200 sccm. In some embodiments, the flow rate of O2 is about 50 sccm to about 150 sccm. In some embodiments, the duration of the second spacer etching is about 5 seconds to about 50 seconds. In some embodiments, the RF power used to generate the plasma containing hydrogen and fluorine for the second spacer etch is about 400 W to about 500 W. In some embodiments, the pressure maintained in the process chamber during the second spacer etch is about 10 mTorr to about 50 mTorr. In some embodiments, the temperature maintained in the process chamber during the second spacer etch is about 20° C. to about 70° C. In some embodiments, various etching parameters of the second spacer etch are adjusted to achieve the desired etching of the fins 222A, 222B in the S / D region 250. In some embodiments, various etching parameters of the first spacer etch are adjusted to achieve the desired thickness and / or desired profile of the gate spacer 242 and / or the fin spacer 244.

[0037] Then, if Figures 3E to 3G and FIG. 4E to FIG. 4G As shown, the process continues to implement a three-step source / drain etching process to form source / drain recesses 250 in the S / D regions of the fins 222A, 222B. After the three-step source / drain etching process, the source / drain recesses 250 extend to a target depth TD in the fins 222A, 222B. In some embodiments, the target depth TD is about 80% to about 120% of the fin height FH (e.g., about 120% of the fin height FH). In some embodiments, the target depth TD is about 30nm to about 80nm. When the gate spacers 242 are manufactured to begin forming the source / drain recesses 250, such as in the depicted embodiment, the three-step source / drain etching process completes the formation of the source / drain recesses 250. In the depicted embodiment, the three-step source / drain etching process includes a first anisotropic source / drain etch ( Figure 3E and Figure 4E ), isotropic source / drain etching ( Figure 3F and Figure 4F) and the second anisotropic source / drain etch ( Figure 3G and Figure 4G ). The three-step source / drain etching process can accurately control the tip position of the epitaxial source / drain component (particularly the depth of the tip in the fins 222A, 222B and the proximity (distance) of the tip to the channel region of the fins 222A, 222B) and the distance between the bottom of the epitaxial source / drain component and the channel region and / or the gate stack. For example, before extending the source / drain recess to the target depth TD, the first anisotropic source / drain etch and the isotropic source / drain etch are adjusted to achieve the position of the tip of the epitaxial source / drain component. In some embodiments, the position of the tip of the epitaxial source / drain component is defined before the source / drain recess reaches a depth greater than about 80% of the fin height FH (i.e., the depth of the source / drain recess after the first anisotropic source / drain etch and the isotropic source / drain etch is less than or equal to about 80% of the fin height FH). After defining the position of the tip of the epitaxial source / drain feature, extending the source / drain recess to a target depth can pull the bottom of the epitaxial source / drain feature back from the gate footer GF, which reduces the parasitic capacitance between the epitaxial source / drain feature and the gate stack.

[0038] Go to Figure 3E and Figure 4E, the first anisotropic source / drain etch extends the source / drain recess 250 to a depth d3 in the S / D regions of the fins 222A, 222B. After the first anisotropic source / drain etch, the depth d3 is measured between the respective top surfaces of the fins 222A, 222B and the respective portions of the fins 222A, 222B that define the bottommost surface of the source / drain recess 250. The depth d3 is less than the target depth TD and is selected based on the desired tip depth of the source / drain recess 250 (i.e., the depth of the tip along the fin height FH). In some embodiments, the depth d3 is about 10% to about 80% of the fin height FH, depending on the desired tip depth. In some embodiments, after the three-step source / drain recess etch, the position of the tip depth along the fin height FH is about 40% to about 60% of the depth d3 (i.e., 0.4d3≤tip depth≤0.6d3). In such an embodiment, a first anisotropic source / drain etch is performed until a depth d3 is about 50% of the fin height FH, with a desired tip depth of about 20% to about 30% of the fin height FH. In some embodiments, the depth d3 is selected so that the tip depth is less than about 50% of the fin height FH. For example, the depth d3 is selected to obtain a tip depth of about 10% to about 30% of the fin height FH. In such an embodiment, the depth d3 can be about 25% to about 50% of the fin height FH. In some embodiments, the depth d3 is about 10nm to about 60nm. At the location where the first spacer etch and the second spacer etch begin to form the source / drain recess 250, such as in the described embodiment, the depth d3 is greater than the depth d1, the depth d2, and the sum of the depth d1 and the depth d2.

[0039] The first anisotropic source / drain etch is controlled to produce a source / drain recess 250 having a U-shaped profile in the YZ plane. For example, after the first anisotropic source / drain etch, the source / drain recess 250 is defined by a sidewall segment A, a sidewall segment B, and a bottom segment C extending between the sidewall segment A and the sidewall segment B. The sidewall segment A is substantially linear, the sidewall segment B is substantially linear, and the bottom segment C is curved. In the described embodiment, the sidewall segment A and the sidewall segment B extend substantially parallel to each other along the z direction. The source / drain recess 250 has a width w1. In some embodiments, the width w1 is about 10 nm to about 35 nm. In further described embodiments, the source / drain recesses 250 extend under the gate spacers 242 such that the sidewall segments A are offset along the y-direction from the outer sidewalls OS of the corresponding gate spacers 242 along the gate stack 230A, and the sidewall segments B are offset along the y-direction from the outer sidewalls OS of the corresponding gate spacers 242 along the gate stack 230B. In such embodiments, the width w1 is greater than the spacing S between the outer sidewalls OS of the gate spacers 242. In some embodiments, the source / drain recesses 250 do not extend under the gate spacers 242. For example, the sidewall segments A may be substantially aligned along the z-direction with the outer sidewalls OS of the corresponding gate spacers 242 along the gate stack 230A, and the sidewall segments B may be substantially aligned along the z-direction with the outer sidewalls OS of the corresponding gate spacers 242 along the gate stack 230B. In such embodiments, the width w1 is approximately equal to the spacing S between the outer sidewalls OS of the gate spacers 242. The present invention also contemplates embodiments in which sidewall segment A and sidewall segment B are substantially linear with a slight slope in the YZ plane, such as sidewall segment A having a slight negative slope and sidewall segment B having a slight positive slope.

[0040] The first anisotropic source / drain etch selectively removes the fins 222A, 222B relative to the gate spacers 242, the fin spacers 244, the gate stacks 230A, 230B, and / or the isolation features 225. In other words, the first anisotropic source / drain etch substantially removes the fins 222A, 222B, but does not remove or substantially does not remove the gate spacers 242, the fin spacers 244, the gate stacks 230A, 230B, and / or the isolation features 225. The vertical etch rate of the first anisotropic source / drain etch is greater than the horizontal etch rate (in some embodiments, the horizontal etch rate is zero). Therefore, the first anisotropic source / drain etch removes portions of the fins 222A, 222B in a substantially vertical direction (here, the z-direction), while removing minimal (to no) material in the horizontal direction (here, the x-direction and / or the y-direction). For example, the ratio of the vertical etch rate (VER) to the horizontal etch rate (HER) of the first anisotropic source / drain etch is greater than about 20 (e.g., 20≤VER / HER≤80). In some embodiments, the first anisotropic source / drain etch is controlled to exhibit a desired degree of anisotropy (A), defined as one minus the ratio of HER to VER (i.e., A=1HER / VER). In some embodiments, the degree of anisotropy is about 0.95 to about 1. In some embodiments, vertical etching refers to etching downward in a direction perpendicular to the top surfaces of the fins 222A, 222B, while horizontal etching refers to etching in a direction parallel to the top surfaces of the fins 222A, 222B. In some embodiments, the first anisotropic source / drain etch is a dry etching process, such as a RIE process, which uses a bromine-containing etching gas to remove the material (e.g., silicon) of the fins 222A, 222B at a higher rate than the material of the gate spacers 242 (e.g., silicon nitride), the fin spacers 244 (e.g., silicon nitride), the gate stacks 230A, 230B (e.g., oxide hard mask or polysilicon), and / or the isolation features 225 (e.g., silicon oxide) (i.e., the etchant has a high etching selectivity relative to silicon). The bromine-containing etching gas includes bromine (Br), hydrogen bromide (HBr), methyl bromide (CH3Br), dibromomethane (CH2Br2), bromoform (CHBr3), other bromine-containing etchants, or combinations thereof. In some embodiments, the first anisotropic source / drain etch is configured to generate a bromine-containing plasma from the bromine-containing etching gas, so that the first anisotropic source / drain etch removes portions of the fins 222A, 222B in the S / D regions using plasma-excited bromine-containing species.The first anisotropic source / drain etch may alternatively or additionally use a hydrogen-containing etching gas (e.g., H2 and / or CH4), a nitrogen-containing etching gas (e.g., N2 and / or NH3), a chlorine-containing etching gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), an oxygen-containing etching gas (e.g., O2), a fluorine-containing etching gas (e.g., F2, CH3F, CH2F2, CHF3, CF4, C2F6), an iodine-containing etching gas, other suitable etching gases, or a combination thereof. In some embodiments, a carrier gas is used to transport the etching gas. The carrier gas may be an inert gas, such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, other suitable inert gases, or a combination thereof. In some embodiments, the first anisotropic source / drain etch is a wet anisotropic etching process.

[0041] Adjust the various etching parameters of the first anisotropic source / drain etching to control the selective etching and anisotropic etching of the fins 222A, 222B to produce the desired depth d3 and the U-shaped profile of the source / drain groove 250, and the various etching parameters such as etching gas composition, carrier gas composition, etching gas flow rate, carrier gas flow rate, etching time, etching pressure, etching temperature, source power, RF and / or DC bias voltage, RF and / or DC bias power, other suitable etching parameters or combinations thereof. In some embodiments, the first anisotropic source / drain etching utilizes an etching gas including HBr, wherein the flow rate, etching time, etching temperature, etching pressure and / or RF power of HBr can be adjusted to achieve the desired etching selectivity and / or the desired source / drain groove profile. In such an embodiment, the flow rate of HBr is about 100 sccm to about 200 sccm. In some embodiments, the duration of the first anisotropic source / drain etching is about 30 seconds to about 80 seconds. In some embodiments, the RF power used to generate the bromine-containing plasma is about 300 W to about 400 W. In some embodiments, the pressure maintained in the process chamber during the first anisotropic source / drain etch is about 5 mTorr to about 30 mTorr. In some embodiments, the temperature maintained in the process chamber during the first anisotropic source / drain etch is about 20° C. to about 70° C. In some embodiments, the first anisotropic source / drain etch utilizes an etching gas including Cl2, wherein the flow rate of Cl2, etching time, etching temperature, etching pressure and / or RF power can be adjusted to achieve a desired etching selectivity and / or a desired source / drain recess profile.

[0042] Go to Figure 3F and Figure 4F, an isotropic source / drain etch is performed to widen the source / drain recess 250 and control the tip proximity of the tip source / drain recess 250. The isotropic source / drain etch is controlled to produce a source / drain recess 250 having a bowl-shaped profile in the YZ plane. For example, after the isotropic source / drain etch, the source / drain recess 250 is defined by a sidewall segment A', a sidewall segment B', and a bottom segment C' extending between the sidewall segment A' and the sidewall segment B'. The sidewall segment A' is curved, the sidewall segment B' is curved, and the bottom segment C' is curved. The sidewall segment A' extends from the top surface of the fins 222A, 222B toward the gate stack 230A to the source / drain tip v1, where the sidewall segment A' intersects with the bottom segment C'. The sidewall segment B' extends from the top surface of the fins 222A, 222B toward the gate stack 230B to the source / drain terminal v2, where the sidewall segment B' intersects the bottom segment C'. Such a configuration allows the source / drain recess 250 to have a wide central portion disposed between narrower ends, wherein the width of the narrower ends gradually decreases from the wide central portion along the z-direction. The source / drain recess 250 thus has a width w2 that varies along the fin height FH, wherein the width w2 is equal to the maximum width of the source / drain recess 250 between the source / drain tip v1 and the source / drain tip v2. The source / drain tips v1, v2 have an initial tip depth dti, wherein the tip depth generally refers to the vertical distance between the portion of the gate stack (and / or the top surface of the fin) and the source / drain component closest to the gate stack (i.e., the tip). In some embodiments, the initial tip depth dti is about 10% to about 40% of the fin height FH. The source / drain tips v1, v2 also have an initial tip proximity pi, where the tip proximity generally refers to the lateral distance between the sidewall of the gate stack and the portion of the source / drain component closest to the sidewall of the gate stack (i.e., the distance between the source / drain tips v1, v2 and the corresponding channel region). In some embodiments, the initial tip proximity pi is about 60% to about 90% of the thickness t1 of the gate spacer 242 (e.g., 0.6t1≤p≤0.9t1). In some embodiments, the initial tip proximity pi is about 5nm to about 8nm. The isotropic source / drain etch can also deepen the source / drain recess 250, for example, extending the source / drain recess 250 to a depth d4 that is greater than the depth d3 and less than the target depth TD. After the isotropic source / drain etch, a depth d4 is measured between respective top surfaces of the fins 222A, 222B and respective portions of the bottommost surfaces of the fins 222A, 222B defining the source / drain recesses 250. In some embodiments, the depth d4 is about 10% to about 80% of the fin height FH, such as about 50% of the fin height FH. In some embodiments, the depth d4 is about 10 nm to about 70 nm.

[0043] The isotropic source / drain etch selectively removes the fins 222A, 222B relative to the gate spacers 242, the fin spacers 244, the gate stacks 230A, 230B, and / or the isolation features 225. In other words, the isotropic source / drain etch substantially removes the fins 222A, 222B, but does not remove or substantially does not remove the gate spacers 242, the fin spacers 244, the gate stacks 230A, 230B, and / or the isolation features 225. In contrast to the first anisotropic source / drain etch, the isotropic source / drain etch etches along multiple directions (in some embodiments, the vertical etching rate is the same as the horizontal etching rate). The isotropic source / drain etch thus removes portions of the fins 222A, 222B in all directions (here, the z-direction, the y-direction, and the x-direction). For example, the ratio of VER to HER for the isotropic source / drain etch is about 1. In some embodiments, the ratio of VER to HER of the isotropic source / drain etch is about 1 to about 5 (e.g., 1≤VER / HER≤5). In some embodiments, the isotropic source / drain etch is controlled to exhibit a degree of anisotropy that is less than the degree of anisotropy of the first anisotropic source / drain etch. For example, the degree of anisotropy of the isotropic source / drain etch is less than about 0.8 (0 in some embodiments). In some embodiments, the isotropic source / drain etch is a dry etch process, such as an RIE process, which uses an etching gas containing fluorine and chlorine to remove the material of the fins 222A, 222B (e.g., silicon) at a higher rate than the material of the gate spacers 242 (e.g., silicon nitride), the fin spacers 244 (e.g., silicon nitride), the gate stacks 230A, 230B (e.g., oxide hard mask or polysilicon), and / or the isolation features 225 (e.g., silicon oxide) (i.e., the etchant has a high etch selectivity relative to silicon). The fluorine- and chlorine-containing etching gas includes a fluorine-containing etchant (e.g., F2, CH3F, CH2F2, CHF3, CF4, C2F6, SF6, NF3, other fluorine-containing etchants, or combinations thereof) and a chlorine-containing etchant (e.g., Cl2, CHCl3, CCl4, BCl3, other chlorine-containing etchants, or combinations thereof). In some embodiments, the isotropic source / drain etch is configured to generate a fluorine- and chlorine-containing plasma from the fluorine- and chlorine-containing etching gas, such that the isotropic source / drain etch removes portions of the fins 222A, 222B using plasma-excited fluorine-containing species and / or plasma-excited chlorine-containing species. The isotropic source / drain etch may alternatively or additionally use a hydrogen-containing etching gas (e.g., H2 and / or CH4), a nitrogen-containing etching gas (e.g., N2 and / or NH3), an oxygen-containing etching gas (e.g., O2), a bromine-containing etching gas (e.g., HBr and / or CHBr3), an iodine-containing etching gas, other suitable etching gases, or combinations thereof. In some embodiments, a carrier gas is used to deliver the etching gas.The carrier gas may be an inert gas, such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, the isotropic source / drain etching is a wet etching process using an etching solution comprising nitric acid (HNO3) and hydrofluoric acid (HF). In some embodiments, the etching solution further comprises acetic acid (CH3COOH). The present invention contemplates other etching solutions for isotropic and selective wet etching.

[0044] Various etching parameters of the isotropic source / drain etch may be adjusted to control the selective etching and isotropic etching of the fins 222A, 222B to produce a desired tip proximity pi, a desired tip depth di, and a desired source / drain recess 250, such as etching gas composition, carrier gas composition, etching gas flow rate, carrier gas flow rate, etching time, etching pressure, etching temperature, source power, RF and / or DC bias voltage, RF and / or DC bias power, other suitable etching parameters, or combinations thereof. In some embodiments, the isotropic source / drain etch utilizes an etching gas including NF3 and Cl2 to selectively etch the fins 222A, 222B, wherein the ratio of the flow rate of NF3 to the flow rate of Cl2, the flow rate of NF3, the flow rate of Cl2, the etching time, the etching temperature, the etching pressure, and / or the RF power may be adjusted to achieve a desired etching selectivity and / or a desired source / drain recess profile. In some embodiments, the ratio of the flow rate of NF3 to the flow rate of Cl2 is from about 1:7 to about 1:1. In some embodiments, the flow rate of NF3 is from about 100 sccm to about 300 sccm. In some embodiments, the flow rate of Cl2 is from about 100 sccm to about 200 sccm. In some embodiments, the duration of the isotropic source / drain etch is from about 5 seconds to about 50 seconds. In some embodiments, the RF power used to generate the fluorine and oxygen containing plasma for the isotropic source / drain etch is from about 300 W to about 400 W. In some embodiments, the pressure maintained in the process chamber during the isotropic source / drain etch is from about 5 mTorr to about 50 mTorr. In some embodiments, the temperature maintained in the process chamber during the isotropic source / drain etch is from about 20°C to about 70°C.

[0045] Go to Figure 3G and Figure 4G, the second anisotropic source / drain etch extends the source / drain recess 250 to a depth d5, which is substantially equal to the target depth TD. After the second anisotropic source / drain etch, the depth d5 ​​is measured between the respective top surfaces of the fins 222A, 222B and the respective portions of the bottommost surfaces of the fins 222A, 222B that define the source / drain recess 250. In some embodiments, the depth d5 ​​is about 80% to about 120% of the fin height FH (e.g., about 120% of the fin height FH). In some embodiments, the depth d5 ​​is about 30 nm to about 80 nm. The second anisotropic source / drain etch is controlled to produce a source / drain recess 250 having a profile in the YZ plane similar to a light portion of a candle-shaped bulb. For example, after the second anisotropic source / drain etch, the source / drain recess 250 is defined by sidewall segment A", sidewall segment B", and a bottom segment C" extending between sidewall segment A" and sidewall segment B". Sidewall segment A" is substantially linear and has a positive slope in the YZ plane, sidewall segment B" is substantially linear and has a negative slope in the YZ plane, and bottom segment C" is curved. Therefore, sidewall segment A" extends from the top surface of the fins 222A, 222B toward the gate stack 230A to the source / drain tip v1, where sidewall segment A" intersects with bottom segment C", and sidewall segment B" extends from the top surface of the fins 222A, 222B toward the gate stack 230B to the source / drain tip v2, where sidewall segment B" intersects with bottom segment C". Such a configuration allows the source / drain groove 250 to maintain a maximum width between the source / drain tip v1 and the source / drain tip v2. The first portion of the source / drain groove 250 (defined between the sidewall segment A” and the sidewall segment B”) has a width w3 that increases from the top surface of the fins 222A, 222B to the maximum width of the source / drain groove 250. The second portion of the source / drain groove 250 (defined between the sidewall portions of the bottom C”) has a width w4 that decreases from the maximum width of the source / drain groove 250 to a width less than the maximum width (0 in some embodiments). In the described embodiment, the bottom segment C” has a blunt top profile that is substantially V-shaped. For example, bottom segment C" has a substantially linear sidewall, wherein the substantially linear sidewall has an opposite slope and tapers to a curved bottom rather than a point. The present invention also contemplates embodiments in which sidewall segment A" and / or sidewall segment B" are curved. For example, sidewall segment A" and / or sidewall segment B" may first bend toward each other from the top surfaces of fins 222A, fins 222B, and then bend away from each other toward source / drain tips v1, v2, respectively, thereby forming a convex surface defining a first portion of a source / drain recess 250 therebetween.

[0046] The profile of the source / drain recess 250 improves the performance of the FinFET device 200 compared to the profile of the conventional source / drain recess 250', which is caused by the source / drain manufacturing technology to tailor the location of the source / drain tips after reaching the target depth TD. For example, the source / drain tips v1, v2 are located closer to the gate stack 230A, 230B (and therefore closer to the channel region of the FinFET device 200) than the location of the source / drain tips z1, z2 of the conventional source / drain recess 250'. The source / drain tips v1, v2 have a tip depth dt and a tip proximity pt, thereby optimizing the performance of the FinFET device 200. In some embodiments, the tip depth dt is about 10% to about 40% of the fin height FH, and the tip proximity pt is about 50% to about 90% of the thickness t1 of the gate spacer 242, which has been observed to reduce the parasitic resistance between the subsequently formed source / drain features and the subsequently formed metal gate. In some embodiments, the tip depth dt is about 10 nm to about 30 nm (e.g., about 20 nm), and the tip proximity pt is about 5 nm to about 8 nm (e.g., about 6 nm). It has been observed that the tip depth dt is greater than about 40% of the fin height FH (in some embodiments, greater than about 30 nm), thereby pulling the bottom of the source / drain recess 250 toward the gate stack 230A, 230B during processing, as described herein, undesirably reducing the footing proximity pf and increasing the parasitic capacitance between the subsequently formed source / drain features and the subsequently formed metal gate. A tip depth dt less than about 10% of the fin height FH (in some embodiments, less than about 10 nm) can increase the parasitic resistance. It has been observed that the tip proximity pt is less than 50% of the thickness t1 of the gate spacer 242 (in some embodiments, about 8 nm) to increase the resistance between the subsequently formed source / drain features and the channel region, reducing carrier mobility, although it has been observed that the tip proximity pt is greater than 90% of the thickness t1 of the gate spacer 242 (in some embodiments, about 5 nm), pushing the subsequently formed source / drain features too close to the channel region, which may cause undesirable short channel effects and / or off-state current leakage. The tip depth dt can be greater than, less than, or equal to the initial tip depth dti. In some embodiments, depending on the various etching parameters of the second anisotropic source / drain etch, the second anisotropic source / drain etch can increase, decrease, and / or have no effect on the tip depth. In the described embodiment, the second anisotropic source / drain etch causes the tip depth dt to be greater than the initial tip depth dti. In some embodiments, the second anisotropic source / drain etch may increase the tip proximity and / or have no effect on the tip proximity, depending on various etch parameters of the second anisotropic source / drain etch.In the described embodiment, the second anisotropic source / drain etch is adjusted to ensure that the tip proximity pt is substantially the same as the initial tip proximity pi. After the second source / drain anisotropic etch, the proximity of the bottom of the source / drain recess 250 (particularly the bottom section C") to the gate footing GF (referred to as the footing proximity pf) also improves the performance of the FinFET device 200. For example, since the positions of the source / drain tips v1, v2 are substantially defined by the first source / drain anisotropic etch and the isotropic source / drain etch before the source / drain recess 250 reaches the target depth TD, the footing proximity pf of the source / drain recess 250 pf' is greater than the footing proximity pf' of conventional source / drain recesses 250', which is caused by conventional source / drain manufacturing techniques. In some embodiments, particularly at depths greater than about 80% of the fin height FH, the footing proximity pf is greater than or equal to about 8 nm. Increasing the footing proximity (e.g., greater than or equal to about 8 nm) at such depths (e.g., greater than about 80% of the fin height FH) reduces the parasitic capacitance between subsequently formed source / drain features and the gate footing GF, as compared to having similar Compared to the conventional source / drain recessed FinFET device with source / drain recessed 250', this reduces DIBL and improves short channel control of the FinFET device 200. It has been observed that the footing proximity is less than 8nm at a depth greater than about 80% of the fin height FH. The taper of the bottom segment C" from the source / drain tip v1, v2 to the target depth TD is also greater than the taper from the source / drain tip z1, z2 to the bottom segment at the target depth TD, so that the source / drain recessed 250' has a lower DIBL and a lower short channel control. The distance between the bottom segment C" of the source / drain recess 250 and the gate stack 230A, 230B is greater than the distance between the bottom segment of the conventional source / drain recess 250' and the gate stack 230A, 230B. The increase in distance can further reduce parasitic capacitance compared to the conventional source / drain recess 250'. In some embodiments, at a depth greater than about 50% of the fin height FH, the distance between the bottom segment C" of the source / drain recess 250 and the gate stack 230A, 230B is greater than or equal to about 6 nm. When the distance between the bottom segment C" of the source / drain recess and the gate stack 230A, 230B is less than about 6 nm, such as the distance observed between the bottom segment C' of the conventional source / drain recess 250' and the gate stack 230A, 230B, the parasitic capacitance between the lower portion of the subsequently formed source / drain feature and the subsequently formed metal gate is increased, thereby increasing DIBL and reducing short channel control.

[0047] The second anisotropic source / drain etch selectively removes the fins 222A, 222B relative to the gate spacers 242, the fin spacers 244, the gate stacks 230A, 230B, and / or the isolation features 225. In other words, the second anisotropic source / drain etch substantially removes the fins 222A, 222B, but does not remove or substantially does not remove the gate spacers 242, the fin spacers 244, the gate stacks 230A, 230B, and / or the isolation features 225. The second anisotropic source / drain etch has a vertical etch rate greater than a horizontal etch rate (in some embodiments, the horizontal etch rate is zero), such that the second anisotropic source / drain etch removes portions of the fins 222A, 222B in a substantially vertical direction (here, the z-direction) with minimal (to no) material removal in a horizontal direction (here, the x-direction and / or the y-direction). For example, the ratio of VER to HER of the second anisotropic source / drain etch is greater than about 20 (e.g., 20≤VER / HER≤80). In some embodiments, the second anisotropic source / drain etch is controlled to exhibit a degree of anisotropy substantially the same as the degree of anisotropy of the first anisotropic source / drain etch. For example, the degree of anisotropy of the second anisotropic source / drain etch is about 0.95 to about 1. In some embodiments, the second anisotropic source / drain etch is a dry etch process, such as an RIE process, which uses a bromine-containing etching gas to remove the material (e.g., silicon) of the fins 222A, 222B at a higher rate than the material of the gate spacers 242 (e.g., silicon nitride), the fin spacers 244 (e.g., silicon nitride), the gate stacks 230A, 230B (e.g., oxide hard mask or polysilicon), and / or the isolation features 225 (e.g., silicon oxide) (i.e., the etchant has a high etch selectivity relative to silicon). The bromine-containing etching gas includes Br, HBr, CH3Br, CH2Br2, CHBr3, other bromine-containing etchants, or combinations thereof. In some embodiments, the second anisotropic source / drain etching is configured to generate a bromine-containing plasma from the bromine-containing etching gas, so that the second anisotropic source / drain etching uses plasma-excited bromine-containing species to remove portions of the fins 222A, 222B in the S / D regions. The second anisotropic source / drain etching may optionally or additionally use a hydrogen-containing etching gas (e.g., H2 and / or CH4), a nitrogen-containing etching gas (e.g., N2 and / or NH3), a chlorine-containing etching gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), an oxygen-containing etching gas (e.g., O2), a fluorine-containing etching gas (e.g., F2, CH3F, CH2F2, CHF3, CF4, C2F6), an iodine-containing etching gas, other suitable etching gases, or combinations thereof. In some embodiments, a carrier gas is used to deliver the etching gas. The carrier gas may be an inert gas, such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, other suitable inert gases, or combinations thereof.

[0048] The various etching parameters of the second anisotropic source / drain etching can be adjusted to control the selective etching and anisotropic etching of the fins 222A, 222B to ensure that the source / drain groove 250 reaches the target depth TD and forms a profile similar to the light portion of a candle-shaped bulb in the YZ plane, and the various etching parameters such as etching gas composition, carrier gas composition, etching gas flow rate, carrier gas flow rate, etching time, etching pressure, etching temperature, source power, RF and / or DC bias voltage, RF and / or DC bias power, other suitable etching parameters or combinations thereof. In some embodiments, the second anisotropic source / drain etching utilizes an etching gas including HBr. In such an embodiment, the flow rate of HBr can be about 100 sccm to about 200 sccm. In some embodiments, the duration of the second anisotropic source / drain etching is about 10 seconds to about 50 seconds. In some embodiments, the RF power used to generate bromine-containing plasma is about 300W to about 400W. In some embodiments, the pressure maintained in the process chamber during the second anisotropic source / drain etch is about 5 mTorr to about 50 mTorr. In some embodiments, the temperature maintained in the process chamber during the second anisotropic source / drain etch is about 20° C. to about 70° C. It should be noted that the second anisotropic source / drain etch is substantially the same as the first anisotropic source / drain etch, except that the duration of the second anisotropic source / drain etch is different (in some embodiments, greater) than the duration of the first anisotropic source / drain etch to ensure that the source / drain recess 250 extends to the target depth TD after the second anisotropic source / drain etch. In some embodiments, the second anisotropic source / drain etch utilizes an etching gas including Cl2, wherein the flow rate of Cl2, etching time, etching temperature, etching pressure and / or RF power can be adjusted to achieve a desired etching selectivity and / or a desired source / drain recess profile.

[0049] exist Figure 3H and Figure 4HIn the embodiment of the present invention, epitaxial source / drain features 260 are formed in the source / drain recesses 250. A first gate structure (including gate stack 230A and gate spacer 242) is interposed between corresponding epitaxial source / drain features 260, thereby defining a channel region between corresponding epitaxial source / drain features 260. A second gate structure (including gate stack 230B and gate spacer 242) is interposed between corresponding epitaxial source / drain features 260, thereby defining a channel region between corresponding epitaxial source / drain features 260. In some embodiments, the first gate structure and its corresponding epitaxial source / drain features 260 form part of a first FinFET, and the second gate structure and its corresponding epitaxial source / drain features 260 form part of a second FinFET. In some embodiments, a deposition process is performed to fill the source / drain recesses 250 with epitaxial semiconductor material, thereby forming the epitaxial source / drain features 260. For example, semiconductor material is epitaxially grown from the portion of the fins 222A, 222B and / or the substrate 210 that defines the source / drain recess 250. The epitaxial process may implement a CVD deposition technique (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or a combination thereof. The epitaxial process may use gaseous (e.g., Si-containing gas (such as SiH4) and / or Ge-containing gas (such as GeH4)) and / or liquid precursors that interact with the composition of the fins 222A, 222B and / or the substrate 210. The epitaxial source / drain component 260 is doped with an n-type dopant and / or a p-type dopant. In some embodiments, the epitaxial source / drain component 260 is an epitaxial layer including silicon and / or carbon. The silicon-containing epitaxial layer or the silicon-carbon-containing epitaxial layer is doped with phosphorus, other n-type doping substances, or a combination thereof. In some embodiments, the epitaxial source / drain component 260 is an epitaxial layer including silicon and germanium, wherein the epitaxial layer including silicon and germanium is doped with boron, other p-type dopants, or a combination thereof. In some embodiments, the epitaxial source / drain component 260 includes materials and / or dopants that achieve a desired tensile stress and / or compressive stress in the channel region. In some embodiments, the epitaxial source / drain component 260 is doped by adding impurities to the source material of the epitaxial process during deposition. In some embodiments, the epitaxial source / drain component 260 is doped by an ion implantation process after the deposition process. In some embodiments, an annealing process is performed to activate dopants in the epitaxial source / drain component 260 and / or other source / drain regions (e.g., HDD regions and / or LDD regions) of the FinFET device 200.

[0050] The epitaxial source / drain feature 260 has a candle-shaped bulb-shaped profile in the YZ plane. For example, the epitaxial source / drain feature 260 has a top portion 262A (a portion of the epitaxial source / drain feature 260 disposed above the top surface of the fins 222A, 222B along the z-direction), a middle portion 262B (a portion of the epitaxial source / drain feature 260 disposed between the top surface of the fins 222A, 222B and the tip T), and a bottom portion 262C (a portion of the epitaxial source / drain feature 260 disposed between the tip T and the target depth TD). The top portion 262A is similar to the base of a candle-shaped bulb, while the combination of the middle portion 262B and the bottom portion 262C is similar to the light portion of the candle-shaped bulb (e.g., having a wider center portion disposed between two narrower ends), which is configured similarly to the flame of a candle. In the described embodiment, the top portion 262A has a substantially uniform width wt along its thickness tt, the middle portion 262B has a width wm along its thickness tm that increases from the top surface of the fins 222A, 222B to the tip T (i.e., a width that gradually decreases outward along the fin height FH toward the target depth TD), and the bottom portion 262C has a width wb that decreases from the tip T to the target depth TD along its thickness tb (i.e., a width that gradually tapers inward along the fin height FH toward the target depth TD). The maximum width of the epitaxial source / drain features 260 is defined between the tips T. In some embodiments, the maximum width is about 20 nm to about 35 nm. In some embodiments, as described, the width wt is substantially equal to the spacing S between the gate spacers 242, so that the top portion 262A physically contacts the outer sidewall OS of the gate spacer 242. In some embodiments, the width wt is less than the spacing S, so that the top portion 262A does not physically contact or only partially physically contacts the outer sidewall OS of the gate spacer 242. In a further described embodiment, the bottom 262C is defined by a V-shaped blunt tip, such that the bottom 262C forms a blunt bottom tip of the epitaxial source / drain feature 260. In the XZ plane, the epitaxial source / drain feature 260 has a top 264A (a portion of the epitaxial source / drain feature 260 disposed above the top surface of the fins 222A, 222B along the z-direction) and a bottom 264B (a portion of the epitaxial source / drain feature 260 disposed below the top surface of the fins 222A, 222B along the z-direction). In the described embodiment, the top 264A has a varying width wt1 along its thickness tt, and the bottom 264B has a varying width wb1 along its thickness that is substantially equal to the depth d5 ​​(i.e., the target depth TD). In some embodiments, the width wt1 of at least a portion of the top 264A is greater than the width of the fins 222A, 222B. In some embodiments, the top 264A has a wide center portion with narrower ends. In some embodiments, the top 264A has a substantially diamond-shaped profile. In some embodiments, top portion 264A has a substantially hexagonal profile.In some embodiments, a width wb1 of a first portion of the bottom portion 264B is substantially the same as a width of the fins 222A, 222B, while a width b1 of a second portion of the bottom portion 264B decreases along the z-direction toward the target depth TD.

[0051] Due to the three-step source / drain recess etching process described herein, the tip T of the epitaxial source / drain component 260 is closer to the top surface of the fins 222A, 222B than conventional source / drain manufacturing processes. For example, the tip T has a tip depth dt and a tip proximity pt, the advantages of which are described in detail herein. The epitaxial source / drain component 260 also has a larger footing proximity pf than can be achieved by conventional source / drain manufacturing processes, the advantages of which will be described in detail herein. In contrast to conventional source / drain manufacturing processes that define the position of the tip after extending the source / drain recess to a target depth TD, the proposed three-step source / drain recess etching process defines the position of the tip T before extending the source / drain recess to a target depth TD. This manufacturing technique raises the position of the tip T to a position that reduces the parasitic resistance between the epitaxial source / drain feature 260 and the subsequently formed metal gate, while pulling back (in other words, increasing) the bottom of the epitaxial source / drain feature 260 to the position of the subsequently formed metal gate (particularly, the footing proximity pf), which reduces the parasitic capacitance between the epitaxial source / drain feature 260 and the metal gate. Therefore, the epitaxial source / drain feature 260 having the proposed candlelight bulb-shaped profile reduces the DIBL, thereby improving the short channel control of the FinFET device 200. In addition, the three-step source / drain etching process enables the position (positioning) of the tip T to be controlled (adjusted) within about 10% of the fin height FH to about 80% of the fin height FH, while pulling back the bottom proximity of the epitaxial source / drain feature 260. For example, as Figure 5 As described, the depth dt of the source / drain tips v1, v2 is about 10% of the fin height FH (corresponding to Figure 5 source / drain recess 250-1 in the fin height FH) or about 80% of the fin height FH (corresponding to Figure 5 The three-step source / drain recess etch process produces a footing proximity pf less than the footing proximity pf' at a depth greater than or equal to about 80% of the fin height FH, at which the gate footing GF and the corresponding capacitive coupling effect are most prevalent. Different embodiments may have different advantages, and no particular advantage is required for any embodiment.

[0052] Go to Figure 6 , according to various aspects of the present invention, channel resistance and DIBL characteristics of FinFET devices having epitaxial source / drain features with various profiles are shown. Figure 6, a graph 300 illustrates a tradeoff between DIBL and channel resistance (Rch). For example, graph 300 relates DIBL (in mV / V) (x-axis) to Rch (in ohms) (y-axis), where curve xx corresponds to a FinFET device having epitaxial source / drain features fabricated using conventional source / drain recess technology, and curve xy corresponds to a FinFET device having epitaxial source / drain features fabricated using the proposed three-step source / drain etch process. Both curve xx and curve xy illustrate that as channel resistance decreases, e.g., from pushing the tip proximity closer to the channel region of the FinFET device, DIBL increases, e.g., from pulling the bottom of the epitaxial source / drain features closer to the channel region of the FinFET device due to the tip proximity pushing (thereby reducing the distance between the bottom of the epitaxial source / drain features and the gate footing GF). In curve xx, R1 corresponds to the channel resistance and DIBL characteristics of a FinFET device having epitaxial source / drain features (having a profile (e.g., a substantially U-shaped profile) obtained by anisotropically etching to extend the source / drain recesses to a target depth TD), while R2 corresponds to the channel resistance and DIBL characteristics of a FinFET device having epitaxial source / drain features (having a profile obtained by anisotropically etching to extend the source / drain recesses to a target depth), followed by isotropic etching to reduce the tip proximity (and thus increase the width) of the source / drain recesses, such as by Figure 3H Those defined by the conventional source / drain recesses 250' described. Figure 6 As can be seen in Fig. 1 , although the conventional source / drain recess 250' achieves a FinFET device with a smaller channel resistance, the conventional source / drain recess 250' significantly increases the DIBL because the bottom (especially the bottom tapered portion) of the conventional source / drain recess 250' is also pushed closer to the channel region during the isotropic etching. In curve xy, R3 corresponds to the channel resistance and DIBL characteristics of a FinFET device having epitaxial source / drain features (having a profile defined by the proposed three-step source / drain recess etching process), such as those defined by the source / drain recess 250. As shown in Fig. 1 , the conventional source / drain recess 250' has a lower channel resistance than the conventional source / drain recess 250'. As shown in Fig. 1 , the conventional source / drain recess 250' has a lower channel resistance than the conventional source / drain recess 250'. Figure 6 As can be seen, the FinFET device obtained by the source / drain recess 250 has a lower channel resistance than the channel resistance obtained by the conventional source / drain recess 250', and also restores the increase in DIBL suffered by the FinFET device with the conventional source / drain recess 250'. Therefore, compared with the conventional FinFET device, the FinFET device with the epitaxial source / drain features (having the outline defined by the source / drain recess 250) shows a reduced channel resistance and reduced DIBL, thereby providing better short channel control for the FinFET device.

[0053] In some embodiments, Figure 7 As described, the epitaxial source / drain feature 260 has a multi-layer structure, such as a first epitaxial semiconductor layer 260-1 disposed above a second epitaxial semiconductor layer 260-2. The first epitaxial semiconductor layer 260-1 and the second epitaxial semiconductor layer 260-2 include at least one of the same composition, wherein the concentration of the component in the first epitaxial semiconductor layer 260-1 is greater than the concentration of the component in the second epitaxial semiconductor layer 260-2 to enhance conductivity and reduce resistance between the epitaxial source / drain feature 260 and a subsequently formed contact. For example, each of the first epitaxial semiconductor layer 260-1 and the second epitaxial semiconductor layer 260-2 includes silicon germanium, wherein the germanium concentration in the first epitaxial semiconductor layer 260-1 is greater than the germanium concentration in the second epitaxial semiconductor layer 260-2. In some embodiments, the germanium concentration in the first epitaxial semiconductor layer 260-1 is about 40% to about 60%, and the germanium concentration in the second epitaxial semiconductor layer 260-2 is about 20% to about 40%. In another example, the first epitaxial semiconductor layer 260-1 and the second epitaxial semiconductor layer 260-2 include the same material (e.g., silicon or silicon germanium), wherein the dopant concentration of the dopant in the first epitaxial semiconductor layer 260-1 (e.g., the dopant concentration of phosphorus or boron) is greater than the dopant concentration of the dopant in the second epitaxial semiconductor layer 260-2. In some embodiments, when the first epitaxial semiconductor layer 260-1 and the second epitaxial semiconductor layer 260-2 include silicon, the phosphorus dopant concentration in the first epitaxial semiconductor layer 260-1 is about 1×10 21 cm -3 About 5×10 21 cm -3 , and the phosphorus dopant concentration in the second epitaxial semiconductor layer 260 - 2 is about 1×10 20 cm -3 About 1×10 21 cm -3 In some embodiments, when the first epitaxial semiconductor layer 260 - 1 and the second epitaxial semiconductor layer 260 - 2 include silicon germanium, the boron dopant concentration in the first epitaxial semiconductor layer 260 - 1 is about 5×10 20 cm -3 About 1×10 21 cm -3 , and the boron dopant concentration in the second epitaxial semiconductor layer 260 - 2 is about 1×10 20 cm -3 About 5×10 20 cm -3In some embodiments, the second epitaxial semiconductor layer 260-2 is a buffer layer configured to reduce lattice mismatch between the fins 222A, 222B and the epitaxial source / drain features 260. In such embodiments, the concentration of the component can be graded in the second epitaxial semiconductor layer 260-2 from the fins 222A, 222B to the first epitaxial semiconductor layer 260-1.

[0054] Go to Fig. 3I and Fig. 4I , the FinFET device 200 may undergo additional processes. For example, a dielectric layer 270 is formed over the fins 222A, 222B, the gate stacks 230A, 230B, the gate spacers 242, the fin spacers 244, and the epitaxial source / drain features 260. In some embodiments, the dielectric layer 270 forms part of a multi-layer interconnect (MLI) feature. The dielectric layer 270 may include an interlayer dielectric (ILD) layer disposed over a contact etch stop layer (CESL). The ILD layer includes dielectric materials including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), PSG, BSG, boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, polyparaxylene, benzocyclobutene (BCB) based dielectric materials, SiLK (Dow Chemical, Midland, Michigan), polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the ILD layer includes a low-k dielectric material, which generally refers to a dielectric material having a low dielectric constant relative to the dielectric constant of silicon dioxide (k≈3.9). For example, the dielectric constant of the low-k dielectric material is less than about 3.9. In some embodiments, the dielectric constant of the low-k dielectric material is less than about 2.5, which can be referred to as an extremely low-k (ELK) dielectric material. In the described embodiments, the ILD layer includes a low-k dielectric material. The CESL includes a material different from the ILD layer, such as a dielectric material different from the dielectric material of the ILD layer. The ILD layer and / or the CESL may include a multilayer structure having multiple dielectric materials. In which the ILD layer includes silicon and oxygen (e.g., SiCOH, SiO xIn the described embodiments of the present invention, the CESL includes nitrogen and / or carbon (e.g., SiN, SiCN, SiCON, SiON, SiC, SiCO, metal nitrides and / or metal carbonitrides). The ILD layer and / or CESL are formed by a deposition process, such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, other suitable methods or combinations thereof. In some embodiments, the ILD layer is formed by a flowable CVD (FCVD) process, including, for example, depositing a flowable material (such as a liquid compound) on the substrate 210, and converting the flowable material into a solid material by an appropriate technique, such as thermal annealing and / or treating the flowable material with ultraviolet radiation. After the ILD layer and / or CESL are deposited, a CMP process and / or other planarization process is performed so that the ILD layer and / or CESL has a substantially flat surface.

[0055] In some embodiments, after forming the dielectric layer 270, the gate stacks 230A, 230B are replaced with metal gate stacks 280A, 280B using any suitable gate replacement process, including various etching processes, deposition processes, photolithography processes, and / or planarization processes. For example, a portion or all of the gate stacks 230A, 230B (e.g., a dummy gate electrode layer, and in some embodiments, a dummy gate dielectric layer) are removed to form a gate trench (opening) that exposes the fin structure 222A, 222B, the interface layer, and / or the gate dielectric layer, and a metal gate stack 280A, 280B is formed in the gate trench. According to the design requirements of the FinFET device 200, the metal gate stacks 280A, 280B are configured to achieve the desired function, so that the metal gate stack 280A may include the same or different layers and / or materials as the metal gate stack 280B. In some embodiments, the metal gate stack 280A, 280B includes a gate dielectric (e.g., a gate dielectric layer) and a gate electrode (e.g., a work function layer and a body conductive layer). The metal gate stack 280A, 280B may include many other layers, for example, a cap layer, an interface layer, a diffusion layer, a barrier layer, a hard mask layer, or a combination thereof. In some embodiments, the gate dielectric layer is disposed above the interface layer (including a dielectric material such as silicon oxide), and the gate electrode is disposed above the gate dielectric layer. The gate dielectric layer includes a dielectric material such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination thereof. Examples of high-k dielectric materials include hafnium dioxide (HfO2), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, or a combination thereof. A high-k dielectric material generally refers to a dielectric material having a higher dielectric constant relative to the dielectric constant of silicon dioxide (k≈3.9). For example, a high-k dielectric material has a dielectric constant greater than about 3.9. In some embodiments, the gate dielectric layer is a high-k dielectric layer. The gate electrode includes a conductive material such as polysilicon, Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the work function layer is a conductive layer adjusted to have a desired work function (e.g., an n-type work function or a p-type work function), and the conductor layer is a conductive layer formed above the work function layer. In some embodiments, the work function layer includes an n-type work function material, such as Ti, Ag, Mn, Zr, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type work function materials, or combinations thereof.In some embodiments, the work function layer includes a p-type work function material, such as Ru, Mo, Al, TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The bulk (or fill) conductive layer includes a suitable conductive material, such as Al, W, and / or Cu. The bulk conductive layer may additionally or jointly include polysilicon, Ti, Ta, metal alloys, other suitable materials, or combinations thereof.

[0056] In some embodiments, the various interconnects of the MLI component are formed to facilitate the operation of the FinFET device 200. The MLI component electrically couples the various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate structures and / or source / drain devices) of the FinFET device 200 so that the various devices and / or components can operate in accordance with the design requirements of the FinFET device. The MLI component includes a combination of a dielectric layer such as the dielectric layer 270 and a conductive layer configured to form various interconnects. During the operation of the FinFET device 200, the interconnects are configured to route signals between the devices and / or components of the FinFET device 200 and / or distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to the devices and / or components of the FinFET device 200. The conductive layer is configured to form vertical interconnects, such as device-level contacts and / or vias, and / or horizontal interconnects, such as wires. The vertical interconnects typically connect horizontal interconnects in different layers (or different planes) of the MLI component. Device-level contacts (also referred to as local interconnects or local contacts) electrically and / or physically couple IC device components to other conductive features of MLI components, such as vias. Device-level contacts include metal-to-polysilicon (MP) contacts, which generally refer to contacts to gate structures, such as polysilicon gate structures or metal gate structures, and metal-to-device (MD) contacts, which generally refer to contacts to conductive regions of FinFET devices 200, such as epitaxial source / drain features 260. Fig. 3I , MD contacts such as source / drain contacts 290 extend through dielectric layer 270 to corresponding epitaxial source / drain features 260. Source / drain contacts 290 include conductive materials such as metals. Metals include aluminum, aluminum alloys (such as aluminum / silicon / copper alloys), copper, copper alloys, titanium, titanium nitride, tantalum, tantalum alloys, tantalum nitride, tungsten, tungsten alloys, cobalt, cobalt alloys, ruthenium, ruthenium alloys, polysilicon, metal silicides, other suitable metals, or combinations thereof. Metal silicides may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some embodiments, a damascene process and / or a dual damascene process is used to form copper-based MLI features.

[0057] In embodiments where epitaxial source / drain features 260 include a multi-layer structure, such as Figure 7 As described, the candle bulb-shaped profile of the epitaxial source / drain feature 260 provides additional advantages. In some embodiments, the source / drain contact 290 has a critical dimension D1 (e.g., a width along the y-direction or gate length direction), while the epitaxial source / drain feature 260 has a critical dimension D2 (e.g., a minimum width of the first epitaxial semiconductor layer 260-1 in the middle portion 262B of the epitaxial source / drain feature 260). Since the three-step source / drain etching process increases the width of the source / drain recess and defines the location of the tip T, and then extends the source / drain recess to the target depth DT, the source / drain recess 250 is wider than the conventional source / drain recess 250' and has a depth less than about 40% of the fin height FH. Therefore, the critical dimension D2 of the epitaxial source / drain feature 260 is greater than the critical dimension D3 (e.g., the minimum width of the first epitaxial semiconductor layer in the middle portion) of the epitaxial source / drain feature having a profile defined by the conventional source / drain recess 250', which reduces the resistance between the epitaxial source / drain feature 260 and the source / drain contact 290. In some embodiments, the critical dimension D2 is greater than the critical dimension D1, and the critical dimension D3 is substantially the same as the critical dimension D1. In some embodiments, the critical dimension D2 is at least 5 nm greater than the critical dimension D1. In some embodiments, the distance between the sidewall of the source / drain contact 290 and the portion of the first epitaxial semiconductor layer 260-1 defining the critical dimension D2 is greater than or equal to about 2 nm. In some embodiments, in contrast to the epitaxial source / drain features having contours defined by conventional source / drain recesses 250 ′, the epitaxial first semiconductor layer 260 - 1 in the middle portion 262B of the epitaxial source / drain features 260 does not extend beyond the outer sidewalls OS of the gate spacers 242 .

[0058] The present invention provides various source and drain formation techniques for fin field effect transistors (FinFETs). The source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier reduction. An exemplary three-step etching method for forming source / drain grooves in the source / drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are adjusted to define the position of the source / drain tip. After the first anisotropic etch and the isotropic etch, the depth of the source / drain groove is less than the target depth. The second anisotropic etch is adjusted to extend the depth of the source / drain groove to the target depth. The source / drain tip is close to the top of the fin to reduce the channel resistance, while the bottom of the source / drain groove is spaced a certain distance from the gate footing, so that the DIBL can be minimized. The source / drain groove is filled with epitaxial semiconductor material. In some embodiments, the first anisotropic etching process and the second anisotropic etching process implement the same etching gas. The first duration of the first anisotropic etching process may be different from the second duration of the second anisotropic etching process. In some embodiments, the first anisotropic etching process, the isotropic etching process, and the second anisotropic etching process are selective dry etching processes. In some embodiments, the first anisotropic etching process and the second anisotropic etching process implement etching gases containing hydrogen and bromine, while the isotropic etching process implements etching gases containing fluorine and chlorine. In some embodiments, filling the source / drain grooves with epitaxial semiconductor material includes forming a first epitaxial semiconductor layer along a surface of the fin defining the source / drain grooves, and forming a second epitaxial semiconductor layer above the first epitaxial semiconductor layer. The first epitaxial semiconductor layer has a first concentration of a component, and the second epitaxial semiconductor layer has a second concentration of a component, the second concentration being greater than the first concentration.

[0059] In some embodiments, the method further comprises performing a third anisotropic etching process to form a gate spacer. The third anisotropic etching process may begin to form a source / drain recess. In some embodiments, the method comprises adjusting a first parameter of the first anisotropic etching process and a second parameter of the isotropic etching process to define the location of the source / drain tip, and adjusting a third parameter of the second anisotropic etching process to extend the depth of the source / drain recess to a target depth. In some embodiments, the first parameter of the first anisotropic etching process is adjusted to provide a source / drain recess having a U-shaped profile, the second parameter of the isotropic etching process is adjusted to provide a source / drain recess having a bowl-shaped profile, and the third parameter of the second anisotropic etching process is adjusted to provide a source / drain recess having a profile similar to the bright portion of a candle-shaped bulb.

[0060] Another exemplary method includes forming a gate stack over a channel region of a fin and forming a gate spacer along a sidewall of the gate stack. The channel region of the fin is disposed between the source / drain regions of the fin. The method also includes performing a first etching process to form a source / drain groove in the source / drain region of the fin. The source / drain groove has a first width and a first depth, and the first depth is less than a target depth of the source / drain groove. The method also includes performing a second etching process to increase the first width of the source / drain groove to a second width, and performing a third etching process to increase the first depth of the source / drain groove to a target depth. The method also includes forming a semiconductor source / drain component in the source / drain groove. In some embodiments, performing the first etching process and the third etching process includes removing fin material in a substantially vertical direction, and performing the second etching process includes removing fin material in a substantially vertical direction and a substantially horizontal direction. In some embodiments, the fin has a fin height, the first depth is equal to about 10% to about 80% of the fin height, and the target depth is equal to about 80% to about 120% of the fin height.

[0061] In some embodiments, performing the first etching process and performing the second etching process include controlling the tip depth and tip proximity of the source / drain groove along the fin height of the fin. In some embodiments, the fin has a fin height, each gate spacer has a gate spacer thickness, the first depth is less than about 50% of the fin height, the tip depth is about 10% of the fin height to about 30% of the fin height, and the tip proximity is about 60% of the gate spacer thickness to about 90% of the gate spacer thickness. In some embodiments, forming the gate spacer along the sidewall of the gate stack includes forming a spacer layer over the gate stack and the source / drain region of the fin, performing a first spacer etch, and performing a second spacer etch. The first spacer etch and the second spacer etch remove portions of the spacer layer and begin to form the source / drain groove. The source / drain groove has a second depth after the first spacer etch and a third depth after the second spacer etch. The second depth and the third depth are less than the first depth. In some embodiments, the fin has a fin height, the second depth is less than about 10% of the fin height, the third depth is about 10% to about 20% of the fin height, the first depth is about 10% to about 80% of the fin height, and the target depth is about 80% to about 120% of the fin height.

[0062] An exemplary device includes a fin having a fin height, a gate stack disposed above a channel region of the fin, a gate spacer disposed along a sidewall of the gate stack, and an epitaxial source / drain component disposed in a source / drain region of the fin. The gate spacer has a thickness of the gate spacer. The epitaxial source / drain component has a candle bulb-shaped cross-sectional profile such that the epitaxial source / drain component includes a top portion disposed above a top surface of the fin, a middle portion disposed between the top surface of the fin and a tip of the epitaxial source / drain component, and a bottom portion disposed between the top surface of the fin and a depth of the epitaxial source / drain component in the fin. The tip depth of the tip of the epitaxial source / drain component is about 10% of the fin height to about 30% of the fin height. At a depth greater than about 80% of the fin height, the footing proximity of the bottom of the epitaxial source / drain component is greater than about 8nm. In some embodiments, the tip proximity of the tip of the epitaxial source / drain component is about 60% of the gate spacer thickness to about 90% of the gate spacer thickness. In some embodiments, the first width of the top portion is substantially the same along the first thickness of the top portion, the second width of the middle portion increases along the second thickness of the middle portion, and the third width of the bottom portion decreases along the third thickness of the bottom portion. The first thickness, the second thickness, and the third thickness extend substantially parallel to the fin height direction. The third thickness may be greater than the second thickness and greater than the first thickness.

[0063] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a source / drain groove in a source / drain region of a fin, wherein forming the source / drain groove comprises: performing a first anisotropic etching process, then performing an isotropic etching process, and then performing a second anisotropic etching process; and filling the source / drain groove with an epitaxial semiconductor material. In some embodiments, the method further comprises: adjusting a first parameter of the first anisotropic etching process and a second parameter of the isotropic etching process to define the position of the source / drain tip, wherein the depth of the source / drain groove after the first anisotropic etching process and the isotropic etching process is less than a target depth of the source / drain groove. In some embodiments, the method further comprises adjusting a third parameter of the second anisotropic etching process to extend the depth of the source / drain groove to the target depth. In some embodiments, the first anisotropic etching process and the second anisotropic etching process perform the same etching gas, wherein the first duration of the first anisotropic etching process is different from the second duration of the second anisotropic etching process. In some embodiments, the first anisotropic etching process, the isotropic etching process, and the second anisotropic etching process are selective dry etching processes. In some embodiments, the first anisotropic etching process and the second anisotropic etching process implement etching gases containing hydrogen and bromine, and the isotropic etching process implements etching gases containing fluorine and chlorine. In some embodiments, the method further includes: adjusting a first parameter of the first anisotropic etching process to provide the source / drain recess having a U-shaped profile; adjusting a second parameter of the isotropic etching process to provide the source / drain recess having a bowl-shaped profile; and adjusting a third parameter of the second anisotropic etching process to provide a source / drain recess having a profile similar to a light portion of a candle-shaped bulb. In some embodiments, filling the source / drain recesses with the epitaxial semiconductor material comprises: forming a first epitaxial semiconductor layer along a surface of the fin defining the source / drain recesses, wherein the first epitaxial semiconductor layer has a first concentration of a component; and forming a second epitaxial semiconductor layer over the first epitaxial semiconductor layer, wherein the second epitaxial semiconductor layer has a second concentration of a component, wherein the second concentration is greater than the first concentration. In some embodiments, the method further comprises performing a third anisotropic etching process to form gate spacers, wherein the third anisotropic etching process begins to form the source / drain recesses

[0064] An embodiment of the present invention also provides a semiconductor device, comprising: a fin having a fin height; a gate stack disposed above a channel region of the fin; a gate spacer disposed along a sidewall of the gate stack, wherein the gate spacer has a gate spacer thickness; and an epitaxial source / drain component disposed in a source / drain region of the fin, wherein the epitaxial source / drain component has a candlelight bulb-shaped cross-sectional profile, so that the epitaxial source / drain component comprises: a top portion disposed above a top surface of the fin, a middle portion disposed between a top surface of the fin and a tip of the epitaxial source / drain component, and a bottom portion disposed between a top surface of the fin and a depth of the epitaxial source / drain component in the fin, wherein: a tip depth of the tip of the epitaxial source / drain component is from 10% to 40% of the fin height; and a footing proximity of the bottom of the epitaxial source / drain component is greater than 8nm at a depth greater than 80% of the fin height. In some embodiments, the tip of the epitaxial source / drain feature has a tip proximity of 50% to 90% of the thickness of the gate spacer. In some embodiments, the first width of the top portion is substantially the same along the first thickness of the top portion, the second width of the middle portion increases along the second thickness of the middle portion, and the thickness of the third width of the bottom portion decreases along the third thickness of the bottom portion, wherein the first thickness, the second thickness, and the third thickness extend substantially parallel to the fin height direction. In some embodiments, the third thickness is greater than the second thickness and greater than the first thickness. In some embodiments, the semiconductor device further includes a source / drain contact extending through the top portion and to the middle portion. In some embodiments, the middle portion of the epitaxial source / drain feature includes a first epitaxial layer and a second epitaxial layer; and the first epitaxial layer is disposed between a sidewall of the source / drain contact and the second epitaxial layer. In some embodiments, the thickness of the first epitaxial layer disposed between the sidewall of the source / drain contact and the second epitaxial layer is greater than or equal to 2 nm.

[0065] An embodiment of the present invention further provides a semiconductor device, comprising: a fin, arranged above the substrate, wherein the fin extends along a first direction; a gate structure, arranged above a channel region of the fin, wherein the gate structure extends along a second direction different from the first direction, the gate structure comprising a metal gate and a gate spacer arranged along a sidewall of the metal gate, the metal gate having a gate foot at an interface between the fin and the metal gate, and the gate spacer having a gate spacer thickness along the first direction; and an epitaxial source / drain component, arranged in a source / drain region of the fin, wherein the gate structure is arranged between the epitaxial source / drain components along the first direction, and wherein each of the epitaxial source / drain components comprises: a first portion having a first width along the first direction, wherein the first width a second portion disposed above the first portion, wherein the second portion has a second width along the first direction, and the second width decreases from the maximum width of the epitaxial source / drain component along the first direction to the top surface of the fin, a third portion disposed above the second portion, wherein the second portion has a third width along the first direction, wherein the third width is substantially the same from the top surface of the fin to the top surface of the epitaxial source / drain component, and wherein a distance between the maximum width of the epitaxial source / drain component and a sidewall of the metal gate along the first direction is 5 nm to 8 nm, and a distance between the gate footer and the first portion of the epitaxial source / drain component is greater than 6 nm. In some embodiments, the metal gate has a gate length along the first direction and a gate height along a third direction different from the first direction and the second direction; and a ratio of the gate height to the gate length is greater than or equal to 5. In some embodiments, the maximum width of the epitaxial source / drain features in the fin has a depth of 10 nm to 30 nm. In some embodiments, each of the epitaxial source / drain features includes a first semiconductor layer disposed above the second semiconductor layer, each of the first semiconductor layer and the second semiconductor layer having a composition. A first concentration of the composition in the first semiconductor layer is greater than a second concentration of the composition in the second semiconductor layer; and the first semiconductor layer is disposed between a sidewall of the source / drain contact and the second semiconductor layer.

[0066] The parts of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: Forming a source / drain recess in a source / drain region of the fin, wherein forming the source / drain recess comprises: performing a first anisotropic etching process, adjusting a first parameter of the first anisotropic etching process to provide the source / drain recess having a U-shaped profile, Afterwards, an isotropic etching process is performed. adjusting a second parameter of the isotropic etching process to provide the source / drain recess with a bowl-shaped profile, Afterwards, a second anisotropic etching process is performed, and adjusting a third parameter of the second anisotropic etching process to provide a source / drain recess having a profile of a light portion of a candle-shaped bulb, and The source / drain recesses are filled with epitaxial semiconductor material.

2. The method according to claim 1, further comprising: A first parameter of the first anisotropic etching process and a second parameter of the isotropic etching process are adjusted to define a position of a source / drain tip, wherein a depth of the source / drain recess after the first anisotropic etching process and the isotropic etching process is less than a target depth of the source / drain recess. 3 . The method according to claim 2 , further comprising adjusting a third parameter of the second anisotropic etching process to extend the depth of the source / drain recess to the target depth.

4. The method according to claim 1, wherein: The first anisotropic etching process and the second anisotropic etching process are performed using the same etching gas, wherein a first duration of the first anisotropic etching process is different from a second duration of the second anisotropic etching process.

5. The method according to claim 1, wherein: The first anisotropic etching process, the isotropic etching process, and the second anisotropic etching process are selective dry etching processes.

6. The method according to claim 5, wherein: The first anisotropic etching process and the second anisotropic etching process implement an etching gas containing hydrogen and bromine, and the isotropic etching process implements an etching gas containing fluorine and chlorine.

7. The method according to claim 1, wherein: The fin has a fin height, the source / drain recess has a tip, and a tip depth of the tip is 10% to 40% of the fin height.

8. The method according to claim 1, wherein: Filling the source / drain recesses with the epitaxial semiconductor material comprises: forming a first epitaxial semiconductor layer along a surface of the fin defining the source / drain recess, wherein the first epitaxial semiconductor layer has a component of a first concentration; and A second epitaxial semiconductor layer is formed over the first epitaxial semiconductor layer, wherein the second epitaxial semiconductor layer has a component at a second concentration, wherein the second concentration is greater than the first concentration. 9 . The method of claim 1 , further comprising performing a third anisotropic etching process to form gate spacers, wherein the third anisotropic etching process starts to form the source / drain recesses.

10. A semiconductor device comprising: fin, having a fin height; a gate stack disposed above the channel region of the fin; a gate spacer disposed along a sidewall of the gate stack, wherein the gate spacer has a gate spacer thickness; and An epitaxial source / drain component disposed in a source / drain region of the fin, wherein the epitaxial source / drain component has a candlelight bulb-shaped cross-sectional profile such that the epitaxial source / drain component includes: a top portion disposed above a top surface of the fin, an intermediate portion disposed between a top surface of the fin and a tip of the epitaxial source / drain feature, and a bottom portion disposed between a top surface of the fin and a depth of an epitaxial source / drain feature in the fin, wherein: The tip of the epitaxial source / drain feature has a tip depth of 10% to 40% of the fin height; and A footing proximity of the bottom of the epitaxial source / drain feature is greater than 8 nm at a depth greater than 80% of the fin height.

11. The semiconductor device according to claim 10, wherein: The tip of the tip of the epitaxial source / drain feature has a tip proximity of 50% to 90% of the thickness of the gate spacer.

12. The semiconductor device according to claim 10, wherein: The first width of the top portion is the same along the first thickness of the top portion, the second width of the middle portion increases along the second thickness of the middle portion, and the thickness of the third width of the bottom portion decreases along the third thickness of the bottom portion, wherein the first thickness, the second thickness, and the third thickness extend parallel to the fin height direction.

13. The semiconductor device according to claim 12, wherein: The third thickness is greater than the second thickness and greater than the first thickness.

14. The device of claim 10, further comprising source / drain contacts extending through the top portion and to the middle portion.

15. The semiconductor device according to claim 14, wherein: The middle portion of the epitaxial source / drain feature includes a first epitaxial layer and a second epitaxial layer; and The first epitaxial layer is disposed between sidewalls of the source / drain contacts and the second epitaxial layer.

16. The semiconductor device according to claim 15, wherein: The thickness of the first epitaxial layer disposed between the sidewalls of the source / drain contacts and the second epitaxial layer is greater than or equal to 2 nm.

17. A semiconductor device comprising: A fin is disposed above the substrate, wherein the fin extends along a first direction; a gate structure disposed above the channel region of the fin, wherein the gate structure extends along a second direction different from the first direction, the gate structure comprises a metal gate and a gate spacer disposed along a sidewall of the metal gate, the metal gate has a gate footing at an interface between the fin and the metal gate, and the gate spacer has a gate spacer thickness along the first direction; and epitaxial source / drain features disposed in a source / drain region of the fin, wherein the gate structure is disposed between the epitaxial source / drain features along the first direction, and wherein each of the epitaxial source / drain features comprises: a first portion having a first width along the first direction, wherein the first width increases along the first direction from a bottom of the epitaxial source / drain feature to a maximum width of the epitaxial source / drain feature, a second portion disposed above the first portion, wherein the second portion has a second width along the first direction, and the second width decreases along the first direction from a maximum width of the epitaxial source / drain feature to a top surface of the fin, a third portion disposed above the second portion, wherein the second portion has a third width along the first direction, wherein the third width is the same from a top surface of the fin to a top surface of the epitaxial source / drain feature, and The distance between the maximum width of the epitaxial source / drain component and the sidewall of the metal gate along the first direction is 5nm to 8nm, and the distance between the gate footing and the first part of the epitaxial source / drain component is greater than 6nm.

18. The semiconductor device according to claim 17, wherein: The metal gate has a gate length along the first direction and a gate height along a third direction different from the first direction and the second direction; and A ratio of the gate height to the gate length is greater than or equal to 5.

19. The semiconductor device according to claim 17, wherein: The maximum width of the epitaxial source / drain features in the fin has a depth of 10 nm to 30 nm.

20. The semiconductor device according to claim 17, wherein: Each of the epitaxial source / drain features includes a first semiconductor layer disposed over a second semiconductor layer, each of the first semiconductor layer and the second semiconductor layer having a composition; a first concentration of a component in the first semiconductor layer is greater than a second concentration of a component in the second semiconductor layer; and The first semiconductor layer is disposed between sidewalls of the source / drain contacts and the second semiconductor layer.

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