Integrated circuit device and method of manufacturing the same

Abstract

An integrated circuit device and a manufacturing method thereof are provided. The integrated circuit device includes a substrate including an active region, a device isolation film defining the active region, a word line arranged above the active region and the device isolation film and extending in a first horizontal direction, and a gate dielectric film arranged between the substrate and the word line and between the device isolation film and the word line, wherein, in a second horizontal direction orthogonal to the first horizontal direction, a width of a second portion of the word line above the plurality of active regions is greater than a width of a first portion of the word line above the active region. To manufacture the integrated circuit device, an impurity region is formed in the substrate and the device isolation film by implanting dopant ions into the substrate and the device isolation film, and a thickness of a portion of the impurity region is reduced.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0063311, filed on May 29, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to an integrated circuit device and a method of manufacturing the integrated circuit device, and more specifically, to an integrated circuit device having buried word lines and a method of manufacturing the integrated circuit device. Background Technology

[0004] As the integration density of integrated circuit devices increases, problems arising from increased resistance across multiple word lines and reduced spacing between them can adversely affect the refresh characteristics of these devices. Recently, buried word line transistors (BLTs) have been used to increase effective channel length, suppress subthreshold leakage, and increase the integration density of integrated circuit devices. Hydrogen (H) passivation has been used to address interface dangling bonds and oxygen vacancies (Vo) in the gate oxide of BLTs and enhance the refresh characteristics of integrated circuit devices. However, since the Vo-H bonds formed through the hydrogen (H) passivation process can be destroyed during user handling of the final product, the threshold voltage of the gate electrode of the BLT may change undesirably. Therefore, a novel technique is needed to precisely control the threshold voltage of the gate electrode and improve the reliability of integrated circuit devices. Summary of the Invention

[0005] The present invention provides an integrated circuit device having a structure capable of precisely controlling the threshold voltage of the gate electrode and exhibiting enhanced reliability.

[0006] The present invention also provides a method for manufacturing an integrated circuit device having a structure capable of precisely controlling the threshold voltage of the gate electrode and exhibiting enhanced reliability.

[0007] According to an aspect of the present inventive concept, there is provided an integrated circuit device including: a substrate including a plurality of active regions spaced apart from each other; a device isolation film disposed on the substrate and surrounding the plurality of active regions; a word line disposed on the plurality of active regions and the device isolation film and extending longitudinally in a first horizontal direction; and a gate dielectric film disposed between the substrate and the word line and between the device isolation film and the word line, wherein a second portion of the word line has a width greater than a width of a first portion of the word line in a second horizontal direction orthogonal to the first horizontal direction, wherein the first portion is disposed on the plurality of active regions, and the second portion is disposed on the device isolation film.

[0008] According to another aspect of the present inventive concept, there is provided an integrated circuit device including: a substrate including a device isolation trench defining a plurality of active regions spaced apart from each other; a device isolation film formed in the device isolation trench; a word line trench extending longitudinally across the plurality of active regions and the device isolation film in a first horizontal direction; a gate dielectric film covering an inner wall of the word line trench; and a word line disposed on the gate dielectric film and partially filling the word line trench, wherein a second portion of the word line has a width greater than a width of a first portion of the word line in a second horizontal direction orthogonal to the first horizontal direction, wherein the first portion is disposed on the plurality of active regions, and the second portion is disposed on the device isolation film.

[0009] According to still another aspect of the present inventive concept, there is provided an integrated circuit device including: a substrate including a plurality of active regions spaced apart from each other; a device isolation film disposed on the substrate and surrounding the plurality of active regions; a word line disposed on the plurality of active regions and the device isolation film and extending longitudinally in a first horizontal direction; a gate dielectric film disposed between the substrate and the word line and between the device isolation film and the word line; and an impurity region disposed on the substrate and the device isolation film and in contact with the gate dielectric film, wherein a second portion of the word line has a width greater than a width of a first portion of the word line in a second horizontal direction orthogonal to the first horizontal direction, wherein the first portion is disposed on the plurality of active regions, and the second portion is disposed on the device isolation film.

[0010] According to still another aspect of the present inventive concept, there is provided a method of manufacturing an integrated circuit device, the method comprising: forming a device isolation trench by etching a substrate, the device isolation trench defining a plurality of active regions spaced apart from each other; forming a device isolation film in the device isolation trench; forming a word line trench by partially removing both the plurality of active regions and the device isolation film, the word line trench extending longitudinally across the plurality of active regions and the device isolation film in a first horizontal direction; forming an impurity region in the substrate and the device isolation film by implanting dopant ions into the substrate and the device isolation film through the word line trench; reducing a thickness of a portion of the impurity region; forming a gate dielectric film in the word line trench, the gate dielectric film being in contact with the impurity region; and forming a word line on the gate dielectric film to partially fill the word line trench, the word line having a variable width in a second horizontal direction orthogonal to the first horizontal direction. BRIEF DESCRIPTION OF DRAWINGS

[0011] Exemplary embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a schematic plan layout showing main components of a memory cell array region of an integrated circuit device according to exemplary embodiments of the present inventive concept;

[0013] Figures 2A-2D is a diagram showing an integrated circuit device according to exemplary embodiments of the present inventive concept, and in particular, Figure 2A is a cross-sectional view of a region corresponding to a cross-section taken along a line X1-X1' of Figure 1 is a cross-sectional view of a region corresponding to a cross-section taken along a line X2-X2' of Figure 2B is a cross-sectional view of some components in a cross-section taken along a line Y1-Y1' of Figure 1 is an enlarged plan layout showing some components of the integrated circuit device shown in Figure 2C Figure 1 Figure 2D is a diagram showing an integrated circuit device according to exemplary embodiments of the present inventive concept, and in particular, Figures 2A-2C is a cross-sectional view of a region corresponding to a cross-section taken along a line X1-X1' of

[0014] Figure 3A and Figure 3B is a diagram showing an integrated circuit device according to exemplary embodiments of the present inventive concept, and in particular, Figure 3A is a cross-sectional view of a region corresponding to a cross-section taken along a line X1-X1' of Figure 1 is a cross-sectional view of some components in a region corresponding to a cross-section taken along a line Y1-Y1' of Figure 3B Figure 1

[0015] Figure 4A and Figure 4B ​​​​This is a diagram illustrating an integrated circuit device according to an exemplary embodiment of the present invention, specifically, Figure 4A Is along Figure 1 A cross-sectional view of the region corresponding to the section intercepted by line X1-X1', and Figure 4B It is shown along Figure 1 A cross-sectional view of some components in the region corresponding to the section intercepted by line Y1-Y1';

[0016] Figure 5A and Figure 5B This is a diagram illustrating an integrated circuit device according to an exemplary embodiment of the present invention, specifically, Figure 5A Is along Figure 1 A cross-sectional view of the region corresponding to the section intercepted by line X1-X1', and Figure 5B It is shown along Figure 1 A cross-sectional view of some components in the region corresponding to the section intercepted by line Y1-Y1';

[0017] Figures 6A-6H A cross-sectional view illustrating a sequential process of a method for manufacturing an integrated circuit device according to an exemplary embodiment of the present invention is shown;

[0018] Figures 7A-7C A cross-sectional view illustrating a sequential process of a method for manufacturing an integrated circuit device according to an exemplary embodiment of the present invention is shown;

[0019] Figure 8 A cross-sectional view illustrating a method of manufacturing an integrated circuit device according to an exemplary embodiment of the present invention is shown; and

[0020] Figure 9 A cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an exemplary embodiment of the present invention is shown.

[0021] because Figures 1-9 The accompanying drawings are for illustrative purposes, and therefore the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for clarity. Detailed Implementation

[0022] In the following description, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Throughout the specification, the same components will be denoted by the same reference numerals, and repeated descriptions thereof will be omitted.

[0023] Figure 1 This is a schematic planar layout of the main components of the memory cell array region of an integrated circuit device according to an exemplary embodiment of the present invention.

[0024] Reference Figure 1The integrated circuit device 10 may include a plurality of active regions AC, which are spaced apart from each other and extend longitudinally in an inclined direction relative to a first horizontal direction (X direction) and a second horizontal direction (Y direction) in the XY plane. Therefore, the second horizontal direction is orthogonal to the first horizontal direction. As shown, the plurality of active regions AC can be arranged in a diagonal or oblique stripe form, and by depositing the plurality of active regions AC in a diagonal or oblique direction, the maximum possible distance between contacts can be provided for the integrated circuit device 10. A plurality of word lines WL may be spaced apart from each other in the second horizontal direction (Y direction) and may extend longitudinally across the plurality of active regions AC in the first horizontal direction (X direction). In the second horizontal direction (Y direction), the portion of the plurality of word lines WL arranged above the plurality of active regions AC may have a width smaller than the width of the other portions of the plurality of word lines WL. Therefore, each of the plurality of word lines WL may have a variable width in the first horizontal direction (X direction) as its length direction. The plurality of word lines WL may be arranged at a uniform spacing.

[0025] Multiple bit lines BL can be arranged on multiple word lines WL to extend parallel to each other in a second horizontal direction (Y direction) and can be spaced apart from each other in a first horizontal direction (X direction). The multiple bit lines BL can be connected to multiple active regions AC via direct contacts DC and can be arranged at uniform spacing. Each direct contact DC can be arranged in the center region of an active region AC.

[0026] Multiple buried contacts BC can be arranged between two adjacent bit lines BL and at both ends of multiple active regions AC. Multiple conductive landing pads LP can be arranged on the multiple buried contacts BC. The multiple buried contacts BC and the multiple conductive landing pads LP can connect the bottom electrode of the capacitor formed on the multiple bit lines BL to the active region AC. For example, the multiple conductive landing pads LP can be arranged between the multiple buried contacts BC and the bottom electrode of the capacitor. Each of the multiple conductive landing pads LP can at least partially overlap with a buried contact BC.

[0027] Figures 2A-2D This is a diagram illustrating an integrated circuit device according to an exemplary embodiment of the present invention, specifically, Figure 2A Is along Figure 1 A cross-sectional view of the region corresponding to the section intercepted by line X1-X1'. Figure 2B Is along Figure 1 A cross-sectional view of the region corresponding to the section intercepted by line X2-X2'. Figure 2C It shows along Figure 1 Cross-sectional views of some components taken from the section intercepted by line Y1-Y1', and Figure 2D It is shownFigures 2A-2C Enlarged plan layout of some components of the integrated circuit device shown.

[0028] Referring to Figures 2A-2D The integrated circuit device 100 includes a substrate 102 in which a plurality of active regions AC is defined by a device isolation trench 104T. The device isolation trench 104T can be filled with a device isolation film 104. The device isolation film 104 can be disposed on the substrate 102 to surround the plurality of active regions AC. Thus, the plurality of word lines WL described above with reference to Figure 1 may be disposed on the plurality of active regions AC and the device isolation film 104, and can extend longitudinally in a first horizontal direction (X direction). The device isolation film 104 can include, for example, a silicon oxide (SiO2) film, a silicon nitride (Si3N4) film, or a combination thereof. A level of a bottom surface of the device isolation trench 104T can vary with a lateral width of the device isolation trench 104T. As the lateral width of the device isolation trench 104T increases, the level of the bottom surface of the device isolation trench 104T can be lower. As used herein, the term "level" refers to a height from a main surface 102M of the substrate 102 in a vertical direction (Z direction or -Z direction).

[0029] The substrate 102 can include silicon (Si), for example, single-crystal silicon (Si), polycrystalline silicon (Si), or amorphous silicon (Si). The substrate 102 can be a bulk silicon (Si) substrate or a silicon-on-insulator (SOI) substrate. In an exemplary embodiment of the inventive concept, the substrate 102 can include at least one selected from, for example, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium antimonide (InSb), lead telluride (PbTe), gallium phosphide (GaP), gallium antimonide (GaSb), and indium phosphide (InP). In an exemplary embodiment of the inventive concept, the substrate 102 can include a conductive region, for example, a dopant-doped well or a dopant-doped structure.

[0030] A plurality of word line trenches WT is formed in the substrate 102 to extend parallel to each other in the first horizontal direction (X direction). An interior of each of the plurality of word line trenches WT can be filled with a gate dielectric film 120, a word line WL, and a buried insulating film 128.

[0031] In the plurality of word line trenches WT, a level of a bottom surface of a portion of the plurality of word line trenches WT above the plurality of active regions AC can be higher than a level of a bottom surface of a portion of the plurality of word line trenches WT above the device isolation film 104. For example, in a process of forming the plurality of word line trenches WT, an etching rate of the substrate 102 can be different from an etching rate of the device isolation film 104, for example, the etching rate of the substrate 102 can be lower than the etching rate of the device isolation film 104. Thus, after the etching process, a position of a lowermost portion of the word line trench WT formed in the substrate 102 can be different from a position of a lowermost portion of the word line trench WT formed in the device isolation film 104, for example, the position of the lowermost portion of the word line trench WT formed in the substrate 102 can be higher than the position of the lowermost portion of the word line trench WT formed in the device isolation film 104. Thus, a profile of the bottom surface of each of the plurality of word line trenches WT can have a non-flat shape, and the bottom surface of the word line WL can have a non-flat shape corresponding to the profile of the bottom surface of each of the word line trenches WT. The plurality of fin regions AF can be respectively formed in the plurality of active regions AC to protrude upward in the vertical direction (Z direction) from below the word line WL toward the word line WL corresponding to the profile of the bottom surface of each of the word line trenches WT.

[0032] Each of the plurality of word line trenches WT can include a first trench portion T1A arranged in the substrate 102 and having a lowest surface at a first level LV1, and a second trench portion T1B arranged in the device isolation film 104 and having a lowest surface at a third level LV3 lower than the first level LV1.

[0033] The gate dielectric film 120 can conformally cover the inner surface of the word line trench WT to contact the active region AC and the device isolation film 104, and can extend along the sidewall and the bottom surface of the word line trench WT. Accordingly, the gate dielectric film 120 can be disposed between the active region AC (or the substrate 102) and the word line WL and between the device isolation film 104 and the word line WL. The gate dielectric film 120 can include, for example, a silicon oxide (SiO2) film, a silicon oxynitride (SiON) film, an oxide / nitride / oxide (ONO) film, a metal oxide film including a high-k dielectric film, or a combination thereof. The high-k dielectric film is a film having a dielectric constant higher than that of a silicon oxide (SiO2) film, can have a dielectric constant in the range of about 10 to about 25, and can include, for example, hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO3), tantalum oxide (Ta2O3), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), yttrium oxide (Y2O3), or titanium oxide (TiO2), but the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, the gate dielectric film 120 can include an oxide film substantially free of oxygen vacancies (hereinafter, can also be referred to as "Vo") or an oxygen-rich oxide film. For example, the gate dielectric film 120 can include, for example, a silicon oxide (SiO2) film substantially free of oxygen vacancies, a metal oxide film substantially free of oxygen vacancies, an oxygen-rich silicon oxide film, or an oxygen-rich metal oxide film. The gate dielectric film 120 can have a thickness in the range of about 10 nm to about 30 nm.

[0034] Each of the plurality of word lines WL can be disposed on the gate dielectric film 120 to partially fill the word line trench WT. In the second horizontal direction (Y direction), a first width Q1 of a portion of the word line WL disposed over the active region AC can be different from a second width Q2 of a portion of the word line WL disposed over the device isolation film 104. In an exemplary embodiment of the inventive concept, the second width Q2 of the portion of the word line WL over the device isolation film 104 can be greater than the first width Q1 of the portion of the word line WL over the active region AC.

[0035] The word line WL may have a multilayer structure and may include a metal-containing barrier film 122 conformally covering the gate dielectric film 120, a lower word line 124 having a first work function, and an upper word line 126 having a second work function lower than the first work function. The metal-containing barrier film 122 may contact the gate dielectric film 120. The lower word line 124 may be surrounded by the metal-containing barrier film 122 and the upper word line 126. The metal-containing barrier film 122 may include a metal nitride, and the lower word line 124 may include, for example, a metal, a metal nitride, a metal carbide, or a combination thereof. In an exemplary embodiment of the inventive concept, the metal-containing barrier film 122 may include, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. In an exemplary embodiment of the present invention, the lower letter 124 may include, for example, titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), titanium silicon nitride (TiSiN), silicon tungsten nitride (WSiN), aluminum (Al), copper (Cu), cobalt (Co), nickel (Ni), platinum (Pt), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. The upper letter 126 may include doped polycrystalline silicon. For example, the metal-containing barrier film 122 may include TiN, the lower letter 124 may include W, and the upper letter 126 may include doped polycrystalline silicon, but the present invention is not limited thereto. In an exemplary embodiment of the present invention, at least one of the metal-containing barrier film 122 and the upper letter 126 may be omitted.

[0036] The buried insulating film 128 can be disposed on each of the multiple word lines WL to fill the remaining space of the word line groove WT, and can include, for example, a silicon nitride (Si3N4) film, a silicon oxynitride (SiON) film, a silicon oxide (SiO2) film, a silicon carbonitride (SiCN) film, a silicon carbon oxynitride (SiOCN) film, or a combination thereof.

[0037] Multiple source / drain regions (SDs) are formed in multiple active regions (ACs) on both sides of multiple word lines (WLs).

[0038] The integrated circuit device 100 may include a first impurity region DA disposed between a substrate 102 and a gate dielectric film 120, and a second impurity region DB disposed between a device isolation film 104 and a gate dielectric film 120. Each of the first impurity region DA and the second impurity region DB may extend along the inner wall of the word line trench WT while surrounding the bottom surface of the word line trench WT.

[0039] Each of the first impurity region DA and the second impurity region DB can include dopant ions selected from, for example, oxygen (O) ions, silicon (Si) ions, helium (He) ions, argon (Ar) ions, fluorine (F) ions, and combinations thereof. As used herein, the term "dopant" can be a component different from or the same as a main component of a target film into which the dopant is implanted. When the dopant is a component different from the main component of the target film, the dopant can be implanted into the target film so that the dopant can be placed at an interstitial position in a crystal structure constituting the target film, can replace an atom of the main component of the target film, or can accelerate a surrounding atom around the dopant implantation position to a lattice point. When the dopant is a component the same as the main component of the target film, the dopant can be implanted into the target film so that a crystal structure in the target film can be changed or the crystal structure of the target film can be amorphized. For example, in addition to implanting the dopant into the target film, ion implantation can also damage a crystal structure by lattice displacement through energy transfer to lattice atoms. Lattice displacement occurs when energy is transferred to a lattice atom through nuclear collision. Displacement of a lattice atom can simultaneously generate an interstitial atom and a vacancy, so the crystal structure can be changed or can be amorphized.

[0040] The first impurity region DA can have a first thickness TH1. The second impurity region DB can have a second thickness TH2 smaller than the first thickness TH1 of the first impurity region DA. Here, the first thickness TH1 of the first impurity region DA refers to a minimum distance from an inner wall of the first trench portion T1A to an interface between the first impurity region DA and the substrate 102, and the second thickness TH2 of the second impurity region DB refers to a minimum distance from an inner wall of the second trench portion T1B to an interface between the second impurity region DB and the device isolation film 104. Because the ion-implanted portion of the device isolation film 104 can be partially etched by an etchant in a subsequent process, the thickness of the ion-implanted portion of the device isolation film 104 can be reduced in the subsequent process, thereby forming the second impurity region DB having the second thickness TH2 smaller than the first thickness TH1 of the first impurity region DA. For example, the first thickness TH1 of the first impurity region DA can be selected from a range of about 10 nm to about 20 nm, and the second thickness TH2 of the second impurity region DB can be selected from a range of about 5 nm to about 15 nm and can be smaller than the first thickness TH1 of the first impurity region DA. However, the thickness of each of the first impurity region DA and the second impurity region DB is not limited to the above-described examples.

[0041] In exemplary embodiments of the inventive concept, when the substrate 102 includes a crystalline semiconductor and the dopant ions included in the first impurity region DA include, for example, oxygen (O) ions, silicon (Si) ions, helium (He) ions, argon (Ar) ions, fluorine (F) ions, or a combination thereof, the first impurity region DA can include an amorphous semiconductor layer including interstitial atoms including the dopant ions. For example, when the substrate 102 includes crystalline silicon and the dopant ions included in the first impurity region DA include oxygen (O) ions, the first impurity region DA can include an amorphous silicon layer, and oxygen (O) atoms originating from the dopant ions can exist as interstitial oxygen (O) in the first impurity region DA. For example, oxygen (O) ions can be implanted into the substrate 102 including crystalline silicon, and thereby an oxygen (O) ion-implanted portion of the substrate 102 can be amorphized to form the first impurity region DA including an amorphous silicon layer including interstitial oxygen (O).

[0042] The second impurity region DB can include an insulating film including dopant ions selected from, for example, oxygen (O) ions, silicon (Si) ions, helium (He) ions, argon (Ar) ions, fluorine (F) ions, or a combination thereof. When the device isolation film 104 includes, for example, a silicon oxide (SiO2) film, a silicon nitride (Si3N4) film, or a combination thereof, and the dopant ions included in the second impurity region DB include oxygen (O) ions, the second impurity region DB can include, for example, an oxygen-rich silicon oxide film, a silicon oxynitride (SiON) film, or a combination thereof. As used herein, the term “oxygen-rich silicon oxide film” refers to a silicon oxide film having an oxygen (O) atom content higher than a stoichiometric oxygen (O) atom content in a SiO2 film. When the device isolation film 104 includes, for example, a silicon oxide (SiO2) film, a silicon nitride (Si3N4) film, or a combination thereof, and the dopant ions included in the second impurity region DB include silicon (Si) ions, the second impurity region DB can include, for example, a silicon-rich silicon oxide film, a silicon-rich silicon nitride film, or a combination thereof. As used herein, the term “silicon-rich silicon oxide film” refers to a silicon oxide film having a silicon atom content higher than a stoichiometric silicon atom content in a SiO2 film. As used herein, the term “silicon-rich silicon nitride film” refers to a silicon nitride film having a silicon atom content higher than a stoichiometric silicon atom content in a Si3N4 film.

[0043] The second impurity region DB includes dopant ions selected from, for example, oxygen (O) ions, silicon (Si) ions, helium (He) ions, argon (Ar) ions, fluorine (F) ions, and combinations thereof, such that the crystal structure of the host component of the second impurity region DB can be in a damaged state due to the dopant ions described above. In an exemplary embodiment of the inventive concept, the second impurity region DB can include interstitial atoms including the dopant ions described above and interstitial oxygen (O) originating from a silicon oxide (SiO2) film that is the host component film of the second impurity region DB. Thus, the second impurity region DB can include a host component film having a damaged lattice structure, for example, a silicon oxide (SiO2) film having a damaged lattice structure. For example, oxygen (O) ions can be implanted into the device isolation film 104 including a silicon oxide (SiO2) lattice structure, whereby the lattice structure of the oxygen (O) ion implanted portion of the device isolation film 104 can be damaged to form the second impurity region DB including a silicon oxide (SiO2) layer having a damaged lattice structure including interstitial oxygen (O).

[0044] The dopant ions present in the first impurity region DA and the second impurity region DB or the interstitial oxygen (O) caused by the dopant ions can move to the interface between the substrate 102 and the gate dielectric film 120 or into the gate dielectric film 120, such that oxygen (O) vacancies (hereinafter referred to as "Vo") can be substantially excluded from the gate dielectric film 120 or at the interface between the substrate 102 and the gate dielectric film 120. For example, the oxygen (O) vacancies in the gate dielectric film 120 or at the interface between the substrate 102 and the gate dielectric film 120 can be eliminated by the dopant ions or the interstitial oxygen (O).

[0045] Generally, when Vo exists in the gate dielectric film 120 and at the interface between the substrate 102 and the gate dielectric film 120, this can cause deterioration of the transistor including the gate dielectric film 120. In order to ensure stable electrical characteristics in the transistor including the gate dielectric film 120, it is necessary to reduce Vo in the gate dielectric film 120 and at the interface between the substrate 102 and the gate dielectric film 120. When the gate dielectric film 120 includes a silicon oxide (SiO2) film, a dangling bond can exist at and near the interface between the substrate 102 and the gate dielectric film 120 due to the breaking of a bond between a silicon atom and an oxygen (O) atom. This dangling bond can be in a metastable state by trapping hydrogen (H) supplied from a surrounding film, and this region of trapped hydrogen (H) can inadvertently become an electron trap capable of trapping electrons or become an electron generation source. As such, Vo can have an adverse effect on controlling the threshold voltage of the transistor by trapping hydrogen (H). In addition, a Vo-H bond formed by bonding between hydrogen (H) supplied from a surrounding film and Vo of the gate dielectric film 120 can be broken during use of the end product by a user, the threshold voltage of the transistor can change in an undesirable direction and can cause defect formation. Therefore, in order not to adversely affect the electrical characteristics of the transistor, it is necessary to reduce the Vo density at or near the interface between the gate dielectric film 120 and the substrate 102.

[0046] According to at least one embodiment of the present inventive concept, the interstitial oxygen (O) in the first and second impurity regions DA and DB in contact with and surrounding the gate dielectric film 120 can move to the interface between the gate dielectric film 120 and the first impurity region DA, to the interface between the gate dielectric film 120 and the second impurity region DB, and into the gate dielectric film 120, as a result of which excess oxygen (O) can be supplied to the above-mentioned interfaces and into the gate dielectric film 120. Thus, at the above-mentioned interfaces and in the gate dielectric film 120, Vo is filled with oxygen (O) and is in a stable state, so that Vo can be eliminated or the density of Vo can be significantly reduced. Thus, the problem caused by the presence of dangling bonds, which can be oxygen vacancies Vo, at the above-mentioned interfaces and the problem caused by the presence of oxygen vacancies Vo in the gate dielectric film 120 can be mitigated by eliminating dangling bonds and oxygen vacancies Vo using the interstitial oxygen (O) formed in the first and second impurity regions DA and DB. As used herein, the term "excess oxygen" refers to oxygen (O) in excess of the stoichiometric oxygen (O) content in the oxide that makes up the gate dielectric film 120. The excess oxygen (O) originating from the first and second impurity regions DA and DB can move between the first and second impurity regions DA and DB and the gate dielectric film 120. The movement of the excess oxygen (O) can include the case where it moves between the first and second impurity regions DA and DB and the gate dielectric film 120, and the case where it moves by being replaced by oxygen (O) that makes up each of the first and second impurity regions DA and DB and the gate dielectric film 120. Alternatively, Vo in the gate dielectric film 120 can continuously trap oxygen (O) atoms adjacent thereto, so that the position of Vo can be moved.

[0047] When trapping hydrogen, Vo can be in a metastable state, while when trapping oxygen (O), Vo can be in a stable state. According to the present inventive concept, the excess oxygen (O) originating from the first and second impurity regions DA and DB can be supplied to the above-mentioned interfaces and into the gate dielectric film 120 to eliminate Vo and repair dangling bonds before Vo at the above-mentioned interfaces and in the gate dielectric film 120 trap hydrogen to repair dangling bonds in a subsequent process, so that the above-mentioned interfaces as well as the interior of the gate dielectric film 120 can be in a stable state. Thus, in a transistor including the gate dielectric film 120, the threshold voltage can be precisely controlled and stable electrical characteristics can be ensured.

[0048] The main surface 102M of the substrate 102, the device isolation film 104, and the buried insulating film 128 can be covered with a buffer insulating film 130. The buffer insulating film 130 can include, for example, an oxide film, a nitride film, or a combination thereof.

[0049] The plurality of direct contacts DC can be respectively arranged on a portion of the plurality of active regions AC. The plurality of bit lines BL can be arranged on the buffer insulating film 130 and the plurality of direct contacts DC and extend longitudinally in the second horizontal direction (Y direction), and can be electrically connected to the plurality of active regions AC via the plurality of direct contacts DC. The plurality of bit lines BL can be respectively covered by the plurality of insulating cover patterns 138.

[0050] The plurality of conductive plugs 140P and the plurality of insulating fences 142 can be alternately and repeatedly arranged in lines along the second horizontal direction (Y direction) between a pair of adjacent bit lines BL among the plurality of bit lines BL. The plurality of insulating fences 142 can respectively fill a plurality of recesses 128R formed in a top surface of the buried insulating film 128, and can be arranged one after another between the plurality of conductive plugs 140P. In the second horizontal direction (Y direction), two side walls of each of the plurality of conductive plugs 140P can be covered by the plurality of insulating fences 142. The plurality of conductive plugs 140P arranged in lines along the second horizontal direction (Y direction) can be insulated from each other by the plurality of insulating fences 142. For example, the plurality of insulating fences 142 can limit or define positions of the plurality of conductive plugs 140P, and can be adjacent to side walls of the pair of adjacent bit lines BL and the pair of adjacent insulating cover patterns 138. The plurality of conductive plugs 140P can respectively constitute Figure 1 The plurality of buried contacts BC shown.

[0051] Each of the plurality of bit lines BL can be connected to an active region AC via a direct contact DC. One direct contact DC and a pair of conductive plugs 140P can be respectively connected to active regions AC different from each other among the plurality of active regions AC, wherein the pair of conductive plugs 140P face each other and the one direct contact DC is arranged between the pair of conductive plugs 140P. In an example embodiment of the inventive concept, the direct contact DC can include, for example, silicon (Si), germanium (Ge), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or a combination thereof. For example, the direct contact DC can include an epitaxial silicon layer.

[0052] Each of the plurality of bit lines BL can include a lower conductive layer 132, an intermediate conductive layer 134, and an upper conductive layer 136, which are sequentially formed on the upper face of the substrate 102 in the order. A top surface of the lower conductive layer 132 and a top surface of the direct contact DC can extend on the same plane. Although Figure 2A and Figure 2BEach of the plurality of bit lines BL is shown as having a three-layer structure including a lower conductive layer 132, an intermediate conductive layer 134, and an upper conductive layer 136, but the present inventive concept is not limited thereto. For example, each of the plurality of bit lines BL can have a single-layer structure, a two-layer structure, or a stacked structure including four or more layers. In an exemplary embodiment of the present inventive concept, the lower conductive layer 132 can include conductive polysilicon. Each of the intermediate conductive layer 134 and the upper conductive layer 136 can include, for example, titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten silicide (WSi), tungsten nitride (WN), or a combination thereof. For example, the intermediate conductive layer 134 can include titanium nitride (TiN) and / or titanium silicon nitride (TiSiN), and the upper conductive layer 136 can include tungsten (W). Each of the plurality of insulating cap patterns 138 can include, for example, a silicon nitride (Si3N4) film or a silicon oxynitride (SiON) film.

[0053] Each of the plurality of conductive plugs 140P can have a columnar shape extending in a vertical direction (Z direction) along a space between the plurality of bit lines BL on the substrate 102. A bottom surface of each of the plurality of conductive plugs 140P can contact the active area AC. A portion of each of the plurality of conductive plugs 140P can be located at a level lower than a level of the main surface 102M of the substrate 102. Each of the plurality of conductive plugs 140P can include, for example, a dopant-doped semiconductor material, a metal, a conductive silicide, a conductive metal nitride, or a combination thereof.

[0054] Each of the plurality of insulating fences 142 can have a columnar shape extending in a vertical direction (Z direction) between the plurality of bit lines BL and can include a silicon nitride (Si3N4) film. Each of the plurality of insulating fences 142 can also use other insulating films, such as a silicon oxide (SiO2) film or a silicon oxynitride (SiON) film.

[0055] Two sidewalls of each of the plurality of bit lines BL, the plurality of insulating cap patterns 138, and the plurality of direct contacts DC can be covered by a plurality of insulating spacers 146. The plurality of insulating spacers 146 can be arranged on two sidewalls of the plurality of bit lines BL to extend longitudinally in parallel to the plurality of bit lines BL in a second horizontal direction (Y direction). Each of the plurality of insulating spacers 146 can include, for example, an oxide film, a nitride film, an air spacer, or a combination thereof. As used herein, the term "air" can refer to a space including an atmosphere or other gas that can be present during a manufacturing process.

[0056] Each of the plurality of conductive plugs 140P can be spaced apart from the bit line BL in the first horizontal direction (X direction) by an insulating spacer 146 interposed between the conductive plug 140P and the bit line BL. Each of the plurality of insulating fences 142 can be spaced apart from the bit line BL in the first horizontal direction (X direction) by an insulating spacer 146 interposed between the insulating fence 142 and the bit line BL. In an exemplary embodiment of the inventive concept, an air gap region can be formed in combination with a nitride film and / or an oxide film to form each of the plurality of insulating spacers 146. Since the air gap region is filled with air having a dielectric constant less than that of silicon oxide (SiO2), the integrated circuit device 100 can reduce a parasitic capacitance between the bit line BL and the conductive plug 140P. Further, since the air gap region is disposed between the bit line BL and the insulating fence 142, a capacitance distribution of the bit line BL can be reduced.

[0057] The metal silicide film 172 and the conductive landing pad LP can be sequentially formed on the conductive plug 140P in the order described. The metal silicide film 172 and the conductive landing pad LP can be arranged to vertically overlap the conductive plug 140P. Each of the plurality of metal silicide films 172 is spaced apart from the bit line BL by an insulating spacer 146 interposed between the metal silicide film 172 and the bit line BL, and is arranged between the conductive plug 140P and the conductive landing pad LP. The metal silicide film 172 can include, for example, cobalt silicide (CoSi2), nickel silicide (NiSi2), or manganese silicide (MnSi2).

[0058] Each of the plurality of conductive landing pads LP can be connected to the conductive plug 140P via the metal silicide film 172. The plurality of conductive landing pads LP can extend from a space between the plurality of insulating cover patterns 138 to a space above the plurality of insulating cover patterns 138 to vertically overlap a portion of the plurality of bit lines BL. For example, the conductive landing pad LP can vertically overlap a sidewall of the bit line BL, and can have a width greater than a width of the conductive plug 140P in the second horizontal direction (Y direction). A center of the conductive landing pad LP can be offset away from a center of the conductive plug 140P in the first horizontal direction (X direction). Each of the plurality of conductive landing pads LP can include a conductive barrier film 174 and a conductive layer 176. The conductive barrier film 174 can include, for example, titanium (Ti), titanium nitride (TiN), or a combination thereof. The conductive layer 176 can include, for example, a metal, a metal nitride, conductive polysilicon, or a combination thereof. For example, the conductive layer 176 can include tungsten (W).

[0059] In a plan view, the plurality of conductive landing pads LP can have a shape of a plurality of island patterns. The plurality of conductive landing pads LP can be electrically insulated from each other by an insulating film 180 that fills insulating spaces 180S around the plurality of conductive landing pads LP. The insulating film 180 can include, for example, a silicon nitride (Si3N4) film, a silicon oxide (SiO2) film, or a combination thereof.

[0060] In Figures 2A-2D In the integrated circuit device 100 illustrated, the width (e.g., the second width Q2) of the portions of the plurality of word lines WL that are located above the device isolation film 104 can be greater than the width (e.g., the first width Q1) of the portions of the plurality of word lines WL that are located above the active region AC of the substrate 102. Thus, the space occupied by those portions of the plurality of word lines WL that are located above the device isolation film 104 can be expanded, resulting in an increase in the volume of the plurality of word lines WL. Thus, the resistance of the plurality of word lines WL can be reduced. In addition, because the integrated circuit device 100 includes the first impurity region DA and the second impurity region DB in contact with the gate dielectric film 120, the interstitial oxygen (O) generated due to the dopant ions contained in the first impurity region DA and the second impurity region DB can move to the interface between the gate dielectric film 120 and the first impurity region DA, to the interface between the gate dielectric film 120 and the second impurity region DB, and into the gate dielectric film 120, and the excess oxygen (O) is supplied to the above-mentioned interfaces and into the gate dielectric film 120, whereby Vo can be filled with oxygen (O) and be in a stable state at the above-mentioned interfaces and in the gate dielectric film 120. Thus, in the transistor including the gate dielectric film 120, the threshold voltage can be accurately controlled and stable electrical characteristics can be ensured.

[0061] Figure 3A And Figure 3B is a diagram illustrating an integrated circuit device according to an example embodiment of the present inventive concept, specifically, Figure 3A is a cross-sectional view of a region corresponding to a cross-section taken along a line X1-X1' of Figure 1 , and Figure 3B is a cross-sectional view illustrating some components in a region corresponding to a cross-section taken along a line Y1-Y1' of Figure 1 . In Figure 3A and Figure 3B , the same reference numerals as in Figures 2A-2D denote the same members, respectively, and a repeated description thereof will be omitted.

[0062] Referring to Figure 3A and Figure 3B , the integrated circuit device 200 has substantially the same configuration as that of the integrated circuit device 100 described with reference to Figures 2A-2D . The integrated circuit device 200 can haveFigure 1 and Figure 2D The integrated circuit device 200 includes the device isolation film 204 having a multi-layer structure instead of the device isolation film 104.

[0063] The device isolation film 204 can include an insulating liner 204A and a gap-fill insulating film 204B, which are sequentially formed in the device isolation trench 104T in the order described. The insulating liner 204A in the device isolation trench 104T can have a structure surrounding the gap-fill insulating film 204B. In an exemplary embodiment of the inventive concept, the insulating liner 204A can include a silicon oxide (SiO2) film, and the gap-fill insulating film 204B can include a silicon nitride (Si3N4) film, but the inventive concept is not limited thereto.

[0064] In the integrated circuit device 200, a first impurity region DA2 can be disposed between the substrate 102 and the gate dielectric film 120. A second impurity region DB2 can be disposed between the device isolation film 204 and the gate dielectric film 120. In an exemplary embodiment of the inventive concept, each of the first impurity region DA2 and the second impurity region DB2 can include a dopant ion selected from, for example, an oxygen (O) ion, a silicon (Si) ion, a helium (He) ion, an argon (Ar) ion, a fluorine (F) ion, and combinations thereof. The first impurity region DA2 and the second impurity region DB2 can have substantially the same configuration as that described with respect to the first impurity region DA and the second impurity region DB described in Figure 2A , Figure 2C and Figure 2D .

[0065] In an exemplary embodiment of the inventive concept, when the insulating liner 204A includes a silicon oxide (SiO2) film and the gap-fill insulating film 204B includes a silicon nitride (Si3N4) film, and when the dopant ion includes an oxygen (O) ion, a portion of the second impurity region DB2 facing the insulating liner 204A can include an oxygen-rich silicon oxide film, and a portion of the second impurity region DB2 facing the gap-fill insulating film 204B can include a silicon oxynitride (SiON) film. Accordingly, the integrated circuit device 200 includes the first impurity region DA2 and the second impurity region DB2 having excess oxygen (O) and in contact with the gate dielectric film 120, whereby at the interface between the gate dielectric film 120 and the first impurity region DA2, at the interface between the gate dielectric film 120 and the second impurity region DB2, and in the gate dielectric film 120, the density of Vo can be eliminated or significantly reduced by the excess oxygen (O) supplied from the first impurity region DA2 and the second impurity region DB2. Accordingly, in the transistor including the gate dielectric film 120, the threshold voltage can be precisely controlled and stable electrical characteristics can be ensured.

[0066] Figure 4Aand Figure 4B is a diagram showing an integrated circuit device according to an example embodiment of the present inventive concept, specifically, Figure 4A is a cross-sectional view of a region corresponding to a cross-section taken along a line X1-X1' of Figure 1 , and Figure 4B is a cross-sectional view of some components in a region corresponding to a cross-section taken along a line Y1-Y1' of Figure 1 . In Figure 4A and Figure 4B , the same reference numerals as those in Figures 2A-2D denote the same members, respectively, and repetitive description thereof will be omitted.

[0067] Referring to Figure 4A and Figure 4B , the integrated circuit device 300 has substantially the same configuration as that of the integrated circuit device 100 described with reference to Figures 2A-2D . The integrated circuit device 300 can have a planar layout configuration as shown in Figure 1 . However, the integrated circuit device 300 can include a plurality of word line trenches WT3 extending in parallel to each other in a first horizontal direction (X direction) in the substrate 102, a first impurity region DA3 arranged between the substrate 102 and the gate dielectric film 120 to extend along a portion of an inner wall of each of the word line trenches WT3, and a second impurity region DB3 arranged between the device isolation film 104 and the gate dielectric film 120 to extend along a portion of the inner wall of each of the word line trenches WT3.

[0068] Each of the plurality of word line trenches WT3 can include a first trench portion T3A in the substrate 102 and a second trench portion T3B in the device isolation film 104. The first trench portion T3A can have substantially the same configuration as that of the first trench portion T1A shown in Figure 2A , Figure 2C and Figure 2D . In a second horizontal direction (Y direction), a lower width of the second trench portion T3B can be greater than an upper width of the second trench portion T3B. In the second horizontal direction (Y direction), the upper width of the second trench portion T3B can be approximately equal to or similar to a width of the first trench portion T3A.

[0069] An inside of each of the plurality of word line trenches WT3 can be filled with the gate dielectric film 120, the word line WL3, and the buried insulating film 128. The plurality of word lines WL3 can have substantially the same configuration as that of the word line WL1 described with reference to Figure 2A , Figure 2C and Figure 2DThe structures described for the multiple word lines WL are substantially the same. However, in the second horizontal direction (Y direction), the lower width of the portion of each word line WL3 filling the second trench portion T3B can be greater than the upper width of the multiple word lines WL3. Therefore, in the second horizontal direction (Y direction), the lower width of the portion of the multiple word lines WL3 arranged on the device isolation membrane 104 can be greater than the upper width of the multiple word lines WL3. In the second horizontal direction (Y direction), the portion of each of the multiple word lines WL3 filling the first trench portion T3A can have a first width Q31, and the lower portion of each of the multiple word lines WL3 filling the second trench portion T3B can have a second width Q32 greater than the first width Q31. In this way, the portion of the multiple word lines WL3 arranged on the device isolation membrane 104 can have a relatively large width, thereby reducing the resistance of the multiple word lines WL3. For example, the space occupied by the portions of the multiple word lines WL3 located above the device isolation film 104 can be increased, thereby increasing the volume of the multiple word lines WL3. Therefore, the resistance of the multiple word lines WL3 can be reduced.

[0070] The first impurity region DA3 and the second impurity region DB3 can respectively have the characteristics related to... Figure 2A , Figure 2C and Figure 2D The first impurity region DA and the second impurity region DB shown have substantially the same structure. However, the first impurity region DA3 and the second impurity region DB3 may not be formed in the region adjacent to the main surface 102M of the substrate 102 and the region adjacent to the top surface of the device isolation film 104, respectively. The first impurity region DA3 may not be formed on the upper part of the sidewall of the first trench portion T3A. The second impurity region DB3 may not be formed on the upper part of the sidewall of the second trench portion T3B. The first impurity region DA3 may be arranged along the inner sidewall of the first trench portion T3A at a position separated from the main surface 102M of the substrate 102, and may only surround the portion of the gate dielectric film 120 adjacent to the bottom surface of the first trench portion T3A. The second impurity region DB3 may be arranged along the inner sidewall of the second trench portion T3B at a position separated from the top surface of the device isolation film 104, and may only surround the portion of the gate dielectric film 120 adjacent to the bottom surface of the second trench portion T3B.

[0071] The second thickness TH32 of the second impurity region DB3 can be less than the first thickness TH31 of the first impurity region DA3. Because the ion-implanted portion of the device isolation film 104 can be partially etched with an etchant in a subsequent process, the thickness of the ion-implanted portion of the device isolation film 104 can be reduced in a subsequent process, thereby forming a second impurity region DB3 with a second thickness TH32 that is less than the first thickness TH31 of the first impurity region DA3. For example, the first thickness TH31 of the first impurity region DA3 can be selected from a range of approximately 10 nm to approximately 20 nm, and the second thickness TH32 of the second impurity region DB3 can be selected from a range of approximately 5 nm to approximately 15 nm and can be less than the first thickness TH31 of the first impurity region DA3. However, the thicknesses of the first impurity region DA3 and the second impurity region DB3 are not limited to the examples described above.

[0072] exist Figure 4A and Figure 4B In the integrated circuit device 300 shown, the lower width of the portion of the multiple word lines WL3 arranged on the device isolation film 104 can be greater than the width of the portion of the multiple word lines WL3 arranged on the active region AC. Therefore, the resistance of the multiple word lines WL3 can be reduced. For example, the space occupied by the portions of the multiple word lines WL3 located on the device isolation film 104 can be increased, thereby increasing the volume of the multiple word lines WL3. Therefore, the resistance of the multiple word lines WL3 can be reduced. In addition, the integrated circuit device 300 includes a first impurity region DA3 and a second impurity region DB3 having excess oxygen (O) and in contact with the gate dielectric film 120. Thus, at the interface between the gate dielectric film 120 and the first impurity region DA3, at the interface between the gate dielectric film 120 and the second impurity region DB3, and in the gate dielectric film 120, the excess oxygen (O) supplied by the first impurity region DA3 and the second impurity region DB3 can eliminate Vo or significantly reduce the density of Vo. Therefore, in a transistor including the gate dielectric film 120, the threshold voltage can be precisely controlled and stable electrical characteristics can be ensured.

[0073] Figure 5A and Figure 5B This is a diagram illustrating an integrated circuit device according to an exemplary embodiment of the present invention, specifically, Figure 5A Is along Figure 1 A cross-sectional view of the region corresponding to the section intercepted by line X1-X1', and Figure 5B It is shown along Figure 1 A cross-sectional view of some components in the region corresponding to the section intercepted by line Y1-Y1'. Figure 5A and Figure 5B In, with Figures 2A-2D The same reference numerals in the accompanying drawings denote the same components, and repeated descriptions of them will be omitted.

[0074] Referring to Figure 5A and Figure 5B , the integrated circuit device 400 has substantially the same configuration as that of the integrated circuit device 100 described with reference to Figures 2A-2D . The integrated circuit device 400 can have a planar layout configuration as shown in Figure 1 and Figure 2D . However, the integrated circuit device 400 further includes a dopant region D4 having a flat plate shape and extending in the substrate 102 in parallel to the main surface 102M of the substrate 102. The dopant region D4 can include interstitial atoms including, for example, oxygen (O) atoms, silicon (Si) atoms, helium (He) atoms, argon (Ar) atoms, fluorine (F) atoms, or a combination thereof. The more detailed configuration of the dopant region D4 is substantially the same as that described with respect to the first dopant region DA shown in Figure 2A , Figure 2C and Figure 2D .

[0075] Although Figure 5A and Figure 5B show an example in which the dopant region D4 extends in a flat plate shape at a level LV4 lower than the level of the lowest surface of the device isolation film 104, the inventive concept is not limited thereto. For example, the dopant region D4 can extend in a flat plate shape across the substrate 102 and the device isolation film 104 in parallel to the main surface 102M of the substrate 102 at a level lower than the level of the lowest surface of the word line trench WT and higher than the level of the lowest surface of the device isolation film 104.

[0076] The dopant region D4 can include interstitial atoms including, for example, oxygen (O) ions, silicon (Si) ions, helium (He) ions, argon (Ar) ions, fluorine (F) ions, or a combination thereof. The interstitial atoms included in the dopant region D4 can cause interstitial oxygen (O) or excess oxygen (O) in and around the dopant region D4. The interstitial oxygen (O) or excess oxygen (O) thus generated can move into the gate dielectric film 120 and reach the surface of the gate dielectric film 12 via various paths. Therefore, prior to the capture of Vo by Vo in the gate dielectric film 120 and Vo at the surface of the gate dielectric film 12, due to the interstitial oxygen (O) or excess oxygen (O), Vo can be eliminated or the density of Vo can be significantly reduced, and thus the inside of the gate dielectric film 120 as well as the interface between the substrate 102 and the gate dielectric film 120 can be in a stable state. Therefore, in the transistor including the gate dielectric film 120, the threshold voltage can be precisely controlled and stable electrical characteristics can be ensured.

[0077] In an exemplary embodiment of the inventive concept, the integrated circuit device 200 shown in Figure 3A and Figure 3B as well asFigure 4A and Figure 4B Each of the integrated circuit devices 300 shown may further include a reference. Figure 5A and Figure 5B The impurity region D4 is described.

[0078] Figures 6A-6H A cross-sectional view illustrating a sequential process of a method for manufacturing an integrated circuit device according to an exemplary embodiment of the present invention is shown. (Refer to...) Figures 6A-6H Description of manufacturing Figure 1 as well as Figures 2A-2D An example method of the integrated circuit device 100 shown. Figures 6A-6H Each shows the process sequence and along Figure 1 The cross section intercepted by line X1-X1' and along Figure 1 The cross-section structure corresponding to the section cut by line Y1-Y1'.

[0079] Reference Figure 6A A mask pattern M1 is formed on the main surface 102M of the substrate 102, and a device isolation trench 104T is formed in the substrate 102 by etching the substrate 102 using the mask pattern M1 as an etching mask. The mask pattern M1 can be formed by photolithography and etching processes. The device isolation trench 104T can define a plurality of active regions AC that are separated from each other in the substrate 102. The mask pattern M1 may include a hard mask, which includes, for example, an oxide film, polysilicon, or a combination thereof. In an exemplary embodiment of the inventive concept, the device isolation trench 104T can be formed by removing the upper portion of the substrate 102 using an anisotropic etching process that uses the mask pattern M1 as an etching mask.

[0080] Reference Figure 6B From Figure 6AAfter removing the mask pattern M1 from the resultant product, an insulating film P104 is formed to fill the device isolation trenches 104T and cover the main surface 102M of the substrate 102, and an ion implantation process for forming a plurality of source / drain regions SD in the substrate 102 is performed. In the ion implantation process for forming the plurality of source / drain regions SD, ions are implanted into the substrate 102 at a desired energy and dose. Here, the ions used in the ion implantation process can include a p-type dopant and / or an n-type dopant. Suitable n-type dopants can include, for example, phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), or a combination thereof. Suitable p-type dopants can include, for example, boron (B), aluminum (Al), gallium (Ga), thallium (Tl), indium (In), or a combination thereof. In an exemplary embodiment of the inventive concept, in order to form the plurality of source / drain regions SD, a heat treatment can be performed after implanting the p-type dopant and / or the n-type dopant into the substrate 102 to enhance diffusion of the implanted dopant in the substrate 102. The portion of the insulating film P104 that fills the device isolation trenches 104T can be a device isolation film 104. The portion of the insulating film P104 that covers the main surface 102M of the substrate 102 can protect the main surface 102M of the substrate 102 during the ion implantation process for forming the plurality of source / drain regions SD or during a subsequent etching process.

[0081] Referring to Figure 6C Both the insulating film P104 and the substrate 102 are partially etched using the mask pattern M2 as an etching mask, thereby forming a plurality of word line trenches WT extending across the plurality of active regions AC and the device isolation film 104 in the first horizontal direction (X direction). The word line trenches WT can include a first trench portion T1A having a bottom surface of the substrate 102 exposed at a first level LV1 and a second trench portion T1B having a bottom surface of the device isolation film 104 exposed at a second level LV2 lower than the first level LV1. The mask pattern M2 can include, for example, an oxide film, an amorphous carbon layer (ACL), a silicon oxynitride (SiON) film, or a combination thereof. The mask pattern M2 can be formed by a photolithography process and an etching process.

[0082] To form the plurality of word line trenches WT, a first etching process and a second etching process can be sequentially performed in the order, in the first etching process, the substrate 102 and the device isolation film 104 are etched from the main surface 102M of the substrate 102 under a condition that an etching rate of the substrate 102 is approximately equal to an etching rate of the device isolation film 104, in the second etching process, the substrate 102 and the device isolation film 104 are etched under a condition that the etching rate of the device isolation film 104 is greater than the etching rate of the substrate 102. In an exemplary embodiment of the present inventive concept, the plurality of word line trenches WT can be formed by removing the upper portion of the substrate 102 and the upper portion of the device isolation film 104 through an anisotropic etching process. As a result, a second level LV2 of the second trench portion T1B exposing a bottom surface of the device isolation film 104 can be lower than a first level LV1 of the first trench portion T1A exposing a bottom surface of the substrate 102. The first trench portion T1A and the second trench portion T1B can have substantially equal or approximately similar widths W1 to each other in a second horizontal direction (Y direction), respectively.

[0083] The plurality of active regions AC can include a plurality of fin regions AF protruding upward in a vertical direction (Z direction) from the second level LV2 to the first level LV1 in the plurality of word line trenches WT.

[0084] Referring to Figure 6D , the dopant ions 108 are implanted into the substrate 102 and the device isolation film 104 through the plurality of word line trenches WT, thereby forming a first impurity region DA in the substrate 102 to surround the first trench portion T1A and forming a second impurity region DB in the device isolation film 104 to surround the second trench portion T1B.

[0085] In an exemplary embodiment of the present inventive concept, the dopant ions 108 can include, for example, oxygen (O) ions, silicon (Si) ions, helium (He) ions, argon (Ar) ions, fluorine (F) ions, or a combination thereof.

[0086] In an exemplary embodiment of the present inventive concept, to implant the dopant ions 108 into the substrate 102 and the device isolation film 104, a plasma type ion implantation device can be used. When the plasma type ion implantation device is used, a process of implanting the dopant ions 108 can be performed at an acceleration voltage in a range from approximately 0.1 keV to approximately 50 keV, and a dose can be selected from a range of approximately 1 x 1011 ions / cm2 to approximately 1 x 1014 ions / cm2. 13 2 15 2

[0087] ​​​​The implantation angle of the dopant ions 108 can be selected from a range of about 0 degrees to about 3 degrees from the normal direction of the major surface 102M of the substrate 102, and the ion implantation process can be performed while the rotation angle is periodically changed by up to about 45 degrees, 90 degrees, 135 degrees, or 180 degrees with respect to the notch or orientation flat of the substrate 102 in a direction parallel to the major surface 102M of the substrate 102.

[0088] In exemplary embodiments of the inventive concept, in order to form the first impurity region DA and the second impurity region DB, a heat treatment can be performed after the dopant ions 108 are implanted into the substrate 102 and the device isolation film 104. In exemplary embodiments of the inventive concept, a heat treatment process for diffusing the dopant ions 108 can be omitted directly after the dopant ions 108 are implanted into the substrate 102 and the device isolation film 104, and a subsequent process can be performed. In this case, due to the atmosphere temperature during the formation of the gate dielectric film 120, the dopant ions 108 implanted into the substrate 102 and the device isolation film 104 can diffuse, which will be described below with reference to FIG. 2, so that the first impurity region DA and the second impurity region DB can be formed. Figure 6F In exemplary embodiments of the inventive concept, in order to form the first impurity region DA and the second impurity region DB, a heat treatment can be performed after the dopant ions 108 are implanted into the substrate 102 and the device isolation film 104. In exemplary embodiments of the inventive concept, a heat treatment process for diffusing the dopant ions 108 can be omitted directly after the dopant ions 108 are implanted into the substrate 102 and the device isolation film 104, and a subsequent process can be performed. In this case, due to the atmosphere temperature during the formation of the gate dielectric film 120, the dopant ions 108 implanted into the substrate 102 and the device isolation film 104 can diffuse, which will be described below with reference to FIG. 2, so that the first impurity region DA and the second impurity region DB can be formed.

[0089] Because dopant ions 108 are implanted into the device isolation film 104, the crystal structure of the material constituting the device isolation film 104 can be disrupted by the bombardment caused by the dopant ions 108 within the device isolation film 104. Therefore, the second impurity region DB in the device isolation film 104 and surrounding the second trench portion T1B can include interstitial atoms and interstitial oxygen (O). The interstitial atoms include, for example, oxygen (O) atoms, silicon (Si) atoms, helium (He) atoms, argon (Ar) atoms, or fluorine (F) atoms derived from the dopant ions 108 implanted into the device isolation film 104, while the interstitial oxygen (O) originates from the insulating film (e.g., silicon oxide (SiO2) film) constituting the device isolation film 104. Therefore, unlike the device isolation film 104, the second impurity region DB can have a damaged lattice structure.

[0090] Reference Figure 6E Cleaning in the first etching atmosphere Figure 6D The result product, from Figure 6D The resulting product removes unwanted natural oxide films and contaminants, and removes the portion of the second impurity region DB exposed by the second trench portion T1B.

[0091] In an exemplary embodiment of the present invention, the first etching atmosphere may be a wet etching atmosphere using dilute hydrofluoric acid (HF) (DHF) and ozone (O3). Cleaning with the first etching atmosphere... Figure 6D After obtaining the product, the obtained product can be dried by supplying isopropanol (IPA) and / or nitrogen (N2) gas. For example, when the substrate 102 comprises silicon (Si) and the device isolation film 104 comprises silicon oxide (SiO2), it is cleaned in the first etching atmosphere. Figure 6D Following the resulting product, under a wet etching atmosphere using DHF and O3, the high etching selectivity of silicon oxide (SiO2) relative to silicon (Si) will result in significant film loss in the second impurity region DB, which includes silicon oxide, and no or very small film loss in the first impurity region DA, which includes silicon (Si).

[0092] Because the second impurity region DB has a damaged lattice structure, it is difficult to clean with the first etch atmosphere. Figure 6D When the resulting product is obtained, the second impurity region DB is easily removed by the first etching atmosphere. Therefore, when cleaning with the first etching atmosphere... Figure 6DWhen the resulting product is obtained, a portion of the thickness of the second impurity region DB exposed through the second trench portion T1B can be removed from its exposed surface, thereby reducing the thickness of the second impurity region DB exposed through the second trench portion T1B, and increasing the width and depth of the second trench portion T1B. For example, the reduction of the thickness of the second impurity region DB exposed through the second trench portion T1B can be performed in a wet etching atmosphere. After the cleaning process in the first etching atmosphere, in the second horizontal direction (Y direction), the width W2 of the second trench portion T1B can be greater than the width W1 of the first trench portion T1A, and the level of the lowest surface of the second trench portion T1B can be lower than the second level LV2. Figure 6C Level 3 of )

[0093] After the cleaning process in the first etching atmosphere, the second thickness TH2 of the second impurity region DB can be less than the first thickness TH1 of the first impurity region DA.

[0094] Additionally, during the cleaning process in the first etching atmosphere, a portion of the thickness of the second impurity region DB on the relatively small lateral width of the device isolation film 104 can be removed from its exposed surface, thereby increasing the lateral width and vertical length of the second trench portion T1B. Therefore, the two second trench portions T1B can have no difference or a very small difference in their depth, wherein the two second trench portions T1B are arranged on both sides of the fin region AF in the second horizontal direction (Y direction) by inserting the fin region AF of the substrate 102 between the two second trench portions T1B. As a result, as shown in the following reference... Figure 6G After the word line WL is formed, the portions of the word line WL covering the fin region AF on both sides of the fin region AF in the second horizontal direction (Y direction) may have no difference or very small difference in height. Therefore, in a transistor including a word line WL covering the fin region AF, gate controllability can be enhanced.

[0095] Reference Figure 6F ,exist Figure 6E A gate dielectric film 120 is formed on the resulting product. The gate dielectric film 120 can be formed to conformally cover the first impurity region DA and the second impurity region DB.

[0096] To form the gate dielectric film 120, an atomic layer deposition (ALD) process can be used. In an exemplary embodiment of the inventive concept, the process of forming the gate dielectric film 120 can be performed in a plasma atmosphere by using O2 gas and inert gas as plasma treatment gas. In an exemplary embodiment of the inventive concept, the process of forming the gate dielectric film 120 can be performed in a plasma atmosphere by using O2 gas, inert gas, and H2 gas as plasma treatment gas. In an exemplary embodiment of the inventive concept, during forming the gate dielectric film 120, an in-situ steam generation (ISSG) process using water vapor or a combination of O2 gas and H2 gas can be performed.

[0097] In an exemplary embodiment of the inventive concept, to form the plasma atmosphere, O2 gas and Ar gas can be supplied into the plasma processing apparatus. In an exemplary embodiment of the inventive concept, to form the plasma atmosphere, O2 gas, Ar gas, and H2 gas can be supplied into the plasma processing apparatus. By controlling the amount of oxygen (O) ions or oxygen (O) radicals in the plasma atmosphere, the gate dielectric film 120 can be formed with a uniform thickness on both the surface of the first impurity region DA exposed through the first trench portion T1A and the surface of the second impurity region DB exposed through the second trench portion T1B.

[0098] The process of forming the gate dielectric film 120 can be performed by using, for example, a radial line slot antenna (RLSA) microwave plasma processing apparatus, a remote plasma type plasma processing apparatus, an inductively coupled plasma (ICP) type plasma processing apparatus, an electron cyclotron resonance (ECR) plasma type plasma processing apparatus, a surface reflected wave plasma type plasma processing apparatus, a magnetron plasma type plasma processing apparatus, or the like. The gate dielectric film 120 can have a thickness in a range of from about 1 nm to about 10 nm, but the inventive concept is not limited thereto. to about 10 nm, but the inventive concept is not limited thereto.

[0099] ​The process of forming the gate dielectric film 120 can be performed in an atmosphere at a relatively high temperature in a range from approximately 600°C to approximately 1000°C. Thus, during the process of forming the gate dielectric film 120, the interstitial oxygen (O) in the first impurity region DA and the second impurity region DB can move to the interface between the gate dielectric film 120 and the first impurity region DA, to the interface between the gate dielectric film 120 and the second impurity region DB, and into the gate dielectric film 120, and thus, excess oxygen (O) can be supplied to the above-mentioned interfaces and into the gate dielectric film 120. As a result, at the above-mentioned interfaces and in the gate dielectric film 120, Vo is filled with oxygen (O) and is in a stable state, so that Vo can be eliminated or the density of Vo can be significantly reduced. Thus, in the transistor including the gate dielectric film 120, the threshold voltage can be precisely controlled and stable electrical characteristics can be ensured. The gate dielectric film 120 can include, for example, a silicon oxide (SiO2) film substantially free of Vo, a metal oxide film substantially free of Vo, an oxygen-rich silicon oxide film, or an oxygen-rich metal oxide film.

[0100] Referring to Figure 6G A plurality of word lines WL are formed on the gate dielectric film 120 to partially fill each of the first trench portion T1A and the second trench portion T1B.

[0101] In the exemplary embodiment of the present inventive concept, in order to form the plurality of word lines WL, a metal-containing barrier film 122 which conformally covers exposed surfaces of the gate dielectric film 120 in the first trench portion T1A and the second trench portion T1B, and a lower word line 124 which is disposed on the metal-containing barrier film 122 to fill the first trench portion T1A and the second trench portion T1B can be first formed, and then unnecessary portions of the metal-containing barrier film 122 and the lower word line 124 can be removed by etch-back so that only portions of the metal-containing barrier film 122 and the lower word line 124 which partially fill each of the first trench portion T1A and the second trench portion T1B remain. Next, a conductive layer for forming an upper word line 126 can be formed to cover the metal-containing barrier film 122 and the lower word line 124 in the first trench portion T1A and the second trench portion T1B, and then unnecessary portions of the conductive layer for forming the upper word line 126 can be removed by etch-back so that an upper space of each of the first trench portion T1A and the second trench portion T1B is emptied, thereby leaving the upper word line 126 in the conductive layer for forming the upper word line 126. During the etch-back process, portions of the conductive layer for forming the upper word line 126 in the first trench portion T1A and the second trench portion T1B can be simultaneously removed. Accordingly, an upper surface of the upper word line 126 within the device isolation film 104 and an upper surface of the upper word line 126 within the substrate 102 can be located at substantially the same level. Thus, the metal-containing barrier film 122 can contact the gate dielectric film 120, and the lower word line 124 in each of the first trench portion T1A and the second trench portion T1B can be surrounded by the metal-containing barrier film 122 and the upper word line 126. During the formation of the upper word line 126, each of the mask pattern M2 which covers the main surface 102M of the substrate 102 and the gate dielectric film 120 can be partially consumed and thus have a reduced thickness.

[0102] In the second horizontal direction (Y direction), the portion of each of the plurality of word lines WL which fills the first trench portion T1A can have a first width Q1, and the portion of each of the plurality of word lines WL which fills the second trench portion T1B can have a second width Q2 which is greater than the first width Q1 described above. After the plurality of word lines WL are formed, an upper trench space US can remain above each of the plurality of word lines WL in the word line trench WT.

[0103] Referring to Figure 6H , in Figure 6G , a buried insulating film 128 is formed on the resultant product to fill the upper trench space US, and then unnecessary films or layers on the substrate 102 are removed, thereby exposing the main surface 102M of the substrate 102.

[0104] In the process described with reference to Figures 6A-6H , although the Figures 6D-6GThe process described is performed while the mask pattern M2 remains on the substrate 102, but the mask pattern M2 can be removed in one of the processes as needed, and then the subsequent processes can be performed. Figures 6D-6G The process described is performed while the mask pattern M2 remains on the substrate 102, but the mask pattern M2 can be removed in one of the processes as needed, and then the subsequent processes can be performed.

[0105] Next, the buffer insulating film 130, the plurality of direct contacts DC, the plurality of bit lines BL, the plurality of insulating spacers 146, the plurality of insulating barriers 142, the plurality of conductive plugs 140P, the metal silicide film 172, the conductive landing pad LP, and the insulating film 180 can be formed on or over the substrate 102, thereby manufacturing the integrated circuit device 100 having the configuration shown in FIG. 1. Figures 2A-2D

[0106] To manufacture the integrated circuit device 200 described with reference to Figure 3A and Figure 3B , the method described with reference to Figures 6A-6H may be used. However, instead of the device isolation film 104 described with reference to Figure 6B , a device isolation film 204 can be formed. To form the device isolation film 204, the mask pattern M1 is removed from the resulting product of Figure 6A , then an insulating liner 204A is formed to conformally cover the inner walls of the device isolation trenches 104T and the major surface 102M of the substrate 102, then a gap-fill insulating film 204B can be formed on the insulating liner 204A to a thickness sufficient to fill the remaining spaces of the device isolation trenches 104T. The ion implantation process for forming the plurality of source / drain regions SD in the substrate 102 can then be performed. Next, the processes described with reference to Figures 6C-6H may be performed, then the buffer insulating film 130, the plurality of direct contacts DC, the plurality of bit lines BL, the plurality of insulating spacers 146, the plurality of insulating barriers 142, the plurality of conductive plugs 140P, the metal silicide film 172, the conductive landing pad LP, and the insulating film 180 can be formed on or over the substrate 102, thereby manufacturing the integrated circuit device 200 described with reference to Figure 3A and Figure 3B .

[0107] Figures 7A-7C Cross-sectional views showing sequential processes of a method of manufacturing an integrated circuit device according to example embodiments of the inventive concepts are shown. Reference will be made to Figures 7A-7C describing an example method of manufacturing Figure 4A and Figure 4B . Figures 7A-7C Each shows a cross-sectional configuration corresponding to a cross-section taken along a line X1-X1' of Figure 1 and a cross-section taken along a line Y1-Y1' of Figure 1 .

[0108] Reference will be made to​Figure 7A In the same manner as described with reference to Figures 6A-6C the process is performed until the process of forming the plurality of word line trenches WT, and in a similar manner as described with reference to Figure 6D dopant ions 308 are implanted into the substrate 102 and the device isolation film 104, thereby forming a first impurity region DA3 in the substrate 102 to surround the first trench portion T1A and a second impurity region DB3 in the device isolation film 104 to surround the second trench portion T1B. The dopant ions 308 can have an implantation angle of about 0 degrees with respect to a normal direction of the main surface 102M of the substrate 102. Thus, the first impurity region DA3 and the second impurity region DB3 can not be formed in regions adjacent to the main surface 102M of the substrate 102 and the top surface of the device isolation film 104, respectively. In an exemplary embodiment of the present inventive concept, in order to form the first impurity region DA3 and the second impurity region DB3, a heat treatment can be performed after the dopant ions 308 are implanted into the substrate 102 and the device isolation film 104. In an exemplary embodiment of the present inventive concept, a heat treatment process for diffusing the dopant ions 308 can be omitted directly after the dopant ions 308 are implanted into the substrate 102 and the device isolation film 104, and a subsequent process can be performed. Figure 6D The same configuration as described with reference to the dopant ions 108. However, at the time of implanting the dopant ions 308 into the substrate 102 and the device isolation film 104, an implantation angle of the dopant ions 308 with respect to a normal direction of the main surface 102M of the substrate 102 can be about 0 degrees. Thus, the first impurity region DA3 and the second impurity region DB3 can not be formed in regions adjacent to the main surface 102M of the substrate 102 and the top surface of the device isolation film 104, respectively. In an exemplary embodiment of the present inventive concept, in order to form the first impurity region DA3 and the second impurity region DB3, a heat treatment can be performed after the dopant ions 308 are implanted into the substrate 102 and the device isolation film 104. In an exemplary embodiment of the present inventive concept, a heat treatment process for diffusing the dopant ions 308 can be omitted directly after the dopant ions 308 are implanted into the substrate 102 and the device isolation film 104, and a subsequent process can be performed.

[0109] With reference to Figure 7B , by cleaning the resultant product of Figure 6E in the same manner as described with reference to Figure 7A , unwanted natural oxide films and contaminants are removed from the resultant product of Figure 7A , and the second impurity region DB3 exposed at the inner wall of the second trench portion T1B is partially removed, thereby modifying the plurality of word line trenches WT to a plurality of word line trenches WT3. Each of the plurality of word line trenches WT3 can include a first trench portion T3A in the substrate 102 and a second trench portion T3B in the device isolation film 104.

[0110] The first trench portion T3A can have substantially the same or similar shape as that of the first trench portion T1A (see Figure 7A ). Because the second impurity region DB3 exposed by the second trench portion T1B (see Figure 7A ) has a damaged lattice structure, the second impurity region DB3 is partially removed at the time of cleaning Figure 7AThe second impurity region DB3 can be partially removed during the resultant product of the process described with reference to Figure 7A , and thus has a reduced thickness. For example, the thickness of the second impurity region DB3 exposed by the second trench portion T1B can be reduced in a wet etching atmosphere with a DHF and an O3 etchant. Thus, the width and depth of the second trench portion T3B (see Figure 7A ) increases at the lower portion thereof, so that the second trench portion T3B having a lower portion width greater than an upper portion width in the second horizontal direction (Y direction) can be obtained. The lower portion width W32 of the second trench portion T3B can be greater than the width W31 of the first trench portion T3A in the second horizontal direction (Y direction), and the level of the lowest surface of the second trench portion T3B can be a third level LV33 lower than the second level LV2 Figure 7B After the cleaning process described with reference to Figure 7B , the second thickness TH32 of the second impurity region DB3 can be less than the first thickness TH31 of the first impurity region DA3. The first thickness TH31 of the first impurity region DA3 can be approximately equal to or similar to the thickness thereof before the cleaning process described with reference to

[0111] With reference to Figure 7C , the gate dielectric film 120, the plurality of word lines WL3, and the buried insulating film 128 can be formed by performing the process described with reference to Figure 7B on the resultant product of Figures 6F-6H . Each of the plurality of word lines WL3 is arranged on the gate dielectric film 120 to partially fill each of the first trench portion T3A and the second trench portion T3B. The buried insulating film 128 can be formed on each of the plurality of word lines WL3 to fill the remaining space of the first trench portion T3A and the second trench portion T3B. The portion of each of the plurality of word lines WL3 filling the first trench portion T3A can have a first width Q31, and the portion of each of the plurality of word lines WL3 filling the lower portion of the second trench portion T3B can have a second width Q32 greater than the first width Q31 described above.

[0112] Next, the buffer insulating film 130, the plurality of direct contacts DC, the plurality of bit lines BL, the plurality of insulating spacers 146, the plurality of insulating fences 142, the plurality of conductive plugs 140P, the metal silicide film 172, the conductive landing pad LP, and the insulating film 180 can be formed on or above the substrate 102, so that the integrated circuit device 300 having the configuration shown in Figure 4A and Figure 4B is manufactured.

[0113] Figure 8 Cross-sectional views showing a method of manufacturing an integrated circuit device according to an example embodiment of the present inventive concept are shown. The manufacturing will be described with reference to Figure 8 .Figure 5A and Figure 5B An example method of the integrated circuit device 400 shown. Figure 8 It shows the relationship with along Figure 1 The cross section intercepted by line X1-X1' and along Figure 1 The cross-section structure corresponding to the section cut by line Y1-Y1'.

[0114] Reference Figure 8 By executing the reference Figure 6A and Figure 6B The process described forms a device isolation film 104 of device isolation trench 104T filling substrate 102 and a plurality of source / drain regions SD. However, in this example, before or after forming the plurality of source / drain regions SD, an impurity region D4 is formed in substrate 102 in a planar shape extending parallel to the main surface 102M of substrate 102. Next, reference [further details can be provided]. Figures 6C-6H The described process allows for the formation of a buffer insulating film 130, multiple direct contacts DC, multiple bit lines BL, multiple insulating spacers 146, multiple insulating barriers 142, multiple conductive plugs 140P, a metal silicide film 172, conductive landing pads LP, and an insulating film 180 on or above the substrate 102, thereby manufacturing a Figure 5A and Figure 5B The integrated circuit device 400 shown.

[0115] Figure 9 A cross-sectional view illustrating a method of manufacturing an integrated circuit device according to an exemplary embodiment of the present invention is shown. (Refer to...) Figure 9 Description of manufacturing Figure 5A and Figure 5B Another example method of the integrated circuit device 400 shown. Figure 9 It shows the relationship with along Figure 1 The cross section intercepted by line X1-X1' and along Figure 1 The cross-section structure corresponding to the section cut by line Y1-Y1'.

[0116] Reference Figure 9 In reference Figures 6A-6H The process is performed in the same manner as described until after the formation of multiple word lines WL and the buried insulating film 128, in Figure 6HA buffer insulating film 130 is formed on the resulting product. However, in this example, before or after the formation of the buffer insulating film 130, an impurity region D4 is formed in the substrate 102 in a planar shape, extending parallel to the main surface 102M of the substrate 102. Next, multiple direct contacts DC, multiple bit lines BL, multiple insulating spacers 146, multiple insulating barriers 142, multiple conductive plugs 140P, a metal silicide film 172, conductive landing pads LP, and an insulating film 180 can be formed on or above the buffer insulating film 130 to manufacture a product. Figure 5A and Figure 5B The integrated circuit device 400 shown.

[0117] In reference Figure 8 and Figure 9 In the described process, to form the impurity region D4, a reference procedure can be performed. Figure 6D The implantation process of dopant ion 108 described, reference Figure 7A The implantation process of dopant ions 308 described, or a similar dopant ion implantation process. Although Figure 8 and Figure 9 An example is shown where the impurity region D4 is formed in a flat plate shape and extends at a level LV4 below the lowest surface of the device separator 104, but the inventive concept is not limited thereto. For example, the impurity region D4 may be formed in a flat plate shape across the substrate 102 and the device separator 104 at a level below the lowest surface of the word line trench WT and above the lowest surface of the device separator 104, extending parallel to the main surface 102M of the substrate 102.

[0118] At this point, although it has been referred to Figures 6A-9 Describes manufacturing Figures 1-5B The illustrated integrated circuit devices 100, 200, 300, and 400 are example methods, but those skilled in the art will understand that, without departing from the scope of the inventive concept, different approaches can be taken using the references. Figures 6A-9 The description is modified in various ways to manufacture integrated circuit devices with various modified and altered structures.

[0119] While the inventive concept has been specifically shown and described with reference to certain exemplary embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. An integrated circuit device, comprising: The substrate includes a plurality of active regions spaced apart from each other; A device isolation membrane is disposed on the substrate and surrounds the plurality of active regions; The word line is arranged on the plurality of active areas and the device isolation membrane and extends longitudinally in a first horizontal direction; A gate dielectric film is disposed between the substrate and the word line, and between the device isolation film and the word line; A first impurity region is disposed between the substrate and the gate dielectric film; and A second impurity region is disposed between the device isolation film and the gate dielectric film. The thickness of the second impurity region is smaller than the thickness of the first impurity region. In a second horizontal direction orthogonal to the first horizontal direction, the width of the second portion of the word line is greater than the width of the first portion of the word line, wherein the first portion is arranged on the plurality of active regions and the second portion is arranged on the device isolation membrane.

2. The integrated circuit device according to claim 1, wherein, The first impurity region includes an amorphous semiconductor layer, which includes dopant ions selected from oxygen ions, silicon ions, helium ions, argon ions, fluorine ions, and combinations thereof.

3. The integrated circuit device according to claim 1, wherein, The second impurity region includes an insulating film comprising dopant ions selected from oxygen ions, silicon ions, helium ions, argon ions, fluorine ions, and combinations thereof.

4. The integrated circuit device according to claim 1, wherein, The second impurity region includes an oxygen-rich silicon oxide film, an oxygen nitride film, a silicon-rich silicon oxide film, a silicon-rich silicon nitride film, or a combination thereof.

5. The integrated circuit device according to claim 1, wherein, Each of the first impurity region and the second impurity region includes interstitial oxygen.

6. An integrated circuit device, comprising: A substrate including device isolation trenches defining a plurality of active regions spaced apart from each other; A device isolation membrane is formed in the device isolation trench; The character line groove extends longitudinally across the plurality of active areas and the device isolation membrane in a first horizontal direction; A gate dielectric film that covers the inner wall of the word line trench; Word lines are arranged on the gate dielectric film and partially fill the word line trenches; A first impurity region is disposed between the substrate and the gate dielectric film; and A second impurity region is disposed between the device isolation film and the gate dielectric film. The thickness of the second impurity region is smaller than the thickness of the first impurity region. In a second horizontal direction orthogonal to the first horizontal direction, the width of the second portion of the word line is greater than the width of the first portion of the word line, wherein the first portion is arranged on the plurality of active regions and the second portion is arranged on the device isolation membrane.

7. The integrated circuit device according to claim 6, wherein, The first impurity region extends along the inner wall of the character line groove. The first impurity region includes dopant ions selected from oxygen ions, silicon ions, helium ions, argon ions, fluorine ions, and combinations thereof.

8. The integrated circuit device according to claim 6, wherein, The second impurity region extends along the inner wall of the letter groove. The second impurity region includes dopant ions selected from oxygen ions, silicon ions, helium ions, argon ions, fluorine ions, and combinations thereof.

9. The integrated circuit device according to claim 6, wherein The gate dielectric film includes an oxygen-rich oxide film.

10. The integrated circuit device according to claim 6, in, The first impurity region and the second impurity region are in contact with the gate dielectric film. The first impurity region and the second impurity region include interstitial oxygen.

11. The integrated circuit device according to claim 6, in, The first impurity region is in contact with the gate dielectric film, and the second impurity region is in contact with the gate dielectric film.

12. The integrated circuit device according to claim 6, wherein, Each of the first impurity region and the second impurity region includes interstitial atoms, which include dopant ions selected from oxygen ions, silicon ions, helium ions, argon ions, fluorine ions, and combinations thereof.

13. The integrated circuit device according to claim 6, wherein, The second impurity region includes an oxygen-rich silicon oxide film, an oxynitride film, or a combination thereof.

14. The integrated circuit device according to claim 6 in, The first impurity region extends along a portion of the inner wall of the word line trench and is spaced apart from the main surface of the substrate. The second impurity region extends along another portion of the inner wall of the letter groove and is spaced apart from the top surface of the device isolation membrane. The thickness of the second impurity region is less than the thickness of the first impurity region.

15. The integrated circuit device according to claim 6, wherein, The first impurity region and the second impurity region include interstitial atoms, which include oxygen atoms, silicon atoms, helium atoms, argon atoms, fluorine atoms, or combinations thereof.

16. An integrated circuit device, comprising: The substrate includes a plurality of active regions spaced apart from each other; A device isolation membrane is disposed on the substrate and surrounds the plurality of active regions; The word line is arranged on the plurality of active areas and the device isolation membrane and extends longitudinally along a first horizontal direction; A gate dielectric film is disposed between the substrate and the word line, and between the device isolation film and the word line; and Impurity regions are disposed on the substrate and the device isolation film and are in contact with the gate dielectric film. In a second horizontal direction orthogonal to the first horizontal direction, the width of the second portion of the word line is greater than the width of the first portion of the word line, wherein the first portion is arranged on the plurality of active regions, and the second portion is arranged on the device isolation membrane. The impurity region includes a first impurity region in contact with the substrate and a second impurity region in contact with the device isolation film, wherein the thickness of the second impurity region is less than the thickness of the first impurity region.

17. The integrated circuit device of claim 16, wherein The impurity region includes dopant ions selected from oxygen ions, silicon ions, helium ions, argon ions, fluorine ions, and combinations thereof.

18. The integrated circuit device of claim 16, wherein In the second horizontal direction, the lower width of the second portion of the word line is greater than the upper width of the second portion.

19. A method for manufacturing an integrated circuit device, the method comprising: Device isolation trenches are formed by etching a substrate, the device isolation trenches defining a plurality of active regions spaced apart from each other; A device isolation membrane is formed in the device isolation trench; Word line grooves are formed by partially removing both the plurality of active regions and the device isolation membrane, and the word line grooves extend longitudinally across the plurality of active regions and the device isolation membrane in a first horizontal direction; Impurity regions are formed in the substrate and the device isolation film by implanting dopant ions into the substrate and the device isolation film via the word line trench; Reduce the thickness of a portion of the impurity region; A gate dielectric film is formed in the word line trench, and the gate dielectric film is in contact with the impurity region; and Word lines are formed on the gate dielectric film to partially fill the word line trenches, and the word lines have a variable width in a second horizontal direction orthogonal to the first horizontal direction.

20. The method of claim 19, wherein Forming the impurity region includes: A first impurity region is formed to surround a first trench portion of the word line trench, the first trench portion exposing the substrate; and A second impurity region is formed to surround a second trench portion of the word line groove, the second trench portion exposing the device isolation membrane, and Reducing the thickness of a portion of the impurity region includes reducing the thickness of the second impurity region.

21. The method of claim 19, wherein When forming the word line, in the second horizontal direction, the width of the second portion of the word line is greater than the width of the first portion of the word line, wherein the first portion is arranged on the plurality of active regions and the second portion is arranged on the device isolation membrane.

22. The method of claim 19, wherein When forming the impurity region, the dopant ions include oxygen ions, silicon ions, helium ions, argon ions, fluorine ions, or combinations thereof.

23. The method of claim 19, wherein The thickness of the portion of the impurity region is reduced in a wet etching atmosphere.

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